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A28F010 1024K (128K x 8) CMOS FLASH MEMORY
(Automotive)
Y
Automotive Temperature Range b 40 C to a 125 C Flash Memory Electrical Chip-Erase 1 Second Typical Chip-Erase Quick-Pulse Programming Algorithm 10 ms Typical Byte-Program 2 Second Chip-Program 1 000 Erase Program Cycles Minimum over Automotive Temperature Range 12 0V g5% VPP High-Performance Read 120 ns Maximum Access Time CMOS Low Power Consumption 30 mA Maximum Active Current 300 mA Maximum Standby Current
Y Y
Integrated Program Erase Stop Timer Command Register Architecture for Microprocessor Microcontroller Compatible Write Interface Noise Immunity Features g10% VCC Tolerance Maximum Latch-Up Immunity through EPI Processing ETOX TM III Flash Nonvolatile Memory Technology EPROM-Compatible Process Base High-Volume Manufacturing Experience JEDEC-Standard Pinouts 32-Pin Plastic DIP 32-Lead PLCC
(See Packaging Spec Order 231369)
Y
Y
Y
Y
Y
Y Y
Y
Y
Intel's 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read write random access nonvolatile memory The 28F010 adds electrical chip-erasure and reprogramming to familiar EPROM technology Memory contents can be rewritten in a test socket in a PROM-programmer socket onboard during subassembly test in-system during final test and in-system after-sale The 28F010 increases memory flexibility while contributing to time- and cost-savings The 28F010 is a 1024-kilobit nonvolatile memory organized as 131 072 bytes of 8 bits Intel's 28F010 is offered in 32-pin Plastic DIP or 32-lead PLCC packages Pin assignments conform to JEDEC standards Extended erase and program cycling capability is designed into Intel's ETOX TM III (EPROM Tunnel Oxide) process technology Advanced oxide processing an optimized tunneling structure and lower electric field combine to extend reliable cycling beyond that of traditional EEPROMs With the 12 0V VPP supply the 28F010 performs a minimum of 1 000 erase and program cycles well within the time limits of the Quick-Pulse Programming and Quick-Erase algorithms Intel's 28F010 employs advanced CMOS circuitry for systems requiring high-performance access speeds low power consumption and immunity to noise Its 120 nanosecond access time provides no-WAIT-state performance for a wide range of microprocessors and microcontrollers Maximum standby current of 300 mA translates into power savings when the device is deselected Finally the highest degree of latch-up protection is achieved through Intel's unique EPI processing Prevention of latch-up is provided for stresses up to 100 mA on address and data pins from b 1V to VCC a 1V With Intel's ETOX III process base the 28F010 leverages years of EPROM experience to yield the highest levels of quality reliability and cost-effectiveness In order to meet the rigorous environmental requirements of automotive applications Intel offers the 28F010 in extended automotive temperature range Read and write characteristics are guaranteed over the range of b 40 C to a 125 C ambient
Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
November 1995
Order Number 290266-004
A28F010
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Figure 1 28F010 Block Diagram
AUTOMOTIVE TEMPERATURE FLASH MEMORIES
The Intel Automotive Flash memories have received additional processing to enhance product characteristics The automotive temperature range is b 40 C to a 125 C during the read write erase program operations
Speed Versions 150 120
Packaging Options Plastic DIP AP AP PLCC AN AN
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A28F010
28F010
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Figure 2 28F010 Pin Configurations Table 1 Pin Description Symbol A0 -A16 DQ0 -DQ7 Type INPUT INPUT OUTPUT Name and Function ADDRESS INPUTS for memory addresses Addresses are internally latched during a write cycle DATA INPUT OUTPUT Inputs data during memory write cycles outputs data during memory read cycles The data pins are active high and float to tri-state OFF when the chip is deselected or the outputs are disabled Data is internally latched during a write cycle CHIP ENABLE Activates the device's control logic input buffers decoders and sense amplifiers CE is active low CE high deselects the memory device and reduces power consumption to standby levels OUTPUT ENABLE Gates the devices output through the data buffers during a read cycle OE is active low WRITE ENABLE Controls writes to the control register and the array Write enable is active low Addresses are latched on the falling edge and data is latched on the rising edge of the WE pulse Note With VPP s 6 5V memory contents cannot be altered ERASE PROGRAM POWER SUPPLY for writing the command register erasing the entire array or programming bytes in the array DEVICE POWER SUPPLY (5V g10%) GROUND NO INTERNAL CONNECTION to device Pin may be driven or left floating
CE
INPUT
OE WE
INPUT INPUT
VPP VCC VSS NC
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A28F010
Designing with the in-circuit alterable 28F010 eliminates socketed memories reduces overall material costs and drastically cuts the labor costs associated with code updates With the 28F010 code updates are implemented locally via an edge-connector or remotely over a serial communication link The 28F010's electrical chip-erasure byte reprogrammability and complete nonvolatility fit well with data accumulation needs Electrical chip-erasure gives the designer a ``blank-slate'' in which to log data Data can be periodically off-loaded for analysis erasing the slate and repeating the cycle Or multiple devices can maintain a ``rolling window'' of accumulated data With high density nonvolatility and extended cycling capability the 28F010 offers an innovative alternative for mass storage Integrating main memory and backup storage functions into directly executable flash memory boosts system performance shrinks system size and cuts power consumption Reliability exceeds that of electromechanical media with greater durability in extreme environmental conditions A high degree of on-chip feature integration simplifies memory-to-processor interfacing Figure 3 depicts two 28F010s tied to the 80C186 system bus The 28F010's architecture minimizes interface circuitry needed for complete in-circuit updates of memory contents With cost-effective in-system reprogramming and extended cycling capability the 28F010 fills the functionality gap between traditional EPROMs and EEPROMs EPROM-compatible specifications straightforward interfacing and in-circuit alterability allows designers to easily augment memory flexibility and satisfy the need for updatable nonvolatile storage in today's designs
APPLICATIONS
The 28F010 flash-memory adds electrical chip-erasure and reprogrammability to EPROM non-volatility and ease of use The 28F010 is ideal for storing code or data-tables in applications where periodic updates are required The 28F010 also serves as a dense nonvolatile data acquisition and storage medium The need for code updates pervades all phases of a system's life from prototyping to system manufacture to after-sale service In the factory during prototyping revisions to control code necessitate ultraviolet erasure and reprogramming of EPROM-based prototype codes The 28F010 replaces the 15- to 20-minute ultraviolet erasure with one-second electrical erasure Electrical chip-erasure and reprogramming occur in the same workstation or PROMprogrammer socket Diagnostics performed at subassembly or final assembly stages often require the socketing of EPROMs Socketed test codes are ultimately replaced with EPROMs containing the final program With electrical chip-erasure and reprogramming the 28F010 is soldered to the circuit board Test codes are programmed into the 28F010 as it resides on the circuit board Ultimately the final code can be downloaded to the device The 28F010's in-circuit alterability eliminates unnecessary handling and less-reliable socketed connections while adding greater test flexibility Material and labor costs associated with code changes increase at higher levels of system integration the most costly being code updates after sale Code ``bugs'' or the desire to augment system functionality prompt after-sale code updates Field revisions to EPROM-based code require the removal of EPROM components or entire boards
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Figure 3 28F010 in a 80C186 System
PRINCIPLES OF OPERATION
Flash-memory augments EPROM functionality with in-circuit electrical erasure and reprogramming The 28F010 introduces a command register to manage this new functionality The command register allows for 100% TTL-level control inputs fixed power supplies during erasure and programming and maximum EPROM compatibility In the absence of high voltage on the VPP pin the 28F010 is a read-only memory Manipulation of the external memory-control pins yields the standard EPROM read standby output disable and Intelligent Identifier operations The same EPROM read standby and output disable operations are available when high voltage is applied to the VPP pin In addition high voltage on VPP enables erasure and programming of the device All functions associated with altering memory contents Intelligent Identifier erase erase verify program and program verify are accessed via the command register Commands are written to the register using standard microprocessor write timings Register contents serve as input to an internal state-machine which controls the erase and programming circuitry Write cycles also internally latch addresses and data
needed for programming or erase operations With the appropriate command written to the register standard microprocessor read timings output array data access the Intelligent Identifier codes or output data for erase and program verification
Integrated Program Erase Stop Timer
Successive command write cycles define the durations of program and erase operations specifically the program or erase time durations are normally terminated by associated program or erase verify commands An integrated stop timer provides simplified timing control over these operations thus eliminating the need for maximum program erase timing specifications Program and erase pulse durations are minimums only When the stop timer terminates a program or erase operation the device enters an inactive state and remains inactive until receiving the appropriate verify or reset command
Write Protection
The command register is only alterable when VPP is at high voltage Depending upon the application the system designer may choose to make the VPP power supply switchable available only when memory updates are desired When high voltage is removed
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Table 2 28F010 Bus Operations Pins Operation Read Output Disable READ-ONLY Standby Intelligent Identifier (Mfr)(2) Intelligent Identifier (Device)(2) Read READ WRITE Output Disable Standby(5) Write VPPL VPPL VPPL VPPL VPPL VPPH VPPH VPPH VPPH A0 X X VIL VIH A0 X X A0 A9 X X VID(3) VID(3) A9 X X A9 VIL VIL VIH VIL VIL VIL VIL VIH VIL VIL VIH X VIL VIL VIL VIH X VIH VIH VIH X VIH VIH VIH VIH X VIL Data Out Tri-State Tri-State Data e 89H Data e B4H Data Out(4) Tri-State Tri-State Data In(6) VPP(1) A0 A9 CE OE WE DQ0 -DQ7
NOTES 1 VPPL may be ground a no-connect with a resistor tied to ground or s 6 5V VPPH is the programming voltage specified for the device Refer to D C Characteristics When VPP e VPPL memory contents can be read but not written or erased 2 Manufacturer and device codes may also be accessed via a command register write sequence Refer to Table 3 All other addresses low 3 VID is the Intelligent Identifier high voltage Refer to DC Characteristics 4 Read operations with VPP e VPPH may access array data or the Intelligent Identifier codes 5 With VPP at high voltage the standby current equals ICC a IPP (standby) 6 Refer to Table 3 for valid Data-In during a write operation 7 X can be VIL or VIH
the contents of the register default to the read command making the 28F010 a read-only memory Memory contents cannot be altered Or the system designer may choose to ``hardwire'' VPP making the high voltage supply constantly available In this instance all operations are performed in conjunction with the command register The 28F010 is designed to accommodate either design practice and to encourage optimization of the processor-memory interface The two-step Program Erase write sequence to the Command Register provides additional software write protection BUS OPERATIONS Read The 28F010 has two control functions both of which must be logically active to obtain data at the outputs Chip-Enable (CE ) is the power control and should be used for device selection Output-Enable (OE ) is the output control and should be used to gate data from the output pins independent of device selection Figure 6 illustrates read timing waveforms When VPP is low (VPPL) the read only operation is active This permits reading the data in the array and outputting the Intelligent Identifier codes (see Ta6
ble 2) When VPP is high (VPPH) the default condition of the device is the read only mode This allows reading the data in the array Further functionality is achieved though the Command Register as shown in Table 3 Output Disable With Output-Enable at a logic-high level (VIH) output from the device is disabled Output pins are placed in a high-impedance state Standby With Chip-Enable at a logic-high level the standby operation disables most of the 28F010's circuitry and substantially reduces device power consumption The outputs are placed in a high-impedance state independent of the Output-Enable signal If the 28F010 is deselected during erasure programming or program erase verification the device draws active current until the operation is terminated Intelligent Identifier Operation The Intelligent Identifier operation outputs the manufacturer code (89H) and device code (B4H) Programming equipment automatically matches the device with its proper erase and programming algorithms
A28F010
With Chip-Enable and Output-Enable at a logic low level raising A9 to high voltage VID (see DC Characteristics) activates the operation Data read from locations 0000H and 0001H represent the manufacturer's code and the device code respectively The manufacturer- and device-codes can also be read via the command register for instances where the 28F010 is erased and reprogrammed in the target system Following a write of 90H to the command register a read from address location 0000H outputs the manufacturer code (89H) A read from address 0001H outputs the device code (B4H) Write Device erasure and programming are accomplished via the command register when high voltage is applied to the VPP pin The contents of the register serve as input to the internal state-machine The state-machine outputs dictate the function of the device The command register itself does not occupy an addressable memory location The register is a latch used to store the command along with address and data information needed to execute the command The command register is written by bringing WriteEnable to a logic-low level (VIL) while Chip-Enable is low Addresses are latched on the falling edge of Write-Enable while data is latched on the rising edge of the Write-Enable pulse Standard microprocessor write timings are used Refer to A C Write Characteristics and the Erase Programming Waveforms for specific timing parameters COMMAND DEFINITIONS When low voltage is applied to the VPP pin the contents of the command register default to 00H enabling read-only operations Placing high voltage on the VPP pin enables read write operations Device operations are selected by writing specific data patterns into the command register Table 3 defines these 28F010 register commands
Table 3 Command Definitions
Command Bus Cycles First Bus Cycle Second Bus Cycle
Req'd Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3) Read Memory Read Intelligent Identifier Codes(4) Set-up Erase Erase(5) Erase Verify(5) Set-up Program Program(6) Program Verify(6) Reset(7) 1 2 2 2 2 2 2 Write Write Write Write Write Write Write X X X EA X X X 00H 90H 20H A0H 40H C0H FFH Read Write Read Write Read Write IA X X PA X X ID 20H EVD PD PVD FFH
NOTES 1 Bus operations are defined in Table 2 2 IA e Identifier address 00H for manufacturer code 01H for device code EA e Address of memory location to be read during erase verify PA e Address of memory location to be programmed Addresses are latched on the falling edge of the Write-Enable pulse 3 ID e Data read from location IA during device identification (Mfr e 89H Device e B4H) EVD e Data read from location EA during erase verify PD e Data to be programmed at location PA Data is latched on the rising edge of Write-Enable PVD e Data read from location PA during program verify PA is latched on the Program command 4 Following the Read Intelligent ID command two read operations access manufacturer and device codes 5 Figure 5 illustrates the Quick-Erase Algorithm 6 Figure 4 illustrates the Quick-Pulse Programming Algorithm 7 The second bus cycle must be followed by the desired command register write
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A28F010
high voltage is applied to the VPP pin In the absence of this high voltage memory contents are protected against erasure Refer to A C Erase Characteristics and Waveforms for specific timing parameters Erase-Verify Command The erase command erases all bytes of the array in parallel After each erase operation all bytes must be verified The erase verify operation is initiated by writing A0H into the command register The address for the byte to be verified must be supplied as it is latched on the falling edge of the Write-Enable pulse The register write terminates the erase operation with the rising edge of its Write-Enable pulse The 28F010 applies an internally-generated margin voltage to the addressed byte Reading FFH from the addressed byte indicates that all bits in the byte are erased The erase-verify command must be written to the command register prior to each byte verification to latch its address The process continues for each byte in the array until a byte does not return FFH data or the last address is accessed In the case where the data read is not FFH another erase operation is performed (Refer to Set-up Erase Erase) Verification then resumes from the address of the last-verified byte Once all bytes in the array have been verified the erase step is complete The device can be programmed At this point the verify operation is terminated by writing a valid command (e g Program Set-up) to the command register Figure 5 the Quick-Erase algorithm illustrates how commands and bus operations are combined to perform electrical erasure of the 28F010 Refer to A C Erase Characteristics and Waveforms for specific timing parameters Set-up Program Program Commands Set-up program is a command-only operation that stages the device for byte programming Writing 40H into the command register performs the set-up operation Once the program set-up operation is performed the next Write-Enable pulse causes a transition to an active programming operation Addresses are internally latched on the falling edge of the Write-Enable pulse Data is internally latched on the rising edge of the Write-Enable pulse The rising edge of Write-Enable also begins the programming operation The programming operation terminates with the next rising edge of Write-Enable used to write the program-verify command Refer to A C Program-
Read Command While VPP is high for erasure and programming memory contents can be accessed via the read command The read operation is initiated by writing 00H into the command register Microprocessor read cycles retrieve array data The device remains enabled for reads until the command register contents are altered The default contents of the register upon VPP power-up is 00H This default value ensures that no spurious alteration of memory contents occurs during the VPP power transition Where the VPP supply is hard-wired to the 28F010 the device powers-up and remains enabled for reads until the command-register contents are changed Refer to the A C Read Characteristics and Waveforms for specific timing parameters Intelligent Identifier Command Flash-memories are intended for use in applications where the local CPU alters memory contents As such manufacturer- and device-codes must be accessible while the device resides in the target system PROM programmers typically access signature codes by raising A9 to a high voltage However multiplexing high voltage onto address lines is not a desired system-design practice The 28F010 contains an inteligent Identifier operation to supplement traditional PROM-programming methodology The operation is initiated by writing 90H into the command register Following the command write a read cycle from address 0000H retrieves the manufacturer code of 89H A read cycle from address 0001H returns the device code of B4H To terminate the operation it is necessary to write another valid command into the register Set-up Erase Erase Commands Set-up Erase is a command-only operation that stages the device for electrical erasure of all bytes in the array The set-up erase operation is performed by writing 20H to the command register To commence chip-erasure the erase command (20H) must again be written to the register The erase operation begins with the rising edge of the Write-Enable pulse and terminates with the rising edge of the next Write-Enable pulse (i e Erase-Verify Command) This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased Also chip-erasure can only occur when
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A28F010
ming Characteristics and Waveforms for specific timing parameters Program-Verify Command The 28F010 is programmed on a byte-by-byte basis Byte programming may occur sequentially or at random Following each programming operation the byte just programmed must be verified The program-verify operation is initiated by writing C0H into the command register The register write terminates the programming operation with the rising edge of its Write-Enable pulse The program-verify operation stages the device for verification of the byte last programmed No new address information is latched The 28F010 applies an internally-generated margin voltage to the byte A microprocessor read cycle outputs the data A successful comparison between the programmed byte and true data means that the byte is successfully programmed Programming then proceeds to the next desired byte location Figure 4 the 28F010 Quick-Pulse Programming algorithm illustrates how commands are combined with bus operations to perform byte programming Refer to A C Programming Characteristics and Waveforms for specific timing parameters Reset Command A reset command is provided as a means to safely abort the erase- or program-command sequences Following either set-up command (erase or program) with two consecutive writes of FFH will safely abort the operation Memory contents will not be altered A valid command must then be written to place the device in the desired state EXTENDED ERASE PROGRAM CYCLING EEPROM cycling failures have always concerned users The high electrical field required by thin oxide EEPROMs for tunneling can literally tear apart the oxide at defect regions To combat this some suppliers have implemented redundancy schemes reducing cycling failures to insignificant levels However redundancy requires that cell size be doubled an expensive solution Intel has designed extended cycling capability into its ETOX-II flash memory technology Resulting improvements in cycling reliability come without increasing memory cell size or complexity First an advanced tunnel oxide increases the charge carrying ability ten-fold Second the oxide area per cell subjected to the tunneling electric field is one-tenth that of common EEPROMs minimizing the probability of oxide defects in the region Finally the peak electric field during erasure is approximately 2 MV cm lower than EEPROM The lower electric field greatly reduces oxide stress and the probability of failure increasing time to wearout by a factor of 100 000 000 The device is programmed and erased using Intel's Quick-Pulse Programming and Quick-Erase algorithms Intel's algorithmic approach uses a series of operations (pulses) along with byte verification to completely and reliably erase and program the device QUICK-PULSE PROGRAMMING ALGORITHM The Quick-Pulse Programming algorithm uses programming operations of 10 ms duration Each operation is followed by a byte verification to determine when the addressed byte has been successfully programmed The algorithm allows for up to 25 programming operations per byte although most bytes verify on the first or second operation The entire sequence of programming and byte verification is performed with VPP at high voltage Figure 4 illustrates the Quick-Pulse Programming algorithm QUICK-ERASE ALGORITHM Intel's Quick-Erase algorithm yields fast and reliable electrical erasure of memory contents The algorithm employs a closed-loop flow similar to the Quick-Pulse Programming algorithm to simultaneously remove charge from all bits in the array Erasure begins with a read of memory contents The 28F010 is erased when shipped from the factory Reading FFH data from the device would immediately be followed by device programming For devices being erased and reprogrammed uniform and reliable erasure is ensured by first programming all bits in the device to their charged state (Data e 00H) This is accomplished using the Quick-Pulse Programming algorithm in approximately two seconds Erase execution then continues with an initial erase operation Erase verification (data e FFH) begins at address 0000H and continues through the array to the last address or until data other than FFH is encountered With each erase operation an increasing number of bytes verify to the erased state Erase efficiency may be improved by storing the address of the last byte verified in a register Following the next erase operation verification starts at that stored address location Erasure typically occurs in one second Figure 5 illustrates the Quick-Erase algorithm
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Bus Command Operation
Comments
Standby
Wait for VPP Ramp to VPPH(1)
Initialize Pulse-Count
Write
Set-up Program Program
Data e 40H
Write
Valid Address Data
Standby Write Program(3) Verify
Duration of Program Operation (tWHWH1) Data e C0H Stops Program Operation(2) tWHGL Read Byte to Verify Programming
Standby Read
Standby
Compare Data Output to Data Expected
Write
Read
Data e 00H Resets the Register for Read Operations Wait for VPP Ramp to VPPL(1)
Standby
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NOTES 1 See DC Characteristics for value of VPPH The VPP power supply can be hard-wired to the device or switchable When VPP is switched VPPL may be ground no-connect with a resistor tied to ground or less than 6 5V Refer to Principles of Operation 2 Refer to Principles of Operation
3 Program Verify is only performed after byte programming A final read compare may be performed (optional) after the register is written with the Read command 4 CAUTION The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device
Figure 4 28F010 Quick-Pulse Programming Algorithm
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Bus Command Operation
Comments
Entire Memory Must e 00H Before Erasure
Use Quick-Pulse Programming Algorithm (Figure 4) Standby Wait for VPP Ramp to VPPH(1)
Initialize Addresses and Pulse-Count Write Write Set-up Erase Erase Data e 20H Data e 20H
Standby
Duration of Erase Operation (tWHWH2) Erase(3) Verify Addr e Byte to Verify Data e A0H Stops Erase Operation(2) tWHGL Read Byte to Verify Erasure
Write Standby Read
Standby
Compare Output to FFH Increment Pulse-Count
Write
Read
Data e 00H Resets the Register for Read Operations Wait for VPP Ramp to VPPL(1)
Standby
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NOTES 1 See DC Characteristics for value of VPPH The VPP power supply can be hard-wired to the device or switchable When VPP is switched VPPL may be ground no-connect with a resistor tied to ground or less than 6 5V Refer to Principles of Operation 2 Refer to Principles of Operation
3 Erase Verify is performed only after chip-erasure A final read compare may be performed (optional) after the register is written with the read command 4 CAUTION The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device
Figure 5 A28F010 Quick-Erase Algorithm 11
A28F010
DESIGN CONSIDERATIONS Two-Line Output Control
Flash-memories are often used in larger memory arrays Intel provides two read-control inputs to accommodate multiple memory connections Two-line control provides for a the lowest possible memory power dissipation and b complete assurance that output bus contention will not occur To efficiently use these two control inputs an address-decoder output should drive chip-enable while the system's read signal controls all flashmemories and other parallel memories This assures that only enabled memory devices have active outputs while deselected devices maintain the low power standby condition
Power Up Down Protection
The 28F010 is designed to offer protection against accidental erasure or programming caused by spurious system-level signals that may exist during power transitions Also with its control register architecture alteration of memory contents only occurs after successful completion of the two-step command sequences Power supply sequencing is not required Internal circuitry of the 28F010 ensures that the command register architecture is reset to the read mode on power up A system designer must guard against active writes for VCC voltages above the VLKO when VPP is active Since both WE and CE must be low for a command write driving either to VIH will prohibit writes The control register architecture provides an added level of protection since alteration of memory contents only occurs after successful completion of the two-step command sequences
Power Supply Decoupling
Flash memory power-switching characteristics require careful device decoupling System designers are interested in three supply current (ICC) issues standby active and transient current peaks produced by falling and rising edges of chip-enable The capacitive and inductive loads on the device outputs determine the magnitudes of these peaks Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks Each device should have a 0 1 mF ceramic capacitor connected between VCC and VSS and between VPP and VSS Place the high-frequency low-inherent-inductance capacitors as close as possible to the devices Also for every eight devices a 4 7 mF electrolytic capacitor should be placed at the array's power supply connection between VCC and VSS The bulk capacitor will overcome voltage slumps caused by printedcircuit-board trace inductance and will supply charge to the smaller capacitors as needed
28F010 Power Dissipation
When designing portable systems designers must consider battery power consumption not only during device operation but also for data retention during system idle time Flash nonvolatility increases the usable battery life of your system because the 28F010 does not consume any power to retain code or data when the system is off Table 4 illustrates the power dissipated when updating the 28F010 Table 4 28F010 Typical Update Power Dissipation(4) Operation Array Program Program Verify Array Erase Erase Verify One Complete Cycle Power Dissipation (Watt-Seconds) 0 171 0 136 0 478 Notes 1 2 3
VPP Trace on Printed Circuit Boards
Programming flash-memories while they reside in the target system requires that the printed circuit board designer pay attention to the VPP power supply trace The VPP pin supplies the memory cell current for programming Use similar trace widths and layout considerations given the VCC power bus Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots
NOTES 1 Formula to calculate typical Program Program Verify Bytes c typical Prog Pulses Power e VPP c (tWHWH1 c IPP2 typical a tWHGL c IPP4 typical) a VCC c Bytes c typical Prog Pulses (tWHWH1 c ICC2 typical a tWHGL c ICC4 typical 2 Formula to calculate typical Erase Erase Verify Power e VPP (VPP3 typical c tERASE typical a IPP5 typical c tWHGL c Bytes) a VCC (ICC3 typical c tERASE typical c ICC5 typical c tWHGL c Bytes) 3 One Complete Cycle e Array Preprogram a Array Erase a Program 4 ``Typicals'' are not guaranteed but based on a limited number of samples from production lots
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VCC Supply Voltage with Respect to Ground Output Short Circuit Current Maximum Junction Temperature (TJ)
ABSOLUTE MAXIMUM RATINGS
Operating Temperature During Read During Erase Program Temperature Under Bias Storage Temperature Voltage on Any Pin with Respect to Ground Voltage on Pin A9 with Respect to Ground VPP Supply Voltage with Respect to Ground During Erase Program
b 40 C to a 125 C(1) b 40 C to a 125 C b 40 C to a 125 C b 65 C to a 150 C b 2 0V to a 7 0V(2) b 2 0V to a 13 5V(2 3)
b 2 0V to a 7 0V(2)
100 mA(4)
a 140 C
NOTICE This is a production data sheet The specifications are subject to change without notice
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
b 2 0V to a 14 0V(2 3)
NOTES 1 Operating temperature is for automotive product defined by this specification 2 Minimum DC input voltage is b0 5V During transitions inputs may undershoot to b2 0V for periods less than 20 ns Maximum DC voltage on output pins is VCC a 0 5V which may overshoot to VCC a 2 0V for periods less than 20 ns 3 Maximum DC voltage on A9 or VPP may overshoot to a 14 0V for periods less than 20 ns 4 Output shorted for no more than one second No more than one output shorted at a time
OPERATING CONDITIONS Symbol TA VCC Parameter Min Operating Temperature VCC Supply Voltage
b 40
Limits Max
a 125
Unit C V
Comments For Read-Only and Read Write Operations
4 50
5 50
DC CHARACTERISTICS
Symbol ILI ILO ICCS ICC1 ICC2 ICC3 ICC4 ICC5 IPPS IPP1 Parameter Input Leakage Current Output Leakage Current VCC Standby Current VCC Active Read Current
TTL NMOS COMPATIBLE
Notes 1 1 1 1 12 12 12 12 1 1 90 10 10 50 50 50 Limits Min Typical Max
g1 0 mA VCC e VCC Max VIN e VCC or VSS g10 mA VCC e VCC Max VOUT e VCC or VSS
Unit
Test Conditions
10 30 30 30 30 30
mA VCC e VCC Max CE e VIH mA VCC e VCC Max CE e VIL f e 6 MHz IOUT e 0 mA mA Programming in Progress mA Erasure in Progress mA VPP e VPPH Program Verify in Progress mA VPP e VPPH Erase Verify in Progress mA VPP l VCC
VCC Programming Current VCC Erase Current VCC Program Verify Current VCC Erase Verify Current VPP Leakage Current VPP Read Current or Standby Current
g10 mA VPP s VCC
200
g10 mA VPP s VCC
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A28F010
DC CHARACTERISTICS
Symbol IPP2 IPP3 IPP4 IPP5 VIL VIH VOL VOH1 VID IID VPPL VPPH VLKO Parameter VPP Programming Current VPP Erase Current
TTL NMOS COMPATIBLE (Continued)
Notes 12 12 12 12
b0 5
Limits Min Typical 80 40 20 20 Max 30 30 50 50 08 VCC a 0 5 0 45 24 11 50 13 00 10 90 0 00 11 40 25 30 500 65 12 60
Unit
Test Conditions
mA VPP e VPPH Programming in Progress mA VPP e VPPH Erasure in Progress mA VPP e VPPH Program Verify in Progress mA VPP e VPPH Erase Verify in Progress V V V IOL e 2 1 mA VCC e VCC Min V IOH e b 2 5 mA VCC e VCC Min V A9 e VID mA mA V NOTE Erase Program are Inhibited when VPP e VPPL V V A9 e VID
VPP Program Verify Current VPP Erase Verify Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage A9 Intelligent Identifer Voltage VCC ID Current VPP ID CURRENT VPP during Read-Only Operations VPP during Read Write Operations VCC Erase Write Lock Voltage
20
1
DC CHARACTERISTICS
Symbol ILI ILO ICCS ICC1 ICC2 ICC3 IPPS IPP1 Parameter Input Leakage Current
CMOS COMPATIBLE
Notes Min 1 1 1 1 12 12 1 1 90 10 10 50 Limits Typical Max
g1 0
Unit mA mA mA mA mA mA mA mA
Test Conditions VCC e VCC Max VIN e VCC or VSS VCC e VCC Max VOUT e VCC or VSS VCC e VCC Max CE e VCC g0 2V VCC e VCC Max CE e VIL f e 6 MHz IOUT e 0 mA Programming in Progress Erasure in Progress VPP s VCC VPP l VCC VPP s VCC
Output Leakage Current VCC Standby Current VCC Active Read Current VCC Programming Current VCC Erase Current VPP Leakage Current VPP Read Current or Standby Current
g10
300 30 30 30
g10
200
g10
14
A28F010
DC CHARACTERISTICS
Symbol IPP2 Parameter VPP Programming Current VPP Erase Current VPP Program Verify Current VPP Erase Verify Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
CMOS COMPATIBLE (Continued)
Notes 12 Limits Min Typical 80 Max 30 Unit mA Test Conditions VPP e VPPH Programming in Progress VPP e VPPH Erasure in Progress VPP e VPPH Program Verify in Progress VPP e VPPH Erase Verify in Progress
IPP3 IPP4 IPP5 VIL VIH VOL VOH1 VOH2 VID IID IID VPPL
12 12 12
b0 5
40 20 50
30 50 50 08 VCC a 0 5 0 45
mA mA mA V V V
0 7 VCC
IOL e 2 1 mA VCC e VCC Min IOH e b 2 5 mA VCC e VCC Min IOH e b 100 mA VCC e VCC Min
0 85 VCC VCC b 0 4
V
A9 Intelligent Identifier Voltage VCC ID Current VPP ID Current VPP during ReadOnly Operations VPP during Read Write Operations VCC Erase Write Lock Voltage 1 1 0 00
11 50 10 90
13 00 30 500 65
V mA mA V A9 e ID A9 e ID NOTE Erase Programs are Inhibited when VPP e VPPL
VPPH
11 40
12 60
V
VLKO
25
V
CAPACITANCE(3) TA e 25 C f e 1 0 MHz Symbol CIN COUT Parameter Min Address Control Capacitance Output Capacitance Limits Max 8 12 pF pF VIN e 0V VOUT e 0V Unit Conditions
NOTES 1 All currents are in RMS unless otherwise noted Typical values at VCC e 5 0V VPP e 12 0V T e 25 C 2 Not 100% tested characterization data available 3 Sampled not 100% tested 4 ``Typicals'' are not guaranteed but are based on a limited number of samples from production lots
15
A28F010
AC TESTING INPUT OUTPUT WAVEFORM
AC TESTING LOAD CIRCUIT
290266 - 7 AC Testing Inputs are driven at 2 4V for a logic ``1'' and 0 45V for a logic ``0'' Testing measurements are made at 2 0V for a logic ``1'' and 0 8V for a logic ``0'' Rise Fall time s 10 ns CL e 100 pF CL includes Jig Capacitance
290266 - 8
AC TEST CONDITIONS Input Rise and Fall Times (10% to 90%) 10 ns Input Pulse Levels 0 45V and 2 4V Input Timing Reference Level Output Timing Reference Level 0 8V and 2 0V 0 8V and 2 0V
AC CHARACTERISTICS
Versions Symbol tAVAV tRC tELQV tCE tAVQV tACC tGLQV tOE tELQX tLZ tEHQZ tGLQX tOLZ tGHQZ tDF tOH tWHGL
Read-Only Operations(2)
Notes 3 28F010-120 Min 120 120 120 50 3 3 3 4 13 0 6 0 30 0 6 0 55 0 35 0 55 Max 28F010-150 Min 150 150 150 55 Max Unit ns ns ns ns ns ns ns ns ns ms
Characteristic Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable to Output in Low Z Output Disable to Output in High Z Output Hold from Address CE or OE Change Write Recovery Time before Read
NOTES 1 Whichever occurs first 2 Rise Fall Time s 10 ns 3 Not 100% tested characterization data available 4 Guaranteed by design
16
A28F010
Figure 6 AC Waveforms for Read Operations 17
290266- 9
A28F010
AC CHARACTERISTICS
Versions Symbol tAVAV tWC tAVWL tAS tWLAX tAH tDVWH tDS tWHDX tDH tWHGL tGHWL tELWL tCS tWHEH tCH tWLWH tWP tELEH tWHWL tWPH tWHWH1 tWHWH2 tVPEL
Write Erase Program Operations(1 3)
Notes 28F010-120 Min 120 0 2 60 50 10 6 0 2 20 0 2 2 80 80 20 4 4 10 95 10 Max 28F010-150 Min 150 0 60 50 10 6 0 20 0 80 80 20 10 95 10 Max Unit ns ns ns ns ns ms ms ns ns ns ns ns ms ms ms
Characteristic Write Cycle Time Address Set-Up Time Address Hold Time Data Set-up Time Data Hold Time Write Recovery Time before Read Read Recovery Time before Write Chip Enable Set-Up Time before Write Chip Enable Hold Time Write Pulse Width(2) Alternative Write(2) Pulse Width Write Pulse Width High Duration of Programming Operation Duration of Erase Operation VPP Set-Up Time to Chip Enable Low
NOTES 1 Read timing characteristics during read write operations are the same as during read-only operations Refer to AC Characteristics for Read-Only Operations 2 Chip-Enable Controlled Writes Write operations are driven by the valid combination of Chip-Enable and Write-Enable In systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up hold and inactive Write-Enable times should be measured relative to the Chip-Enable waveform 3 Rise Fall time s 10 ns 4 The internal stop timer terminates the programming erase operations thereby eliminating the need for a maximum specification
ERASE AND PROGRAMMING PERFORMANCE Parameter Chip Erase Time Chip Program Time Erase Program Cycles Notes Min 1346 124 15 1 000 Limits Typ 1 2 100 000 Max 60 12 5 Sec Sec Cycles Excludes 00H Programming Prior to Erasure Excludes System-Level Overhead Unit Comments
NOTES 1 ``Typicals'' are not guaranteed but based on a limited number of samples taken from production lots Data taken at T e 25 C VPP e 12 0V VCC e 5 0V 2 Minimum byte programming time excluding system overhead is 16 msec (10 msec program a 6 msec write recovery) while maximum is 400 msec byte (16 msec x 25 loops allowed by algorithm) Max chip programming time is specified lower than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte 3 Excludes 00H programming prior to erasure 4 Excludes system-level overhead 5 Refer to RR-60 ``ETOX Flash Memory Reliability Data Summary'' for typical cycling data and failure rate calculations 6 Maximum erase specification is determined by algorithmic limit and accounts for cumulative effect of erasure at T e b40 C 1 000 cycles VPP e 11 4V VCC e 4 5V
18
A28F010
290266 - 17
290266 - 18
Figure 7 28F010 Typical Programming Capability See Note 1 Page 18
Figure 8 28F010 Typical Program Time at 12V
19
A28F010
290266 - 19
290266 - 20
Figure 9 28F010 Typical Erase Capability See Note 1 Page 18
Figure 10 28F010 Typical Erase Time at 12V
20
A28F010
Figure 11 AC Waveforms for Programming Operations 21
Alternative Write Timing
290266- 14
A28F010
Figure 12 AC Waveforms for Erase Operations 22
290266- 15
A28F010
Ordering Information
290266 - 16
Valid Combinations AP28F010-120 AP28F010-150 AN28F010-120 AN28F010-150
ADDITIONAL INFORMATION
ER-20 ``ETOX TM II Flash Memory Technology'' ER-24 ``Intel Flash Memory'' RR-60 ``ETOX TM Flash Memory Reliability Data Summary'' AP-316 ``Using Flash Memory for In-System Reprogrammable Nonvolatile Storage'' AP-325 ``Guide to Flash Memory Reprogramming''
Order Number 294005 294008 293002 292046 292059
REVISION HISTORY
Number 003 004 Description Changed Erase Program Cycles to 1 000 minimum Added 120 ns Characteristics
23

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