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CXB1590Q
SDH 8 bit 622 Mbps Transceiver
Description The CXB1590Q is a transceiver IC with built-in PLL for ATM network. For a receiver 622 Mbps serial data is received and output it as the 8-bit parallel data; for a transmitter 622 Mbps 8-bit parallel data is output as the serial data. 80 pin QFP (Plastic)
Features * Transmitter and receiver in a single chip * TTL/ECL compatible * Single +3.3 V power supply * PLL for clock generation and clock / data recovery * 8:1 Parallel/Serial Converter, 1:8 Serial/Parallel Converter, Frame (A1/A1/A1/A2/A2/A2, A1 : 11110110, A2 : 00101000 ) detector * Selectable 4 modes input/output REFCLK (19.44, 25.92, 51.84, 77.76 MHz) * Adjustable timing between input parallel data and transmitting parallel clock * Lock detector for a receiver PLL * Selectable ECL-output 4 signals (retimed data, transmitted bit rate clock, recovered bit rate clock, received serial data through) in a test mode * Selectable operation clock of transmitter site recovered bit rate clock in a test mode * Local loop back circuit (parallel data to parallel data) * Low power consumption (1.0 W typical) * 80-pin plastic QFP package (body size : 14 mm x 14 mm)
REFSEL <1 ,0> CDRLK
LOSE
RLPF0
TLPB
LOST
LOSE
RLPF1
LOST
N=8, 12, 24, 32
T
T
T
E
E
A
A
T
T
622/N MHz
T REFCKO
/N
Clock 622MHz
T OOF
Frame Detect
RSDP E RSDN E
622Mbps
T FP
1 0
CDR (Rx PLL)
Data 622Mbps
S/P 1:8
77.76Mbps
T RPD <7..0> T RPCLK
/8
77.76MHz
T TPDLC
622Mbps
T DLY <1,0>
1 0 P/S 1:8
77.76Mbps
TSDP E TSDN E
T TPD <7..0>
1 CLK x N (Tx CLK) 0
Clock 622MHz
/8
77.76MHz
T TPCLK T REFCKI
622/N MHz
T
RESET
T
FLPB
A
TLPF0
A
TLPF1
A
REXTP
A
REXTV
T
TCKSEL
T TTL I/O E ECL I/O A Analog
Fig. 1 Block Diagram
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E97905A83-TE
CXB1590Q
Table 1 Absolute Maximum Ratings Description Power supply voltage TTL DC input voltage ECL DC input voltage ECL peak-to-peak differential input voltage swing TTL output current (High) TTL output current (Low) ECL output current Ambient temperature Storage temperature Symbol VCC VI_T VI_E VIS_E IOH_T IOL_T IO_E Ta Tstg Min. -0.3 -0.5 VCC-2.0 -4.0 -20 0 -30 -55 -65 Typ.
(VEEE, VEET, VEEG, VEEP=GND) Max. 4.0 5.5 VCC 4.0 0 20 0 70 150 Unit V V V V mA mA mA C C Conditions
Under bias
Table 2 Recommended Operating Conditions Description Power supply voltage Ambient temperature Symbol VCC Ta Min. 3.135 0 Typ. 3.3
(on PCB with 2 planes, no air flow) Max. 3.465 70 Unit V C Conditions
60 RSDNT RSDPT VCCE VEEE RSDN RSDP VEET VCCG VEEG TCKSEL VEEG VCCG TLPB FLPB ECKEN REFCKI VEET OOF VCCG VEEG 61
ECK RLPF1 RLPF0 REXTP REXTV VEEP VEEP TLPF1 TLPF0 VCCP DLY1 DLY0 LOSE LOSE VEEE VCCE TSDN TSDP REFSEL1 REFSEL0
50 41 40 LOST LOST RESET VEET CDRLK VEEG VCCG VCCT TPCLK VEET TPD7 TPD6 TPD5 TPD4 TPD3 TPD2 TPD1 TPD0 VCCG VEEG 70 30 80 1 10 20 21
VCCT FP VEET RPD0 RPD1 VCCT RPD2 RPD3 VEET RPD4 RPD5 VCCT RPD6 RPD7 VEET RPCLK VCCT REFCKO VEET TPDLC
Fig. 2 Pin Configuration (Top View) --2--
CXB1590Q
Table 3 DC Characteristics Description Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Output HIGH voltage (TTL) Output LOW voltage (TTL) Input HIGH voltage (ECL) Input LOW voltage (ECL) Peak-to-peak differential input voltage swing (ECL) Output HIGH voltage (ECL) Output LOW voltage (ECL) Peak-to-peak differential output voltage swing (ECL) Supply current Power dissipation Symbol VIH_T VIL_T IIH_T IIL_T VOH_T VOL_T VIH_E VIL_E VIS_E 1) VOH_E VOL_E VOS_E 2) ICC Pd Min. 2.0 0.0 -400 2.2 VCC-1.17 VCC-1.81 100 VCC-1.30 VCC-1.90 1200 224 694
(Under the recommended conditions. See Table 2.) Typ. Max. 5.5 0.8 20 Unit V V A A V V V V mV V V mV mA mW Outputs open Outputs open Conditions
0.5 VCC-0.88 VCC-1.48 2000 VCC-0.81 VCC-1.55 2000 296 977 412 1442
Vin=VCC Vin=0 IOH=-0.4mA IOL=2mA
AC coupled 50 to VCC-2 V 50 to VCC-2 V
Note : 1) Peak-to-peak differential input voltage swing (ECL) 2) Peak-to-peak differential output voltage swing (ECL)
Voltage VCC signal-in+ VIH_E
Vi1
Vi2
VIL_E signal-in- VEE=GND 1) VIS_E= |Vi1| + |Vi2| Voltage VCC signal-out+ VOH_E
Vo1
Vo2
VOL_E signal-out- VEE=GND 2) VOS_E= |Vo1| + |Vo2|
Fig. 3 ECL peak-to-peak differential input/output voltage swing --3--
CXB1590Q
Table 4 AC Characteristics Description Operating Frequency Input TTL rise time of TX Input TTL fall time of TX Input TTL rise time of REFCKI Input TTL fall time of REFCKI Output TTL rise time Output TTL fall time Output ECL rise time Output ECL fall time Duty Cycle of REFCKI RPD setup time to RPCLK rise RPD hold time to RPCLK rise FP setup time to RPCLK rise FP hold time to RPCLK rise TPD setup time to TPCLK rise Symbol Fop Tir_TX Tif_TX Tir_REF Tif_REF Tor_T Tof_T Tor_E Tof_E DC_RCI Ts_RPD Th_RPD Ts_FP Th_FP Ts_TPD Min. 600 0.7 0.7 0.7 0.7
(Under the recommended conditions. See Table 2.) Typ. 622 Max. 650 4.8 4.8 2.4 2.4 3.5 3.5 400 400 67 Unit Mbps ns ns ns ns ns ns ps ps % ns ns ns ns ns ns ns ns ns ns ns ns ns ns % % deg deg kHz kHz deg deg kHz kHz kHz kHz UI Conditions 0.8 V to 2.0 V 2.0 V to 0.8 V 0.8 V to 2.0 V 2.0 V to 0.8 V 0.8 V to 2.0 V, CL=10 pF 2.0 V to 0.8 V, CL=10 pF 20 % to 80 %, CL=2 pF 20 % to 80 %, CL=2 pF CL=10 pF CL=10 pF CL=10 pF CL=10 pF timing mode : DLY0 timing mode : DLY1 timing mode : DLY3 timing mode : DLY5 timing mode : DLY7 timing mode : DLY0 timing mode : DLY1 timing mode : DLY3 timing mode : DLY5 timing mode : DLY7 in frequency lock in frequency lock Serial data output Serial data output OC-12 template STM-4 template R4=R5=620 R4=R5=1 kohm OC-12 Template, R4=R5=620 STM-4 template, R4=R5=620 OC-12 template, R4=R5=1 k STM-4 template, R4=R5=1 k Serial data input
TPD hold time to TPCLK rise
Th_TPD
Duty Cycle of REFCKO Duty Cycle of RPCLK TSDP/TSDN Deterministic jitter (p-p) TSDP/TSDN Random jitter (rms) Clock generator PLL band width Recovered clock Random jitter (rms) CDR PLL band width
DC_RCO DC_RPC TxDJ TxRJ TxBW
33 3.0 5.5 3.5 5.0 3.6 5.4 8.3 11.6 14.5 0.0 -1.8 -4.8 -8.0 -10.9 40 40
60 60 55 5.5
600 500
RxRj RxBW
5300 4500 6.5 6.0 700 700 1100 1100
Jitter Tolerance
JT --4--
0.7
CXB1590Q
Table 5 PLL AC Characteristics Description Frequency Acquisition Time of TX PLL Bit Synchronization Time of RX PLL Symbol Tfa Tbs Min.
(Under the recommended conditions. See Table 2.) Typ. Max. 1000 6500 Unit s bit Conditions Loop Damping Capacitor=0.022 F
--5--
CXB1590Q
Table 6 Pin Description Pin No. 66 65 39 40 47 48 73 Pin Name RSDP RSDN LOST LOST LOSE LOSE* TLPB Type I_ECL I_TTL I_TTL I_ECL Description Received serial data (RSDP/RSDN) are the differential input of 622 Mbps Rx bit stream. Loss of signal (LOST/LOST, LOSE/LOSE) indicate that RSDP/RSDN dosen't exist in order to prevent the PLL from runaway. RSDP/RSDN are masked and RxPLL goes training mode when LOST=H and LOST=L and LOSE/LOSE=H/L. Terminal loop back (TLPB) switch the RxPLL input to the loop backed signal form P/S converter when it's Low. Clock data recovery in lock (CDRLK) indicate that RxPLL is lock to Rx bit stream. It's active-high. Reference clock output (REFCKO) is 622/N MHz clock made from the recovered clock by RxPLL. Received parallel clock (RPCLK) is 77.76 MHz clock made from the recovered clock by RxPLL. It provides timing of RPD <7..0> and FP. Received parallel data (RPD <7..0>) are the bus of 77.76 Mbps Rx byte stream. RPD7 is the first bit received, RPD0 is the last. They should be latched on the rising edge of RPCLK. Frame position (FP) indicate the 3rd A2 byte in ATM frame header. It is active-high signal. Out of frame (OOF) enable the frame detector to find A1/A1/A1/A2/A2/A2 stream in RSDP/RSDN, output the flag to FP and establish the boundary when it's High. The frame detector dosen't output flag or re-establish the byte boundary when it's low. Reference clock input (REFCKI) is the 622/N MHz clock for transmitting clock source. TxPLL multiply it by N to generate the transmitting clock. It's also used for RxPLL training when loss of signal. Transmitting parallel clock (TPCLK) is 77.76 MHz clock made from the transmitting clock by the divider. It provides timing of TPD <7..0>. Transmitting parallel data (TPD <7..0>) are the bus of 77.76 Mbps Tx byte stream. TPD7 is the first bit transmitting, TPD0 is the last. They are latched on the rising edge of TPCLK when TPDLC=High. The latch timing is adjustable when TPDLC=Low by DLY <1, 0>. --6-- Equivalent circuit (c) (a) (a) (c)
I_TTL
(a)
36 18
CDRLK REFCKO
O_TTL O_TTL
(b) (b)
16 4, 5, 7, 8, 10, 11, 13, 14 2
RPCLK
O_TTL
(b)
RPD <0..7>
O_TTL
(b)
FP
O_TTL
(b)
78
OOF
I_TTL
(a)
76
REFCKI
I_TTL
(a)
32
TPCLK
O_TTL
(b)
23-30
TPD <0..7>
I_TTL
(a)
CXB1590Q
Pin No.
Pin Name
Type
Description Transmitting parallel data latch control (TPDLC) enable the timing adjust between TPCLK and TPD <7..0> by DLY <1,0>. It's active-low. DLY <1, 0> act as timing adjuster between TPCLK and TPD <7..0> when TPDLC=Low. They should be open or High when TPDLC=High, other setting is for testing in fabrication. Transmitting serial data (TSDP/TSDN) are the differential output of 622 Mbps Tx bit stream. Facility loop back (FLPB) enable the direct loop back from RSDP/RSDN to TSDP/TSDN when it's Low. REFSEL <1, 0> control N to select the Reference clock frequency. N=8, 12, 24, 32. (REFCKI=77.76, 51.84, 25.92, 19.44 MHz.) Received serial data through (RSDPT/RSDNT) are connected to RSDP/RSDN through the chip for ECL signal termination. Rx loop filter (RLPF0/RLPF1). They should be tied via external LPF devices (-R-C-R). Tx loop filter (TLPF0/TLPF1). They should be tied via external LPF devices (-R-C-R). External resistor for VCO (REXTV). It should be tied to VEEP via external resistor to setting the center frequency of VCO in both RxPLL and TxPLL. External resistor for charge pump (REXTP). It should be tied to VEEP va external resistor to setting the charge-pump current of RxPLL. Reset (RESET) is the active-low reset. It's for testing in the fabrication. Leave it open in normal operation. Transmitting clock act as the recovered clock when it's Low. Leave it open in normal operation. External clock (ECK) act as the transmitting and recovered clock input when ECKEN=Low. It's for testing in the fabrication. Leave it open in normal operation. External clock enable (ECKEN) enable the ECK when it's Low. It's for testing in the fabrication. Leave it open in normal operation
Equivalent circuit (a)
20
TPDLC
I_TTL
49 50 43 44 74 41 42 62 61 58 59 52 53 56
DLY0 DLY1 TSDP TSDN FLPB REFSEL0 REFSEL1 RSDPT RSDNT RLPF0 RLPF1 TLPF0 TLPF1 REXTV
I_TTL I_TTL O_ECL I_TTL I_TTL I_TTL
(a) (a) (e) (a) (a) (a)
EX
--
EX EX
(f) (f)
EX
(g)
57
REXTP
EX
(h)
38 70
RESET TCKSEL
I_TTL I_TTL
(a) (a)
60
ECK
I_ECL
(d)
75
ECKEN
I_TTL
(a)
--7--
CXB1590Q
Pin No. 45, 63 1, 6, 12, 17, 33 22, 34, 68, 72, 79 51 46, 64 3, 9, 15, 19, 31, 37, 67, 77 21, 35, 69, 71, 80 54, 55
Pin Name VCCE VCCT VCCG VCCP VEEE VEET
Type PS PS PS PS PS PS
Description Power supply for ECL output : Normally 3.3 V Power supply for TTL output : Normally 3.3 V Power supply for internal logic gates : Normally 3.3 V Power supply for PLL : Normally 3.3 V Ground for ECL output : Normally 0 V Ground for TTL output : Normally 0 V
Equivalent circuit -- -- -- -- -- --
VEEG VEEP
PS PS
Ground for internal logic gates : Normally 0 V Ground for PLL : Normally 0 V
-- --
Table 7 Pin Type Definition Type PS I_TTL O_TTL I_ECL O_ECL EX Definition Power supply or ground Input TTL Output TTL Input ECL Output ECL External circuit node
--8--
CXB1590Q
Equivalent Circuit
VCCG
VCCT3
TTL-OUT TTL-IN
VEET (a) TTL input equivalent circuit
VEET (b) TTL output equivalent circuit
VEET
VCCE
VCCG
VCCE
VCCG
ECL-IN VCCE - 1.3V ECL-IN
ECL-IN
VCCE - 1.3V
VEEE (c) ECL input equivalent circuit (differential)
VEEG
VEEE (d) ECL input equivalent circuit (single)
VEEG
VCCE
ECL-OUT
ECL-OUT
VEEE (e) ECL output equivalent circuit
--9--
CXB1590Q
VCCP LPF0 LPF1
VEEP2 (f) LPF0/LPF1-pin equivalent circuit
VEEP1
VCCP
VCCP
REXT
REXT
VEEP2 (g) REXTV-pin equivalent circuit (h) REXTP-pin equivalent circuit
VEEP2
Fig. 4 Equivalent CIrcuit
--10--
CXB1590Q
Selection Table Table 8 Input Data to RxPLL Selection Table TLPB 1 0 0 TPDLC X X 0 DLY0 X 1 X DLY1 X 1 Serial-data from P/S-conv. X Input data to RxPLL RSDP/RSDN
Table 9 Monitor Output (TSDP/TSDN) Selection Table FLPB 0 1 1 1 1 1 TPDLC X 1 1 0 X 1 DLY0 X 0 0 X 1 1 DLY1 X 0 1 X Serialized data 1 0 RSDP/RSDN TSDP/TSDN Rx retimed data Recovered bit rate clock Transmitted bit rate clock
Table 10 Reference Clock Frequency Selection Table REFSEL0 0 0 1 1 REFSEL1 0 1 0 1 REFCKI-Frequency 77.76 MHz 51.84 MHz 19.44 MHz 25.92 MHz
--11--
CXB1590Q
I/O Timing 1. Transmitter Transmitting parallel clock (TPCLK) is 77.76 MHz clock made from transmitting clock by the divider. It provides timing of TPD<7..0>. Transmitting parallel data (TPD<7..0>) are the bus of 77.76 Mbps Tx byte stream. TPD is converted into output-serial-data by P/S converter. Timing between TPCLK and TPD<7..0> is able to adjust by another inputs (TPDLC, DLY0, DLY1). This timing has 5 kinds ; DLY0, DLY1, DLY3, DLY5, DLY7. Timing of TPD for TPCLK (set up, hold time) is shown in Fig. 5 and Table 11.
TPCLK 77.76MHz TTL-output Vth=1.4V
Ts_TPD Th_TPD
TPD 77.76Mbps TTL-input Vth=1.4V
Valid
FIg. 5 Transmitter Section Timing
Table 11 Timing Mode Selection Table TPDLC 1 0 0 0 0 DLY0 X 0 1 0 1 DLY1 X 0 0 1 1 timing DLY0 DLY1 DLY3 DLY5 DLY7 Ts_TPD (nsec) 3.6 5.4 8.3 11.6 14.5 Th_TPD (nsec) 0.0 -1.8 -4.8 -8.0 -10.9
--12--
CXB1590Q
2. Receiver Received parallel clock (RPCLK) is 77.76 MHz clock extracted from the recovered data by RxPLL. It provides timing of RPD<7..0> and FP. Received parallel data (RPD<7..0>) are the bus of 77.76 Mbps Rx byte stream. Input-serial-data is converted into RPD by S/P converter with RPCLK. When OOF is set "High", frame position (FP) indicate the 3rd A2 byte in ATM frame header. FP is active high signal which is detected by frame-detector, and width of active high signal is 1 byte. Timing of RPD and FP for RPCLK are shown in Fig. 5. And bounds of "OOF=1" for enable FP detection is shown in Fig. 6.
--13--
CXB1590Q
A1 A1 A1 A2 A2 A2 111 10 110 1 111 01 10 11 110 11 0 0 01 01 000 0 010 10 00 00 101 00 0 RSDP High speed serial data input
DATA1
DATA2
OOF Out of frame signal input
bounds of "OOF = 1" for enable FP detection Ts_FP Th_FP 2.0V 2.0V
FP Frame position output Reset
RPCLK Byte clock output
1.4V
RPD7
0
RPD6
0
RPD5
1
Parallel data outputs
RPD4
0
RPD3
1
RPD2
0
RPD1
0
RPD0
0 Ts_RPD Th_RPD 2.0V 2.0V
RPD<7-0> Parallel data outputs summary 0.8V
A2
DATA1 0.8V
Fig. 6 Receiver Section Timing --14--
CXB1590Q
Notes on Operation 1. External Components PLLs CXB1590Q is the transceiver. It has the clock synthesizer for the transmitter and the clock recovery circuit for the receiver. (1) Clock Synthesizer CXB1590Q has the internal clock synthesizer based on PLL, which locks to REFCKI and generates bit rate clock frequency. It needs external loop filter and a resistor which determines the free-run frequency of VCO. Typical values of external components are indicated below. To minimize temperature dependency in VCO frequency, C1 should be a capacitor with less temperature coefficient.
56 R3 55 54 R1 53 52 R2
C1
fREFCLK (MHz) R1 () R2 () R3 () C1 (F)
19.44 2.7 k 2.7 k
25.92 2.0 k 2.0 k 1.5 k 22 n
51.84 1.0 k 1.0 k
77.76 680 680
Fig. 7 External Loop Filter and Resistor for Tx-PLL (2) Clock Recovery Circuit CXB1590Q has internal clock recovery circuit based on the PLL which locks to incoming data stream. It needs external loop filter and the resistor which determines the current of the charge pump. Typical values of external components are indicated below. There are two-sets recommended values ; (1) the one is to minimization jitter generation, (2) the another is to be satisfied the template (STM-4, OC-12) in jitter transfer measurement. To minimize temperature dependency in VCO frequency, C2 should be a capacitor with less temperature coefficient.
59 R4 58 R5 57 R6 55 54
C2
R4 () R5 () R6 () C2 (F)
(1) 1.0 k 1.0 k 680 68n
(2) 620 620
Fig. 8 External Loop Filter and Resistor for Rx-PLL --15--
CXB1590Q
2. High speed ECL compatible differential input The high speed ECL compatible differential inputs in CXB1590Q is biased to VBB (VCC-1.3 V) with 18 k. High speed input applications are shown in Fig. 9.
VCC=3.3V, VEE=GND
VCC=3.3V, VEE=GND VBB (VCC-1.3V)
160 3.3V ECL output buffer
160
18k
ECL differential input buffer VCC
(a) ECL differential signal from 3.3 V ECL output buffer
VCC=GND, VEE=-4.5V
220k
0.01F
330 ECL 100K output buffer
0.01F 330 VEE
18k
ECL differential input buffer
(b) ECL differential signal from ECL 100 K output buffer
VCC
220k
0.01F 50 TRANS. LINE 0.01F 50
50
18k
ECL differential input buffer
VTT (VCC-2V)
(c) ECL differential signal form 50 transmission line
VCC
220k
0.01F
0.01F
18k
ECL differential input buffer
50 TRANS. LINE
50
VTT (VCC-2V)
(d) ECL single signal from 50 transmission line
Fig. 9 High Speed Input Application --16--
18k
18k
VCC=3.3V, VEE=GND VBB (VCC-1.3V)
18k
VCC=3.3V, VEE=GND VBB (VCC-1.3V)
18k
VCC=3.3V, VEE=GND VBB (VCC-1.3V)
CXB1590Q
3. Electrical Characteristics Measurement Circuit
II_T
Device under test TTL_IN TTL_OUT IO_T
A
VI_T
V VO_T
(a) TTL I/O DC characteristics measurement circuit
Device under test Probe Pulse generator TTL_IN TTL_OUT CL Oscilloscope
CL=10pF (including the probe capacitance)
(b) TTL I/O AC characteristics measurement circuit
II_E
Device under test ECL_IN ECL_OUT 50
A
VI_TE
V VO_E
VCCE-2V
(c) ECL I/O DC characteristics measurement circuit
VCCE-2V 50 Pulse generator 50 0.1F 0.1F Device under test ECL_IN ECL_IN ECL_OUT ECL_OUT
VCCE-2V 50 Oscilloscope 50 VCCE-2V CL2pF (input capacitance of the measurement equipment and floating capacitance)
VCCE-2V 50 Transmission line
(d) ECL I/O AC characteristics measurement circuit
--17--
CXB1590Q
Random Pattern CH1 CH8 Pulse Pattern Generator 560 C3355 560 TRIG 330
CXB1590Q TPD0 TPD7 REFCKI Pulse Pattern Generator TRIG Sampling Oscilloscope
TPCLK 0.47F TSDP TSDN TSD Monitor Serialized data 220 or TXCLK 0.47F 220 51
Pulse Pattern Generator
2^23-1 Random Pattern CXB1563Q 622bps 0.022F D Q D 0.022F 330 Q
0.47F RSDP RSDN 0.47F 330 100 220 RSDPT RSDNT
TLPF0 TLPF1
R1 C1 R2 R4 C2 R5
RLPF0 RLPF1
51
51 SD SD 220
LOSE LOSE 330 330 REXTP REXTV
R6
CXB1563Q : 2R IC Reshaped, Regenerated IC Signal-Detect signal generated
R3
(e) TX random jitter measurement circuit
Random Pattern CH1 CH8 Pulse Pattern Generator 560 C3355 560 TRIG 330 TSDP TSDN TSD Monitor RXCLK 220 0.47F 220 51 TPCLK 0.47F TRIG CXB1590Q TPD0 TPD7 REFCKI Pulse Pattern Generator
Sampling Oscilloscope
Pulse Pattern Generator
2^23-1 Random Pattern CXB1563Q 622bps 0.022F D Q D 0.022F 330 Q
0.47F RSDP RSDN 0.47F 330 100 220 RSDPT RSDNT
TLPF0 TLPF1
R1 C1 R2 R4 C2 R5
RLPF0 RLPF1
51
51 SD SD 220
LOSE LOSE 330 330 REXTP REXTV
R6
CXB1563Q : 2R IC Reshaped, Regenerated IC Signal-Detect signal generated
R3
(f) RX random jitter measurement circuit
--18--
CXB1590Q
Random Pattern CH1 CH8 Pulse Pattern Generator 560 C3355 560 TRIG 330
CXB1590Q TPD0 TPD7 REFCKI CLKOUT Jitter Analyzer 0.47F TSDP TSDN TSD Monitor TXCLK 0.47F 220 220 51 CLKIN
TPCLK
Pulse Pattern Generator
2^23-1 Random Pattern CXB1563Q 622bps 0.022F D Q D 0.022F 330 Q
0.47F RSDP RSDN 0.47F 330 100 220 RSDPT RSDNT
TLPF0 TLPF1
R1 C1 R2 R4 C2 R5
RLPF0 RLPF1
51
51 SD SD 220
LOSE LOSE 330 330 REXTP REXTV
R6
CXB1563Q : 2R IC Reshaped, Regenerated IC Signal-Detect signal generated
R3
(g) TX jitter transfer measurement circuit
Random Pattern CH1 CH8 Pulse Pattern Generator 560 C3355 560 TRIG 330 TSDP TSDN TSD Monitor RXCLK 220 0.47F 220 51 TPCLK 0.47F CLKIN CXB1590Q TPD0 TPD7 REFCKI Pulse Pattern Generator Jitter Analyzer
2^23-1 CXB1563Q Random Pattern 622bps 0.022F D Q D 0.022F 330 51 51 220 SD SD 220 CXB1563Q : 2R IC Reshaped, Regenerated IC Signal-Detect signal generated 330 Q
0.47F RSDP RSDN 0.47F 330 100 RSDPT RSDNT
TLPF0 TLPF1
R1 C1 R2 R4 C2 R5
RLPF0 RLPF1
LOSE LOSE 330 REXTP REXTV
R6
R3
(h) RX jitter transfer measurement circuit
Fig. 10 Electrical Characteristics Measurement Circuit --19--
DATAOUT
CXB1590Q
Example of Representative Characteristics
Example of TX-clock (622MHz) Rj measurement
R1=R2=1.0k R3=1.5k C1=22nF REFCKI input 51.84MHz
Rj=17.4psec x : 50psec/div y : 100mV/div
Serial Transmit Data Output Eye Pattern (622MHz Operation)
VOH_E
VOL_E
R1=R2=1.0k R3=1.5k C1=22nF REFCKI input 51.84MHz
x : 200psec/div y : 100mV/div
--20--
CXB1590Q
Example of RX-clock (622MHz) Rj measurement
R1=R2=1.0k R3=1.5k C1=22nF R4=R5=1.0k R6=680 C2=68nF REFCKI input 51.84MHz Serial Data input 2^23-1 Random pattern
Rj=19.5psec x : 50psec/div y : 100mV/div
--21--
CXB1590Q
TX-clock (622MHz) Jitter Transfer OC-12 Template 1
0
-1
Jitter Transfer (dB)
-2 Ta=27C REFCKI frequency : 51.84MHz R1=R2=1.0k R3=1.5k C1=22nF
-3
-4
-5
-6
-7
10
100
1k
10k
100k
1M
10M
REFCKI modulation frequency (Hz)
RX-clock (622MHz) Jitter Transfer OC-12 Template 5
0
-5
Jitter Transfer (dB)
-10 Ta=27C REFCKI frequency : 51.84MHz R1=R2=1.0k R3=1.5k C1=22nF R4=R5=620 R6=680 C2=68nF Serial Data input : 2^23-1 Random pattern
-15
-20
-25
-30
-35
10
100
1k
10k
100k
1M
10M
Serial-Data modulation frequency (Hz)
--22--
CXB1590Q
RX-clock (622MHz) Jitter Transfer OC-12 Template 5
0
-5
Jitter Transfer (dB)
-10
-15
-20
Ta=27C REFCKI frequency : 51.84MHz R1=R2=1.0k R3=1.5k C1=22nF R4=R5=1.0k R6=680 C2=68nF Serial Data input : 2^23-1 Random pattern
-25
-30
10
100
1k
10k
100k
1M
10M
Serial-Data modulation frequency (Hz)
--23--
CXB1590Q
Package Outline
Unit : mm
80PIN QFP (PLASTIC)
+ 0.35 1.5 - 0.15 + 0.1 0.127 - 0.05 0.1 41 40
16.0 0.4 + 0.4 14.0 - 0.1 60 61
80 1 0.65 20 0.24
21
+ 0.15 0.1 - 0.1
M 0 to 10
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L03 QFP080-P-1414 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.6g
--24--
This data sheet has been made from recycled paper to help protect the environment.
0.5 0.2
+ 0.15 0.3 - 0.1
(15.0)

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