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| PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I 6:1, SINGLE-ENDED MULTIPLEXER FEATURES * 6:1 single-ended multiplexer * Q0 nominal output impedance: 7 (VDDO =3 .3V) * Maximum output frequency: 250MHz * Propagation delay: 2.6ns (typical) * Input skew: 35ps (typical) * Part-to-part skew: TBD * Additive phase jitter, RMS (12KHz - 20MHz): 0.16ps (typical) * Operating supply modes: VDD/VDDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V * -40C to 85C ambient operating temperature GENERAL DESCRIPTION The ICS83056I is a low skew, 6:1, Single-ended Multiplexer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS83056I has six selectable singleended clock inputs and one single-ended clock output. The output has a VDDO pin which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug. The device operates up to 250MHz and is packaged in a 16 TSSOP. ICS BLOCK DIAGRAM CLK0 CLK1 CLK2 Q0 CLK3 CLK4 CLK5 SEL2 SEL1 SEL0 OE PIN ASSIGNMENT Q0 nc OE nc GND CLK5 SEL2 CLK4 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDDO CLK0 SEL0 CLK1 VDD CLK2 SEL1 CLK3 ICS83056I 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 83056AGI www.icst.com/products/hiperclocks.html REV. A NOVEMBER 9, 2004 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I 6:1, SINGLE-ENDED MULTIPLEXER TABLE 1. PIN DESCRIPTIONS Number 1 2, 4 6, 8, 9, 11, 13, 15 3 5 7, 10, 14 12 16 Name Q0 nc CLK5, CLK4, CLK3, CLK2, CLK1, CLK0 OE GND SEL2, SEL1, S E L0 VDD VDDO Type Output Unused Input Input Power Input Power Power Description Single-ended clock output. LVCMOS/LVTTL interface levels. No connect. Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. Output enable. When LOW, outputs are in HIGH impedance state. When HIGH, outputs are active. LVCMOS / LVTTL interface levels. Power supply ground. Clock select input. See Control Input Function Table. Pulldown LVCMOS / LVTTL interface levels. Core supply pin. Pullup Output supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP RPULLDOWN C PD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance Test Conditions Minimum Typical 4 51 51 11 5 7 12 Maximum Units pF K K pF TABLE 3. CONTROL INPUT FUNCTION TABLE SEL2 0 0 0 0 1 1 Control Inputs SEL1 0 0 1 1 0 0 SEL0 0 1 0 1 0 1 Input Selected to Q0 CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 83056AGI www.icst.com/products/hiperclocks.html 2 REV. A NOVEMBER 9, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I 6:1, SINGLE-ENDED MULTIPLEXER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 89C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40C TO 85C Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 31 3 Maximum 3.465 3.465 Units V V mA mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 31 3 Maximum 3.465 2.625 Units V V mA mA TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 1.6 Typical 3.3 1.8 31 3 Maximum 3.465 2.0 Units V V mA mA TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = -40C TO 85C Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 28 3 Maximum 2.625 2.625 Units V V mA mA TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C Symbol VDD VDDO IDD IDDO 83056AGI Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 2.375 1.6 Typical 2.5 1.8 28 3 Maximum 2.625 2.0 Units V V mA mA www.icst.com/products/hiperclocks.html REV. A NOVEMBER 9, 2004 3 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I 6:1, SINGLE-ENDED MULTIPLEXER TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40C TO 85C Symbol Parameter CLK0:CLK5 VIH Input High Voltage OE, SEL0:SEL2 CLK0:CLK5 VIL Input Low Voltage OE, SEL0:SEL2 Input High Current CLK0:CLK5, SEL0:SEL2 OE CLK0:CLK5, SEL0:SEL2 OE Test Conditions VDD = 3.3V 5% VDD = 2.5V 5% VDD = 3.3V 5% VDD = 2.5V 5% VDD = 3.3V 5% VDD = 2.5V 5% VDD = 3.3V 5% VDD = 2.5V 5% VDD = 3.3V or 2.5V 5% VDD = 3.3V or 2.5V 5% VDD = 3.3V or 2.5V 5% VDD = 3.3V or 2.5V 5% VDDO = 3.3V 5%; NOTE 1 VOH Output HighVoltage VDDO = 2.5V 5%; NOTE 1 VDDO = 1.8V 0.2V; NOTE 1 VDDO = 3.3V 5%; NOTE 1 VOL Output Low Voltage VDDO = 2.5V 5%; NOTE 1 VDDO = 1.8V 0.2V; NOTE 1 -5 -150 2.6 1.8 VDD - 0.3 0.5 0.45 0.35 Minimum 2 1.7 2 1.7 -0.3 -0.3 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 1.3 0.7 1.3 0.7 150 5 Units V V V V V V V V A A A A V V V V V V IIH IIL Input Low Current NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams. TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = -40C TO 85C Symbol Parameter fMAX tpLH tpHL Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 5 Par t-to-Par t Skew; NOTE 2, 5 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 4 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 3 Output Disable Time; NOTE 3 Test Conditions Minimum Typical Maximum 250 2.6 2.9 35 TBD Integration Range: 12KHz - 20MHz 20% to 80% 0.16 250 50 5 5 Units MHz ns ns ps ps ps ps % ns ns dB t sk(i) t sk(pp) tjit tR / tF odc t EN tDIS @ 100MHz 45 MUXISOL MUX Isolation NOTE 1A: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Driving only one input clock. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 83056AGI www.icst.com/products/hiperclocks.html 4 REV. A NOVEMBER 9, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I 6:1, SINGLE-ENDED MULTIPLEXER TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = -40C TO 85C Symbol Parameter fMAX tpLH tpHL Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 5 Par t-to-Par t Skew; NOTE 2, 5 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 4 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 3 Output Disable Time; NOTE 3 Test Conditions Minimum Typical Maximum 250 2.8 2.9 35 TBD Integration Range: 12KHz - 20MHz 20% to 80% 0.04 275 50 5 5 Units MHz ns ns ps ps ps ps % ns ns dB t sk(i) t sk(pp) tjit tR / tF odc tEN tDIS @ 100MHz 45 MUXISOL MUX Isolation NOTE 1A: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Driving only one input clock. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = -40C TO 85C Symbol Parameter fMAX tpLH tpHL Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 5 Par t-to-Par t Skew; NOTE 2, 5 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 4 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 3 Output Disable Time; NOTE 3 Test Conditions Minimum Typical Maximum 250 3.2 3.15 60 TBD Integration Range: 12KHz - 20MHz 20% to 80% 0.07 310 50 5 5 Units MHz ns ns ps ps ps ps % ns ns dB t sk(i) t sk(pp) tjit tR / tF odc t EN tDIS MUXISOL MUX Isolation @ 100MHz 45 NOTE 1A: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Driving only one input clock. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 83056AGI www.icst.com/products/hiperclocks.html REV. A NOVEMBER 9, 2004 5 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I 6:1, SINGLE-ENDED MULTIPLEXER TABLE 5D. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5%, TA = -40C TO 85C Symbol Parameter fMAX tpLH tpHL Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 5 Par t-to-Par t Skew; NOTE 2, 5 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 4 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 3 Output Disable Time; NOTE 3 Test Conditions Minimum Typical Maximum 250 2.85 3.10 50 TBD Integration Range: 12KHz - 20MHz 20% to 80% 0.11 290 50 5 5 Units MHz ns ns ps ps ps ps % ns ns dB t sk(i) t sk(pp) tjit tR / tF odc t EN tDIS @ 100MHz 45 MUXISOL MUX Isolation NOTE 1A: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Driving only one input clock. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5E. AC CHARACTERISTICS, VDD = 2.5V 5%, VDDO = 1.8V -0.2V, TA = -40C TO 85C Symbol Parameter fMAX tpLH tpHL Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 5 Par t-to-Par t Skew; NOTE 2, 5 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 4 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 3 Output Disable Time; NOTE 3 Test Conditions Minimum Typical Maximum 250 3.15 3.25 70 TBD Integration Range: 12KHz - 20MHz 20% to 80% 0.06 330 50 5 5 Units MHz ns ns ps ps ps ps % ns ns dB t sk(i) t sk(pp) tjit tR / tF odc t EN tDIS @ 100MHz 45 MUXISOL MUX Isolation NOTE 1A: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Driving only one input clock. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 83056AGI www.icst.com/products/hiperclocks.html 6 REV. A NOVEMBER 9, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I 6:1, SINGLE-ENDED MULTIPLEXER ADDITIVE PHASE JITTER The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter (Random) at 155.52MHz (12KHz - 20MHz) = 0.16ps typical SSB PHASE NOISE dBc/HZ 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 83056AGI www.icst.com/products/hiperclocks.html REV. A NOVEMBER 9, 2004 7 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I 6:1, SINGLE-ENDED MULTIPLEXER PARAMETER MEASUREMENT INFORMATION 1.65V5% 1.25V5% VDD, VDDO SCOPE Qx VDD, VDDO SCOPE Qx LVCMOS GND LVCMOS GND -1.65V5% -1.25V5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.05V5% 1.25V5% 2.40.065V 0.9V0.1V V DD VDDO SCOPE Qx V DD VDDO SCOPE Qx LVCMOS GND LVCMOS GND -1.25V5% -0.9V0.1V 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 1.6V0.025V 0.9V0.1V 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT VDD VDDO SCOPE Qx Part 1 Qx V DDO 2 LVCMOS GND Part 2 Qy V DDO 2 tsk(pp) -0.9V0.1V 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 83056AGI PART-TO-PART SKEW REV. A NOVEMBER 9, 2004 www.icst.com/products/hiperclocks.html 8 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I 6:1, SINGLE-ENDED MULTIPLEXER VDD 80% 20% tR 80% 20% tF CLK0:CLK5 2 VDDO Q0 2 tpLH Clock Outputs PROPAGATION DELAY OUTPUT RISE/FALL TIME CLKx V DDO Q0 tPD1 Q0 Pulse Width t 2 PERIOD odc = t PW t PERIOD CLKy Q0 tPD2 INPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 83056AGI www.icst.com/products/hiperclocks.html REV. A NOVEMBER 9, 2004 9 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I 6:1, SINGLE-ENDED MULTIPLEXER RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W 200 118.2C/W 81.8C/W 500 106.8C/W 78.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS83056I is: 874 83056AGI www.icst.com/products/hiperclocks.html 10 REV. A NOVEMBER 9, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I 6:1, SINGLE-ENDED MULTIPLEXER PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum Reference Document: JEDEC Publication 95, MO-153 83056AGI www.icst.com/products/hiperclocks.html REV. A NOVEMBER 9, 2004 11 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I 6:1, SINGLE-ENDED MULTIPLEXER TABLE 8. ORDERING INFORMATION Part/Order Number ICS83056AGI ICS83056AGIT Marking 83056AGI 83056AGI Package 16 Lead TSSOP 16 Lead TSSOP on Tape and Reel Count 94 per tube 2500 Temperature -40C to 85C -40C to 85C The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83056AGI www.icst.com/products/hiperclocks.html 12 REV. A NOVEMBER 9, 2004 |
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