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Integrated Circuit Systems, Inc.
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
FEATURES
* 4 LVCMOS/LVTTL outputs * Selectable differential or LVCMOS/LVTTL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * LVCMOS_CLK supports the following input types: LVCMOS, LVTTL * Maximum output frequency: 350MHz * Output skew: 40ps (maximum) * Part-to-part skew: 700ps (maximum) * Additive phase jitter, RMS: 0.04ps (typical) * 3.3V core, 3.3V, 2.5V or 1.8V output operating supply * -40C to 85C ambient operating temperature * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS8305I is a low skew, 1-to-4, Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a HiPerClockSTM member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8305I has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state.
ICS
Guaranteed output and part-to-part skew characteristics make the ICS8305I ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_EN D Q LE LVCMOS_CLK CLK nCLK CLK_SEL Q2
PIN ASSIGNMENT
GND OE VDD CLK_EN CLK nCLK CLK_SEL LVCMOS_CLK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Q0 VDDO Q1 GND Q2 VDDO Q3 GND
00 1
1 Q0
Q1
ICS8305I
16-Lead TSSOP 4.4mm x 3.0mm x 0.92mm package body G Package Top View
Q3
OE
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Integrated Circuit Systems, Inc.
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Type Power Input Power Input Input Input Input Input Output Power Description
TABLE 1. PIN DESCRIPTIONS
Number 1, 9, 13 2 3 4 5 6 7 8 10, 12, 14, 16 11, 15 Name GND OE VDD CLK_EN CLK nCLK CLK_SEL LVCMOS_CLK Q3, Q2, Q1, Q0 VDDO Power supply ground. Output enable. When LOW, outputs are in HIGH impedance state. Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. Core supply pin. Synchronizing clock enable. When LOW, the output clocks are Pullup disabled. When HIGH, output clocks are enabled. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Clock select input. When HIGH, selects CLK, nCLK inputs. Pullup When LOW, selects LVCMOS_CLK input. LVCMOS / LVTTL interface levels. Pulldown LVCMOS / LVTTL clock input. Clock outputs. LVCMOS / LVTTL interface levels. Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance Test Conditions Minimum Typical 4 51 51 11 5 7 12 Maximum Units pF k k pF
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REV. B MAY 19, 2005
Integrated Circuit Systems, Inc.
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Inputs CLK_SEL 0 1 0 1 Outputs Q0:Q3 Disabled; LOW Disabled; LOW Enabled Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
OE 1 1 1 1 CLK_EN 0 0 1 1 Selected Source LVCMOS_CLK CLK, nCLK LVCMOS_CLK CLK, nCLK
0 X X HiZ NOTE: After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
Disabled
nCLK CLK, LVCMOS_CLK CLK_EN
Enabled
Q0:Q3
FIGURE 1. CLK_EN TIMING DIAGRAM
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Integrated Circuit Systems, Inc.
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 89C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 2.375 1.65 Typical 3.3 3.3 2.5 1.8 Maximum 3.465 3.465 2.625 1.95 21 5 Units V V V V mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol Parameter VIH VIL IIH IIL Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_EN, CLK_SEL, OE LVCMOS_CLK CLK_EN, CLK_SEL, OE LVCMOS_CLK CLK_EN, CLK_SEL, OE LVCMOS_CLK CLK_EN, CLK_SEL, OE LVCMOS_CLK VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDDO = 3.3V 5% VOH Output High Voltage; NOTE 1 VDDO = 2.5V 5% VDDO = 1.8V 0.15V VDDO = 3.3V 5% VOL IOZL IOZH Output Low Voltage; NOTE 1 Output Tristate Current Low Output Tristate Current High VDDO = 2.5V 5% VDDO = 1.8V 0.15V -5 5 -150 -5 2.6 1. 8 VDDO - 0.3 0.5 0.5 0.4 Test Conditions Minimum Typical 2 2 -0.3 -0.3 Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 5 150 Units V V V V A A A A V V V V V V A A
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
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Integrated Circuit Systems, Inc.
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Test Conditions nCLK CLK nCLK CLK VIN = VDD = 3.465V VIN = VDD = 3.465V VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V -150 -5 1.3 VDD - 0.85 Minimum Typical Maximum 150 150 Units A A A A V V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; GND + 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = -40C TO 85C
Symbol Parameter fMAX Output Frequency LVCMOS_CLK; Propagation Delay, NOTE 1A Low to High CLK, nCLK; NOTE 1B Output Skew; NOTE 2, 6 Par t-to-Par t Skew; NOTE 3, 6 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 4 Test Conditions Ref = CLK/nCLK Ref = LVCMOS_CLK 1.75 Measured on the Rising Edge Minimum Typical Maximum 350 300 2.8 40 700 0.04 20% to 80% 200MHz > 200MHz 100 45 42 700 55 58 5 5 Units MHz MHz ns ps ps ps ps % % ns ns
tpLH
t sk(o) t sk(pp) tjit
tR / tF o dc tEN
Output Disable Time; NOTE 4 tDIS NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: Driving only one input clock. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
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Integrated Circuit Systems, Inc.
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = -40C TO 85C
Symbol Parameter fMAX Output Frequency LVCMOS_CLK; Propagation Delay, NOTE 1A Low to High CLK, nCLK; NOTE 1B Output Skew; NOTE 2, 6 Par t-to-Par t Skew; NOTE 3, 6 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 4 Test Conditions Ref = CLK/nCLK Ref = LVCMOS_CLK 1.75 Measured on the Rising Edge Minimum Typical Maximum 350 300 2.95 40 800 0.04 20% to 80% 166MHz f > 166MHz 100 45 42 700 55 58 5 Units MHz MHz ns ps ps ps ps % % ns
tpLH
t sk(o) t sk(pp) t jit
tR / tF o dc tEN
Output Disable Time; NOTE 4 5 ns tDIS NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: Driving only one input clock. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V -0.15V, TA = -40C TO 85C
Symbol Parameter fMAX Output Frequency LVCMOS_CLK; Propagation Delay, NOTE 1A Low to High CLK, nCLK; NOTE 1B Output Skew; NOTE 2, 6 Par t-to-Par t Skew; NOTE 3, 6 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 4 Output Disable Time; NOTE 4 Test Conditions Ref = CLK/nCLK Ref = LVCMOS_CLK 1.75 Measured on the Rising Edge Minimum Typical Maximum 350 300 3.7 45 900 0.04 20% to 80% 166MHz f > 166MHz 100 45 42 700 55 58 5 5 Units MHz MHz ns ps ps ps ps % % ns ns
tpLH
t sk(o) t sk(pp) tjit
tR / tF o dc tEN tDIS
For notes, see Table 5B.
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ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter at 155.52MHz
= 0.04ps typical
SSB PHASE NOISE dBc/HZ
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
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Integrated Circuit Systems, Inc.
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5%
2.05V5%
1.25V5%
VDD, VDDO
SCOPE
Qx
VDD VDDO
Qx
SCOPE
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.4V0.09V 0.9V0.075V VDD
VDD VDDO
Qx
SCOPE
nCLK
V
CLK
LVCMOS
PP
Cross Points
V
CMR
GND
GND -0.9V0.075V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
V
Qx
PART 1
V
DDO
DDO
2
Qx
2
V
Qy
PART 2
V
DDO
DDO
2 tsk(o)
Qy
2 tsk(pp)
OUTPUT SKEW
8305AGI
PART-TO-PART SKEW
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ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
LVCMOS_CLK
VDD 2
80%
nCLK CLK
80% 20%
Clock Outputs
20% tR tF
Q0:Q3
VDDO 2 t
PD
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
V
DDO
Q0:Q3
2
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
8305AGI
BY
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ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
is driven by an LVCMOS driver. CLK_EN is set at logic low to select LVCMOS_CLK input.
SCHEMATIC EXAMPLE
This application note provides general design guide using ICS8305I LVCMOS buffer. Figure 4 shows a schematic example of the ICS8305I LVCMOS clock buffer. In this example, the input
VDD Zo = 50 VDD R1 43 R4 1K VDD R5 1K U1 1 2 3 4 5 6 7 8 R6 1K GND OE VDD CLK_EN CLK nCLK CLK_SEL LVCMOS_CLK ICS8305 (U1,3) VDD C1 C2 0.1u C3 0.1u (U1,11) (U1,15) LVCMOS Receiv er Q0 VDDO Q1 GND Q2 VDDO Q3 GND 16 15 14 13 12 11 10 9 LVCMOS Receiv er Zo = 50 R2 43
Zo = 50 Ro ~ 7 Ohm
R3 3,.3V LVCMOS
43
VDD=3.3V
0.1u
FIGURE 4. EXAMPLE ICS8305I LVCMOS CLOCK OUTPUT BUFFER SCHEMATIC
RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8305I is: 459
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ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
FOR
PACKAGE OUTLINE - G SUFFIX
16 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
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LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS8305AGI ICS8305AGIT ICS8305AGILF ICS8305AGILFT NOTE: Par ts that are ordered Marking Package Shipping Packaging Temperature 8305AGI 16 Lead TSSOP tube -40C to 85C 8305AGI 16 Lead TSSOP 2500 tape & reel -40C to 85C 8305AGIL 16 Lead "Lead-Free" TSSOP tube -40C to 85C 8305AGIL 16 Lead "Lead-Free" TSSOP 2500 tape & reel -40C to 85C with an"LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8305AGI
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ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
REVISION HISTORY SHEET
Rev A B B B
Table T8 T5A - T5C T1 T8
Page 14 5&6 7 2 14
Description of Change Ordering Information table - corrected Par t/Order Number typo from ICS88305AGIT to ICS8305AGIT. AC Characteristics Tables - changed tjit from 0.05ps typical to 0.04ps typical. Updated Additive Phase Jitter plot. Pin Description Table - corrected CLK_EN description. Ordering Information Table - added Lead-Free par t number
Date 1/20/04 2/26/04 12/7/04 5/19/05
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