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M14256 M14128
Memory Card IC 256/128 Kbit Serial IC Bus EEPROM
PRELIMINARY DATA
s s
Compatible with I2C Extended Addressing Two Wire I2C Serial Interface Supports 400 kHz Protocol Single Supply Voltage (2.5 V to 5.5 V) Hardware Write Control BYTE and PAGE WRITE (up to 64 Bytes) BYTE, RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behaviour 100,000 Erase/Write Cycles (minimum) 40 Year Data Retention (minimum) 5 ms Programming Time (typical)
Micromodule (D22)
s s s s
s s s s s s
DESCRIPTION Each device is an electrically erasable programmable memory (EEPROM) fabricated with STMicroelectronics's High Endurance, Double Polysilicon, CMOS technology. This guarantees an endurance typically well above 100,000 Erase/ Write cycles, with a data retention of 40 years. The memory operates with a power supply as low as 2.5 V. The M14256 and M14128 are available in micromodule form only. For availability of the M14256 or
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
SDA Serial Data/Address Input/ Output Serial Clock Write Control Supply Voltage Ground
SCL WC M14xxx
SDA
SCL WC VCC GND
GND
AI02217
October 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M14256, M14128
Figure 2. D22 Contact Connections When writing data to the memory, the memory device inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a NoACK for READ. Power On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is held active until the VCC voltage has reached the POR threshold value, and all operations are disabled - the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid V CC must be applied before applying any logic signal. SIGNAL DESCRIPTION Serial Clock (SCL) The SCL input pin is used to synchronize all data in and out of the memory. A pull up resistor can be connected from the SCL line to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). Serial Data (SDA) The SDA pin is bi-directional, and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from the SDA bus to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated).
VCC WC
GND
SCL
SDA
AI02204
M14128 in wafer form, please contact your ST sales office. Each memory device is compatible with the I2C extended memory standard. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The memory device carries a built-in 7-bit unique Device Type Identifier code (1010000) in accordance with the I 2C bus definition. Only one memory device can be attached to each I2C bus. The memory device behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition, generated by the bus master. The START condition is followed by the Device Select Code which is composed of a stream of 7 bits (1010000), plus one read/write bit (R/W) and is terminated by an acknowledge bit.
Table 2. Absolute Maximum Ratings 1
Symbol TA TSTG VIO VCC VESD Electrostatic Discharge Voltage (Machine model) 3 400 V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100 pF, 1500 ) 3. EIAJ IC-121 (Condition C) (200 pF, 0 )
Parameter Ambient Operating Temperature Storage Temperature Input or Output range Supply Voltage Electrostatic Discharge Voltage (Human Body model) 2
Value 0 to 70 -40 to 120 -0.6 to 6.5 -0.3 to 6.5 4000
Unit C C V V V
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M14256, M14128
Write Control (WC) The hardware Write Control contact (WC) is useful for protecting the entire contents of the memory from inadvertent erase/write. The Write Control signal is used to enable (WC=V IL) or disable (WC=VIH) write instructions to the entire memory area. When unconnected, the WC input is internally read as VIL and write operations are allowed. When WC=1, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged. Please see the Application Note AN404 for a more detailed description of the Write Control feature. DEVICE OPERATION The memory device supports the XI2C (Extended I2C) protocol, as summarized in Figure 4. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the master, and the other as the slave. A data transfer can only be initiated by the master, which will also provide the serial clock for synchronization. The memory device is always a slave device in all communication. Start Condition START is identified by a high to low transition of the SDA line while the clock, SCL, is stable in the high state. A START condition must precede any data transfer command. The memory device continuously monitors (except during a programming cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given. Stop Condition STOP is identified by a low to high transition of the SDA line while the clock, SCL, is stable in the high state. A STOP condition terminates communication between the memory device and the bus master. A STOP condition at the end of a Read command, after (and only after) a NoACK, forces the memory device into its standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK) An acknowledge signal is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 data bits. Data Input During data input, the memory device samples the SDA bus signal on the rising edge of the clock, SCL. For correct device operation, the SDA signal must be stable during the clock low-to-high transition, and the data must change only when the SCL line is low. Memory Addressing To start communication between the bus master and the slave memory, the master must initiate a START condition. Following this, the master sends 8 bits to the SDA bus line (with the most significant bit first). These bits represent the Device Select Code (7 bits) and a RW bit. The seven most significant bits of the Device Select Code are the Device Type Identifier, according to the I2C bus definition. For the memory device, the seven bits are fixed at 1010000b (A0h), as shown in Table 5. The 8th bit is the read or write bit (RW). This bit is set to `1' for read and `0' for write operations. If a match occurs on the Device Select Code, the cor-
Figure 3. Maximum R L Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC 20 Maximum RP value (k) 16 RL 12 8 4 0 10 100 CBUS (pF)
AI01665
RL
SDA MASTER fc = 100kHz fc = 400kHz SCL CBUS
CBUS 1000
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M14256, M14128
Figure 4. I2C Bus Protocol
SCL
SDA START CONDITION SDA INPUT SDA CHANGE STOP CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP CONDITION
AI00792
responding memory gives an acknowledgment on the SDA bus during the 9th bit time. If the memory does not match the Device Select code, it will deselect itself from the bus, and go into stand-by mode. Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 3) is sent first, followed by the Least significant Byte (Table 4). Bits b15 to b0 form the address of the byte in memory. Bit b15 is treated as a Don't Care bit on the M14256 memory. Bits b15 and b14 are treated as Don't Care bits on the M14128 memory. Table 5. Device Select Code 1
Device Code b7 Device Select 1 b6 0 b5 1
Table 3. Most Significant Byte
b15 b14 b13 b12 b11 b10 b9 b8
Note: 1. b15 is Don't Care on the M14256 series. b15 and b14 are Don't Care on the M14128 series.
Table 4. Least Significant Byte
b7 b6 b5 b4 b3 b2 b1 b0
Chip Enable b4 0 b3 0 b2 0 b1 0
RW b0 RW
Note: 1. The most significant bit, b7, is sent first.
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M14256, M14128
Write Operations Following a START condition the master sends a Device Select code with the RW bit set to '0', as shown in Table 6. The memory acknowledges it and waits for two bytes of address, which provides access to the memory area. After receipt of each byte address, the memory again responds with an acknowledge and waits for the data byte. Writing in the memory may be inhibited if the input pin WC is taken high. Any write command with WC=1 (during a period of time from the START condition until the end of the two bytes address) will not modify the memory content and will NOT be acknowledged on data bytes, as shown in Figure 5. Byte Write In the Byte Write mode, after the Device Select code and the address, the master sends one data byte. If the addressed location is write protected by the WC pin, the memory replies with a NoACK, and the location is not modified. If, instead, the WC Figure 5. Write Mode Sequences with WC=1
WC ACK BYTE WRITE START DEV SEL R/W ACK ACK NO ACK DATA IN STOP ACK ACK NO ACK DATA IN 1 DATA IN 2 BYTE ADDR R/W BYTE ADDR NO ACK STOP
pin has been held at 0, as shown in Figure 6, the memory replies with an ACK. The master terminates the transfer by generating a STOP condition. Page Write The Page Write mode allows up to 64 bytes to be written in a single write cycle, provided that they are all located in the same 'row' in the memory: that is the most significant memory address bits (b14-b6 for the M14256 and b13-b6 for the M14128) are the same. The master sends from one up to 64 bytes of data, each of which is acknowledged by the memory if the WC pin is low. If the WC pin is high, each data byte is followed by a NoACK and the location is not modified. After each byte is transferred, the internal byte address counter (the six least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid address counter 'roll-over' which could result in data being overwritten. Note that, for any
BYTE ADDR
BYTE ADDR
WC ACK PAGE WRITE START WC (cont'd) NO ACK PAGE WRITE (cont'd) DEV SEL
DATA IN N
AI01120B
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M14256, M14128
Table 6. Operating Modes
Mode Current Address Read Random Address Read `1' Sequential Read Byte Write Page Write
Note: 1. X = VIH or VIL.
RW bit `1' `0'
WC 1 X X X X VIL VIL
Bytes 1
Initial Sequence START, Device Select, RW = `1' START, Device Select, RW = `0', Address
1 1 1 64
reSTART, Device Select, RW = `1' Similar to Current or Random Mode START, Device Select, RW = `0' START, Device Select, RW = `0'
`1' `0' `0'
Figure 6. Write Mode Sequences with WC=0
WC ACK BYTE WRITE START DEV SEL R/W ACK ACK DATA IN STOP ACK ACK DATA IN 1 ACK DATA IN 2 BYTE ADDR R/W BYTE ADDR ACK DATA IN N STOP ACK
BYTE ADDR
BYTE ADDR
WC ACK PAGE WRITE START WC (cont'd) ACK PAGE WRITE (cont'd) DEV SEL
AI01106B
byte or page write mode, the generation by the master of the STOP condition starts the internal memory program cycle. This STOP condition triggers an internal memory program cycle only if the STOP condition is internally decoded immediately
after the ACK bit; any STOP condition decoded out of this "10th bit" time slot will not trigger the internal programming cycle. All inputs are disabled until the completion of this cycle and the Memory will not respond to any request.
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M14256, M14128
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle in Progress
START Condition DEVICE SELECT with RW = 0
NO First byte of instruction with RW = 0 already decoded by M14xxx
ACK Returned YES
NO
Next Operation is Addressing the Memory
YES
ReSTART
Send Byte Address
STOP
Proceed WRITE Operation
Proceed Random Address READ Operation
AI02165
Minimizing System Delays by Polling On ACK During the internal write cycle, the memory disconnects itself from the bus, and copies the data from its internal latches to the memory cells. The maximum write time (t w) is indicated in Table 7, but the typical time is shorter. To make use of this, an ACK polling sequence can be used by the master. The sequence, as shown in Figure 7, is as follows: - Initial condition: a Write is in progress. - Step 1: the master issues a START condition followed by a device select byte (first byte of the new instruction). - Step 2: if the memory is busy with the internal write cycle, no ACK will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it responds with an ACK, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction having been sent during Step 1).
Read Operations Read operations are independent of the state of the WC pin. On delivery, the memory content is set at all "1's" (FFh). Current Address Read The memory has an internal address counter. Each time a byte is read, this counter is incremented. For the Current Address Read mode, following a START condition, the master sends a device select with the RW bit set to `1'. The memory acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The master must not acknowledge the byte output, and terminates the transfer with a STOP condition, as shown in Figure 8. Random Address Read A dummy write is performed to load the address into the address counter, as shown in Figure 8. This is followed by another START condition from the master and the device select is repeated with
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M14256, M14128
Figure 8. Read Mode Sequences
ACK CURRENT ADDRESS READ START DEV SEL R/W NO ACK DATA OUT STOP ACK
ACK RANDOM ADDRESS READ START DEV SEL * R/W
ACK DEV SEL * START
ACK
NO ACK DATA OUT STOP ACK
BYTE ADDR
BYTE ADDR
R/W
ACK SEQUENTIAL CURRENT READ START DEV SEL R/W
ACK
ACK
NO ACK
DATA OUT 1
DATA OUT N STOP
ACK SEQUENTIAL RANDOM READ START DEV SEL *
ACK
ACK DEV SEL * START
ACK
BYTE ADDR R/W
BYTE ADDR
DATA OUT 1 R/W
ACK
NO ACK
DATA OUT N STOP
AI01105C
Note: 1. The seven most significant bits of the Device Select bytes of a Random Read (in the 1 and 4 bytes) must be identical.
st
th
the RW bit set to `1'. The memory acknowledges this, and outputs the byte addressed. The master must not acknowledge the byte output, and terminates the transfer with a STOP condition. Sequential Read This mode can be initiated with either a Current Address Read or a Random Address Read. However, in this case the master does acknowledge the data byte output, and the memory continues to output the next byte in sequence. To terminate the stream of bytes, the master must not acknowledge the last byte output, and must generate a STOP condition. The output data comes from consecu-
tive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter will `roll-over' and the memory will continue to output data from the start of the memory block. Acknowledge in Read Mode In all read modes the memory waits for an acknowledgment during the 9th bit time. If the master does not pull the SDA line low during this time, the memory terminates the data transfer and switches to its standby state.
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M14256, M14128
Table 7. AC Characteristics (TA = 0 to 70 C; VCC = 2.5 V to 5.5 V)
Symbol Alt. Parameter Fast I2C 400 kHz Min tCH1CH2
2
I2C 100 kHz Min Max 1000 300 20 20 4700 4000 4000 0 4.7 250 4000 4.7 1000 300
Unit
Max 300 300
tR tF tR tF tSU:STA tHIGH tHD:STA tHD:DAT tLOW tSU:DAT tSU:STO tBUF tAA tDH fSCL tWR
Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) Clock Low to Input Transition Clock Pulse Width Low Input Transition to Clock Transition Clock High to Input High (STOP) Input High to Input Low (Bus Free) Clock Low to Data Out Valid Data Out Hold Time After Clock Low Clock Frequency Write Time 200 20 20 600 600 600 0 1.3 100 600 1.3
ns ns ns ns ns ns ns s s ns ns s
tCL1CL2 2 tDH1DH2
2
300 300
tDL1DL2 2 tCHDX 1 tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV tCLQX fC tW
1000 200 400 10
3500
ns ns
100 10
kHz ms
Note: 1. For a reSTART condition, or following a write cycle. 2. Sampled only, not 100% tested
Table 8. DC Characteristics (TA = 0 to 70 C; VCC = 2.5 V to 5.5 V)
Symbol ILI ILO ICC Parameter Input Leakage Current (SCL, SDA) Output Leakage Current Supply Current VCC =2.5V, fc=400kHz (rise/fall time < 30ns) Supply Current (Stand-by) Input Low Voltage (SCL, SDA) Input High Voltage (SCL, SDA) Input Low Voltage (WC) Input High Voltage (WC) Output Low Voltage IOL = 3 mA, VCC = 5 V IOL = 2.1 mA, VCC = 2.5 V VIN = VSS or VCC , VCC = 5 V VIN = VSS or VCC , VCC = 2.5 V - 0.3 0.7 VCC - 0.3 VCC - 0.5 1 20 2 0.3 VCC VCC + 1 0.5 VCC + 1 0.4 0.4 mA A A V V V V V V Test Condition 0 V VIN VCC 0 V VOUT VCC, SDA in Hi-Z VCC=5V, fc=400kHz (rise/fall time < 30ns) Min. Max. 2 2 2 Unit A A mA
ICC1 VIL VIH VIL VIH VOL
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M14256, M14128
Figure 9. AC Waveforms
tCHCL SCL tDLCL SDA IN tCHDX START CONDITION tCLDX SDA INPUT SDA CHANGE STOP & BUS FREE tDHDL tDXCX tCHDH tCLCH
SCL tCLQV SDA OUT DATA VALID tCLQX
DATA OUTPUT
SCL tW SDA IN tCHDH STOP CONDITION WRITE CYCLE tCHDX START CONDITION
AI00795B
Table 9. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages 50 ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC
Figure 10. AC Testing Input Output Waveforms
0.8VCC 0.7VCC 0.3VCC
AI00825
0.2VCC
Table 10. Input Parameters1 (TA = 25 C, f = 400 kHz)
Symbol CIN CIN tNS Parameter Input Capacitance (SDA) Input Capacitance (other pins) Low Pass Filter Input Time Constant (SCL & SDA Inputs) 100 Test Condition Min. Max. 8 6 400 Unit pF pF ns
Note: 1. Sampled only, not 100% tested.
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M14256, M14128
Table 11. Ordering Information Scheme
Example: M14256 W D22
Delivery Form D22 Module on Super 35 mm film
Memory Capacity 256 128 256 Kbit 128 Kbit W Operating Voltage 2.5 V to 5.5 V
ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all `1's (FFh). The notation used for the device number is as shown in Table 11. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M14256, M14128
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) 1999 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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