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January 1997
ML6680 Token Ring Copper-to-Fiber Converter
GENERAL DESCRIPTION
The ML6680 is a single-chip conversion between Token Ring ISO/IEC8802-5 copper-based media and Token Ring ISO/IEC8802-5 fiber-based media. The ML6680 fiber-optic interface contains a data quantizer, circuitry for fiber optic key signal generation and recognition, pin-selectable signal switching, and current driven transmitter outputs. The ML6680 copper interface consists of a twisted pair line equalizer, receive squelch circuit, pin selectable phantom wire fault detection and signal switching, and a transmit driver. This section supports the ISO/IEC8802-5 standard requirements. The ML6680 provides an optional PECL compatible interface. The ML6680 may be configured to one of four modes: 1. 2. 3. 4. Standard Media Converter Concentrator Media Converter Lobe or Ring Out Port Media Converter Ring In Port Media Converter
FEATURES
s s s s s s s s s
Single-chip copper-to-fiber converter for Token Ring 16Mbps and 4Mbps data rates with the same external components Four modes of operation covering a wide variety of applications Full duplex operation Highly stable data quantizer with 55dB input dynamic range Current driven fiber optic LED driver for accurate launch power Current driven output for low RFI noise and low jitter Capable of driving 100 UTP or 150 STP Pin selectable phantom wire fault detection and signal switching
BLOCK DIAGRAM
EQA TPINP TPINN TWISTED PAIR EQUALIZER LED DRIVER EQB RTSETOP OPVCC OPOUT
TPINOK
TWISTED PAIR RECEIVE SQUELCH
SIGNAL MUX
FIBER OPTIC RECEIVE SQUELCH
OPINOK
RTSETTP TPOUTP TPOUTN TWISTED PAIR DRIVER FIBER OPTIC QUANTIZER OPINP OPINN VDC PHTM1 PHTM2 PHANTOM DRIVER CONTROL LOGIC BIAS
XTAL1 CRYSTAL OSCILLATOR XTAL2
KEYGEN
INSERTED
1
ML6680
PIN CONFIGURATION
ML6680 28-Pin PLCC (Q28)
OPINP
26 25 24 23 22 21 20 19 18
XTAL1
XTAL2
28
4 TPINP TPINN PHTM1 PHTM2 GND2 TPOUTP TPOUTN 5 6 7 8 9 10 11 12
3
2
1
27
QVCC
VCC2
EQA
EQB
OPINN QGND VDC KEYGEN GND1 OPGND OPOUT
13 14
15
16
17
RTSETOP
INSERTED
OPINOK
TPINOK
RTSETTP
VCC1
TOP VIEW
2
OPVCC
ML6680
PIN DESCRIPTION
PIN# NAME FUNCTION PIN# NAME FUNCTION
1, 28 XTAL1, XTAL2
Crystal inputs. A 32.768kHz watch crystal connected between these pins provides timing for the fiber optic insertion key signal. An external clock can be used to drive XTAL1 while grounding XTAL2. The frequency of the external clock should be between 32.7kHz and 34.5kHz. Positive 5V power supply.
13
RTSETTP
Twisted pair transmit level set resistor input. A precision resistor between RTSETTP and VCC sets the amplitude of the TPOUTP/N output. Positive 5V power supply.
14 15
VCC1
2 3, 4
VCC2
EQA, EQB Equalizer network pins. An external combination of two resistors and a capacitor connected at EQA and EQB sets up the on-chip twisted pair receive equalizer. Receive twisted pair inputs. This differential input pair receives differential Manchester signals from the coupling transformer (or PECL compatible levels). Phantom drive/sense inputs/outputs. In configuration 1, these pins are TTL inputs from two external opto isolators. They are low when phantom power is present and high when phantom power is removed. These pins provide the phantom drive current and are used to check for a wire fault on the phantom circuits when it is required in configuration 2. In configuration 3, these pins are don't cares. In configuration 4, these pins are low for normal operation, or any or both of them is high to force the ML6680 into the "Bypass State." Ground.
5, 6 TPINP/N
INSERTED Insertion indicator. It is an active low, open collector LED driver. In configurations 1, 3 and 4 this output goes low when the ML6680 is in the "Insert State." In configuration 2 this output goes low when the ML6680 is in the "Insert State" and no wire fault is detected. This input is tied to ground to disable the frequency squelch, and to reduce the time constant of the amplitude squelch of the optical input. RTSETOP A precision resistor between RTSETOP and VCC sets the amplitude of the OPOUT output. Valid fiber optic input signal indicator. It is an active low, open collector LED driver. This output goes low when the signal at OPINP/N meets frequency and amplitude squelch limit for received signals at TPINP/N. Positive 5V power supply for fiber optic LED driver. Fiber optic LED driver output. The fiber optic LED connects between this pin and OPVCC. Ground for the fiber optic LED driver. Ground. Key generation select CMOS input. This input is low for configurations 2 and 3 of the general description, and is high for configurations 1 and 4. Offset correction time constant capacitor input. An external capacitor between this pin and QGND determines the time constant of the internal offset correction circuit for the fiber optic quantizer. Quantizer's ground. Receive fiber inputs. This pair of inputs receive differential Manchester signals from the fiber optic receiver/preamp and present them to the on-chip fiber optic quantizer. These inputs should be capacitively coupled to the input source. The input resistance is approximately 1.3k. Quantizer's positive 5V power supply.
16
7, 8 PHTM1/2
17
OPINOK
18 19
OPVCC OPOUT
20 21 22
OPGND GND1 KEYGEN
9
GND2
10, 11 TPOUTP/N Transmit twisted pair outputs. This differential current output pair drives differential Manchester signals into the network coupling transformer and transmit filter. Output edge rates are controlled to allow use of a simpler filter than would otherwise be required. These outputs can be PECL compatible with an external resistor network. 12 TPINOK Valid twisted pair input signal indicator. It is an active low, open collector LED driver. This output goes low when the signal at TPINP/N meets frequency and amplitude squelch requirements. This input is tied to ground for configurations 3 and 4 to enable signal path switching.
23
VDC
24
QGND
26, 25 OPINP/N
27
QVCC
3
ML6680
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Power Supply Voltage Range, VCC .................... -0.3 to 6V Input Voltage Range ........................................ -0.3 to VCC Output Current TPOUTP, TPOUTN .............................................. 50mA OPOUT ............................................................... 70mA PHTM1, PHTM2 .................................................. 10mA Input Current RTSETTP, RTSETOP, TPINOK, OPINOK, INSERTED ........................................... 20mA Storage Temperature ................................. -65C to 150C Lead Temperature (soldering, 10 sec.) ....................... 260 Thermal Resistance .............................................. 68C/W
OPERATING CONDITIONS
Power Supply Voltage, VCC ................................. 5V 5% All VCC supply pins must be within 0.1V of each other. All GND pins must be within 0.1V of each other. Ambient Temperature,TA ................................ 0C to 70C Junction Temperature, TJ ....................................... 0C to 125C LED on Current ......................................................... 4mA RTSETOP ......................................................... 115 1% RTSETTP ......................................................... 255 1%
ELECTRICAL CHARACTERISTICS
Over full range of operating conditions unless otherwise specified (Note 1).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY CURRENT ICC1 ICC2 VCC Supply Current VCC Supply Current No transmitting, phantom power off RTSETTP = 255, RTSETOP = 115, transmitting, phantom power on (Note 2) 30 36 50 mA
120
160
mA
CMOS INPUTS PHTM1, PHTM2 (when KEYGEN = High or TPINOK is grounded) AND KEYGEN VILC VIHC Input Low Voltage Input High Voltage 0.9 x VCC 0.1 x VCC V V
TTL INPUT: XTAL1 VILT VIHT IILT IIHT RIX1 Input Low Voltage Input High Voltage Input Low Current Input High Current Input Resistance V(XTAL1) = 0V V(XTAL1) = 2.7V 400 2 -100 100 560 0.8 V V A A k
CONTROL INPUTS: INSERTED, TPINOK VILS IILS Input Low Voltage Input Low Current VIN = 0V -50 0.1 V A
STATUS LED OUTPUTS: INSERTED, TPINOK, OPINOK IOLS IOHS Output Low Current Output Off Current Pin connected to VCC 14 19 3 24 10 mA A
4
ML6680
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS PHANTOM DRIVE OUTPUTS: PHTM1, PHTM2 RNF RSC ROC VOHP No Fault Phantom Load Resistance Short Circuit Phantom Load Resistance Open Circuit Phantom Load Resistance Phantom Output High Voltage IOHP > -1mA IOHP > -2mA ISC IOFFP Phantom Short Circuit Current Phantom Off Current V(PHTM1) or V(PHTM2) = 0V V(PHTM1) or V(PHTM2) = 0V -100 50 4.1 3.5 -1.8 -1.2 100 2.9 5.5 50 k k V V mA A
TWISTED PAIR RECEIVER: TPINP, TPINN VOSRTP VDSTP VPSTP VCMTP RIDRTP Differential Offset Voltage Differential Squelch Threshold Differential Post-Squelch Threshold Open-Circuit Common Mode Bias Voltage Differential Input Resistance 8 -35 200 100 2.4 9.6 12.5 35 300 150 mV mVP-P mVP-P V k
TWISTED PAIR TRANSMITTER: TPOUTP, TPOUTN ITTP IOFFTP IDCI Peak Output Current Off State Output Current Differential Current Im Balance RTSETTP = 255, Pins Connected to VCC -300 27 29.5 1.5 300 mA mA A
OPTICAL RECEIVER: OPINP, OPINN VCMOP VIROP VOSROP EN RIDROP VDSOP VPSOP H Open Circuit Common Mode Bias Voltage Input Signal Range Differential Offset Voltage Input Referred Voltage Noise Differential Input Resistance Differential Squelch Threshold Differential Post Squelch Threshold Hysteresis 50MHz BW 1.8 5 4 20 VDSOP 3 25 2.6 3.3 6 5 1.6 1600 V mVP-P mV VRMS k mVP-P mVP-P %
OPTICAL TRANSMITTER: OPOUT ITOP IOFFOP Peak Output Current Off State Output Current RTSETOP = 115 47 52 57 1 mA mA
5
ML6680
AC CHARACTERISTICS
Over full range of operating conditions unless otherwise specified. (Note 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CLOCK REFERENCE: XTAL1 fXO DXO Reference Clock Frequency Reference Clock Duty Cycle 32.7 30 34.5 70 kHz %
TWISTED PAIR RECEIVER: TPINP, TPINN tTHTP tUSQTP tREJTP Input Pulse Width Threshold Time to Unsquelch (Off to On) Time to Reject (On to Off) 550 2 550 1000 5 1000 ns s ns
OPTICAL RECEIVER: OPINP, OPINN tTHOP tUSQOP Input Pulse Width Threshold Time to Unsquelch (Off to On) V(INSERTED) > 0.7V V(INSERTED) > 0.7V V(INSERTED) = 0V tREJOP Time to Reject (On to Off) V(INSERTED) > 0.7V V(INSERTED) = 0V PROPAGATION DELAYS STEADY STATE tTPOP tOPTP tTPTP tOPOP TPINP-TPINN to OPOUT OPINP-OPINN to TPOUTP-TPOUTN TPINP-TPINN to TPOUTP-TPOUTN OPINP-OPINN to OPOUT 20 30 30 20 ns ns ns ns 550 3 0.8 3 0.8 1000 9 1.2 9 1.2 ns s s s s
INSERTION AND BYPASS KEY GENERATION (Fig. 1) T_K1 T_K2 T_K3 T_BYP T_KINIT1 Key Element #1 (avg. PO < PO_Off) Key Element #2 (avg. PO > PO_Off) Key Element #3 (avg. PO < PO_Off) Bypass Element (avg. PO > PO_Off) Time that phantom power should be applied in config 1 before generating the insertion key. Time that the optical input should be valid in config 4 before generating the insertion key. Time that the optical input should be invalid before generating the bypass key. V(KEYGEN) = VCC, V(TPINOK) > 0.7V 808 1616 1616 4.85 26.5 26.5 858 1717 s s s ms ms
T_KINIT4
V(KEYGEN) = VCC, V(TPINOK) = 0V V(PHTM1) = 0V, V(PHTM2) = 0V
26.5
ms
T_KOFF
V(KEYGEN) = VCC, V(TPINOK) = 0V V(PHTM1) = 0V, V(PHTM2) = 0V
26.5
ms
6
ML6680
AC CHARACTERISTICS (continued)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS INSERTION KEY ECHO AND BYPASS KEY RECOGNITION (Fig. 1) T_ECHO Time since starting insertion key generation until receiving the insertion key echo. Key Echo From T_K1 Key Echo From T_K2 Key Echo From T_K3 766 1533 1533 4 4.5 100 ms
T_E1Key T_E2Key T_E3Key
900 1800
s s s ms
T_BYPDET Time of optical input not valid before recognizing a bypass key
Note 1: Note 2:
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Current into all VCC pins, external bias resistors, and external transmit loads. Does not include status LED's current.
GENERATED INSERTION KEY T_K1 RECEIVED INSERTION KEY ECHO T_ECHO GENERATED BYPASS KEY T_BYP T_E1 T_E2 T_E1 T_E3 T_K2 T_K1 T_K3
RECEIVED BYPASS KEY
INSERTED
T_BYPDET
Figure 1
7
ML6680
FUNCTIONAL DESCRIPTION
Fiber Optic LED Driver The output stage of the transmitter is a current mode switch which develops the output light by sinking current from OPVCC through the LED into the OPOUT pin. Once the current requirement for the LED is determined, the RTSETOP resistor is selected. The following equation is used to select the correct RTSETOP resistor: RTSETOP = (52mA/IOUT) x 115 No current is provided during the off cycles of the Insertion, Bypass, or Echo Keys, or when the input signal that should be routed to the Fiber Optic LED Driver does not meet the corresponding input squelch requirements. Fiber Optic Quantizer The OPINP, OPINN input signal is fed into a limiting amplifier with a gain of about 100 and input resistance of 1.3k. Maximum sensitivity is achieved through the use of a DC restoration feedback loop and AC coupling the input. When AC coupled, the input DC bias voltage is set by an on-chip network at about 1.7V. These coupling capacitors, in conjunction with the input impedance of the amplifier, establish a high pass filter with 3dB corner frequency, fL, at fL = 1/(2 x x 1300 x C) Since the amplifier has a differential input, two capacitors of equal value are required. If the signal driving the input is single ended, one of the coupling capacitors can be tied to VCC. The internal amplifier has a lowpass filter built-in to band limit the input signal which in turn will improve the signal to noise ratio. Although the input is AC coupled, the offset voltage, VOS, within the amplifier will be present at the amplifier's output. In order to reduce this error a DC feedback loop nulls the offset voltage, forcing VOS to be zero. The comparator is a high-speed differential zero crossing detector that slices and accurately digitizes the receive signal. The output of the comparator is fed in parallel into both the fiber optic squelch circuit and the signal MUX. The capacitor between pin VDC and QGND should be set to 500pF. Fiber Optic Squelch The ML6680 monitors the frequency and amplitude of the input from a fiberoptic receiver. The optical squelch circuit rejects signals whose frequencies are lower than 1MHz or whose amplitudes are lower than -32dBm. If both requirements are met, the LED output OPINOK goes low, and the amplitude threshold is lowered 20%.
FREQUENCY OK AMPLITUDE OK SET RESET Q OPINOK
Copper Pair Driver The output stage of the twisted pair transmitter is a current mode switch which develops the output voltage by driving current through the terminating resistor and the output filter. The harmonic content is controlled to simplify the filter design. The transmitter employs a center tap 2:1 transformer where the center tap is tied to VCC. While one pin of the transmit pair is pulled low, the other pin floats. The output pins to the twisted pair wires, TPOUTP and TPOUTN, can drive shielded or unshielded twisted pair cable through the appropriate isolation transformer. The output current is set by the value of RTSETTP. No transitions are generated at TPOUTP and TPOUTN when the input signal that should be routed to the Copper Pair Driver does not meet the corresponding input squelch requirements. PECL compatible output are obtained with an external network of 3 resistors. In this case the current of the output stage can be reduced by adjusting the value of RTSETTP. Twisted Pair Line Equalizer The receive equalizer compensates for twisted pair cable dispersion, which otherwise would give rise to inter-symbol interference (ISI). The amount of equalization varies with the average amplitude of the received signal. The received signal amplitude gives a rough value for the length of the attached cable. The filter/equalizer characteristic is the inverse of the cable's dispersion characteristic. Both UTP and STP cables approximate a low-pass filter, so the filter/ equalizer approximates an inverse square root equalizer. Two external resistors and one external capacitors are required between pins EQA and EQB. The output of the equalizer is fed into the signal MUX. On a PECL application these pins should be connected between each other. Twisted Pair Squelch Circuit The twisted pair line receiver internally sets the common mode bias of the input TPINP and TPINN. Voltage offset comparators are used to set the amplitude squelch threshold, and analog timers are used to set the pulse width squelch threshold. When the input signal meets amplitude and pulse width requirements, the squelch circuit reduces the offset voltage of the comparators, decreasing the amplitude squelch threshold by half. This hysteresis allows the receiver to stay on in the presence of a fading input signal. The twisted pair squelch circuit rejects signals whose frequencies are lower than 1MHz or whose amplitudes are lower than 300mVP-P. If both requirements are met, the LED output TPINOK goes low. Clock Oscillator The ML6680 provides an on-chip clock oscillator by connecting a 32.768kHz watch crystal between pins XTAL1 and XTAL2. The part can also be driven by an external clock applied at XTAL1 and tying XTAL2 to ground. The frequency of the external clock should be between 32.7kHz and 34.5kHz. Status LED Drivers The ML6680 has three status LED drivers. The LED driver pins are active low. The LED's are tied to their respective pins through a 300 resistor to VCC.
8
ML6680
Modes of Operation Four configurations are possible with the ML6680, as follows: 1.Standard Media Converter: Senses ISO/IEC8802-5 phantom power and generates ISO/IEC8802-5 fiberoptic insertion or bypass requests. 2.Concentrator Media Converter: Recognizes the ISO/ IEC8802-5 fiberoptic insertion or bypass requests and drives the ISO/IEC8802-5 phantom circuits. 3.Lobe or Ring Out Port Media Converter: Recognizes the ISO/IEC8802-5 fiberoptic insertion or bypass requests. 4.Ring In Port Media Converter: Generates ISO/ IEC8802-5 fiberoptic insertion or bypass requests. Modifies the internal signal paths depending on the presence or absence of a fiberoptic link, and on the reception of the ISO/IEC8802-5 "Insertion Key Echo."
CONFIGURATION 3
Lobe or Ring Out Port Media Converter: This configuration is selected by tying both KEYGEN and TPINOK to ground. When the ML6680 is in the "Insert State," the signal paths are from TPINP and TPINN to OPVCC and OPOUT, and from OPINP and OPINN to TPOUTP and TPOUTN. Otherwise, the signal paths are from TPINP and TPINN to TPOUTP and TPOUTN, and from OPINP and OPINN to OPVCC and OPOUT. The part powers on in the "Bypass State" and goes to the "Insert State" after recognizing an "Insertion Key" at its fiber optic inputs. It goes back to the "Bypass State" after recognizing a "Bypass Key." While it is at the "Insert State," the LED output INSERTED stays low.
CONFIGURATION 4
Ring In Port Media Converter: This configuration is selected by tying KEYGEN to VCC and TPINOK to ground. When the part is in the "Insert State," the signal paths are from TPINP and TPINN to OPVCC and OPOUT, and from OPINP and OPINN to TPOUTP and TPOUTN. Otherwise, the input at TPINP and TPINN is routed to TPOUTP and TPOUTN, and also to OPVCC and OPOUT. The "Insertion Key" is generated when activity is detected at OPINP and OPINN for at least 26.5ms and, PHTM1 and PHTM2 stay low. If the "Insertion Key Echo" is received within the following 100ms, the ML6680 goes to the "Insert State" and the LED output INSERTED goes low. During the generation of the "Insertion Key," and while waiting for the "Insertion Key Echo" the logic states of PHTM1 and PHTM2 do not have any effect. When the part is in the "Insert State" and no activity is detected at OPINP and OPINN for at least 26.5ms, or either PHTM1 or PHTM2 goes high, the LED output INSERTED goes high, the part leaves the "Insert State," generates the "Bypass Key," and starts waiting for 26.5ms of optical input activity again. Low Frequency Signaling Mode Some old implementations of discrete media converters, use a non-standard protocol with frequencies between 1 and 10kHz. To facilitate the migration to the ML6680, a specific operating mode is provided by grounding the pin INSERTED. Pin KEYGEN should also be grounded to prevent the generation of unwanted "Insertion" or "Bypass Keys." In this operating mode, the optical frequency squelch circuitry is disabled and the time constant of the amplitude squelch is significantly reduced. For each edge of the low frequency optical input, the ML6680 generates a pulse at the led output OPINOK. It also generates a pulse at the TPOUTP output for each rising edge and another at the TPOUTN output for each falling edge.
CONFIGURATION 1
Standard Media Converter: This configuration is selected by tying KEYGEN to VCC. There are always two fixed signal paths, one from TPINP and TPINN to OPVCC and OPOUT, and another from OPINP and OPINN to TPOUTP and TPOUTN. The generation of the "Insertion Key" or "Bypass Key" is exclusively controlled by the logic values at PHTM1 and PHTM2. The "Insertion Key" is generated when both PHTM1 and PHTM2 go low, and stay low for at least 26.5ms. If the "Insertion Key Echo" is received within the following 100ms, the part goes to the "Insert State" and the LED output INSERTED goes low. During the generation of the "Insertion Key," and while waiting for the "Insertion Key Echo" the states of PHTM1 and PHTM2 do not have any effect. When the part is in the "Insert State" and either PHTM1 or PHTM2 goes high, the LED output INSERTED goes high, the part leaves the "Insert State," generates the "Bypass Key," and starts waiting for PHTM1 and PHTM2 to go low again.
CONFIGURATION 2
Concentrator Media Converter: This configuration is selected by tying KEYGEN to ground. There are always two fixed signal paths, one from TPINP and TPINN to OPVCC and OPOUT, and another from OPINP and OPINN to TPOUTP and TPOUTN. The part powers on in the "Bypass State" where it neither applies phantom current nor checks for a phantom wire fault. After recognizing an "Insertion Key" at its fiber optic inputs, it applies phantom power by providing current at PHTM1 and PHTM2, goes to the "Phantom Wire Fault Check State," and starts waiting for a "Bypass Key." At this state, the LED output INSERTED stays low while no phantom wire fault is detected. When the part is in the "Phantom Wire Fault Check State" and a "Bypass Key" is recognized, the part leaves this state, removes the phantom power, and starts waiting for a "Insertion Key" again.
9
C16
32KHz
EQB
VCC2
XTAL1
OPINP
CONFIG. 1 PHANTOM SENSE R16 1 TPINN PHTM1 7 1 7 6 5 OC2 10 TPOUTP TPOUTN 11 R17 8 PHTM2 4.7K 9 GND2 8 7 6 5 3 4 OC1 14 15 16 2.7K 2 R18 8 3 3 4 2 1 2.7K 2 R13 118 6
TPINP
XTAL2
QVCC
5
EQA
237
R11 237
TPINOK
RTSETTP
VCC1
INSERTED
RTSETOP
OPINOK
OPVCC
C15
R12
10
4.7H FVCC L1 47F C19 C20 2416 L2 4.7H FGND 10 50pF X2 R4 27 OPINN QGND VDC KEYGEN GND1 OPGND OPOUT 26 25 24 23 22 21 20 19 J1 500pF C1 10 1nF C2 C13 0.1F C8 R19 4.7K 4 3 2 1 28 50pF C4 698 220pF C14 0.1F R14 R15 C12 1nF C3 1 2 3 4 U3 8 7 6 5 0.1F J5
VCC +5V
ML6680
D4
47F
0.1F
R20 500
C17
C18
J4
0.1F
3
3
8
7
6
5
4
4
4
T1
5
5
ML6680 U1
6
6
9
10
11
12
13
U2 RJ45
0.1F C5 1414 1 8 0.1F 2 7 C21 R3 1K 3 4 U4 6 5
0.1F
CONFIG. 2 PHANTOM DRIVE
12
13
14
15
16
17
18
Figure 2. ML6680 Configurations 1 and 2
J2 C7 0.1F D3 R1 255 D2 R2 115 D1 R10 300 R6 300 R5 300
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
RJ45
RJ45
0.1F C6
CONFIGURATION ADJUSTMENTS:
STANDARD MEDIA CONVERTER CONFIGURATION 1: REMOVE J4 AND J5 AND CONNECT J1 TO FVCC
CONCENTRATOR MEDIA CONVERTER CONFIGURATION 2: CONNECT J4 AND J5, AND CONNECT J1 TO FGND. REMOVE OC1, OC2, R16, R17, R18 AND R19 SHORT THE LOCATIONS OF PINS 2 AND 6 OF OC1 SHORT THE LOCATIONS OF PINS 2 AND 6 OF OC2
U1: ML6680 U2: RJ45 CONNECTOR U3: HFBR2416 (HP) OR OP2416 (OPTEK) OPTICAL RECEIVER U4: HFBR1414 (HP) OR OP1414(OPTEK) OPTICAL TRANSMITTER OC1: MOTOROLA MOC217 X2: 32.768KHz CRYSTAL OSCILLATOR T1: TRANSFORMER MODULE, VALOR SF1304 OR BEL S553-2793-03 D1-4: LED, SURFACE MOUNT, PANASONIC LN146IC-(TR)
ML6680
VCC +5V
4.7H L1
FVCC
D4 R20 500
47F C17
0.1F C18 L2 4.7H
47F C19
0.1F C20 1 1nF C3 0.1F C4 2 3 4 U3 27 26 10 R4 1nF C2 HFBR 2416 8 7 6 5
FGND CLOCK 0.1F NC 28
FROM THE UPSTREAM LOBE PORT IN CONFIG. 3 FROM THE UPSTREAM RING OUT PORT IN CONFIG. 4
TO THE DOWNSTREAM RING IN PORT IN CONFIG. 3 TO THE DOWNSTREAM LOBE PORT IN CONFIG. 4
INSERTED
RTSETOP
OPINOK
RTSETTP
TPINOK
OPVCC
VCC1
CONFIGURATION 3: LOBE OR RING OUT PORT, J1 TO FGND CONFIGURATION 4: RING IN PORT, J1 TO FVCC R6 300 R5 300 U1: ML6680 U3: HFBR2416 (HP) OR OP2416 (OPTEK) OPTICAL RECEIVER U4: HFBR1414 (HP) OR OP1414 (OPTEK) OPTICAL TRANSMITTERS D1, 2, 4: LED, SURFACE MOUNT, PANASONIC LN146IC (TR)

CINP CINN 25nF C10
25nF C9
5 6 7 8
OPINP
XTAL1
XTAL2
QVCC
VCC2
EQB
EQA
C8 TPINP TPINN PHTM1 PHTM2 GND2
4
3
2
1
OPINN QGND VDC
25 24 23 22 21 20 19
500pF C1 J1 0.1F C21 0.1F 1 HFBR 8 C5 2 7 R3 1K 3 4 U4 6 5
R7 49.9 COUTP COUTN
R8 49.9
9 10 11
ML6680 U1
KEYGEN GND1 OPGND OPOUT
TPOUTP TPOUTN
12
13
14
15
16
17
18
0.1F C7 R1 499
J2 R2 115 D2 D1
0.1F C6
Figure 3. ML6680 Configurations 3 and 4
11
ML6680
PHYSICAL DIMENSIONS inches (millimeters)
Package: Q28 28-Pin PLCC
0.485 - 0.495 (12.32 - 12.57) 0.450 - 0.456 (11.43 - 11.58) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS)
0.042 - 0.048 (1.07 - 1.22)
PIN 1 ID 8 22 0.450 - 0.456 0.485 - 0.495 (11.43 - 11.58) (12.32 - 12.57) 0.300 BSC (7.62 BSC) 0.390 - 0.430 (9.90 - 10.92)
15 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.009 - 0.011 (0.23 - 0.28)
0.099 - 0.110 (2.51 - 2.79)
0.013 - 0.021 (0.33 - 0.53)
SEATING PLANE
ORDERING INFORMATION
PART NUMBER ML6680CQ TEMPERATURE RANGE 0C to 70C PACKAGE 28-PIN PLCC (Q28)
(c) Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
DS6680-01
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