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PLL-Frequency Synthesizer
PMB 2306T
Preliminary Data
CMOS IC
Features
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Low operating current consumption (typically 3.5 mA) High input sensitivity, high input frequencies (220 MHz) Extremely fast phase detector without dead zone Linearization of the phase detector output by current sources Synchronous programming of the counters (n-, n/a-, r-counters) and system parameters Fast modulus switchover for 65-MHz operation Switchable modulus trigger edge Large dividing ratios for small channel spacing A scaler 0 to 127 N scaler 3 to 16.380 R scaler 3 to 65.535 Serial control (3-wire bus: data, clock, enable) for fast programming (fmax ~ 10 MHz) Switchable polarity and phase detector current programmable 2 Multifunction outputs Digital phase detector output signals (e.g. for external charge pump) frn, fvn outputs of the R and N scalers Port 1 output (e.g. for standby of the prescaler) External current setting for PD output Lock detect output with gated anti-backlash pulse (quasi digital lock detect)
P-DSO-14
Type PMB 2306T PMB 2306T
Version V2.2 V2.2
Ordering Code Q67100-H6423 Q67106-H6423
Package P-DSO-14 (SMD) P-DSO-14 (SMD, Tape & Reel)
The PMB 2306T PLL is a high speed CMOS IC, especially designed for use in battery powered radio equipment and mobile telephones. The primary applications will be in digital systems e.g. GSM, PCN, ADC, JDC and DECT systems. The wide range of dividing ratios also allows application in analog systems.
Semiconductor Group
1
01.94
PMB 2306T
Pin Configuration (top view)
Pin Definitions and Functions Pin No. 6 2 11 9 Symbol Function Positive supply voltage for serial control logic. Ground for serial control logic. Positive supply voltage for the preamplifiers, counters, phase detector and charge pump. Ground for the preamplifiers, counters, phase detector and charge pump. (Note: The pins VDD and VDD1 respectively VSS and VSS1 have to have the same supply voltage.) 3-Line Bus: Enable Enable line of the serial control with internal pull-up resistor. When EN = H the input signals CLK and DA are disabled internally. When EN = L the serial control is activated. The received data are transferred into the latches with the positive edge of the EN-signal. 3-Line Bus: Data Serial data input with internal pull-up resistor. The last two bits before the ENsignal define the destination address. In a byte-oriented data structure the transmitted data have to end with the EN-signal, i.e. bits to be filled in (don't care) are transmitted first. 3-Line Bus: Clock Clock line with internal pull-up resistor. The serial data are read into the internal shift register with the positive edge (see pulse diagram for serial data control).
VDD VSS VDD1 VSS1
3
EN
4
DA
5
CLK
Semiconductor Group
2
PMB 2306T
Pin Definitions and Functions (cont'd) Pin No. 7 Symbol MOD Function Modulus Control Output for external dual modulus prescaler. The modulus output is low at the beginning of the cycle. When the a-counter has reached its set value, MOD switches to high. When the n-counter has reached its set value, MOD switches to low again, and the cycle starts from the top. When the prescaler has the counter factor P or P + 1 (P for MOD = H, P +1 for MOD = L), the overall scaling factor is NP + A. The value of the a-counter must be smaller than that of the n-counter. The trigger edge of the modulus signal to the input signal can be selected (see programming tables and MOD A, B) according to the needs of the prescaler. In single modulus operation and for standby operation in dual modulus operation, the output is low. VCO-Frequency Input with highly sensitive preamplifier for 14-bit n-counter and 7-bit a-counter. With small input signals AC coupling must be set up, where DC coupling can be used for large input signals. Reference Frequency Input with highly sensitive preamplifier for 16-bit r-counter. With small input signals AC coupling must be set up, where DC coupling can be used for large input signals. Phase Detector Tristate charge pump output. The integrated, positive and negative current sources can be programmed with respect to their current density by means of the serial control. Activation and deactivation depend on the phase relationship of the scaled-down input signals FI:N, RI:R. (See phase detector output waveforms.) frequency fV < fR or fV lagging: p-channel current source active frequency fV > fR or fR leading: n-channel current source active frequency fV = fR and PLL locked: current sources are switched off, PD-output is tristate In standby mode the PD-output is set to tristate. The assignment of the current sources to the output signals of the phase detector can be swapped in it's polarity, i.e. the sign of the phase detector constant can be controlled. Lock Detector Output (open drain). Unipolar output of the phase detector in the form of a pulse-width modulated signal. The L-pulse width corresponds to the phase difference. Phase differences < 20 ns are not indicated due to gating of the antibacklash impuls. In the locked state the LD-signal is at H-level. In standby mode the output is resistive. Only for ABL status 11 no gating of ABL impulse is performed.
8
FI
1
RI
10
PD
14
LD
Semiconductor Group
3
PMB 2306T
Pin Definitions and Functions (cont'd) Pin No. 12 13 Symbol MFO1 MFO2 Function Multifunction Output for the signals fRN, V, VN and port 1. Multifunction I/O-Pin for the output signals fVN, RN and the input signal IREF. - The signals R and V are the digital output signals of the phase and frequency detector for use in external active current sources (see phase detector output wave forms). - The signals fRN and fVN are the scaled down signals of the reference frequency and VCO-frequency. The L-time corresponds to 1/fRI and 1/fFI respectively. - In the port function the port 1 output signal is assigned to the information of the status program. The output switches with the rising edge of the EN-signal. The standby mode does not affect the port function. - In the internal charge pump mode the input signal IREF determines the value of the PD-output current.
Reference current for charge pump: IREF = (VDD - VREF)/R1 R1: see application circuit
VREF: see AC/DC characteristics
Semiconductor Group
4
PMB 2306T
Block Diagram
Semiconductor Group
5
PMB 2306T
Circuit Description General Description The circuit consists of a reference-, a- and n-counter, a dual modulus control logic, a phase detector with charge pump output and a serial control logic. The setting of the operating mode and the selection of the counter ratios is done serially at the ports CLK, DA and EN. The operating modes allow the selection of single or dual operation, asynchronous or synchronous data acquisition, 4 different antibacklash-impulse times, 8 different PD-output current modes, polarity setting of the PD-output signal, adjustment of the trigger-edge of the MOD-output signal, 2 standby modes and the control of the multifunction outputs MFO1 and MFO2. The reference frequency is applied at the RI-input and scaled down by the r-counter. It's maximum value is 100 MHz. The VCO-frequency is applied at the FI-input and scaled down by the n- or n/acounter according to single or dual mode operation. The maximum value at FI is 220 MHz at single-, and 65 MHz at dual mode operation. The phase and frequency sensitive phase detector produces an output signal with adjustable antibacklash impulses in order to prevent a dead zone for very small phase deviations. Phase differences of less than 100 ps can be resolved. In general the shortest anti-backlash pulse gives the best system performance. Programming Programming of the IC is done by a serial data control. The contents of the message are assigned to the functional units according to the address. Single or dual mode operation as well as asynchronous or synchronous data acquisition is set by status 2 and should therefore precede the programming of the counters. Data acquisition The PMB 2306T offers the possibility of synchronous data acquisition to avoid error signals at the phase detector due to non-corresponding dividing factors in the counters produced by asynchronous loading. Synchronous programming guarantees control during changes of frequency or channel. That means that the state of the phase detector or the phase difference is kept maintained, and in case of "lock in", the control process starts with the phase difference "zero". This is done as follows: 1. Setting of synchronous data acquisition by status 2. 2. Programming of the r-counter, status 1 (optional)-data is being loaded into shadow registers. 3. Programming of the n- or n/a-counter-data is being loaded into shadow registers, the EN-signal starts the synchronous loading procedure. 4. Synchronous programming - which means data transfer of all data from the shadow registers to the data registers - takes place at that point in time when the respective counter reaches "zero + 1", the maximum repetition rate for channel change is therefore fFI:N. 5. Transfer of status 1 information into the corresponding data register is tied to the n-counter loading, but follows the loading of the n-data register in the distance of one n-counter dividing ratio, this guarantees that for example a new PD-current value becomes valid at the same time when the counters are loaded with the new data. Semiconductor Group 6
PMB 2306T
Synchronous avoids additional phase error caused by programming. Synchronous data acquisition is of especial advantage, when large steps in frequency are to be made in a short time. For this purpose a high reference frequency can be programmed in order to achieve rapid - "rough" - transient response. This method increases the fundamental frequency nearly by the square route of the reference frequency relation. When rough lock is achieved, another synchronous data transfer is needed to switch back to the original channel spacing. A "fine" lock in will finish the total step response. It may not be necessary to change reference frequency, but it make sense to perform synchronous data acquisition in any case. Especially for GSM, PCN, DECT, DAMPS, JDC, PHP systems the synchronous mode should be used to get best performance of the PMB 2306T. Standby Condition The PMB 2306T has two standby modes (standby 1, 2) to reduce the current consumption. - Standby 1 switches off the whole circuit, the current consumption is reduced below 1 A. - Standby 2 switches off the counters, the charge pump and the outputs, only the preamplifiers stay active. The standby modes do not affect the port output signal. For the influence on the other output signals see standby table. Note: fRN, fVN, RN and VN are the inverted signals of fR, fV, R and V. Programming Tables Status Bits Mode 2 0 0 1 1 Mode 1 0 1 0 1 Multifunction Outputs MFO 1 MFO 2 Remarks test mode external charge pump mode 1 external charge pump mode 2 internal charge pump mode
fRN
V VN Port 1
fVN
RN RN
IREF
Status Bits PD-Current 3 0 0 0 0 1 1 1 1 PD-Current 2 0 0 1 1 0 0 1 1 PD-Current 1 0 1 0 1 0 1 0 1
PD-Current Mode 0.175 0.25 0.35 0.5 0.7 1 1.4 2
Semiconductor Group
7
PMB 2306T
Programming Tables (cont'd) Status Bits Anti-Backlash Pulse Width 2 0 0 1 1
* *
Anti-Backlash Pulse Width 1 0 1 0 1
tw (typ.)
[ns] 1.3 5 10 13*
Application
VDD = 5 V
not recommended any application where continuous lock detect required
No ABL gating performed In general the shortest anti-backlash pulse gives the best system performance.
Status Bits Single/ Dual Mode 0 0 1 1 Preamplifier Select 0 1 0 1
Preamplifier Function Mode
FI-input frequency, single HF-mode FI-input frequency, single LF-mode FI-input frequency, dual mode, FI-trigger edge LH, MOD A FI-input frequency, dual mode, FI-trigger edge HL, MOD B
Standby Table Output Pins Status Standby 1 Standby 2 MFO 1 V low low VN high high high high resistive resistive tristate tristate low low MFO 2 LD PD MOD
Semiconductor Group
8
PMB 2306T
Serial Control Data Format (status 1, 2) Status 1 Status 2 0 Data acquisition mode Mode 1 Mode 2 PD-polarity Standby 1 Standby 2 Anti-backlash pulse width 1 Anti-backlash pulse width 2 Preamplifier select Single / dual mode Port 1 PD-current 1 PD-current 2 PD-current 3 0 Address 0 0 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EN asynchronous synchronous see table see table negative standby standby positive active active 1
see table see table see table single low see table see table see table dual high
1 2 3 4 5 6 EN
Semiconductor Group
9
PMB 2306T
Serial Control Data Format (n-, n/a-counter) Dual Mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 EN 1 0 MSB Single Mode
a-Counter
LSB MSB MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 0 15 16 EN
n-Counter
LSB Address
LSB
Semiconductor Group
10
PMB 2306T
Serial Control Data Format (r-counter)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 EN
MSB
r-Counter
LSB 1 Address 1
Semiconductor Group
11
PMB 2306T
Phase Detector Output Waveforms
Semiconductor Group
12
PMB 2306T
Absolute Maximum Ratings TA = - 40 to 85 C Parameter Supply voltage Input voltage Output voltage Power dissipation per output Total power dissipation Ambient temperature Storage temperature Operating Range Supply voltage Input frequency dual mode Input frequency single HF-mode Input frequency single LF-mode Input reference frequency Input frequency dual mode Input frequency single HF-mode Input frequency single LF-mode Input reference frequency PD-output current PD-output voltage PD-output voltage Ambient temperature Typical Supply Current IDD Supply voltage Supply current single mode HF dual mode standby 2 standby 1 Test conditions: fFI = 50 MHz, VFI = 150 mVrms fRI = 10 MHz, VRI = 150 mVrms IPD = 0.25 mA, Iref = 100 A
All pins are protected against ESD. Unused inputs without pullup resistors must be connected to either VDD or VSS.
Symbol min.
Limit Values max. 6 - 0.3 - 0.3 GND
Unit V V V mW mW C C
Remarks
VDD VI VQ PQ Ptot TA Tstg
VDD + 0.3 VDD
10 300
- 40 - 50
85 125
in operation
VDD fFI fFI fFI fRI fFI fFI fFI fRI
/ IPD /
3.0 0.1 0.1 0.1 0.1 0.1 0.1
5.5 65 220 90 100 30 120 35 20 4
V MHz MHz MHz MHz MHz MHz MHz MHz mA V V C
VDD = 4.5 ... 5.5 V VDD = 4.5 ... 5.5 V VDD = 4.5 ... 5.5 V VDD = 4.5 ... 5.5 V VDD = 3.3 V VDD = 3.3 V VDD = 3.3 V VDD = 3.3 V VDD = 4.5 - 5.5 V VDD = 3.3 V
VPD VPD TA
0.5 0.5 - 40
VDD - 0.5 VDD - 0.5
85
VDD IDD IDD IDD IDD
3.3 1.63 1.76 0.11
5 2.6 2.80 0.62
5.5 2.94 3.17 0.75 1
V mA mA mA A
Semiconductor Group
13
PMB 2306T
AC/DC Characteristics TA = - 20 to 85 C Parameter Symbol min. Limit Values typ. max. Unit Test Condition
Input Signals DA, CLK, EN (with internal pull-up resistors) H-input voltage L-input voltage Input capacity H-input current L-input current Input Signal RI Input voltage Input voltage Slew rate Input capacity H-input current L-input current
VIH VIL CI IH IL
0.7 VDD 0
VDD
- 40
V 0.3 VDD V 5 pF 10 A A
VI = VDD = 5.5 V VI = GND
VI VI CI IH IL
100 100 2.5 3 10 - 10
mVrms mVrms V/s pF A A
f = 4 ... 100 MHz, VDD = 4.5 V f = 4 ... 20 MHz, VDD = 3.3 V VDD = 3.3 ... 5.5 V VI = VDD = 5.5 V VI = GND
Input Signal FI (dual mode) Input voltage Input voltage Slew rate Input capacity H-input current L-input current Input voltage VI
VI VI CI IH IL VI
180 180 4 3 10 - 10 50
mVrms mVrms V/s pF A A mVrms
f = 4 ... 65 MHz, VDD = 4.5 V f = 4 ... 30 MHz, VDD = 3.3 V VDD = 3.3 ... 5.5 V VI = VDD = 5.5 V VI = GND f = 10 ... 30 MHz, VDD = 3.3 V
Input Signal FI (single HF-mode) Input voltage Input voltage Slew rate Input capacity H-input current L-input current Input voltage
VI VI CI IH IL VI
200 200 2.5 3 10 - 10 50
mVrms mVrms V/s pF A A mVrms
f = 4 ... 220 MHz, VDD = 4.5 V f = 4 ... 120 MHz, VDD = 3.3 V VDD = 3.3 ... 5.5 V VI = VDD = 5.5 V VI = GND f = 10 ... 50 MHz, VDD = 4.5 V
Semiconductor Group
14
PMB 2306T
AC/DC Characteristics (cont'd) TA = - 20 to 85 C Parameter Symbol min. Input Signal FI (single LF-mode) Input voltage Input voltage Slew rate Input capacity H-input current L-input current Output Current IPD Current mode "0.175 mA" "0.25 mA" "0.35 mA" "0.5 mA" "0.7 mA" "1.0 mA" "1.4 mA" "2.0 mA" "Standby" * guaranteed by design Limit Values typ. max. Unit Test Condition
VI VI CI IH IL
100 100 2.5 3 10 - 10
mVrms mVrms V/s pF A A
f = 4 ... 90 MHz, VDD = 4.5 V f = 4 ... 35 MHz, VDD = 3.3 V VDD = 3.3 ... 5.5 V VI = VDD = 5.5 V VI = GND
IPROG IPROG IPROG IPROG IPROG IPROG IPROG IPROG / IPD /
- 20 % - 20 % - 20 % - 20 % - 20 % - 10 % - 10 % - 10 % 0.1
+ 20 % + 20 % + 20 % + 20 % + 20 % + 10 % + 10 % + 10 % 50
mA mA mA mA mA mA mA mA nA
VDD = 4.5 ... 5.5 V VPD = VDD/2 IREF = 100 A
VDD = 5.5 V
Output Tolerances IPD IPD / IPROG IPD / IPROG - 20 % t.b.d. +3%
VPD = VDD/2, VDD = 3.3 V VPD = 1 ... 4 V, VDD = 5 V
Input Voltage MFO2 (internal charge pump mode) Reference voltage
VREF
0.9
1.1
1.3
V
VDD = 4.5 ... 5.5 V, IREF = 100 A
Semiconductor Group
15
PMB 2306T
AC/DC Characteristics (cont'd) TA = - 20 to 85 C Parameter Symbol min. Output Signal MFO1 (push pull) H-output voltage L-output voltage H-output voltage L-output voltage Rise time Fall time Rise time Fall time Limit Values typ. max. Unit Test Condition
VQH VQL VQH VQL tR tF tR tF
VDD - 1
1
VDD - 1
2.5 2.0 4.0 2.5 1 10 10 10 10
V V V V ns ns ns ns
VDD = 4.5 ... 5.5 V, IQH = 2 mA VDD = 4.5 ... 5.5 V, IQL = 2 mA VDD = 3.3 V, IQH = 1.2 mA VDD = 3.3 V, IQL = 1.2 mA VDD = 4.5 ... 5.5 V, CI = 10 pF VDD = 4.5 ... 5.5 V, CI = 10 pF VDD = 3.3 V, CI = 10 pF VDD = 3.3 V, CI = 10 pF
Output Signal MFO2 (push pull) H-output voltage L-output voltage H-output voltage L-output voltage Rise time Fall time Rise time Fall time
VQH VQL VQH VQL tR tF tR tF
VDD - 1
1
VDD - 1
2 2 3 3 1 10 10 10 10
V V V V ns ns ns ns
VDD = 4.5 ... 5.5 V, IQH = 2 mA VDD = 4.5 ... 5.5 V, IQL = 2 mA VDD = 3.3 V, IQH = 1.2 mA VDD = 3.3 V, IQL = 1.2 mA VDD = 4.5 ... 5.5 V, CI = 10 pF VDD = 4.5 ... 5.5 V, CI = 10 pF VDD = 3.3 V, CI = 10 pF VDD = 3.3 V, CI = 10 pF
Output Signal LD (n-channel open drain) L-output voltage L-output voltage Fall time Fall time
VQL VQL tF tF
3 4.5
0.4 0.4 10 10
V V ns ns
VDD = 4.5 ... 5.5 V, IQL = 0.5 mA VDD = 3.3 V, IQL = 0.5 mA VDD = 4.5 ... 5.5 V, CI = 10 pF VDD = 3.3 V, CI = 10 pF
Semiconductor Group
16
PMB 2306T
Equivalent I/O Schematics
Semiconductor Group
17
PMB 2306T
Equivalent I/O Schematics (cont'd)
Semiconductor Group
18
PMB 2306T
AC/DC Characteristics (cont'd) TA = - 20 to 85 C Parameter Symbol min. Output Signal MOD (push-pull) H-output voltage L-output voltage H-output voltage L-output voltage Rise time Fall time Propagation delay time H-L to FI Propagation delay time L-H to FI Rise time Fall time Propagation delay time H-L to FI Propagation delay time L-H to FI Limit Values typ. max. Unit Test Condition
VQH VQL VQH VQL tR tF tDQHL tDQLH tR tF tDQHL tDQLH
VDD
- 0.4 0.4
V V V 0.4 3 3 12 12 4 4 V ns ns ns ns ns ns ns ns
VDD
- 0.4 1.5 1.3 8 8 2.8 1.6 12 12
VDD = 4.5 ... 5.5 V, IQH = 0.5 mA VDD = 4.5 ... 5.5 V, IQL = 0.5 mA VDD = 3.3 V, IQH = 0.3 mA VDD = 3.3 V, IQL = 0.3 mA VDD = 4.5 ... 5.5 V, CI = 5 pF VDD = 4.5 ... 5.5 V, CI = 5 pF VDD = 4.5 ... 5.5 V, CI = 5 pF VDD = 4.5 ... 5.5 V, CI = 5 pF VDD = 3.3 V, CI = 5 pF VDD = 3.3 V, CI = 5 pF VDD = 3.3 V, CI = 5 pF VDD = 3.3 V, CI = 5 pF
Semiconductor Group
19
PMB 2306T
Pulse Diagram
Semiconductor Group
20
PMB 2306T
Serial Control Data Input Timing
Parameter Clock frequency H-pulsewidth (CL) Data setup Setup time clock-enable Setup time enable-clock H-pulsewidth (enable) Rise, fall time Propagation delay time EN-PORT
Symbol min.
Limit Values max. 10 60 20 20 20 60 10 1
Unit MHz ns ns ns ns ns s s
fCL tWHCL tDS tCLE tECL tWHEN tR, tF tDEP
21
Semiconductor Group
PMB 2306T
Input Sensitivity
Semiconductor Group
22
PMB 2306T
GSM Application Circuit Semiconductor Group 23
PMB 2306T
List of Components Item Quantity Reference 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 2 1 1 1 1 4 1 1 1
Part 100 150 220 330 3.3 k 6.8 k 8.2 k 18 k 22 k 39 k 22 nH 1.2 pF 2.2 pF 10 pF 22 pF 33 pF 100 pF 330 pF 560 pF 5.6 nF 100 nF 22 F BBY 51 BFR 280 BFT 92 1,0 nF SMA 1.3 GHz PMB 2306T P-DSO-14 PMB 2306T P-DSO-14 PMB 2312 P-DSO-8 SMD/0805 B54102-A1101-X60 SMD/0805 B54102-A1151-J60 SMD/0805 B54102-A1221-J60 SMD/0805 B54102-A1331-J60 SMD/0805 B54102-A1332-J60 SMD/0805 B54102-A1682-J60 SMD/0805 B54102-A1822-J60 SMD/0805 B54102-A1183-J60 SMD/0805 B54102-A1223-J60 SMD/0805 B54102-A1393-J60 SIMID 01 B82412-A3220-M COG/0805 B37940-K5010-C262 COG/0805 B37940-K5020-C262 COG/0805 B37940-K5100-J62 COG/0805 B37940-K5220-J62 COG/0805 B37940-K5330-J62 COG/0805 B37940-K5101-J62 COG/0805 B37940-K5331-J62 COG/0805 B37940-K5561-J62 COG/1210 X7R/1210 B37950-K5104-K62 SIEMENS SIEMENS SIEMENS SIEMENS SIEMENS SIEMENS SIEMENS SIEMENS SIEMENS SIEMENS SIEMENS SIEMENS SIEMENS SIEMENS SIEMENS SIEMENS SIEMENS SIEMENS SIEMENS SIEMENS
R7 R13, R14 R6 R8 R10 R12 R9, R3, R5, R11 R4 R2 R2
1 L1 1 1 1 6 3 1 1 1 1 1 1
C11 C13 C8 C20, C10, C12, C14, C15, C16 C17, C1, C2 C9 C3 C5 C7 C6 C19
1 D1 2 T3, T2 1 T1 1 2 1 1 C4 X2, X1 RX IC1
Q62702-B631 Q62702-F1298 Q62702-F1062
SIEMENS SIEMENS SIEMENS
1 IC2
Connector B69620-G1307-A410 Q67100-H6333 (TUBE) Q67106-H6333 ( T+R ) Q67000-A6039
S+M SIEMENS SIEMENS SIEMENS
Semiconductor Group
24
PMB 2306T
Phase Noise Close to the Carrier
Semiconductor Group
25
PMB 2306T
Spectrum at Lower End of GSM TX Board (Mobile)
Semiconductor Group
26
PMB 2306T
Lock-In Time for GSM Application
Semiconductor Group
27
PMB 2306T
Measurement Set-Up for Lock- In Time
Semiconductor Group
28
PMB 2306T
Package Outlines P-DSO-14-1 (Plastic Dual-Small-Outline Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device
Dimensions in mm
Semiconductor Group
29
gps05093

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