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| S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PRODUCT OVERVIEW 1 PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals and various mask-programmable ROM sizes. Important CPU features include: -- Efficient register-oriented architecture -- Selectable CPU clock sources -- Idle and Stop power-down mode release by interrupt -- Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels. S3C80E5/C80E7 MICROCONTROLLER The S3C80E5/C80E7 single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process, based on Samsung's newest CPU architecture. The S3C80E5/C80E7 is the microcontroller which has 16/24-Kbyte mask-programmable ROM. The S3P80E5/P80E7 is the microcontroller which has 16/24-Kbyte one-time-programmable EPROM. Using a proven modular design approach, Samsung engineers developed the S3C80E5/C80E7 by integrating the following peripheral modules with the powerful SAM87 core: -- Four programmable I/O ports, including three 8-bit ports and one 2-bit port, for a total of 26 pins. -- Internal LVD circuit and twelve bitprogrammable pins for external interrupts. -- One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset). -- One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes. -- One 8-bit counter with auto-reload function and one-shot or repeat control. The S3C80E5/C80E7 is a versatile general-purpose microcontroller which is especially suitable for use as unified remote transmitter controller. It is currently available in a 32-pin SOP and SDIP package for S3C80E5 and S3C80E7. And available in 40 DIP package only for S3C80E7. OTP The S3P80E5/P80E7 is an OTP (One Time Programmable) version of the S3C80E5/C80E7 microcontroller. The S3P80E5/P80E7 microcontroller has an on-chip 16/24-Kbyte one-time-programmable EPROM instead of a masked ROM. The S3P80E5/P80E7 is comparable to the S3C80E5/C80E7, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) FEATURES CPU * SAM87 CPU core Carrier Frequency Generator * One 8-bit counter with auto-reload function and one-shot or repeat control (Counter A) Memory * * * * 16-Kbyte internal program memory (ROM): S3C80E5 24-Kbyte internal program memory (ROM): S3C80E7 256-byte internal (RAM): 8000-80FFH Data memory: 317-byte internal register file Back-up mode * When reset pin is low level or when VDD is lower than VLVD, the chip enters back-up mode to reduce current consumption. Low Voltage Detect Circuit * * Low voltage detect for reset or back-up mode input. Low level detect voltage : 2.2 V (Typ) -100 mV/+ 200 mV Instruction Set * * 78 instructions IDLE and STOP instructions added for powerdown modes Operating Temperature Range * - 40C to + 85 C Instruction Execution Time * 750 ns at 8 MHz f OSC (minimum) Operating Voltage Range * 2.0 V to 5.5 V at 4 MHz fOSC 2.1 V to 5.5 V at 8 MHz fOSC Interrupts * * * Six interrupt levels and 18 interrupt sources 15 vectors (14 sources have a dedicated vector address and four sources share a single vector) Fast interrupt processing feature (for one selected interrupt level) * Package Type * * * 32-pin SOP 32-pin SDIP 40-pin DIP I/O Ports * * Three 8-bit I/O ports (P0-P2) and one 2-bit port (P3) for a total of 26 bit-programmable pins Twelve input pins for external interrupts Timers and Timer/Counters * One programmable 8-bit basic timer (BT) for oscillation stabilization control or watchdog timer (software reset) function One 8-bit timer/counter (Timer 0) with three operating modes; Interval, Capture, and PWM One 16-bit timer/counter (Timer 1) with two operating modes; Interval and Capture * * 1-2 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PRODUCT OVERVIEW BLOCK DIAGRAM P0.0-P0.7 (INT0-INT4) P1.0-P1.7 PORT 0 PORT 1 RESET TEST VDD LVD INTERNAL BUS PORT2 P2.0-P2.3 (INT5-INT8) P2.4-P2.7 XIN XOUT MAIN OSC I/O PORT and INTERRUPT CONTROL P3.0/T0PWM/ T0CAP/T1CAP 8-BIT BASIC TIMER SAM87 CPU PORT 3 P3.1/REM/T0CK 8-BIT TIMER/ COUNTER PROGRAM MEMORY (16/24-Kbyte Program Memory and 256-Byte Program RAM) 317-BYTE REGISTER FILE CARRIER GENERATOR (COUNTER A) 16-BIT TIMER/ COUNTER Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PIN ASSIGNMENTS VSS XIN XOUT TEST P2.0/INT5 P2.1/INT6 P2.2/INT7 P2.3/INT8 P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/INT3 P0.4/INT4 P0.5/INT4 P0.6/INT4 P0.7/INT4 1 2 3 4 5 6 S3C80E5 7 S3C80E7 8 32-SOP/SDIP 9 10 (Top View) 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD RESET/BACK-UP MODE P3.1/REM/T0CK P3.0/T0PWM/T0CAP/T1CAP P2.7 P2.6 P2.5 P2.4 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 Figure 1-2. Pin Assignment (32-Pin SOP/SDIP Package) VSS XIN XOUT TEST NC NC P2.0/INT5 P2.1/INT6 P2.2/INT7 P2.3/INT8 P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/INT3 NC NC P0.4/INT4 P0.5/INT4 P0.6/INT4 P0.7/INT4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S3C80E5 S3C80E7 40-DIP (Top View) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD RESET/BACK-UP MODE P3.1/REM/T0CK P3.0/T0PWM/T0CAP/T1CAP NC NC P2.7 P2.6 P2.5 P2.4 P1.7 P1.6 P1.5 P1.4 NC NC P1.3 P1.2 P1.1 P1.0 Figure 1-3. Pin Assignment (40-Pin DIP Package) 1-4 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PRODUCT OVERVIEW Table 1-1. Pin Descriptions Pin Names P0.0-P0.7 Pin Type I/O Pin Description I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors are assignable by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/disable, and interrupt pending control. I/O port with bit-programmable pins. Configurable to C-MOS input mode or output mode. Pin circuits are either pushpull or n-channel open-drain type. Pull-up resistors are assignable by software. General-purpose I/O port with bitprogrammable pins. Configurable to CMOS input mode, push-pull output mode, or n-channel open-drain output mode. Pull-up resistors are assignable by software. Lower nibble pins, P2.3-P2.0, can be assigned as external interrupt inputs with noise filters, interrupt enable/disable, and interrupt pending control. 2-bit I/O port with bit-programmable pins. Configurable to C-MOS input mode, pushpull output mode, or n-channel open-drain output mode. Pull-up resistors are assignable by software. The two port 3 pins have high current drive capability. System clock input and output pins System reset signal input pin and back-up mode input pin. The pin circuit is a C-MOS input. Test signal input pin (for factory use only; must be connected to VSS). Power supply input pin Ground pin Circuit Type 1 Pin No. (32-pin) 9-16 Pin No. (40-pin) 11-14, 17-20 Shared Functions INT0-INT4 P1.0-P1.7 I/O 2 17-24 21-24, 27-30 - P2.0-P2.3 P2.4-P2.7 I/O 3 4 5-8, 25-28 7-10, 31-34 INT5-INT8 - P3.0 P3.1 I/O 5 29 30 37 38 T0PWM/ T0CAP/ T1CAP/ REM/T0CK XIN, XOUT RESET/ BACK-UP MODE TEST VDD VSS - I - 6 2, 3 31 2, 3 39 - - I - 4 4 - - - - - 32 1 40 1 - - 1-5 PRODUCT OVERVIEW S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PIN CIRCUITS VDD PULL-UP RESISTOR (Typical 21 K) PULL-UP ENABLE VDD DATA I/O OUTPUT DISABLE VSS INTERRUPT INPUT IRQ6,7 (INT0-4) NOISE FILTER NORMAL INPUT Oscillator Release (SED and R circuit) STOP NOTE: To prevent and recover from abnormal stop status caused by battery bouncing, the S3P80E5 has a special logic_ SED and R circuit -related to P0 and P1. This is a specific function for key input/output of universal remote controller. When these ports (P0, P1) are used as a normal input pin, unexpected stop mode recovery can occur by input level switching. Hence, the user should be aware of input level switching, if P0 and P1 are to be used as normal input ports. Figure 1-4. Pin Circuit Type 1 (Port 0) 1-6 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PRODUCT OVERVIEW VDD PULL-UP RESISTOR (Typical 21 K) PULL-UP ENABLE VDD DATA I/O OUTPUT DISABLE VSS NORMAL INPUT NOISE FILTER STOP Oscillator Release (SED and R circuit) NOTE: To prevent and recover from abnormal stop status caused by battery bouncing, the S3P80E5 has a special logic -SED and R circuit -related to P0 and P1. This is a specific function for key input/output of universal remote controller. When these ports (P0, P1) are used as a normal input pin, unexpected stop mode releasing can occur by input level switching. Hence, the user should be aware of input level switching, if P0 and P1 are to be used as normal input ports. Figure 1-5. Pin Circuit Type 2 (Port 1) 1-7 PRODUCT OVERVIEW S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) VDD PULL-UP RESISTOR (Typical 21 K) PULL-UP ENABLE VDD DATA I/O OPEN-DRAIN OUTPUT DISABLE VSS EXTERNAL INTERRUPT IRQ5 (INT5-8) NOISE FILTER NORMAL INPUT Figure 1-6. Pin Circuit Type 3 (Ports 2.0-2.3) 1-8 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PRODUCT OVERVIEW VDD PULL-UP RESISTOR (Typical 21 K) PULL-UP ENABLE VDD DATA I/O OPEN-DRAIN OUTPUT DISABLE VSS NORMAL INPUT Figure 1-7. Pin Circuit Type 4 (P2.4-P2.7) - 1-9 PRODUCT OVERVIEW S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) VDD PULL-UP RESISTOR (Typical 21 K) PULL-UP ENABLE SELECT VDD PORT 3 DATA ALTERNATIVE OUTPUT M U X DATA I/O OPEN-DRAIN OUTPUT DISABLE VSS NORMAL INPUT ALTERNATIVE INPUT NOISE FILTER Figure 1-8. Pin Circuit Type 5 (P 3) BACK-UP MODE RESET/ BACK-UP MODE NOISE FILTER SYSTEM RESET Figure 1-9. Pin Circuit Type 6 (RESET BACK-UP MODE) RESET/BACK-UP MODE 1-10 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) ELECTRICAL DATA 14 OVERVIEW ELECTRICAL DATA In this section, the S3C80E5/C80E7 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- D.C. electrical characteristics -- Characteristics of low voltage detect circuit -- Data retention supply voltage in Stop mode -- Stop mode release timing when initiated by an external interrupt -- Stop mode release timing when initiated by a RESET -- Stop mode release timing when initiated by a LVD -- I/O capacitance -- A.C. electrical characteristics -- Input timing for external interrupts (port 0, P2.3-P2.0) -- Input timing for RESET -- Oscillation characteristics -- Oscillation stabilization time -- Operating voltage range 14-1 ELECTRICAL DATA S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) Table 14-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Output voltage Output current High Symbol VDD VIN VO I OH I OL All output pins One I/O pin active All I/O pins active Output current Low One I/O pin active Total pin current for ports 0, 1, and 2 Total pin current for port 3 Operating temperature Storage temperature TA TSTG - - Conditions - - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 18 - 60 + 30 + 100 + 40 - 40 to + 85 - 65 to + 150 C C Unit V V V mA mA Table 14-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Operating Voltage Symbol VDD Conditions f OSC = 8 MHz (Instruction clock = 1.33 MHz) f OSC = 4 MHz (Instruction clock = 0.67 MHz) Input High voltage VIH1 VIH2 VIH3 Input Low voltage VIL1 VIL2 VIL3 Output High voltage VOH1 VOH2 All input pins except VIH2 and VIH3 RESET XIN All input pins except VIL2 and VIL3 RESET XIN Port 3.1 only; TA = 25 C Port 3.0 only; TA = 25 C VDD = 2.4 V; IOH = - 6 mA VDD = 2.4 V; IOH = - 3 mA VDD - 0.7 VDD - 0.7 - Min 2.1 2.0 0.8 VDD 0.85 VDD VDD - 0.3 0 - Typ - - - Max 5.5 5.5 VDD VDD VDD 0.2 VDD 0.4 VDD 0.3 - V V V Unit V 14-2 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) ELECTRICAL DATA Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Output High voltage Symbol VOH3 Conditions Port 2.7 only; TA = 25C VDD = 5 V; IOH = - 3 mA VDD = 2 V; IOH = - 1 mA Port 2.7 only; TA = 25C VOH4 VDD = 3.0 V; IOH = - 1 mA All output pins except P3 and P2.7 port; TA = 25C Port 3.1 only; TA = 25C VDD = 2.4 V; IOL = 5 mA IOL = 1 mA VDD = 2.4 V; IOL = 15 mA VDD - 1 Min VDD - 0.25 Typ - Max - Unit V Output Low voltage VOL1 VOL2 VOL3 - 0.4 0.4 0.4 0.5 0.5 1 1 20 V Port 3.0 only; TA = 25C Port 0, 1, and 2; TA = 25C VIN = VDD All input pins except XIN and XOUT VIN = VDD, XIN, and XOUT VIN = 0 V All input pins except XIN, XOUT, and RESET VIN = 0 V XIN and XOUT VOUT = VDD All output pins VOUT = 0 V All output pins TA = 25 C; Ports 0-3 VDD = 5.5 V VIN = 0 V; VDD = 2.4 V - - 44 15 - - 55 21 - - - - A Input High leakage current ILIH1 ILIH2 Input Low leakage current ILIL1 -1 A ILIL2 Output High leakage current Output Low leakage current Pull-up resistors ILOH ILOL RL1 - 20 1 -1 82 32 A A k 14-3 ELECTRICAL DATA S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) Table 14-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 2 V to 5.5 V) Parameter Supply current (note) Symbol IDD1 Conditions Operating mode VDD = 5 V 10 % 8 MHz crystal 4 MHz crystal IDD2 Idle mode VDD = 5 V 10 % 8 MHz crystal 4 MHz crystal IDD3 Stop mode VDD = 6.0 V VDD = 5.5 V VDD = 3.3 V VDD = 0.7 V Min - Typ 6 Max 11 Unit mA 4.5 1.8 9 3.5 1.6 20 18 12 1.0 3 35 25 15 1.5 A NOTE: Supply current does not include the current drawn through internal pull-up resistors or external output current loads. Table 14-3. Characteristics of Low Voltage Detect Circuit (TA = - 40 C to + 85 C) Parameter Hysteresys Voltage of LVD(Slew Rate of LVD) Low level detect voltage Symbol V VLVD Conditions LVDCON = 10001111B LVDCON = 10001111B Min - 2.10 Typ 10 2.20 Max 100 2.40 Unit mV V NOTE: The reset values of bit 1 and bit 0 are in a unknown status, so is recommended to input the value #8FH in LVDCON for typical VLVD (2.2 V -100/+200 mV). Table 14-4. Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions - VDDDR = 1.0 V Stop mode Min 1.0 - Typ - - Max 5.5 1 Unit V A 14-4 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) ELECTRICAL DATA IDLE MODE (Basic Timer active) STOP MODE DATA RETENTION MODE VDD NORMAL OPERATING MODE ~ ~ ~ ~ VDD > VLVD EXECUTION OF STOP INSTRUCTION EXT INT 0.2 V DD t WAIT 0.8 V DD Figure 14-1. Stop Mode Release Timing When Initiated by an External Interrupt RESET OCCURS STOP MODE DATA RETENTION MODE VDD OSCILLATION STABILIZATION TIME NORMAL OPERATING MODE ~ ~ ~ ~ VDD > VLVD EXECUTION OF STOP INSTRUCTION RESET NOTE: t WAIT is the same as 4096 x 16 x 1/f OSC. t WAIT Figure 14-2. Stop Mode Release Timing When Initiated by a RESET 14-5 ELECTRICAL DATA S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) RESET OCCUR OSCILLATION STABILIZATION NORMAL OPERATING MODE ~ ~ STOP MODE BACK-UP MODE VDD VLVD ~ ~ ~ ~ VDDDR EXECUTION OF STOP INSTRUCTION DATA RETENTION MODE t WAIT NOTE: t WAIT is the same as 4096 x 16 x 1/f OSC. Figure 14-3. Stop Mode Release Timing When Initiated by a LVD Table 14-5. Input/output Capacitance (TA = - 40 C to + 85 C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are connected to VSS Min - Typ - Max 10 Unit pF Table 14-6. A.C. Electrical Characteristics (TA = - 40 C to + 85 C) Parameter Interrupt input, High, Low width RESET input Low width Symbol tINTH, tINTL tRSL Conditions P0.0-P0.7, P2.3-P2.0 VDD = 5 V Input VDD = 5 V Min 200 1000 Typ 300 - Max - - Unit ns 14-6 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) ELECTRICAL DATA t INTL t INTH 0.8 V DD 0.2 V DD NOTE: The unit t CPU means one CPU clock period. Figure 14-4. Input Timing for External Interrupts (Port 0, P2.3-P2.0) NORMAL OPERATING MODE RESET OCCRURRS OSCILLATION STABILIZATION TIME NORMAL OPERATING MODE Back-Up Mode (STOP MODE) VDD RESET t WAIT NOTE: t WAIT is the same as 4096 x 16 x 1/f OSC. Figure 14-5. Input Timing for RESET 14-7 ELECTRICAL DATA S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) Table 14-7. Oscillation Characteristics (TA = - 40 C + 85 C) Oscillator Crystal Clock Circuit C1 Conditions CPU clock oscillation frequency Min 1 Typ - Max 8 Unit MHz XIN XOUT C2 Ceramic C1 XIN XOUT C2 CPU clock oscillation frequency 1 - 8 MHz External clock EXTERNAL CLOCK OPEN PIN XIN S3C80E5 S3C80E7 XIN input frequency 1 - 8 MHz XOUT Table 14-8. Oscillation Stabilization Time (TA = - 40 C + 85 C, VDD = 4.5 V to 5.5 V) Oscillator Main crystal Main ceramic External clock (main system) Oscillator stabilization Wait time f OSC > 400 kHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input High and Low width (tXH, tXL) tWAIT when released by a reset (1) tWAIT when released by an interrupt (2) Test Condition Min - - 25 - - Typ - - - 216/fOSC - Max 20 10 500 - - Unit ms ms ns ms ms NOTES: 1. fOSC is the oscillator frequency. 2. The duration of the oscillation stabilization time (tWAIT) when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON. 14-8 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) ELECTRICAL DATA INSTRUCTION CLOCK 1.33 MHz f OSC (Main oscillation frequency) 8 MHz 6 MHz 4 MHz 1.00 MHz 670 kHz 500 kHz 250 kHz 8.32 kHz 1 2 3 4 5 6 7 400 kHz 2.1 SUPPLY VOLTAGE (V) 5.5 INSTRUCTION CL OCK = 1/6n x oscillator frequency (n = 1, 2, 8, 16) Figure 14-6. Operating Voltage Range of S3P80E5/P80E7 14-9 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) MECHANICAL DATA 15 OVERVIEW 12.00 0.2 MECHANICAL DATA The S3C80E5/C80E7 microcontroller is currently available in 32-pin SOP and SDIP package. The S3C80E7 is also available in 40 DIP package. 0-8 #32 #17 10.02 0.1 +0.10 - 0.05 8.34 0.2 32-SOP-450A #1 #16 0.25 2.00 0.1 19.90 0.05 (0.43) 0.40 0.1 1.27 NOTE: Dimensions are in millimeters. Figure 15-1. 32-Pin SOP Package Mechanical Data 0.05 MIN 2.30MAX 0.10 MAX 0.90 0.20 15-1 MECHANICAL DATA S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) #32 #17 0 - 15 * 9.10 0.20 10.16 32-SDIP-400 #1 29.80 MAX 29.40 0.2 #16 3.80 0.2 5.08MAX (1.37) 1.00 0.10 1.778 NOTE: Dimensions are in millimeters. Figure 15-2. 32-Pin SDIP Package Mechanical Data 15-2 0.51MIN 0.45 0.10 3.30 0.3 0.25 +0.1 - 0.0 5 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) MECHANICAL DATA #40 #21 #1 #20 NOTE: Dimensions are in millimeters. Figure 15-3. 40-Pin DIP Package Mechanical Data 3.30 (1.92) 1.27 0.1 0.3 2.54 0.3 MIN 4.10 0.2 52.42 0.2 5.08MAX 52.10 0.2 - +0 0.250.05 .1 13.80 0.2 40-DIP-600B 15.24 15-3 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) S3P80E5/P80E7 OTP 16 OVERVIEW S3P80E5/P80E7 OTP The S3P80E5/P80E7 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C80E5/C80E7microcontroller. It has an on-chip EPROM instead of a masked ROM. The S3P80E5/P80E7 is fully compatible with the S3C80E5/C80E7, both in function and in pin configuration. Because of its simple programming requirements, the S3P80E5/P80E7 is ideal as an evaluation chip for the S3C80E5/C80E7. VSS XIN A14 (2) /XOUT MODE/TEST PGM/P2.0/INT5 MEM_REG/P2.1/INT6 A8/P2.2/INT7 A9/P2.3/INT8 A0/P0.0/INT0 A1/P0.1/INT1 A2/P0.2/INT2 A3/P0.3/INT3 A4/P0.4/INT4 A5/P0.5/INT4 A6/P0.6/INT4 A7/P0.7/INT4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 S3P80E5 26 S3P80E7 32-SOP/SDIP 25 24 (Top View) 23 22 21 20 19 18 17 VDD RESET/VPP P3.1/REM/T0CK/ CE P3.0/T0PWM/T0CAP/T1CAP/ OE P2.7/ A13 P2.6/ A12 P2.5/ A11 P2.4/ A10 P1.7/ D7 P1.6/ D6 P1.5/ D5 P1.4/ D4 P1.3/ D3 P1.2/ D2 P1.1/ D1 P1.0/ D0 NOTES: 1. The bolds indicate an OTP pin name. 2. The address line 14 (A14) be used only for S3P80E7. Figure 16-1. S3P80E5/P80E7 Pin Assignments of 32SOP/32SDIP 16-1 S3P80E5/P80E7 OTP S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) VSS XIN A14/XOUT MODE/TEST NC NC PGM/P2.0/INT5 MEM_REG/P2.1/INT6 A8/P2.2/INT7 A9/P2.3/INT8 A0/P0.0/INT0 A1/P0.1/INT1 A2/P0.2/INT2 A3/P0.3/INT3 NC NC A4/P0.4/INT4 A5/P0.5/INT4 A6/P0.6/INT4 A7/P0.7/INT4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S3P80E5 S3P80E7 40-DIP (Top View) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD RESET/VPP P3.1/REM/T0CK/ CE P3.0/T0PWM/T0CAP/T1CAP/OE NC NC P2.7/A13 P2.6/A12 P2.5/A11 P2.4/A10 P1.7/D7 P1.6/D6 P1.5/D5 P1.4/D4 NC NC P1.3/D3 P1.2/D2 P1.1/D1 P1.0/D0 NOTES: 1. The bolds indicate an OTP pin name. 2. The address line 14 (A14) be used only for S3P80E7. Figure 16-2. S3P80E5/P80E7 Pin Assignments of 40DIP 16-2 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) S3P80E5/P80E7 OTP Table 16-1. 32 SOP/SDIP Pin Descriptions Used to Read/Write the EPROM Pin Name A0-A14 D0-D7 MODE CE OE PGM MEM_REG VDD VPP VSS XIN Pin No. 3, 7- 6, 25-28 17-24 4 30 29 5 6 32 31 1 2 I/O O I/O - I I I I - - - - Function Address lines to read/write EPROM 8-bit data input/output lines to read/write EPROM Select EPROM mode. Chip enable (Connect to VSS, when read/write EPROM) Output enable EPROM Program enable Select Memory space of EPROM Supply voltage (normally 5 V) EPROM Program/Verify voltage (normally 12.5 V) GROUND System Clock input pin CHARACTERISTICS OF EPROM OPERATION When +12.5 V is supplied to VPP and MODE pins of the S3P80E5/P80E7, the EPROM programming mode is entered. The operating mode (read, write) is selected according to the input signals to the pins listed in Table 162 as below. Table 16-2. Operating Mode Selection Criteria VDD 5V MODE VPP VPP 12.5 V PGM 1 0 1 NOTE: "0" means Low level; "1" means High level. MEM 1 1 1 OE 0 1 0 READ PROGRAM Mode PROGRAM VERIFY 16-3 S3P80E5/P80E7 OTP S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) A14- A0 - t OED D7- D0 - t ACC OE t OEW 12.5V MODE t OEH Figure 16-3. OTP Read Timing Table 16-3. OTP Read Characteristics (TA = 25 C 5 C, VDD = 5 V 5 %, VPP = 12.5 V 0.25V) Parameter Address to Output Delay OE to Address Delay OE Pulse Width Output hold from OE whichever occurs first Symbol tACC tOED tOEW TOEH Min - 0 75 0 Typ - - - - Max 75 - - - Units ns 16-4 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) S3P80E5/P80E7 OTP PROGRAM A14- A0 - PROGRAM VERIFY D7- D0 - Data In Stable t DS Data Out Valid t OEH MODE t VS t DH PGM t PW OE t OE t OEW Figure 16-4. Program Memory Write Timing Table 16-4. OTP Program/Program Verify Characteristics (TA = 25 C 5 C, VDD = 5 V 5 %, VPP = 12.5 V 0.25 V) Parameter VPP Setup Time Data Setup Time Data Hold Time PGM Pulse Width Data Valid from OE OE Pulse Width Output Enable to Output Float Delay Symbol tVS tDS tDH tPW tOE tOEW tOEH Min - - - - 75 75 0 Typ 2 2 2 300 - - - Max - - - 500 - - 130 ns Units s 16-5 S3P80E5/P80E7 OTP S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) START Address= First Location VDD =5V, V PP=12.5V x= 0 Program One 1ms Pulse Increment X YES x = 10 NO FAIL Verify Byte Verify 1 Byte FAIL Last Address NO Increment Address VDD = VPP= 5 V FAIL Compare All Byte PASS Device Failed Device Passed Figure 16-5. OTP Programming Algorithm 16-6 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) S3P80E5/P80E7 OTP Table 16-5. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Operating Voltage Symbol VDD Conditions f OSC = 8 MHz (Instruction clock = 1.33 MHz) f OSC = 4 MHz (Instruction clock = 0.67 MHz) Input High voltage VIH1 VIH2 VIH3 Input Low voltage VIL1 VIL2 VIL3 Output High voltage VOH1 VOH2 Output High voltage VOH3 All input pins except VIH2 and VIH3 RESET XIN All input pins except VIL2 and VIL3 RESET XIN Port 3.1 only; TA = 25 C Port 3.0 only; TA = 25 C Port 2.7 only; TA = 25 C VDD = 2.4 V; IOH = - 6 Ma VDD - 0.7 VDD - 0.7 VDD - 0.25 - - V - Min 2.1 2.0 0.8 VDD 0.85 VDD VDD - 0.3 0 - Typ - - - Max 5.5 5.5 VDD VDD VDD 0.2 VDD 0.4 VDD 0.3 - V V V Unit V VDD = 2.4 V; IOH = - 3 mA VDD = 5 V; IOH = - 3 mA VDD = 2 V; IOH = - 1 mA Port 2.7 only; TA = 25 C VOH4 VDD = 3.0 V; IOH = - 1 mA All output pins except P3 and P2.7 port; TA = 25 C VDD = 2.4 V; IOL = 15 mA Port 3.1 only; TA = 25 C Port 3.0 only; TA = 25 C IOL = 1 mA 0.4 - - 1 1 20 A Port 0, 1, and 2; TA = 25 C VIN = VDD All input pins except XIN and XOUT VIN = VDD, XIN, and XOUT VDD = 2.4 V; IOL = 5 mA VDD - 1 Output Low voltage VOL1 VOL2 VOL3 - 0.4 0.4 0.5 0.5 V Input High leakage current ILIH1 ILIH2 16-7 S3P80E5/P80E7 OTP S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) Table 16-5. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Input Low leakage current Symbol ILIL1 Conditions VIN = 0 V All input pins except XIN, XOUT, and RESET VIN = 0 V XIN and XOUT VOUT = VDD All output pins VOUT = 0 V All output pins TA = 25 C; Ports 0-3 VDD = 5.5 V Supply current (note) Min - Typ - Max -1 Unit A ILIL2 Output High leakage current Output Low leakage current Pull-up resistors ILOH ILOL RL1 - 20 - - 44 15 - - - 55 21 6 1 -1 82 32 11 mA A A k VIN = 0 V; VDD = 2.4 V IDD1 Operating mode VDD = 5 V 10 % 8 MHz crystal 4 MHz crystal Idle mode VDD = 5 V 10 % 8 MHz crystal 4 MHz crystal Stop mode; VDD = 6.0 V VDD = 5.5 V VDD = 3.3 V VDD = 0.7 V 4.5 1.8 9 3.5 IDD2 1.6 20 18 12 1.0 3 35 25 15 1.5 A IDD3 NOTE: Supply current does not include the current drawn through internal pull-up resistors or external output current loads. 16-8 S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) S3P80E5/P80E7 OTP INSTRUCTION CLOCK 1.33 MHz f OSC (Main oscillation frequency) 8 MHz 6 MHz 4 MHz 1.00 MHz 670 kHz 500 kHz 250 kHz 8.32 kHz 1 2 3 4 5 6 7 400 kHz 2.1 SUPPLY VOLTAGE (V) 5.5 INSTRUCTION CL OCK = 1/6n x oscillator frequency (n = 1, 2, 8, 16) Figure 16-6. Operating Voltage Range 16-9 |
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