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INTEGRATED CIRCUITS
74ALVCH16841 20-bit bus interface D-type latch (3-State)
Product specification IC24 Data Handbook 1998 Jul 27
Philips Semiconductors
Philips Semiconductors
Product specification
20-bit bus interface D-type latch (3-State)
74ALVCH16841
FEATURES
* Wide supply voltage range of 1.2V to 3.6V * Complies with JEDEC standard no. 8-1A * Wide supply voltage range of 1.2V to 3.6V * CMOS low power consumption * Direct interface with TTL levels * MULTIBYTETM flow-through standard pin-out architecture * Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
PIN CONFIGURATION
1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1Q6 GND 1Q7 1Q8 1Q9 2Q0 2Q1 2Q2 GND 2Q3 2Q4 2Q5 VCC 2Q6 2Q7 GND 2Q8 2Q9 2OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1LE 1D0 1D1 GND 1D2 1D3 VCC 1D4 1D5 1D6 GND 1D7 1D8 1D9 2D0 2D1 2D2 GND 2D3 2D4 2D5 VCC 2D6 2D7 GND 2D8 2D9 2LE
* Current drive 24 mA at 3.0 V * All inputs have bus hold circuitry * Output drive capability 50 transmission lines @ 85C * 3-State non-inverting outputs for bus oriented applications
DESCRIPTION
The 74ALVCH16841 has two 10-bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE) and output enable (nOE) control gates. When nOE is LOW, the data in the registers appears at the outputs. When nOE is High the outputs are in High-impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops. The 74ALVCH16841 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.
SA00076
QUICK REFERENCE DATA
GND = 0V; Tamb = 25C; tr = tf 2.5ns PARAMETER SYMBOL Propagation delay tPHL/tPLH nDn to nQn Propagation delay tPHL/tPLH nLE to nQn CI Input capacitance CPD Power dissipation capacitance per buffer dissi ation ca acitance er CONDITIONS VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF VI = GND to VCC1 Outputs enabled Outputs disabled TYPICAL 2.5 2.4 2.5 2.4 5.0 19 3 UNIT ns ns pF pF F
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE -40C to +85C OUTSIDE NORTH AMERICA 74ALVCH16841 DGG NORTH AMERICA ACH16841 DGG DWG NUMBER SOT364-1
1998 Jul 27
2
853-2093 19785
Philips Semiconductors
Product specification
20-bit bus interface D-type latch (3-State)
74ALVCH16841
PIN DESCRIPTION
PIN NUMBER 1 56 55, 54, 52, 51, 49, 48, 47, 45, 44, 43 2, 3, 5, 6, 8, 9, 10, 12, 13, 14 4, 11, 18, 25, 32, 39, 46, 53 7, 22, 35, 50 28 29 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 SYMBOL 1OE 1LE 1D0 - 1D9 1Q0 - 1Q9 GND VCC 2OE 2LE 2D0 - 2D9 2Q0 - 2Q9 FUNCTION Output enable inputs (active-LOW) Latch enable inputs (active HIGH) Data inputs
LOGIC SYMBOL (IEEE/IEC)
1OE 1LE 2OE 2LE 1D0 1 56 28 29 55 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 30 3D 4 EN2 C1 EN4 C3 1D 2 2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 27 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
Data outputs Ground (0V) Positive supply voltage Output enable inputs (active-LOW) Latch enable inputs (active HIGH) Data inputs Data outputs
1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 2D0 2D1 2D2 2D3
FUNCTION TABLE
INPUTS nOE L L L H L X Z = = = = LE H H L Dx L H X OUTPUT Q L H Q0 Z
2D4 2D5 2D6 2D7 2D8 2D9
SH00152
H X X High voltage level Low voltage level Don't care High impedance "off" state
LOGIC DIAGRAM
nD0
LOGIC SYMBOL
55 54 52 51 49 48 47 45 44 43
D
1D0 1D1 1D2 1D3 1D4 1D5 1D6 56 1 1LE 1OE
1D7 1D8
1D9
LE
nLE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 nOE 2 42 3 41 5 40 6 38 8 37 9 36 10 34 12 33 13 31 14 nQ0 30
SH00151
2D0 2D1 2D2 2D3 2D4 2D5 2D6 29 28 2LE 2OE
2D7 2D8
2D9
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
15
16
17
19
20
21
23
24
26
27
SH00023
1998 Jul 27
3
Philips Semiconductors
Product specification
20-bit bus interface D-type latch (3-State)
74ALVCH16841
BUS HOLD CIRCUIT
VCC
Data Input
To internal circuit
SW00044
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER DC supply voltage 2.5V range (for max. speed performance @ 30 pF output load) VCC DC supply voltage 3.3V range (for max. speed performance @ 50 pF output load) DC Input voltage range DC output voltage range Operating free-air temperature range Input rise and fall times VCC = 2.3 to 3.0V VCC = 3.0 to 3.6V CONDITIONS MIN 2.3 3.0 0 0 -40 0 0 MAX 2.7 V 3.6 VCC VCC +85 20 10 V V C ns/V UNIT
VI VO Tamb tr, tf
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC in ut voltage input DC output diode current DC output voltage DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package -plastic medium-shrink (SSOP) -plastic thin-medium-shrink (TSSOP) For temperature range: -40 to +125 C above +55C derate linearly with 11.3 mW/K above +55C derate linearly with 8 mW/K VI t0 For control pins1 For data inputs1 VO uVCC or VO t 0 Note 1 VO = 0 to VCC CONDITIONS RATING -0.5 to +4.6 -50 -0.5 to +4.6 -0.5 to VCC +0.5 "50 -0.5 to VCC +0.5 "50 "100 -65 to +150 850 600 V mA V mA mA C mW UNIT V mA
NOTE: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jul 27
4
Philips Semiconductors
Product specification
20-bit bus interface D-type latch (3-State)
74ALVCH16841
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIH HIGH level Input voltage VCC = 2.3 to 2.7V VCC = 2.7 to 3.6V LOW level Input voltage VCC = 2.3 to 2.7V VCC = 2.7 to 3.6V VCC = 2 3 to 3 6V; VI = VIH or VIL; IO = -100A 100A 2.3 3.6V; VCC = 2.3V; VI = VIH or VIL; IO = -6mA VO OH HIGH level output voltage VCC = 2.3V; VI = VIH or VIL; IO = -12mA VCC = 2.7V; VI = VIH or VIL; IO = -12mA VCC = 3.0V; VI = VIH or VIL; IO = -12mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2 3 to 3 6V; VI = VIH or VIL; IO = 100A 2.3 3.6V; VCC = 2.3V; VI = VIH or VIL; IO = 6mA VOL LOW level output voltage VCC = 2.3V; VI = VIH or VIL; IO = 12mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VCC = 3.0V; VI = VIH or VIL; IO = 24mA II IOZ ICC ICC IBHL2 IBHH2 IBHLO2 IBHHO2 Input leakage current g 3-State output OFF-state current Quiescent supply current Additional quiescent supply current Bus hold LOW sustaining current Bus hold HIGH sustaining current Bus hold LOW overdrive current Bus hold HIGH overdrive current VCC = 2 3 to 3 6V; 2.3 3.6V; VI = VCC or GND VCC = 2.3 to 3.6V; VI = VIH or VIL; VO = VCC or GND VCC = 2.3 to 3.6V; VI = VCC or GND; IO = 0 VCC = 2.3V to 3.6V; VI = VCC - 0.6V; IO = 0 VCC = 2.3V; VI = 0.7V VCC = 3.0V; VI = 0.8V VCC = 2.3V; VI = 1.7V VCC = 3.0V; VI = 2.0V VCC = 3.6V VCC = 3.6V 45 75 -45 -75 500 -500 -175 VCC*0.2 02 VCC*0.3 VCC*0.6 VCC*0.5 VCC*0.6 VCC*1.0 1.7 2.0 TYP1 1.2 V 1.5 1.2 1.5 VCC VCC*0.08 VCC*0.26 VCC*0.14 VCC*0.09 VCC*0.28 GND 0.07 0.15 0.14 0.27 0.1 0.1 0.2 150 - 150 0.20 0 20 0.40 0.70 0.40 0.55 5 10 40 750 A A A A A A A A V V V V 0.7 V 0.8 MAX UNIT
VIL
NOTES: 1. All typical values are at Tamb = 25C. 2. Valid for data inputs of bus hold parts.
1998 Jul 27
5
Philips Semiconductors
Product specification
20-bit bus interface D-type latch (3-State)
74ALVCH16841
AC CHARACTERISTICS FOR VCC = 2.3V TO 2.7V RANGE
GND = 0V; tr = tf 2.0ns; CL = 30pF SYMBOL LIMITS PARAMETER Propagation delay nDn to nQn Propagation delay nLE to nQn 3-State output enable time nOEn to nQn 3-State output disable time nOEn to nQn nLE pulse width HIGH Set up time nDn to nLE Hold time nDn to nLE WAVEFORM MIN tPLH/tPHL tPLH/tPHL tPZH/tPZL tPHZ/tPLZ tW tSU Th 1, 5 2, 5 4, 5 4, 5 2, 5 3, 5 3, 5 1.0 1.0 1.0 1.1 3.3 1.3 1.4 VCC = 2.3 to 2.7V TYP1 2.5 2.5 2.7 2.2 1.5 0.1 0.3 MAX 5.0 5.6 6.2 5.3 - - - ns ns ns ns ns ns ns UNIT
NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V
GND = 0V; tr = tf 2.5ns; CL = 50pF SYMBOL LIMITS PARAMETER Propagation delay nDn to nQn Propagation delay nLE to nQn 3-State output enable time nOEn to nQn 3-State output disable time nOEn to nQn nLE pulse width HIGH Set up time nDn to nLE Hold time nDn to nLE WAVEFORM MIN tPLH/tPHL tPLH/tPHL tPZH/tPZL tPHZ/tPLZ tW tSU th 1, 5 2, 5 4, 5 4, 5 2, 5 3, 5 3, 5 1.0 1.0 1.0 1.3 3.3 1.0 1.4 VCC = 3.3 0.3V TYP1, 2 2.4 2.4 2.3 2.9 1.5 0.6 0.2 MAX 3.9 4.3 4.9 4.1 - - - MIN 1.0 1.0 1.0 1.3 3.3 1.1 1.7 LIMITS VCC = 2.7V TYP1 2.6 2.6 3.1 3.1 1.5 0.1 0.2 MAX 4.7 5.1 6.0 4.3 - - - ns ns ns ns ns ns ns UNIT
NOTES: 1. All typical values are measured Tamb = 25C. 2. Typical value is measured at VCC = 3.3V
1998 Jul 27
6
Philips Semiconductors
Product specification
20-bit bus interface D-type latch (3-State)
74ALVCH16841
AC WAVEFORMS FOR VCC = 2.3V TO 2.7V AND VCC < 2.3V RANGE
VM = 0.5 VCC VX = VOL + 0.15V VY = VOH -0.15V VOL and VOH are the typical output voltage drop that occur with the output load.
VI nOE INPUT GND VM
tPLZ
tPZL
AC WAVEFORMS FOR VCC = 3.0V TO 3.6V AND VCC = 2.7V RANGE
VM = 1.5 V VX = VOL + 0.3V VY = VOH -0.3V VOL and VOH are the typical output voltage drop that occur with the output load. V = 2.7V I V =V I CC
VI Dn INPUT GND tPHL VOH Qn OUTPUT VOL VM tPLH VM
VCC OUTPUT LOW-to-OFF OFF-to-LOW VX VOL tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled VY VM tPZH VM
SH00137
Waveform 4. 3-State enable and disable times
TEST CIRCUIT
VCC S1 2 * VCC Open GND
SH00153
Waveform 1. The input (Dn) to output (Qn) propagation delay
VI PULSE GENERATOR VI LE INPUT GND VM tW VM RT CL D.U.T. VO
RL = 500
RL = 500
tPHL
VOH Qn OUTPUT VOL VM
tPLH
Test Circuit for switching times DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators.
SH00150
SWITCH POSITION
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 < VCC
GND
Waveform 2. The latch enable (LE) pulse width, the latch enable input to output (Qn) propagation delay
VCC < 2.7V 2.7-3.6V
VI VCC 2.7V
VI Dn INPUT
GND
VI LE INPUT
GND NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 3. The data set up and hold times for the Dn input to the LE input
1998 Jul 27
EEEEEEEEE EEE E EEE E EEEEEEEEE EEE EEEEEEE EEE
VM th th tSU tSU VM
SV00906
Waveform 5. Load circuitry for switching times
SH00149
7
Philips Semiconductors
Product specification
20-bit bus interface D-type latch (3-State)
74ALVCH16841
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
1998 Jul 27
8
Philips Semiconductors
Product specification
20-bit bus interface D-type latch (3-State)
74ALVCH16841
NOTES
1998 Jul 27
9
Philips Semiconductors
Product specification
20-bit bus interface D-type latch (3-State)
74ALVCH16841
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 07-98 9397-750-04561
Philips Semiconductors
1998 Jul 27 10

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