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Section I. Stratix Device Family Data Sheet
This section provides designers with the data sheet specifications for Stratix devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Stratix devices. This section contains the following chapters:

Chapter 1. Introduction Chapter 2. Stratix Architecture Chapter 3. Configuration & Testing Chapter 4. DC & Switching Characteristics Chapter 5. Reference & Ordering Information
Revision History
Chapter
1
The table below shows the revision history for Chapters 1 through 5.
Date/Version
January 2004, v2.2 October 2003, v2.1 July 2003, v2.0
Changes Made
Updated -5 speed grade device information in Table 1-6. Add -8 speed grade device information. Format changes throughout chapter.
Altera Corporation
Section I-1
Stratix Device Family Data Sheet
Stratix Device Handbook, Volume 1
Chapter
2
Date/Version
November 2003, v2.2

Changes Made
Added 672-pin BGA package information in Table 2-37. Removed support for series and parallel on-chip termination. Termination Technology renamed differential on-chip termination. Updated the number of channels per PLL in Tables 2-37, 2-38, 2-39, 2-40, and 2-41. Updated Figures 2-65 and 2-66. Updated DDR I information. Updated Table 2-23. Added Tables 2-26, 2-29, 2-30, and 2-77. Updated Figures 2-59, 2-65, and 2-66. Updated the Lock Detect section. Added reference on page 2-73 to Figures 2-50 and 2-51 for RCLK connections Updated ranges for EPLL post-scale and pre-scale dividers on page 2-85 Updated PLL Reconfiguration frequency from 25 to 22 MHz on page 2-87 New requirement to assert areset signal each PLL when it has to re-acquire lock on either a new clock after loss of lock (page 2-96) Updated max input frequency for CLK[1,3,8,10] from 462 to 500 Table 2-24 Renamed impedance matching to series termination throughout. Updated naming convention for DQS pins on page 2-112 to match pin Tables. Added DDR SDRAM Performance Specification on page 2-117. Added external reference resistor values for terminator technology (page 2136). Added Terminator Technology Specification on pages 2-137 and 2-138. Updated Tables 2-45 to 2-49 to reflect PLL cross-bank support for high speed differential channels at full speed. Wire bond package performance specification for "high" speed channels was increased to 624 Mbps from 462 Mbps throughout chapter. No new changes in Stratix Device Handbook v2.0.
October 2003, v2.1

July 2003, v2.0

3
April 2003, v1.0
Section I-2
Altera Corporation
Stratix Device Family Data Sheet
Chapter
4
Date/Version
November 2003, v2.2 October 2003, v2.1
Changes Made
Updated Tables 4-116, 4-117, 4-118. Added -8 speed grade information Updated performance information in Table 4-35. Updated timing information in Tables 4-52 through 4-93. Updated delay information in Tables 4-94 through 4-99. Updated programmable delay information in Tables 4-100 and 4-101. Updated clock rates in Tables 4-103 through 4-112. Updated speed grade information in the introduction on page 4-1. Corrected figures 4-1 & 4-2 and Table 4-9 to reflect how VID and VOD are specified. Added note 6 to Table 4-32. Updated Stratix Performance Table 4-35. Updated EP1S60 and EP1S80 timing parameters in Tables 4-82 to 4-93. The Stratix timing models are final for all devices. Updated Stratix IOE programmable delay chains in Tables 4-100 to 4-101. Added single-ended I/O standard output pin delay adders for loading in Table 4-102. Added spec for FPLL[10..7]CLK pins in Tables 4-104 and 4-107. Updated high-speed I/O specification for J=2 in Tables 4-114 and 4-115. Updated EPLL specification and fast PLL specification in Tables 4-116 to 4120. No new changes in Stratix Device Handbook v2.0.

July 2003, v2.0

5
April 2003, v1.0
Altera Corporation
Section I-3
Stratix Device Family Data Sheet
Stratix Device Handbook, Volume 1
Section I-4
Altera Corporation
1. Introduction
S51001-2.2
Introduction
The StratixTM family of FPGAs is based on a 1.5-V, 0.13-m, all-layer copper SRAM process, with densities up to 79,040 logic elements (LEs) and up to 7.5 Mbits of RAM. Stratix devices offer up to 22 digital signal processing (DSP) blocks with up to 176 (9-bit x 9-bit) embedded multipliers, optimized for DSP applications that enable efficient implementation of high-performance filters and multipliers. Stratix devices support various I/O standards and also offer a complete clock management solution with its hierarchical clock structure with up to 420-MHz performance and up to 12 phase-locked loops (PLLs). The following shows the main sections in the Stratix Device Family Data Sheet: Section Page
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 TriMatrix Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Digital Signal Processing Block . . . . . . . . . . . . . . . . . . . . . . . . 2-49 PLLs & Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71 I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-101 High-Speed Differential I/O Support. . . . . . . . . . . . . . . . . . 2-133 Power Sequencing & Hot Socketing . . . . . . . . . . . . . . . . . . . 2-144 IEEE Std. 1149.1 (JTAG) Boundary-Scan Support. . . . . . . . . . 3-1 SignalTap Embedded Logic Analyzer . . . . . . . . . . . . . . . . . . . 3-5 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Temperature Sensing Diode. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
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Features
Stratix Device Handbook, Volume 1
Features
The Stratix family offers the following features:

10,570 to 79,040 LEs; see Table 1-1 Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources TriMatrixTM memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers High-speed DSP blocks provide dedicated implementation of multipliers (at up to 250 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters Up to 16 global clocks with 22 clocking resources per device region Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting Support for numerous single-ended and differential I/O standards High-speed differential I/O support on up to 116 channels with up to 80 channels optimized for 840 megabits per second (Mbps) Support for high-speed networking and communications bus standards including RapidIO, UTOPIA IV, CSIX, HyperTransportTM technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4 Differential on-chip termination support for LVDS Support for high-speed external memory, including zero bus turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM), and single data rate (SDR) SDRAM Support for 66-MHz PCI (64 and 32 bit) in -6 and faster speed-grade devices, support for 33-MHz PCI (64 and 32 bit) in -8 and faster speed-grade devices Support for 133-MHz PCI-X in -5 speed-grade devices Support for 100-MHz PCI-X in -6 and faster speed-grade devices Support for 66-MHz PCI-X in -7 speed-grade devices Support for multiple intellectual property megafunctions from Altera MegaCore(R) functions and Altera Megafunction Partners Program (AMPPSM) megafunctions Support for remote configuration updates
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Altera Corporation January 2004
Introduction
Features
Table 1-1. Stratix Device Features -- EP1S10, EP1S20, EP1S25, EP1S30 Feature
LEs M512 RAM blocks (32 x 18 bits) M4K RAM blocks (128 x 36 bits) M-RAM blocks (4K x 144 bits) Total RAM bits DSP blocks Embedded multipliers (1) PLLs Maximum user I/O pins
EP1S10
10,570 94 60 1 920,448 6 48 6 426
EP1S20
18,460 194 82 2 1,669,248 10 80 6 586
EP1S25
25,660 224 138 2 1,944,576 10 80 6 706
EP1S30
32,470 295 171 4 3,317,184 12 96 10 726
Table 1-2. Stratix Device Features -- EP1S40, EP1S60, EP1S80 Feature
LEs M512 RAM blocks (32 x 18 bits) M4K RAM blocks (128 x 36 bits) M-RAM blocks (4K x 144 bits) Total RAM bits DSP blocks Embedded multipliers (1) PLLs Maximum user I/O pins Note to Tables 1-1 and 1-2:
(1)
EP1S40
41,250 384 183 4 3,423,744 14 112 12 822
EP1S60
57,120 574 292 6 5,215,104 18 144 12 1,022
EP1S80
79,040 767 364 9 7,427,520 22 176 12 1,238
This parameter lists the total number of 9 x 9-bit multipliers for each device. For the total number of 18 x 18-bit multipliers per device, divide the total number of 9 x 9-bit multipliers by 2. For the total number of 36 x 36-bit multipliers per device, divide the total number of 9 x 9-bit multipliers by 8.
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Features
Stratix Device Handbook, Volume 1
Stratix devices are available in space-saving FineLine BGATM and ballgrid array (BGA) packages (see Tables 1-3 through 1-5). All Stratix devices support vertical migration within the same package (e.g., the designer can migrate between the EP1S10, EP1S20, and EP1S25 devices in the 672-pin BGA package). Vertical migration means that designers can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. For I/O pin migration across densities, the designer must cross reference the available I/O pins using the device pin-outs for all planned densities of a given package type to identify which I/O pins are migratable. The Quartus(R) II software can automatically cross reference and place all pins except differential pins for migration when given a device migration list. The designer must use the pin-outs for each device to verify the differential placement migration. A future version of the Quartus II software will support differential pin migration.
Table 1-3. Stratix Package Options & I/O Pin Counts Device
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 Note to Table 1-3:
(1) All I/O pin counts include 20 dedicated clock input pins (clk[15.0]p, clk0n, clk2n, clk9n, and clk11n) that can be used for data inputs.
672-Pin BGA
345 426 473
956-Pin BGA
484-Pin FineLine BGA
335 361
672-Pin FineLine BGA
345 426 473
780-Pin FineLine BGA
426 586 597 597 615
1,020-Pin FineLine BGA
1,508-Pin FineLine BGA
706 726 773 773 773 822 1,022 1,203
683 683 683 683
Table 1-4. Stratix BGA Package Sizes Dimension
Pitch (mm) Area (mm2) Length x width (mm x mm)
672 Pin
1.27 1,225 35 x 35
956 Pin
1.27 1,600 40 x 40
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Introduction
Features
Table 1-5. Stratix FineLine BGA Package Sizes Dimension
Pitch (mm) Area (mm2) Length x width (mm x mm)
484 Pin
1.00 529 23 x 23
672 Pin
1.00 729 27 x 27
780 Pin
1.00 841 29 x 29
1,020 Pin
1.00 1,089 33 x 33
1,508 Pin
1.00 1,600 40 x 40
Stratix devices are available in up to four speed grades, -5, -6, -7, and -8, with -5 being the fastest. Table 1-6 shows Stratix device speed-grade offerings.
Table 1-6. Stratix Device Speed Grades Device
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 Note to Table 1-6:
(1) Contact Altera Applications for up to date information on availability for these devices.
672-Pin BGA
-6, -7 -6, -7 -6, -7
956-Pin BGA
484-Pin FineLine BGA
-5, -6, -7 -5, -6, -7
672-Pin FineLine BGA
-6, -7 -6, -7 -6, -7, -8
780-Pin FineLine BGA
-5, -6, -7 -5, -6, -7 -5, -6, -7 -5, -6, -7, -8 -5, -6, -7, -8
1,020-Pin FineLine BGA
1,508-Pin FineLine BGA
-5, -6, -7 -5, -6, -7 -5, -6, -7 -5, -6, -7 -5, -6, -7 -5, -6, -7 -6, -7 -6, -7
-5, -6, -7 -5, -6, -7 -6, -7 -6, -7
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Features
Stratix Device Handbook, Volume 1
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Altera Corporation January 2004
2. Stratix Architecture
S51002-2.2
Functional Description
Stratix devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provides signal interconnects between logic array blocks (LABs), memory block structures, and DSP blocks. The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 318 MHz. M512 blocks are grouped into columns across the device in between certain LABs. M4K RAM blocks are true dual-port memory blocks with 4K bits plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 291 MHz. These blocks are grouped into columns across the device in between certain LABs. M-RAM blocks are true dual-port memory blocks with 512K bits plus parity (589,824 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 144-bits wide at up to 269 MHz. Several M-RAM blocks are located individually or in pairs within the device's logic array. Digital signal processing (DSP) blocks can implement up to either eight full-precision 9 x 9-bit multipliers, four full-precision 18 x 18-bit multipliers, or one full-precision 36 x 36-bit multiplier with add or subtract features. These blocks also contain 18-bit input shift registers for digital signal processing applications, including FIR and infinite impulse response (IIR) filters. DSP blocks are grouped into two columns in each device. Each Stratix device I/O pin is fed by an I/O element (IOE) located at the end of LAB rows and columns around the periphery of the device. I/O pins support numerous single-ended and differential I/O standards. Each IOE contains a bidirectional I/O buffer and six registers for registering input, output, and output-enable signals. When used with
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Functional Description
Stratix Device Handbook, Volume 1
dedicated clocks, these registers provide exceptional performance and interface support with external memory devices such as DDR SDRAM, FCRAM, ZBT, and QDR SRAM devices. High-speed serial interface channels support transfers at up to 840 Mbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O standards. Figure 2-1 shows an overview of the Stratix device. Figure 2-1. Stratix Block Diagram
M512 RAM Blocks for Dual-Port Memory, Shift Registers, & FIFO Buffers DSP Blocks for Multiplication and Full Implementation of FIR Filters M4K RAM Blocks for True Dual-Port Memory & Other Embedded Memory Functions IOEs Support DDR, PCI, GTL+, SSTL-3, SSTL-2, HSTL, LVDS, LVPECL, PCML, HyperTransport & other I/O Standards
IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs
IOEs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs
IOEs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs
IOEs LABs LABs LABs LABs
M-RAM Block
LABs
DSP Block
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Stratix Architecture
Logic Array Blocks
The number of M512 RAM, M4K RAM, and DSP blocks varies by device along with row and column numbers and M-RAM blocks. Table 2-1 lists the resources available in Stratix devices.
Table 2-1. Stratix Device Resources Device
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
M512 RAM M4K RAM Columns/Blocks Columns/Blocks
4 / 94 6 / 194 6 / 224 7 / 295 8 / 384 10 / 574 11 / 767 2 / 60 2 / 82 3 / 138 3 / 171 3 / 183 4 / 292 4 / 364
M-RAM Blocks
1 2 2 4 4 6 9
DSP Block Columns/Blocks
2/6 2 / 10 2 / 10 2 / 12 2 / 14 2 / 18 2 / 22
LAB Columns
40 52 62 67 77 90 101
LAB Rows
30 41 46 57 61 73 91
Logic Array Blocks
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, local interconnect, LUT chain, and register chain connection lines. The local interconnect transfers signals between LEs in the same LAB. LUT chain connections transfer the output of one LE's LUT to the adjacent LE for fast sequential LUT connections within the same LAB. Register chain connections transfer the output of one LE's register to the adjacent LE's register within an LAB. The Quartus II Compiler places associated logic within an LAB or adjacent LABs, allowing the use of local, LUT chain, and register chain connections for performance and area efficiency. Figure 2-2 shows the Stratix LAB.
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Logic Array Blocks
Stratix Device Handbook, Volume 1
Figure 2-2. Stratix LAB Structure
Row Interconnects of Variable Speed & Length
Direct link interconnect from adjacent block
Direct link interconnect from adjacent block
Direct link interconnect to adjacent block
Direct link interconnect to adjacent block
Local Interconnect
LAB
Three-Sided Architecture--Local Interconnect is Driven from Either Side by Columns & LABs, & from Above by Rows
Column Interconnects of Variable Speed & Length
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, M512 RAM blocks, M4K RAM blocks, or DSP blocks from the left and right can also drive an LAB's local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can drive 30 other LEs through fast local and direct link interconnects. Figure 2-3 shows the direct link connection.
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Stratix Architecture
Logic Array Blocks
Figure 2-3. Direct Link Connection
Direct link interconnect from left LAB, TriMatrix memory block, DSP block, or IOE output Direct link interconnect from right LAB, TriMatrix memory block, DSP block, or IOE output
Direct link interconnect to left Local Interconnect LAB
Direct link interconnect to right
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its LEs. The control signals include two clocks, two clock enables, two asynchronous clears, synchronous clear, asynchronous preset/load, synchronous load, and add/subtract control signals. This gives a maximum of 10 control signals at a time. Although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. Each LAB can use two clocks and two clock enable signals. Each LAB's clock and clock enable signals are linked. For example, any LE in a particular LAB using the labclk1 signal will also use labclkena1. If the LAB uses both the rising and falling edges of a clock, it also uses both LAB-wide clock signals. De-asserting the clock enable signal will turn off the LAB-wide clock. Each LAB can use two asynchronous clear signals and an asynchronous load/preset signal. The asynchronous load acts as a preset when the asynchronous load data input is tied high.
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Stratix Device Handbook, Volume 1
With the LAB-wide addnsub control signal, a single LE can implement a one-bit adder and subtractor. This saves LE resources and improves performance for logic functions such as DSP correlators and signed multipliers that alternate between addition and subtraction depending on data. The LAB row clocks [7..0] and LAB local interconnect generate the LABwide control signals. The MultiTrackTM interconnect's inherent low skew allows clock and control signal distribution in addition to data. Figure 2-4 shows the LAB control signal generation circuit. Figure 2-4. LAB-Wide Control Signals
Dedicated Row LAB Clocks Local Interconnect Local Interconnect 8
Local Interconnect Local Interconnect Local Interconnect Local Interconnect labclk1
labclkena1
labclkena2
syncload
labclr2
addnsub
labclk2
asyncload or labpre
labclr1
synclr
Logic Elements
The smallest unit of logic in the Stratix architecture, the LE, is compact and provides advanced features with efficient logic utilization. Each LE contains a four-input LUT, which is a function generator that can implement any function of four variables. In addition, each LE contains a programmable register and carry chain with carry select capability. A single LE also supports dynamic single bit addition or subtraction mode selectable by an LAB-wide control signal. Each LE drives all types of interconnects: local, row, column, LUT chain, register chain, and direct link interconnects. See Figure 2-5.
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Logic Elements
Figure 2-5. Stratix LE
Register chain routing from previous LE LAB-wide Register Bypass Synchronous Load LAB-wide Packed Synchronous Register Select Clear
LAB Carry-In addnsub Carry-In1 Carry-In0
Programmable Register LUT chain routing to next LE Row, column, and direct link routing
data1 data2 data3 data4
ENA CLRN
Look-Up Table (LUT)
Carry Chain
Synchronous Load and Clear Logic
PRN/ALD D Q ADATA
Row, column, and direct link routing
labclr1 labclr2 labpre/aload Chip-Wide Reset
Asynchronous Clear/Preset/ Load Logic
Local Routing
Clock & Clock Enable Select labclk1 labclk2 labclkena1 labclkena2
Register Feedback
Register chain output
Carry-Out0 Carry-Out1 LAB Carry-Out
Each LE's programmable register can be configured for D, T, JK, or SR operation. Each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. Global signals, general-purpose I/O pins, or any internal logic can drive the register's clock and clear control signals. Either general-purpose I/O pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous data. The asynchronous load data input comes from the data3 input of the LE. For combinatorial functions, the register is bypassed and the output of the LUT drives directly to the outputs of the LE. Each LE has three outputs that drive the local, row, and column routing resources. The LUT or register output can drive these three outputs independently. Two LE outputs drive column or row and direct link routing connections and one drives local interconnect resources. This allows the LUT to drive one output while the register drives another output. This feature, called register packing, improves device utilization because the device can use the register and the LUT for unrelated
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functions. Another special packing mode allows the register output to feed back into the LUT of the same LE so that the register is packed with its own fan-out LUT. This provides another mechanism for improved fitting. The LE can also drive out registered and unregistered versions of the LUT output.
LUT Chain & Register Chain
In addition to the three general routing outputs, the LEs within an LAB have LUT chain and register chain outputs. LUT chain connections allow LUTs within the same LAB to cascade together for wide input functions. Register chain outputs allow registers within the same LAB to cascade together. The register chain output allows an LAB to use LUTs for a single combinatorial function and the registers to be used for an unrelated shift register implementation. These resources speed up connections between LABs while saving local interconnect resources. See "MultiTrack Interconnect" on page 2-14 for more information on LUT chain and register chain connections.
addnsub Signal
The LE's dynamic adder/subtractor feature saves logic resources by using one set of LEs to implement both an adder and a subtractor. This feature is controlled by the LAB-wide control signal addnsub. The addnsub signal sets the LAB to perform either A + B or A - B. The LUT computes addition, and subtraction is computed by adding the two's complement of the intended subtractor. The LAB-wide signal converts to two's complement by inverting the B bits within the LAB and setting carry-in = 1 to add one to the least significant bit (LSB). The LSB of an adder/subtractor must be placed in the first LE of the LAB, where the LAB-wide addnsub signal automatically sets the carry-in to 1. The Quartus II Compiler automatically places and uses the adder/subtractor feature when using adder/subtractor parameterized functions.
LE Operating Modes
The Stratix LE can operate in one of the following modes:

Normal mode Dynamic arithmetic mode
Each mode uses LE resources differently. In each mode, eight available inputs to the LE--the four data inputs from the LAB local interconnect; carry-in0 and carry-in1 from the previous LE; the LAB carry-in from the previous carry-chain LAB; and the register chain connection-- are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear,
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Stratix Architecture
Logic Elements
asynchronous preset load, synchronous clear, synchronous load, and clock enable control for the register. These LAB-wide signals are available in all LE modes. The addnsub control signal is allowed in arithmetic mode. The Quartus II software, in conjunction with parameterized functions such as library of parameterized modules (LPM) functions, automatically chooses the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. If required, the designer can also create special-purpose functions that specify which LE operating mode to use for optimal performance.
Normal Mode
The normal mode is suitable for general logic applications and combinatorial functions. In normal mode, four data inputs from the LAB local interconnect are inputs to a four-input LUT (see Figure 2-6). The Quartus II Compiler automatically selects the carry-in or the data3 signal as one of the inputs to the LUT. Each LE can use LUT chain connections to drive its combinatorial output directly to the next LE in the LAB. Asynchronous load data for the register comes from the data3 input of the LE. LEs in normal mode support packed registers. Figure 2-6. LE in Normal Mode
sload sclear (LAB Wide) (LAB Wide) Register chain connection aload (LAB Wide)
addnsub (LAB Wide)
(1)
data1 data2 data3 cin (from cout of previous LE) data4
4-Input LUT
ALD/PRE ADATA Q D ENA CLRN
Row, column, and direct link routing Row, column, and direct link routing
clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide)
Local routing
LUT chain connection Register chain output
Register Feedback
Note to Figure 2-6:
(1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.
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Dynamic Arithmetic Mode
The dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. An LE in dynamic arithmetic mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first two 2-input LUTs compute two summations based on a possible carry-in of 1 or 0; the other two LUTs generate carry outputs for the two chains of the carry select circuitry. As shown in Figure 2-7, the LAB carry-in signal selects either the carry-in0 or carry-in1 chain. The selected chain's logic level in turn determines which parallel sum is generated as a combinatorial or registered output. For example, when implementing an adder, the sum output is the selection of two possible calculated sums: data1 + data2 + carry-in0 or data1 + data2 + carry-in1. The other two LUTs use the data1 and data2 signals to generate two possible carry-out signals--one for a carry of 1 and the other for a carry of 0. The carry-in0 signal acts as the carry select for the carry-out0 output and carry-in1 acts as the carry select for the carry-out1 output. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. The dynamic arithmetic mode also offers clock enable, counter enable, synchronous up/down control, synchronous clear, synchronous load, and dynamic adder/subtractor options. The LAB local interconnect data inputs generate the counter enable and synchronous up/down control signals. The synchronous clear and synchronous load options are LABwide signals that affect all registers in the LAB. The Quartus II software automatically places any registers that are not used by the counter into other LABs. The addnsub LAB-wide signal controls whether the LE acts as an adder or subtractor.
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Logic Elements
Figure 2-7. LE in Dynamic Arithmetic Mode
LAB Carry-In Carry-In0 Carry-In1 addnsub (LAB Wide) (1) sload sclear (LAB Wide) (LAB Wide) Register chain connection aload (LAB Wide)
data1 data2 data3
LUT
ALD/PRE ADATA Q D ENA CLRN
Row, column, and direct link routing Row, column, and direct link routing
LUT
LUT
clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide)
Local routing
LUT
LUT chain connection Register chain output Register Feedback
Carry-Out0
Carry-Out1
Note to Figure 2-7:
(1) The addnsub signal is tied to the carry input for the first LE of a carry chain only.
Carry-Select Chain
The carry-select chain provides a very fast carry-select function between LEs in arithmetic mode. The carry-select chain uses the redundant carry calculation to increase the speed of carry functions. The LE is configured to calculate outputs for a possible carry-in of 1 and carry-in of 0 in parallel. The carry-in0 and carry-in1 signals from a lower-order bit feed forward into the higher-order bit via the parallel carry chain and feed into both the LUT and the next portion of the carry chain. Carry-select chains can begin in any LE within an LAB. The speed advantage of the carry-select chain is in the parallel precomputation of carry chains. Since the LAB carry-in selects the precomputed carry chain, not every LE is in the critical path. Only the propagation delay between LAB carry-in generation (LE 5 and LE 10) are now part of the critical path. This feature allows the Stratix architecture to implement high-speed counters, adders, multipliers, parity functions, and comparators of arbitrary width.
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Figure 2-8 shows the carry-select circuitry in an LAB for a 10-bit full adder. One portion of the LUT generates the sum of two bits using the input signals and the appropriate carry-in bit; the sum is routed to the output of the LE. The register can be bypassed for simple adders or used for accumulator functions. Another portion of the LUT generates carryout bits. An LAB-wide carry in bit selects which chain is used for the addition of given inputs. The carry-in signal for each chain, carry-in0 or carry-in1, selects the carry-out to carry forward to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it is fed to local, row, or column interconnects. The Quartus II Compiler automatically creates carry chain logic during design processing, or the designer can create it manually during design entry. Parameterized functions such as LPM functions automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than 10 LEs by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically allowing fast horizontal connections to TriMatrix memory and DSP blocks. A carry chain can continue as far as a full column.
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Logic Elements
Figure 2-8. Carry Select Chain
LAB Carry-In A1 B1 A2 B2
0 LE1
1 Sum1
LAB Carry-In Carry-In0 Carry-In1
LE2
Sum2
LUT data1 data2 Sum LUT
A3 B3 A4 B4
LE3
Sum3
LE4
Sum4
LUT
A5 B5
LE5
Sum5
LUT
0 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 LE6
1 Sum6
Carry-Out0
Carry-Out1
LE7
Sum7
LE8
Sum8
LE9
Sum9
LE10
Sum10
LAB Carry-Out
Clear & Preset Logic Control
LAB-wide signals control the logic for the register's clear and preset signals. The LE directly supports an asynchronous clear and preset function. The register preset is achieved through the asynchronous load of a logic high. The direct asynchronous preset does not require a NOTgate push-back technique. Stratix devices support simultaneous preset/
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asynchronous load, and clear signals. An asynchronous clear signal takes precedence if both signals are asserted simultaneously. Each LAB supports up to two clears and one preset signal. In addition to the clear and preset ports, Stratix devices provide a chipwide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software controls this pin. This chip-wide reset overrides all other control signals.
MultiTrack Interconnect
In the Stratix architecture, connections between LEs, TriMatrix memory, DSP blocks, and device I/O pins are provided by the MultiTrack interconnect structure with DirectDriveTM technology. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for inter- and intra-design block connectivity. The Quartus II Compiler automatically places critical design paths on faster interconnects to improve design performance. DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement within the device. The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycles that typically follow design changes and additions. The MultiTrack interconnect consists of row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. Dedicated row interconnects route signals to and from LABs, DSP blocks, and TriMatrix memory within the same row. These row resources include:

Direct link interconnects between LABs and adjacent blocks. R4 interconnects traversing four blocks to the right or left. R8 interconnects traversing eight blocks to the right or left. R24 row interconnects for high-speed access across the length of the device.
The direct link interconnect allows an LAB, DSP block, or TriMatrix memory block to drive into the local interconnect of its left and right neighbors and then back into itself. Only one side of a M-RAM block interfaces with direct link and row interconnects. This provides fast communication between adjacent LABs and/or blocks without using row interconnect resources. The R4 interconnects span four LABs, three LABs and one M512 RAM block, two LABs and one M4K RAM block, or two LABs and one DSP block to the right or left of a source LAB. These resources are used for fast
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row connections in a four-LAB region. Every LAB has its own set of R4 interconnects to drive either left or right. Figure 2-9 shows R4 interconnect connections from an LAB. R4 interconnects can drive and be driven by DSP blocks and RAM blocks and horizontal IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4 interconnect. For R4 interconnects that drive to the right, the primary LAB and right neighbor can drive on to the interconnect. For R4 interconnects that drive to the left, the primary LAB and its left neighbor can drive on to the interconnect. R4 interconnects can drive other R4 interconnects to extend the range of LABs they can drive. R4 interconnects can also drive C4 and C16 interconnects for connections from one row to another. Additionally, R4 interconnects can drive R24 interconnects. Figure 2-9. R4 Interconnect Connections
Adjacent LAB can Drive onto Another LAB's R4 Interconnect R4 Interconnect Driving Left C4, C8, and C16 Column Interconnects (1) R4 Interconnect Driving Right
LAB Neighbor
Primary LAB (2)
LAB Neighbor
Notes to Figure 2-9:
(1) (2) C4 interconnects can drive R4 interconnects. This pattern is repeated for every LAB in the LAB row.
The R8 interconnects span eight LABs, M512 or M4K RAM blocks, or DSP blocks to the right or left from a source LAB. These resources are used for fast row connections in an eight-LAB region. Every LAB has its own set of R8 interconnects to drive either left or right. R8 interconnect connections between LABs in a row are similar to the R4 connections shown in Figure 2-9, with the exception that they connect to eight LABs to the right or left, not four. Like R4 interconnects, R8 interconnects can drive and be driven by all types of architecture blocks. R8 interconnects
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can drive other R8 interconnects to extend their range as well as C8 interconnects for row-to-row connections. One R8 interconnect is faster than two R4 interconnects connected together. R24 row interconnects span 24 LABs and provide the fastest resource for long row connections between LABs, TriMatrix memory, DSP blocks, and IOEs. The R24 row interconnects can cross M-RAM blocks. R24 row interconnects drive to other row or column interconnects at every fourth LAB and do not drive directly to LAB local interconnects. R24 row interconnects drive LAB local interconnects via R4 and C4 interconnects. R24 interconnects can drive R24, R4, C16, and C4 interconnects. The column interconnect operates similarly to the row interconnect and vertically routes signals to and from LABs, TriMatrix memory, DSP blocks, and IOEs. Each column of LABs is served by a dedicated column interconnect, which vertically routes signals to and from LABs, TriMatrix memory and DSP blocks, and horizontal IOEs. These column resources include:

LUT chain interconnects within an LAB Register chain interconnects within an LAB C4 interconnects traversing a distance of four blocks in up and down direction C8 interconnects traversing a distance of eight blocks in up and down direction C16 column interconnects for high-speed vertical routing through the device
Stratix devices include an enhanced interconnect structure within LABs for routing LE output to LE input connections faster using LUT chain connections and register chain connections. The LUT chain connection allows the combinatorial output of an LE to directly drive the fast input of the LE right below it, bypassing the local interconnect. These resources can be used as a high-speed connection for wide fan-in functions from LE 1 to LE 10 in the same LAB. The register chain connection allows the register output of one LE to connect directly to the register input of the next LE in the LAB for fast shift registers. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. Figure 2-10 shows the LUT chain and register chain interconnects.
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Figure 2-10. LUT Chain & Register Chain Interconnects
Local Interconnect Routing Among LEs in the LAB LUT Chain Routing to Adjacent LE LE 1
Register Chain Routing to Adjacent LE's Register Input
LE 2 Local Interconnect LE 3 LE 4 LE 5 LE 6
LE 7 LE 8 LE 9
LE 10
The C4 interconnects span four LABs, M512, or M4K blocks up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive either up or down. Figure 2-11 shows the C4 interconnect connections from an LAB in a column. The C4 interconnects can drive and be driven by all types of architecture blocks, including DSP blocks, TriMatrix memory blocks, and vertical IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections.
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Figure 2-11. C4 Interconnect Connections
Note (1)
C4 Interconnect Drives Local and R4 Interconnects up to Four Rows
C4 Interconnect Driving Up
LAB
Row Interconnect
Adjacent LAB can drive onto neighboring LAB's C4 interconnect
Local Interconnect
C4 Interconnect Driving Down
Note to Figure 2-11:
(1) Each C4 interconnect can drive either up or down four rows.
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C8 interconnects span eight LABs, M512, or M4K blocks up or down from a source LAB. Every LAB has its own set of C8 interconnects to drive either up or down. C8 interconnect connections between the LABs in a column are similar to the C4 connections shown in Figure 2-11 with the exception that they connect to eight LABs above and below. The C8 interconnects can drive and be driven by all types of architecture blocks similar to C4 interconnects. C8 interconnects can drive each other to extend their range as well as R8 interconnects for column-to-column connections. C8 interconnects are faster than two C4 interconnects. C16 column interconnects span a length of 16 LABs and provide the fastest resource for long column connections between LABs, TriMatrix memory blocks, DSP blocks, and IOEs. C16 interconnects can cross MRAM blocks and also drive to row and column interconnects at every fourth LAB. C16 interconnects drive LAB local interconnects via C4 and R4 interconnects and do not drive LAB local interconnects directly. All embedded blocks communicate with the logic array similar to LABto-LAB interfaces. Each block (i.e., TriMatrix memory and DSP blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks, labclk[7..0].
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Table 2-2 shows the Stratix device's routing scheme.
Table 2-2. Stratix Device Routing Scheme Destination Direct Link Interconnect
Local Interconnect
M512 RAM Block
R24 Interconnect
C16 Interconnect
Register Chain
M-RAM Block
Source LUT Chain
M4K RAM Block
R4 Interconnect
R8 Interconnect
C4 Interconnect
C8 Interconnect
Column IOE v
DSP Blocks
LUT Chain Register Chain Local Interconnect Direct Link Interconnect R4 Interconnect R8 Interconnect R24 Interconnect C4 Interconnect C8 Interconnect C16 Interconnect LE M512 RAM Block M4K RAM Block M-RAM Block DSP Blocks Column IOE Row IOE
v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v
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Row IOE
LE
Stratix Architecture
TriMatrix Memory
TriMatrix Memory
TriMatrix memory consists of three types of RAM blocks: M512, M4K, and M-RAM blocks. Although these memory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. Table 2-3 shows the size and features of the different RAM blocks.
Table 2-3. TriMatrix Memory Features (Part 1 of 2) Memory Feature
Maximum performance True dual-port memory Simple dual-port memory Single-port memory Shift register ROM FIFO buffer Byte enable Parity bits Mixed clock mode Memory initialization Simple dual-port memory mixed width support True dual-port memory mixed width support Power-up conditions Register clears Outputs cleared
M512 RAM Block (32 x 18 Bits)
(1)
M4K RAM Block (128 x 36 Bits)
(1)
M-RAM Block (4K x 144 Bits)
(1)
v v v v v v v v v v v v v v v v v v v v v
Outputs cleared
v v v
(2)
v v v v
v v
Outputs unknown
Input and output reigsters Input and output registers Output registers
Mixed-port read-during-write Unknown output/old data Unknown output/old data Unknown output
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Table 2-3. TriMatrix Memory Features (Part 2 of 2) Memory Feature
Configurations
M512 RAM Block (32 x 18 Bits)
512 x 1 256 x 2 128 x 4 64 x 8 64 x 9 32 x 16 32 x 18
M4K RAM Block (128 x 36 Bits)
4K x 1 2K x 2 1K x 4 512 x 8 512 x 9 256 x 16 256 x 18 128 x 32 128 x 36
M-RAM Block (4K x 144 Bits)
64K x 8 64K x 9 32K x 16 32K x 18 16K x 32 16K x 36 8K x 64 8K x 72 4K x 128 4K x 144
Notes to Table 2-3:
(1) (2) See Table 4-35 for maximum performance information. The M-RAM block does not support memory initializations. However, the M-RAM block can emulate a ROM function using a dual-port RAM bock. The Stratix device must write to the dual-port memory once and then disable the write-enable ports afterwards.
Memory Modes
TriMatrix memory blocks include input registers that synchronize writes and output registers to pipeline designs and improve system performance. M4K and M-RAM memory blocks offer a true dual-port mode to support any combination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. Figure 2-12 shows true dual-port memory. Figure 2-12. True Dual-Port Memory Configuration
A dataA[ ] addressA[ ] wrenA clockA clockenA qA[ ] aclrA B dataB[ ] addressB[ ] wrenB clockB clockenB qB[ ] aclrB
In addition to true dual-port memory, the memory blocks support simple dual-port and single-port RAM. Simple dual-port memory supports a simultaneous read and write and can either read old data before the write occurs or just read the don't care bits. Single-port memory supports nonsimultaneous reads and writes, but the q[] port will output the data once
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it has been written to the memory (if the outputs are not registered) or after the next rising edge of the clock (if the outputs are registered). For more information, see Chapter 3, Using TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices of the Stratix Device Handbook, Volume 2. Figure 2-13 shows these different RAM memory port configurations for TriMatrix memory. Figure 2-13. Simple Dual-Port & Single-Port Memory Configurations
Simple Dual-Port Memory
data[ ] wraddress[ ] wren inclock inclocken inaclr rdaddress[ ] rden q[ ] outclock outclocken outaclr
Single-Port Memory (1)
data[ ] address[ ] wren inclock inclocken inaclr
q[ ] outclock outclocken outaclr
Note to Figure 2-13:
(1) Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size.
The memory blocks also enable mixed-width data ports for reading and writing to the RAM ports in dual-port RAM configuration. For example, the memory block can be written in x1 mode at port A and read out in x16 mode from port B. TriMatrix memory architecture can implement fully synchronous RAM by registering both the input and output signals to the RAM block. All TriMatrix memory block inputs are registered providing synchronous write cycles. In synchronous operation, the memory block generates its own self-timed strobe write enable (WREN) signal derived from the global or regional clock. In contrast, a circuit using asynchronous RAM must generate the RAM WREN signal while ensuring its data and address
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signals meet setup and hold time specifications relative to the WREN signal. The output registers can be bypassed. Pseudo-asynchronous reading is possible in the simple dual-port mode of M512 and M4K RAM blocks by clocking the read enable and read address registers on the negative clock edge and bypassing the output registers. Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size. The Quartus II software automatically implements larger memory by combining multiple TriMatrix memory blocks. For example, two 256 x 16-bit RAM blocks can be combined to form a 256 x 32-bit RAM block. Memory performance does not degrade for memory blocks using the maximum number of words available in one memory block. Logical memory blocks using less than the maximum number of words use physical blocks in parallel, eliminating any external control logic that would increase delays. To create a larger high-speed memory block, the Quartus II software automatically combines memory blocks with LE control logic.
Parity Bit Support
The memory blocks support a parity bit for each byte. The parity bit, along with internal LE logic, can implement parity checking for error detection to ensure data integrity. Designers can also use parity-size data words to store user-specified control bits. In the M4K and M-RAM blocks, byte enables are also available for data input masking during write operations.
Shift Register Support
The designer can configure embedded memory blocks to implement shift registers for DSP applications such as pseudo-random number generators, multi-channel filtering, auto-correlation, and crosscorrelation functions. These and other DSP applications require local data storage, traditionally implemented with standard flip-flops, which can quickly consume many logic cells and routing resources for large shift registers. A more efficient alternative is to use embedded memory as a shift register block, which saves logic cell and routing resources and provides a more efficient implementation with the dedicated circuitry. The size of a w x m x n shift register is determined by the input data width (w), the length of the taps (m), and the number of taps (n). The size of a w x m x n shift register must be less than or equal to the maximum number of memory bits in the respective block: 576 bits for the M512 RAM block and 4,608 bits for the M4K RAM block. The total number of
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shift register outputs (number of taps n x width w) must be less than the maximum data width of the RAM block (18 for M512 blocks, 36 for M4K blocks). To create larger shift registers, the memory blocks are cascaded together. Data is written into each address location at the falling edge of the clock and read from the address at the rising edge of the clock. The shift register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. Figure 2-14 shows the TriMatrix memory block in the shift register mode. Figure 2-14. Shift Register Memory Configuration
w x m x n Shift Register m-Bit Shift Register w w
m-Bit Shift Register w w
n Number of Taps
m-Bit Shift Register w w
m-Bit Shift Register w w
Memory Block Size
TriMatrix memory provides three different memory sizes for efficient application support. The large number of M512 blocks are ideal for designs with many shallow first-in first-out (FIFO) buffers. M4K blocks
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provide additional resources for channelized functions that do not require large amounts of storage. The M-RAM blocks provide a large single block of RAM ideal for data packet storage. The different-sized blocks allow Stratix devices to efficiently support variable-sized memory in designs. The Quartus II software automatically partitions the user-defined memory into the embedded memory blocks using the most efficient size combinations. The designer can also manually assign the memory to a specific block size or a mixture of block sizes.
M512 RAM Block
The M512 RAM block is a simple dual-port memory block and is useful for implementing small FIFO buffers, DSP, and clock domain transfer applications. Each block contains 576 RAM bits (including parity bits). M512 RAM blocks can be configured in the following modes:

Simple dual-port RAM Single-port RAM FIFO ROM Shift register
When configured as RAM or ROM, the designer can use an initialization file to pre-load the memory contents. The memory address depths and output widths can be configured as 512 x 1, 256 x 2, 128 x 4, 64 x 8 (64 x 9 bits with parity), and 32 x 16 (32 x 18 bits with parity). Mixed-width configurations are also possible, allowing different read and write widths. Table 2-4 summarizes the possible M512 RAM block configurations.
Table 2-4. M512 RAM Block Configurations (Simple Dual-Port RAM) (Part 1 of 2) Write Port Read Port 512 x 1
512 x 1 256 x 2 128 x 4 64 x 8 32 x 16
256 x 2 v v v v v
128 x 4 v v v
64 x 8 v v v
32 x 16 v v v v
64 x 9
32 x 18
v v v v v
v
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Table 2-4. M512 RAM Block Configurations (Simple Dual-Port RAM) (Part 2 of 2) Write Port Read Port 512 x 1
64 x 9 32 x 18
256 x 2
128 x 4
64 x 8
32 x 16
64 x 9 v
32 x 18 v
When the M512 RAM block is configured as a shift register block, a shift register of size up to 576 bits is possible. The M512 RAM block can also be configured to support serializer and deserializer applications. By using the mixed-width support in combination with DDR I/O standards, the block can function as a SERDES to support low-speed serial I/O standards using global or regional clocks. See "I/O Structure" on page 2-101 for details on dedicated SERDES in Stratix devices. M512 RAM blocks can have different clocks on its inputs and outputs. The wren, datain, and write address registers are all clocked together from one of the two clocks feeding the block. The read address, rden, and output registers can be clocked by either of the two clocks driving the block. This allows the RAM block to operate in read/write or input/output clock modes. Only the output register can be bypassed. The eight labclk signals or local interconnect can drive the inclock, outclock, wren, rden, inclr, and outclr signals. Because of the advanced interconnect between the LAB and M512 RAM blocks, LEs can also control the wren and rden signals and the RAM clock, clock enable, and asynchronous clear signals. Figure 2-15 shows the M512 RAM block control signal generation logic. The RAM blocks within Stratix devices have local interconnects to allow LEs and interconnects to drive into RAM blocks. The M512 RAM block local interconnect is driven by the R4, R8, C4, C8, and direct link interconnects from adjacent LABs. The M512 RAM blocks can communicate with LABs on either the left or right side through these row interconnects or with LAB columns on the left or right side with the column interconnects. Up to 10 direct link input connections to the M512 RAM block are possible from the left adjacent LABs and another 10 possible from the right adjacent LAB. M512 RAM outputs can also connect to left and right LABs through 10 direct link interconnects. The M512 RAM block has equal opportunity for access and performance to and from LABs on either its left or right side. Figure 2-16 shows the M512 RAM block to logic array interface.
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Figure 2-15. M512 RAM Block Control Signals
Dedicated Row LAB Clocks Local Interconnect 8
Local Interconnect
Local Interconnect Local Interconnect
Local Interconnect Local Interconnect Local Interconnect Local Interconnect inclock
inclocken
outclocken
wren
outclr
outclock
rden
inclr
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Figure 2-16. M512 RAM Block LAB Row Interface
C4 and C8 Interconnects R4 and R8 Interconnects 10
Direct link interconnect to adjacent LAB
Direct link interconnect to adjacent LAB dataout
Direct link interconnect from adjacent LAB
M512 RAM Block
Direct link interconnect from adjacent LAB
Control Signals datain address Clocks 2 8 Small RAM Block Local Interconnect Region LAB Row Clocks
M4K RAM Blocks
The M4K RAM block includes support for true dual-port RAM. The M4K RAM block is used to implement buffers for a wide variety of applications such as storing processor code, implementing lookup schemes, and implementing larger memory applications. Each block contains 4,608 RAM bits (including parity bits). M4K RAM blocks can be configured in the following modes:

True dual-port RAM Simple dual-port RAM Single-port RAM FIFO ROM Shift register
When configured as RAM or ROM, the designer can use an initialization file to pre-load the memory contents.
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The memory address depths and output widths can be configured as 4,096 x 1, 2,048 x 2, 1,024 x 4, 512 x 8 (or 512 x 9 bits), 256 x 16 (or 256 x 18 bits), and 128 x 32 (or 128 x 36 bits). The 128 x 32- or 36-bit configuration is not available in the true dual-port mode. Mixed-width configurations are also possible, allowing different read and write widths. Tables 2-5 and 2-6 summarize the possible M4K RAM block configurations.
Table 2-5. M4K RAM Block Configurations (Simple Dual-Port) Write Port Read Port 4K x 1
4K x 1 2K x 2 1K x 4 512 x 8 256 x 16 128 x 32 512 x 9 256 x 18 128 x 36
2K x 2 v v v v v v
1K x 4 512 x 8 256 x 16 v v v v v v v v v v v v v v v v v v
128 x 32 512 x 9 256 x 18 v v v v v v v v v v v v
128 x 36
v v v v v v
v v v
Table 2-6. M4K RAM Block Configurations (True Dual-Port) Port B Port A 4K x 1
4K x 1 2K x 2 1K x 4 512 x 8 256 x 16 512 x 9 256 x 18
2K x 2 v v v v v
1K x 4 v v v v v
512 x 8 v v v v v
256 x 16 v v v v v
512 x 9
256 x 18
v v v v v
v v
v v
When the M4K RAM block is configured as a shift register block, the designer can create a shift register up to 4,608 bits (w x m x n).
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M4K RAM blocks support byte writes when the write port has a data width of 16, 18, 32, or 36 bits. The byte enables allow the input data to be masked so the device can write to specific bytes. The unwritten bytes retain the previous written value. Table 2-7 summarizes the byte selection.
Table 2-7. Byte Enable for M4K Blocks byteena[3..0]
[0] = 1 [1] = 1 [2] = 1 [3] = 1 Notes to Table 2-7:
(1) (2)
Notes (1), (2) datain x36
[8..0] [17..9] [26..18] [35..27]
datain x18
[8..0] [17..9] - -
Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, i.e., in x 16 and x 32 modes.
The M4K RAM blocks allow for different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M4K RAM block registers (renwe, address, byte enable, datain, and output registers). Only the output register can be bypassed. The eight labclk signals or local interconnects can drive the control signals for the A and B ports of the M4K RAM block. LEs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Figure 2-17. The R4, R8, C4, C8, and direct link interconnects from adjacent LABs drive the M4K RAM block local interconnect. The M4K RAM blocks can communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources. Up to 10 direct link input connections to the M4K RAM Block are possible from the left adjacent LABs and another 10 possible from the right adjacent LAB. M4K RAM block outputs can also connect to left and right LABs through 10 direct link interconnects each. Figure 2-18 shows the M4K RAM block to logic array interface.
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Figure 2-17. M4K RAM Block Control Signals
Dedicated Row LAB Clocks Local Interconnect 8
Local Interconnect
Local Interconnect Local Interconnect Local Interconnect clocken_a Local Interconnect clock_a renwe_a alcr_b clocken_b alcr_a renwe_b clock_b
Local Interconnect Local Interconnect Local Interconnect Local Interconnect
Figure 2-18. M4K RAM Block LAB Row Interface
C4 and C8 Interconnects R4 and R8 Interconnects
Direct link interconnect to adjacent LAB
10
Direct link interconnect to adjacent LAB dataout
Direct link interconnect from adjacent LAB
M4K RAM Block Byte enable Control Signals Clocks
Direct link interconnect from adjacent LAB
address
datain
8 M4K RAM Block Local Interconnect Region LAB Row Clocks
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Stratix Architecture
TriMatrix Memory
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for applications where a large volume of data must be stored on-chip. Each block contains 589,824 RAM bits (including parity bits). The M-RAM block can be configured in the following modes:

True dual-port RAM Simple dual-port RAM Single-port RAM FIFO
The designer cannot use an initialization file to initialize the contents of a M-RAM block. All M-RAM block contents power up to an undefined value. Only synchronous operation is supported in the M-RAM block, so all inputs are registered. Output registers can be bypassed. The memory address and output width can be configured as 64K x 8 (or 64K x 9 bits), 32K x 16 (or 32K x 18 bits), 16K x 32 (or 16K x 36 bits), 8K x 64 (or 8K x 72 bits), and 4K x 128 (or 4K x 144 bits). The 4K x 128 configuration is unavailable in true dual-port mode because there are a total of 144 data output drivers in the block. Mixed-width configurations are also possible, allowing different read and write widths. Tables 2-8 and 2-9 summarizes the possible M-RAM block configurations:
Table 2-8. M-RAM Block Configurations (Simple Dual-Port) Write Port Read Port 64K x 9
64K x 9 32K x 18 16K x 36 8K x 72 4K x 144
32K x 18 v v v v
16K x 36 v v v v
8K x 72 v v v v
4K x 144
v v v v
v
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Table 2-9. M-RAM Block Configurations (True Dual-Port) Port B Port A 64K x 9
64K x 9 32K x 18 16K x 36 8K x 72
32K x 18 v v v v
16K x 36 v v v v
8K x 72 v v v v
v v v v
The read and write operation of the memory is controlled by the WREN signal, which sets the ports into either read or write modes. There is no separate read enable (RE) signal. Writing into RAM is controlled by both the WREN and byte enable (byteena) signals for each port. The default value for the byteena signal is high, in which case writing is controlled only by the WREN signal. The byte enables are available for the x18, x36, and x72 modes. In the x144 simple dual-port mode, the two sets of byteena signals (byteena_a and byteena_b) are combined to form the necessary 16 byte enables. Tables 2-10 and 2-11 summarize the byte selection.
Table 2-10. Byte Enable for M-RAM Blocks byteena[3..0]
[0] = 1 [1] = 1 [2] = 1 [3] = 1 [4] = 1 [5] = 1 [6] = 1 [7] = 1
Notes (1), (2) datain x72
[8..0] [17..9] [26..18] [35..27] [44..36] [53..45] [62..54] [71..63]
datain x18
[8..0] [17..9] - - - - - -
datain x36
[8..0] [17..9] [26..18] [35..27] - - - -
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TriMatrix Memory
Table 2-11. M-RAM Combined Byte Selection for x144 Mode Notes (1), (2) byteena[15..0]
[0] = 1 [1] = 1 [2] = 1 [3] = 1 [4] = 1 [5] = 1 [6] = 1 [7] = 1 [8] = 1 [9] = 1 [10] = 1 [11] = 1 [12] = 1 [13] = 1 [14] = 1 [15] = 1 Notes to Tables 2-10 and 2-11:
(1) (2) Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, i.e., in x 16, x 32, x 64, and x 128 modes.
datain x144
[8..0] [17..9] [26..18] [35..27] [44..36] [53..45] [62..54] [71..63] [80..72] [89..81] [98..90] [107..99] [116..108] [125..117] [134..126] [143..135]
Similar to all RAM blocks, M-RAM blocks can have different clocks on their inputs and outputs. All input registers--renwe, datain, address, and byte enable registers--are clocked together from either of the two clocks feeding the block. The output register can be bypassed. The eight labclk signals or local interconnect can drive the control signals for the A and B ports of the M-RAM block. LEs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals as shown in Figure 2-19.
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Figure 2-19. M-RAM Block Control Signals
Dedicated Row LAB Clocks Local Interconnect Local Interconnect 8
Local Interconnect
Local Interconnect Local Interconnect
Local Interconnect Local Interconnect Local Interconnect
clocken_a
clocken_b
aclr_b
renwe_b
clock_a
clock_b
aclr_a
renwe_a
One of the M-RAM block's horizontal sides drive the address and control signal (clock, renwe, byteena, etc.) inputs. Typically, the horizontal side closest to the device perimeter contains the interfaces. The one exception is when two M-RAM blocks are paired next to each other. In this case, the side of the M-RAM block opposite the common side of the two blocks contains the input interface. The top and bottom sides of any M-RAM block contain data input and output interfaces to the logic array. The top side has 72 data inputs and 72 data outputs for port B, and the bottom side has another 72 data inputs and 72 data outputs for port A. Figure 2-20 shows an example floorplan for the EP1S60 device and the location of the M-RAM interfaces.
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Figure 2-20. EP1S60 Device with M-RAM Interface Locations
M-RAM pairs interface to top, bottom, and side opposite of block-to-block border.
Note (1)
Independent M-RAM blocks interface to top, bottom, and side facing device perimeter for easy access to horizontal I/O pins.
M-RAM Block
M-RAM Block
M-RAM Block
M-RAM Block
M-RAM Block
M-RAM Block
DSP Blocks
M512 Blocks
M4K Blocks
LABs
DSP Blocks
Note to Figure 2-20:
(1) Device shown is an EP1S60 device. The number and position of M-RAM blocks varies in other devices.
The M-RAM block local interconnect is driven by the R4, R8, C4, C8, and direct link interconnects from adjacent LABs. For independent M-RAM blocks, up to 10 direct link address and control signal input connections to the M-RAM block are possible from the left adjacent LABs for M-RAM
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blocks facing to the left, and another 10 possible from the right adjacent LABs for M-RAM blocks facing to the right. For column interfacing, every M-RAM column unit connects to the right and left column lines, allowing each M-RAM column unit to communicate directly with three columns of LABs. Figures 2-21 through 2-23 show the interface between the M-RAM block and the logic array.
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TriMatrix Memory
Figure 2-21. Left-Facing M-RAM to Interconnect Interface
M512 RAM Block Columns
Notes (1), (2)
Row Unit Interface Allows LAB Rows to Drive Address and Control Signals to M-RAM Block
LABs in Column M-RAM Boundary
Column Interface Block Drives to and from C4 and C8 Interconnects
B1 B2 B3 Port B B4 B5 B6
R11 R10 R9 R8 R7 R6 M-RAM Block
R5 R4 R3 R2
R1 A1 A2
Port A A3 A4 A5 A6
Column Interface Block Allows LAB Columns to Drive datain and dataout to and from M-RAM Block
LABs in Row M-RAM Boundary
LAB Interface Blocks
Notes to Figure 2-21:
(1) (2) Only R24 and C16 interconnects cross the M-RAM block boundaries. The right-facing M-RAM block has interface blocks on the right side, but none on the left. B1 to B6 and A1 to A6 orientation is clipped across the vertical axis for right-facing M-RAM blocks.
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Figure 2-22. M-RAM Row Unit Interface to Interconnect
C4 and C8 Interconnects R4 and R8 Interconnects M-RAM Block
LAB
10
Direct Link Interconnects addressa addressb renwe_a renwe_b byteenaA[ ] byteenaB[ ] clocken_a clocken_b clock_a clock_b aclr_a aclr_b
Up to 24
Row Interface Block M-RAM Block to LAB Row Interface Block Interconnect Region
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Figure 2-23. M-RAM Column Unit Interface to Interconnect
C4 and C8 Interconnects
LAB
LAB
LAB
M-RAM Block to LAB Row Interface Block Interconnect Region Column Interface Block
12 datain
12 dataout
M-RAM Block
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Table 2-12 shows the input and output data signal connections for the column units (B1 to B6 and A1 to A6). It also shows the address and control signal input connections to the row units (R1 to R11).
Table 2-12. M-RAM Row & Column Interface Unit Signals Unit Interface Block
R1 R2 R3 R4 R5 R6
Input SIgnals
addressa[7..0] addressa[15..8] byte_enable_a[7..0] renwe_a clock_a clocken_a clock_b clocken_b byte_enable_b[7..0] renwe_b addressb[15..8] addressb[7..0] datain_b[71..60] datain_b[59..48] datain_b[47..36] datain_b[35..24] datain_b[23..12] datain_b[11..0] datain_a[71..60] datain_a[59..48] datain_a[47..36] datain_a[35..24] datain_a[23..12] datain_a[11..0]
Output Signals
R7 R8 R9 R10 R11 B1 B2 B3 B4 B5 B6 A1 A2 A3 A4 A5 A6
dataout_b[71..60] dataout_b[59..48] dataout_b[47..36] dataout_b[35..24] dataout_b[23..12] dataout_b[11..0] dataout_a[71..60] dataout_a[59..48] dataout_a[47..36] dataout_a[35..24] dataout_a[23..12] dataout_a[11..0]
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Independent Clock Mode
The memory blocks implement independent clock mode for true dualport memory. In this mode, a separate clock is available for each port (ports A and B). Clock A controls all registers on the port A side, while clock B controls all registers on the port B side. Each port, A and B, also supports independent clock enables and asynchronous clear signals for port A and B registers. Figure 2-24 shows a TriMatrix memory block in independent clock mode.
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8 LAB Row Clocks A
D ENA Q
TriMatrix Memory
(1)
B Data In Data In
Q D ENA
8
8 dataB[ ]
Note to Figure 2-24:
Memory Block 256 16 (2) 512 8 1,024 4 2,048 2 4,096 1
D ENA Q
dataA[ ]
byteenaA[ ] Byte Enable A Byte Enable B
Q
D ENA
Figure 2-24. Independent Clock Mode
byteenaB[ ]
addressA[ ]
D ENA Q
Address A
Address B
Q
D ENA
addressB[ ]
Note (1)
All registers shown have asynchronous clear ports.
D ENA Q
wrenA
wrenB
clkenA
clockA
Write Pulse Generator
Write/Read Enable
Write/Read Enable
Q
D ENA
Write Pulse Generator Data Out Data Out
clkenB clockB
D ENA
Q
Q
D ENA
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Altera Corporation November 2003
qA[ ]
qB[ ]
Stratix Architecture
TriMatrix Memory
Input/Output Clock Mode
Input/output clock mode can be implemented for both the true and simple dual-port memory modes. On each of the two ports, A or B, one clock controls all registers for inputs into the memory block: data input, wren, and address. The other clock controls the block's data output registers. Each memory block port, A or B, also supports independent clock enables and asynchronous clear signals for input and output registers. Figures 2-25 and 2-26 show the memory block in input/output clock mode.
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8 LAB Row Clocks 8 A
D ENA Q
TriMatrix Memory
(1)
B Data In
Q D ENA
8 dataB[ ]
Note to Figure 2-25:
Data In Memory Block 256 x 16 (2) 512 x 8 1,024 x 4 2,048 x 2 4,096 x 1 Byte Enable B
Q D ENA Q
dataA[ ]
byteenaA[ ] Byte Enable A
D ENA
byteenaB[ ]
addressA[ ]
D ENA Q
Address A
Address B
Q
D ENA
addressB[ ]
wrenA wrenB
D ENA Q
Figure 2-25. Input/Output Clock Mode in True Dual-Port Mode
All registers shown have asynchronous clear ports.
Write Pulse Generator Data Out Write/Read Enable Write/Read Enable
Q D ENA
clkenA
clockA
Write Pulse Generator Data Out
clkenB
D ENA Q Q D ENA
clockB qA[ ] qB[ ]
Note (1)
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Altera Corporation November 2003
Stratix Architecture
TriMatrix Memory
Figure 2-26. Input/Output Clock Mode in Simple Dual-Port Mode
8 LAB Row Clocks 8 data[ ] D Q ENA
Note (1)
Memory Block 256 16 Data In 512 8 1,024 4 2,048 2 4,096 1 Read Address
address[ ]
D Q ENA
Data Out byteena[ ] D Q ENA Byte Enable
D Q ENA
To MultiTrack Interconnect
wraddress[ ]
D Q ENA
Write Address
rden D Q ENA wren Read Enable
outclken
inclken wrclock
D Q ENA
Write Pulse Generator
Write Enable
rdclock
Note to Figure 2-26:
(1) All registers shown except the rden register have asynchronous clear ports.
Read/Write Clock Mode
The memory blocks implement read/write clock mode for simple dualport memory. The designer can use up to two clocks in this mode. The write clock controls the block's data inputs, wraddress, and wren. The read clock controls the data output, rdaddress, and rden. The memory
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blocks support independent clock enables for each clock and asynchronous clear signals for the read- and write-side registers. Figure 2-27 shows a memory block in read/write clock mode. Figure 2-27. Read/Write Clock Mode in Simple Dual-Port Mode
8 LAB Row Clocks 8 data[ ] D Q ENA
Note (1)
Memory Block 256 x 16 512 x 8 1,024 x 4 Data In 2,048 x 2 4,096 x 1 Data Out D Q ENA To MultiTrack Interconnect
address[ ]
D Q ENA
Read Address
wraddress[ ]
D Q ENA
Write Address
byteena[ ]
D Q ENA
Byte Enable
rden D Q ENA wren Read Enable
outclken
inclken wrclock
D Q ENA
Write Pulse Generator
Write Enable
rdclock
Note to Figure 2-27:
(1) All registers shown except the rden register have asynchronous clear ports.
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Stratix Architecture
Digital Signal Processing Block
Single-Port Mode
The memory blocks also support single-port mode, used when simultaneous reads and writes are not required. See Figure 2-28. A single block in a memory block can support up to two single-port mode RAM blocks in the M4K RAM blocks if each RAM block is less than or equal to 2K bits in size. Figure 2-28. Single-Port Mode
8 LAB Row Clocks
8 data[ ] D Q ENA
RAM/ROM 256 x 16 512 x 8 1,024 x 4 Data In 2,048 x 2 4,096 x 1 Data Out D Q ENA
To MultiTrack Interconnect
address[ ]
D Q ENA
Address
wren
Write Enable outclken
inclken inclock
D Q ENA
Write Pulse Generator
outclock
Digital Signal Processing Block
The most commonly used DSP functions are finite impulse response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, direct cosine transform (DCT) functions, and correlators. All of these blocks have the same fundamental building block: the multiplier. Additionally, some applications need specialized operations such as multiply-add and multiply-accumulate operations. Stratix devices provide DSP blocks to meet the arithmetic requirements of these functions. Each Stratix device has two columns of DSP blocks to efficiently implement DSP functions faster than LE-based implementations. Larger Stratix devices have more DSP blocks per column (see Table 2-13). Each DSP block can be configured to support up to:
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Eight 9 x 9-bit multipliers Four 18 x 18-bit multipliers One 36 x 36-bit multiplier
As indicated, the Stratix DSP block can support one 36 x 36-bit multiplier in a single DSP block. This is true for any matched sign multiplications (either unsigned by unsigned or signed by signed), but the capabilities for dynamic and mixed sign multiplications are handled differently. The following list provides the largest functions that can fit into a single DSP block.

36 x 36-bit unsigned by unsigned multiplication 36 x 36-bit signed by signed multiplication 35 x 36-bit unsigned by signed multiplication 36 x 35-bit signed by unsigned multiplication 36 x 35-bit signed by dynamic sign multiplication 35 x 36-bit dynamic sign by signed multiplication 35 x 36-bit unsigned by dynamic sign multiplication 36 x 35-bit dynamic sign by unsigned multiplication 35 x 35-bit dynamic sign multiplication when the sign controls for each operand are different 36 x 36-bit dynamic sign multiplication when the same sign control is used for both operands This list only shows functions that can fit into a single DSP block. Multiple DSP blocks can support larger multiplication functions.
1
Figure 2-29 shows one of the columns with surrounding LAB rows.
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Digital Signal Processing Block
Figure 2-29. DSP Blocks Arranged in Columns
DSP Block Column
8 LAB Rows
DSP Block
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Table 2-13 shows the number of DSP blocks in each Stratix device.
Table 2-13. DSP Blocks in Stratix Devices Device
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 Notes to Table 2-13:
(1)
Notes (1), (2) Total 18 x 18 Multipliers
24 40 40 48 56 72 88
DSP Blocks
6 10 10 12 14 18 22
Total 9 x 9 Multipliers
48 80 80 96 112 144 176
Total 36 x 36 Multipliers
6 10 10 12 14 18 22
(2)
Each device has either the number of 9 x 9-, 18 x 18-, or 36 x 36-bit multipliers shown. The total number of multipliers for each device is not the sum of all the multipliers. The number of supported multiply functions shown is based on signed/signed or unsigned/unsigned implementations.
DSP block multipliers can optionally feed an adder/subtractor or accumulator within the block depending on the configuration. This makes routing to LEs easier, saves LE routing resources, and increases performance, because all connections and blocks are within the DSP block. Additionally, the DSP block input registers can efficiently implement shift registers for FIR filter applications. Figure 2-30 shows the top-level diagram of the DSP block configured for 18 x 18-bit multiplier mode. Figure 2-31 shows the 9 x 9-bit multiplier configuration of the DSP block.
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Figure 2-30. DSP Block Diagram for 18 x 18-Bit Configuration
Optional Serial Shift Register Inputs from Previous DSP Block
Multiplier Stage Optional Stage Configurable as Accumulator or Dynamic Adder/Subtractor
D Q
D
Q
Output Selection Multiplexer
ENA CLRN
D
Q
ENA CLRN
ENA CLRN
Adder/ Subtractor/ Accumulator 1
D
Q
ENA CLRN
D
Q
D
Q
ENA CLRN
ENA CLRN
Summation
D
Q
ENA CLRN
D
Q
D
Q
ENA CLRN
Summation Stage for Adding Four Multipliers Together
Optional Output Register Stage
ENA CLRN
Adder/ Subtractor/ Accumulator 2
D
Q
Optional Serial Shift Register Outputs to Next DSP Block in the Column
ENA CLRN
D
Q
D
Q
ENA CLRN
Optional Pipeline Register Stage
ENA CLRN
Optional Input Register Stage with Parallel Input or Shift Register Configuration
to MultiTrack Interconnect
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Figure 2-31. DSP Block Diagram for 9 x 9-Bit Configuration
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Adder/ Subtractor/ 1a
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Summation
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Adder/ Subtractor/ 1b
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Output Selection Multiplexer
D Q ENA CLRN
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Adder/ Subtractor/ 2a
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Summation
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Adder/ Subtractor/ 2b
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
To MultiTrack Interconnect
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Digital Signal Processing Block
The DSP block consists of the following elements:

Multiplier block Adder/output block
Multiplier Block
The DSP block multiplier block consists of the input registers, a multiplier, and pipeline register for pipelining multiply-accumulate and multiply-add/subtract functions as shown in Figure 2-32. Figure 2-32. Multiplier Sub-Block within Stratix DSP Block
sign_a (1) sign_b (1) aclr[3..0] clock[3..0] ena[3..0]
shiftin B
shiftin A
Data A
D ENA
Q D ENA Q
Result to Adder blocks Optional Multiply-Accumulate and Multiply-Add Pipeline
CLRN
CLRN
Data B
D ENA
Q
CLRN
shiftout B
shiftout A
Note to Figure 2-32:
(1) These signals can be unregistered or registered once to match data path pipelines if required.
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Input Registers
A bank of optional input registers is located at the input of each multiplier and multiplicand inputs to the multiplier. When these registers are configured for parallel data inputs, they are driven by regular routing resources. Designers can use a clock signal, asynchronous clear signal, and a clock enable signal to independently control each set of A and B inputs for each multiplier in the DSP block. Designers select these control signals from a set of four different clock[3..0], aclr[3..0], and ena[3..0] signals that drive the entire DSP block. Designers can also configure the input registers for a shift register application. In this case, the input registers feed the multiplier and drive two dedicated shift output lines: shiftoutA and shiftoutB. The shift outputs of one multiplier block directly feed the adjacent multiplier block in the same DSP block (or the next DSP block) as shown in Figure 2-33, to form a shift register chain. This chain can terminate in any block, i.e., designers can create any length of shift register chain up to 224 registers. The designer can use the input shift registers for FIR filter applications. One set of shift inputs can provide data for a filter, and the other are coefficients that are optionally loaded in serial or parallel. When implementing 9 x 9- and 18 x 18-bit multipliers, the designer does not need to implement external shift registers in LAB LEs. The designer implements all the filter circuitry within the DSP block and its routing resources, saving LE and general routing resources for general logic. External registers are needed for shift register inputs when using 36 x 36-bit multipliers.
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Figure 2-33. Multiplier Sub-Blocks Using Input Shift Register Connections Note (1)
Data A
D ENA Q
A[n] x B[n]
CLRN D ENA Q
Data B
D ENA
Q
CLRN
CLRN
Data B
Data A
D ENA
Q
A[n 1] x B[n 1]
CLRN D ENA Q
D ENA
Q
CLRN
CLRN
Data B
Data A
D ENA
Q
A[n 2] x B[n 2]
CLRN D ENA Q
D ENA
Q
CLRN
CLRN
Note to Figure 2-33:
(1) Either Data A or Data B input can be set to a parallel input for constant coefficient multiplication.
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Table 2-14 shows the summary of input register modes for the DSP block.
Table 2-14. Input Register Modes Register Input Mode
Parallel input Shift register input
9x9 v v
18 x 18 v v
36 x 36 v
Multiplier
The multiplier supports 9 x 9-, 18 x 18-, or 36 x 36-bit multiplication. Each DSP block supports eight possible 9 x 9-bit or smaller multipliers. There are four multiplier blocks available for multipliers larger than 9 x 9 bits but smaller than 18 x 18 bits. There is one multiplier block available for multipliers larger than 18 x 18 bits but smaller than or equal to 36 x 36 bits. The ability to have several small multipliers is useful in applications such as video processing. Large multipliers greater than 18 x 18 bits are useful for applications such as the mantissa multiplication of a singleprecision floating-point number. The multiplier operands can be signed or unsigned numbers, where the result is signed if either input is signed as shown in Table 2-15. The sign_a and sign_b signals provide dynamic control of each operand's representation: a logic 1 indicates the operand is a signed number, a logic 0 indicates the operand is an unsigned number. These sign signals affect all multipliers and adders within a single DSP block and designers can register them to match the data path pipeline. The multipliers are full precision (i.e., 18 bits for the 18-bit multiply, 36-bits for the 36-bit multiply, etc.) regardless of whether sign_a or sign_b set the operands as signed or unsigned numbers.
Table 2-15. Multiplier Signed Representation Data A
Unsigned Unsigned Signed Signed
Data B
Unsigned Signed Unsigned Signed
Result
Unsigned Signed Signed Signed
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Pipeline/Post Multiply Register
The output of 9 x 9- or 18 x 18-bit multipliers can optionally feed a register to pipeline multiply-accumulate and multiply-add/subtract functions. For 36 x 36-bit multipliers, this register will pipeline the multiplier function.
Adder/Output Blocks
The result of the multiplier sub-blocks are sent to the adder/output block which consist of an adder/subtractor/accumulator unit, summation unit, output select multiplexer, and output registers. The results are used to configure the adder/output block as a pure output, accumulator, a simple two-multiplier adder, four-multiplier adder, or final stage of the 36-bit multiplier. The designer can configure the adder/output block to use output registers in any mode, and must use output registers for the accumulator. The system cannot use adder/output blocks independently of the multiplier. Figure 2-34 shows the adder and output stages.
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Figure 2-34. Adder/Output Blocks
Note (1)
Accumulator Feedback
accum_sload0 (2) Result A
addnsub1 (2)
Adder/ Subtractor/ Accumulator1
overflow0
Output Selection Multiplexer
Result B signa (2)
Summation signb (2)
Output Register Block
Result C
addnsub3 (2)
Adder/ Subtractor/ Accumulator2 overflow1
Result D accum_sload1 (2)
Accumulator Feedback
Notes to Figure 2-34:
(1) (2)
Adder/output block shown in Figure 2-34 is in 18 x 18-bit mode. In 9 x 9-bit mode, there are four adder/subtractor blocks and two summation blocks. These signals are either not registered, registered once, or registered twice to match the data path pipeline.
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Adder/Subtractor/Accumulator
The adder/subtractor/accumulator is the first level of the adder/output block and can be used as an accumulator or as an adder/subtractor. Adder/Subtractor Each adder/subtractor/accumulator block can perform addition or subtraction using the addnsub independent control signal for each firstlevel adder in 18 x 18-bit mode. There are two addnsub[1..0] signals available in a DSP block for any configuration. For 9 x 9-bit mode, one addnsub[1..0] signal controls the top two one-level adders and another addnsub[1..0] signal controls the bottom two one-level adders. A high addnsub signal indicates addition, and a low signal indicates subtraction. The addnsub control signal can be unregistered or registered once or twice when feeding the adder blocks to match data path pipelines. The signa and signb signals serve the same function as the multiplier block signa and signb signals. The only difference is that these signals can be registered up to two times. These signals are tied to the same signa and signb signals from the multiplier and must be connected to the same clocks and control signals. Accumulator When configured for accumulation, the adder/output block output feeds back to the accumulator as shown in Figure 2-34. The accum_sload[1..0] signal synchronously loads the multiplier result to the accumulator output. This signal can be unregistered or registered once or twice. Additionally, the overflow signal indicates the accumulator has overflowed or underflowed in accumulation mode. This signal is always registered and must be externally latched in LEs if the design requires a latched overflow signal.
Summation
The output of the adder/subtractor/accumulator block feeds to an optional summation block. This block sums the outputs of the DSP block multipliers. In 9 x 9-bit mode, there are two summation blocks providing the sums of two sets of four 9 x 9-bit multipliers. In 18 x 18-bit mode, there is one summation providing the sum of one set of four 18 x 18-bit multipliers.
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Output Selection Multiplexer
The outputs from the various elements of the adder/output block are routed through an output selection multiplexer. Based on the DSP block operational mode and user settings, the multiplexer selects whether the output from the multiplier, the adder/subtractor/accumulator, or summation block feeds to the output.
Output Registers
Optional output registers for the DSP block outputs are controlled by four sets of control signals: clock[3..0], aclr[3..0], and ena[3..0]. Output registers can be used in any mode.
Modes of Operation
The adder, subtractor, and accumulate functions of a DSP block have four modes of operation:

Simple multiplier Multiply-accumulator Two-multipliers adder Four-multipliers adder Each DSP block can only support one mode. Mixed modes in the same DSP block is not supported.
1
Simple Multiplier Mode
In simple multiplier mode, the DSP block drives the multiplier sub-block result directly to the output with or without an output register. Up to four 18 x 18-bit multipliers or eight 9 x 9-bit multipliers can drive their results directly out of one DSP block. See Figure 2-35.
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Figure 2-35. Simple Multiplier Mode
signa (1) signb (1) aclr clock ena
shiftin B
shiftin A
Data A
D ENA
Q D ENA Q D ENA Q
Data Out
CLRN
CLRN CLRN
Data B
D ENA
Q
CLRN
shiftout B
shiftout A
Note to Figure 2-35:
(1) These signals are not registered or registered once to match the data path pipeline.
DSP blocks can also implement one 36 x 36-bit multiplier in multiplier mode. DSP blocks use four 18 x 18-bit multipliers combined with dedicated adder and internal shift circuitry to achieve 36-bit multiplication. The input shift register feature is not available for the 36 x 36-bit multiplier. In 36 x 36-bit mode, the device can use the register that is normally a multiplier-result-output register as a pipeline stage for the 36 x 36-bit multiplier. Figure 2-36 shows the 36 x 36-bit multiply mode.
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Figure 2-36. 36 x 36 Multiply Mode
signa (1) signb (1) aclr clock ena
A[17..0]
D ENA
Q D Q ENA CLRN
CLRN
B[17..0]
D ENA
Q
CLRN
A[35..18]
D ENA
Q D Q ENA CLRN D Q ENA
Data Out
CLRN
36 x 36 Multiplier Adder signa (2) signb (2)
CLRN
B[35..18]
D ENA
Q
CLRN
A[35..18]
D ENA
Q D Q ENA CLRN
CLRN
B[17..0]
D ENA
Q
CLRN
A[17..0]
D ENA
Q D Q ENA CLRN
CLRN
B[35..18]
D ENA
Q
CLRN
Notes to Figure 2-36:
(1) (2) These signals are not registered or registered once to match the pipeline. These signals are not registered, registered once, or registered twice for latency to match the pipeline.
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Multiply-Accumulator Mode
In multiply-accumulator mode (see Figure 2-37), the DSP block drives multiplied results to the adder/subtractor/accumulator block configured as an accumulator. A designer can implement one or two multiplyaccumulators up to 18 x 18 bits in one DSP block. The first and third multiplier sub-blocks are unused in this mode, since only one multiplier can feed one of two accumulators. The multiply-accumulator output can be up to 52 bits--a maximum of a 36-bit result with 16 bits of accumulation. The accum_sload and overflow signals are only available in this mode. The addnsub signal can set the accumulator for decimation and the overflow signal will indicate underflow condition. Figure 2-37. Multiply-Accumulate Mode
signa (1) signb (1) aclr clock ena Shiftin B Shiftin A
Data A
D ENA
Q D Q ENA CLRN D Q ENA CLRN
Data Out
Accumulator
CLRN
Data B
D ENA
Q
overflow
CLRN
Shiftout B Shiftout A
addnsub (2) signa (2) signb (2) accum_sload (2)
Notes to Figure 2-37:
(1) (2) These signals are not registered or registered once to match the data path pipeline. These signals are not registered, registered once, or registered twice for latency to match the data path pipeline.
Two-Multipliers Adder Mode
The two-multipliers adder mode uses the adder/subtractor/accumulator block to add or subtract the outputs of the multiplier block, which is useful for applications such as FFT functions and complex FIR filters. A
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single DSP block can implement two sums or differences from two 18 x 18-bit multipliers each or four sums or differences from two 9 x 9-bit multipliers each. Designers can use the two-multipliers adder mode for complex multiplications, which are written as: (a + jb) x (c + jd) = [(a x c) - (b x d)] + j x [(a x d) + (b x c)] The two-multipliers adder mode allows a single DSP block to calculate the real part [(a x c) - (b x d)] using one subtractor and the imaginary part [(a x d) + (b x c)] using one adder, for data widths up to 18 bits. Two complex multiplications are possible for data widths up to 9 bits using four adder/subtractor/accumulator blocks. Figure 2-38 shows an 18-bit two-multipliers adder. Figure 2-38. Two-Multipliers Adder Mode Implementing Complex Multiply
18 A 36 18 C 18 B 36 18 D 18 A 36 18 D 18 B 36 18 C Adder 37 (A x D) + (B x C) (Imaginary Part) 18 18 Subtractor 18 37 (A x C) - (B x D) (Real Part) 18 DSP Block
Four-Multipliers Adder Mode
In the four-multipliers adder mode, the DSP block adds the results of two first -stage adder/subtractor blocks. One sum of four 18 x 18-bit multipliers or two different sums of two sets of four 9 x 9-bit multipliers can be implemented in a single DSP block. The product width for each multiplier must be the same size. The four-multipliers adder mode is useful for FIR filter applications. Figure 2-39 shows the four multipliers adder mode.
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Figure 2-39. Four-Multipliers Adder Mode
signa (1) signb (1) aclr clock ena shiftin B shiftin A
Data A
D ENA
Q D ENA Q
CLRN
Adder/Subtractor
CLRN
Data B
D ENA
Q
CLRN
Data A
D ENA
Q D ENA Q D ENA Q
Data Out
CLRN
CLRN
addnsub1 (2) signa (2) signb (2) addnsub3 (2)
Summation
CLRN
Data B
D ENA
Q
CLRN
Data A
D ENA
Q D ENA Q
CLRN
Adder/Subtractor
CLRN
Data B
D ENA
Q
CLRN
Data A
D ENA
Q D ENA Q
CLRN
CLRN
Data B
D ENA
Q
CLRN
shiftout B
shiftout A
Notes to Figure 2-39:
(1) (2) These signals are not registered or registered once to match the data path pipeline. These signals are not registered, registered once, or registered twice for latency to match the data path pipeline.
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For FIR filters, the DSP block combines the four-multipliers adder mode with the shift register inputs. One set of shift inputs contains the filter data, while the other holds the coefficients loaded in serial or parallel. The input shift register eliminates the need for shift registers external to the DSP block (i.e., implemented in LEs). This architecture simplifies filter design since the DSP block implements all of the filter circuitry. One DSP block can implement an entire 18-bit FIR filter with up to four taps. For FIR filters larger than four taps, DSP blocks can be cascaded with additional adder stages implemented in LEs. Table 2-16 shows the different number of multipliers possible in each DSP block mode according to size. These modes allow the DSP blocks to implement numerous applications for DSP including FFTs, complex FIR, FIR, and 2D FIR filters, equalizers, IIR, correlators, matrix multiplication and many other functions.
Table 2-16. Multiplier Size & Configurations per DSP block DSP Block Mode
Multiplier Multiply-accumulator Two-multipliers adder Four-multipliers adder Note to Table 2-16:
(1) The number of supported multiply functions shown is based on signed/signed or unsigned/unsigned implementations.
9x9
Eight multipliers with eight product outputs Two multiply and accumulate (52 bits) Four sums of two multiplier products each Two sums of four multiplier products each
18 x 18
Four multipliers with four product outputs Two multiply and accumulate (52 bits) Two sums of two multiplier products each One sum of four multiplier products each
36 x 36 (1)
One multiplier with one product output - - -
DSP Block Interface
Stratix device DSP block outputs can cascade down within the same DSP block column. Dedicated connections between DSP blocks provide fast connections between the shift register inputs to cascade the shift register chains. The designer can cascade DSP blocks for 9 x 9- or 18 x 18-bit FIR filters larger than four taps, with additional adder stages implemented in LEs. If the DSP block is configured as 36 x 36 bits, the adder, subtractor, or accumulator stages are implemented in LEs. Each DSP block can route the shift register chain out of the block to cascade two full columns of DSP blocks.
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The DSP block is divided into eight block units that interface with eight LAB rows on the left and right. Each block unit can be considered half of an 18 x 18-bit multiplier sub-block with 18 inputs and 18 outputs. A local interconnect region is associated with each DSP block. Like an LAB, this interconnect region can be fed with 10 direct link interconnects from the LAB to the left or right of the DSP block in the same row. All row and column routing resources can access the DSP block's local interconnect region. The outputs also work similarly to LAB outputs as well. Nine outputs from the DSP block can drive to the left LAB through direct link interconnects and nine can drive to the right LAB though direct link interconnects. All 18 outputs can drive to all types of row and column routing. Outputs can drive right- or left-column routing. Figures 2-40 and 2-41 show the DSP block interfaces to LAB rows. Figure 2-40. DSP Block Interconnect Interface
DSP Block OA[17..0]
MultiTrack Interconnect
MultiTrack Interconnect
A1[17..0] OB[17..0]
B1[17..0] OC[17..0]
A2[17..0] OD[17..0]
B2[17..0] OE[17..0]
A3[17..0] OF[17..0]
B3[17..0] OG[17..0]
A4[17..0] OH[17..0]
B4[17..0]
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Figure 2-41. DSP Block Interface to Interconnect
C4 and C8 Interconnects Direct Link Interconnect from Adjacent LAB R4 and R8 Interconnects Nine Direct Link Outputs to Adjacent LABs Direct Link Interconnect from Adjacent LAB
18 DSP Block Row Structure 10 9 9
LAB
LAB
10
3 Control 18 [17..0] [17..0] 18
Row Interface Block DSP Block to LAB Row Interface Block Interconnect Region 18 Inputs per Row 18 Outputs per Row
A bus of 18 control signals feeds the entire DSP block. These signals include clock[0..3] clocks, aclr[0..3] asynchronous clears, ena[1..4] clock enables, signa, signb signed/unsigned control signals, addnsub1 and addnsub3 addition and subtraction control signals, and accum_sload[0..1] accumulator synchronous loads. The
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clock signals are routed from LAB row clocks and are generated from specific LAB rows at the DSP block interface. The LAB row source for control signals, data inputs, and outputs is shown in Table 2-17.
Table 2-17. DSP Block Signal Sources & Destinations LAB Row at Interface
1 2 3
Control Signals Generated
signa aclr0 accum_sload0 addnsub1 clock0 ena0 aclr1 clock1 ena1 aclr2 clock2 ena2 sign_b clock3 ena3 clear3 accum_sload1 addnsub3
Data Inputs
A1[17..0] B1[17..0] A2[17..0]
Data Outputs
OA[17..0] OB[17..0] OC[17..0]
4
B2[17..0]
OD[17..0]
5
A3[17..0]
OE[17..0]
6
B3[17..0]
OF[17..0]
7 8
A4[17..0] B4[17..0]
OG[17..0] OH[17..0]
PLLs & Clock Networks
Stratix devices provide a hierarchical clock structure and multiple PLLs with advanced features. The large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast PLLs provides a complete clock management solution.
Global & Hierarchical Clocking
Stratix devices provide 16 dedicated global clock networks, 16 regional clock networks (four per device quadrant), and 8 dedicated fast regional clock networks. These clocks are organized into a hierarchical clock structure that allows for up to 22 clocks per device region with low skew and delay. This hierarchical clocking scheme provides up to 48 unique clock domains within Stratix devices.
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There are 16 dedicated clock pins (CLK[15..0]) to drive either the global or regional clock networks. Four clock pins drive each side of the device, as shown in Figures 2-42 and 2-43. Enhanced and fast PLL outputs can also drive the global and regional clock networks.
Global Clock Network
These clocks drive throughout the entire device, feeding all device quadrants. The global clock networks can be used as clock sources for all resources within the device--IOEs, LEs, DSP blocks, and all memory blocks. These resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin. The global clock networks can also be driven by internal logic for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. Figure 2-42 shows the 16 dedicated CLK pins driving global clock networks. Figure 2-42. Global Clocking
CLK[15..12]
Global Clock [15..0]
CLK[3..0]
Global Clock [15..0]
CLK[11..8]
CLK[7..4]
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Regional Clock Network
There are four regional clock networks RCLK[3..0] within each quadrant of the Stratix device that are driven by the same dedicated CLK[15..0] input pins or from PLL outputs. The regional clock networks only pertain to the quadrant they drive into. The regional clock networks provide the lowest clock delay and skew for logic contained within a single quadrant. The CLK clock pins symmetrically drive the RCLK networks within a particular quadrant, as shown in Figure 2-43. Refer to Figures 2-50 and 2-51 for RCLK connectioins from PLLs and CLK pins. Figure 2-43. Regional Clocks
RCLK[15..14] RCLK[13..12]
CLK[15..12]
RCLK[1..0] CLK[3..0]
RCLK[11..10] CLK[11..8]
RCLK[3..2]
RCLK[9..8]
CLK[7..4] Regional Clocks Only Drive a Device Quadrant from Specified CLK Pins or PLLs within that Quadrant RCLK[5..4] RCLK[7..6]
Fast Regional Clock Network
In EP1S25, EP1S20, and EP1S10 devices, there are two fast regional clock networks, FCLK[1..0], within each quadrant, fed by input pins that can connect to fast regional clock networks (see Figure 2-44). In EP1S30 and larger devices, there are two fast regional clock networks within each
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half-quadrant (see Figure 2-45). Dual-purpose FCLK pins drive the fast clock networks. All devices have eight FCLK pins to drive fast regional clock networks. Any I/O pin can drive a clock or control signal onto any fast regional clock network with the addition of a delay. This signal is driven via the I/O interconnect. Figure 2-44. EP1S25, EP1S20 & EP1S10 Device Fast Clock Pin Connections to Fast Regional Clocks
FCLK[1..0] FCLK[7..6]
2 (1), (2) 2 (1), (2)
2
2
FCLK[1..0]
FCLK[1..0]
FCLK[1..0]
FCLK[1..0]
2 (1), (2) 2 (1), (2)
2
2
FCLK[3..2]
FCLK[5..4]
Notes to Figure 2-44:
(1) (2) This is a set of two multiplexers. In addition to the FCLK pin inputs, there is also an input from the I/O interconnect.
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Figure 2-45. EP1S30 Device Fast Regional Clock Pin Connections to Fast Regional Clocks
FCLK1 FCLK0 FCLK7 FCLK6
(1), (2)
(1), (2) (1), (2) (1), (2)
fclk[1..0]
(1), (2)
(1), (2) (1), (2) (1), (2)
FCLK3
FCLK2
FCLK5
FCLK4
Notes to Figure 2-45:
(1) (2) This is a set of two multiplexers. In addition to the FCLK pin inputs, there is also an input from the I/O interconnect.
Combined Resources
Within each region, there are 22 distinct dedicated clocking resources consisting of 16 global clock lines, four regional clock lines, and two fast regional clock lines. Multiplexers are used with these clocks to form eight bit busses to drive LAB row clocks, column IOE clocks, or row IOE clocks. Another multiplexer is used at the LAB level to select two of the eight row clocks to feed the LE registers within the LAB. See Figure 2-46.
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Figure 2-46. Regional Clock Bus
Clocks Available to a Quadrant or Half-Quadrant Global Clock Network [15..0] Regional Clock Network [3..0] Fast Regional Clock Network [1..0] Horizontal I/O Cell IO_CLK[7..0] Clock [21:0] Lab Row Clock [7:0] Vertical I/O Cell IO_CLK[7..0]
IOE clocks have horizontal and vertical block regions that are clocked by eight I/O clock signals chosen from the 22 quadrant or half-quadrant clock resources. Figures 2-47 and 2-48 show the quadrant and halfquadrant relationship to the I/O clock regions, respectively. The vertical regions (column pins) have less clock delay than the horizontal regions (row pins).
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Figure 2-47. EP1S10, EP1S20 & EP1S25 Device I/O Clock Groups
IO_CLKA[7:0] IO_CLKB[7:0]
8
8 I/O Clock Regions
8
22 Clocks in the Quadrant IO_CLKH[7:0]
22 Clocks in the Quadrant IO_CLKC[7:0] 8
8 IO_CLKG[7:0] 22 Clocks in the Quadrant 22 Clocks in the Quadrant IO_CLKD[7:0]
8
8
8
IO_CLKF[7:0]
IO_CLKE[7:0]
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Figure 2-48. EP1S30, EP1S40, EP1S60, EP1S80 Device I/O Clock Groups
IO_CLKA[7:0] IO_CLKB[7:0] IO_CLKC[7:0] IO_CLKD[7:0]
8
8
8
8 I/O Clock Regions
8
8
IO_CLKP[7:0] 22 Clocks in the Half-Quadrant 8 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 8
IO_CLKE[7:0]
IO_CLKO[7:0]
IO_CLKF[7:0]
8
8
IO_CLKN[7:0] 22 Clocks in the Half-Quadrant 8 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 8
IO_CLKG[7:0]
IO_CLKM[7:0]
IO_CLKH[7:0]
8
8
8
8
IO_CLKL[7:0]
IO_CLKK[7:0]
IO_CLKJ[7:0]
IO_CLKI[7:0]
Designers can use the Quartus II software to control whether a clock input pin is either global, regional, or fast regional. The Quartus II software automatically selects the clocking resources if not specified.
Enhanced & Fast PLLs
Stratix devices provide robust clock management and synthesis using up to four enhanced PLLs and eight fast PLLs. These PLLs increase performance and provide advanced clock interfacing and clockfrequency synthesis. With features such as clock switchover, spread spectrum clocking, programmable bandwidth, phase and delay control, and PLL reconfiguration, the Stratix device's enhanced PLLs provide designers with complete control of their clocks and system timing. The
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fast PLLs provide general purpose clocking with multiplication and phase shifting as well as high-speed outputs for high-speed differential I/O support. Enhanced and fast PLLs work together with the Stratix high-speed I/O and advanced clock architecture to provide significant improvements in system performance and bandwidth. The Quartus II software enables the PLLs and their features without requiring any external devices. Tables 2-18 and 2-19 show the PLLs available for each Stratix device, respectively, and their type.
Table 2-18. Stratix Device PLL Availability Fast PLLs Device 1
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
Enhanced PLLs 8 9 10 5(1) v v v 6(1) v v v v v v v v v v v v v 11(2) 12(2)
2 v v v v v v v
3 v v v v v v v
4 v v v v v v v
7
v v v v v v v
v (3) v (3)
v (3) v (3)
v (3) v (3)
v (3) v (3)
v v v v
v v
v v
v v
v v
Notes to Table 2-18:
(1) (2) (3) PLLs 5 and 6 each have eight single-ended outputs or four differential outputs. PLLs 11 and 12 each have one single-ended output. EP1S30 and EP1S40 devices do not support these PLLs in the 780-pin FineLine BGA(R) package.
Table 2-19. Stratix Device PLL Availability Fast PLLs Device 1
EP1S10C EP1S10D EP1S25C EP1S25D EP1S25F EP1S40D EP1S40G
Enhanced PLLs 8 5 v v v v v 6 v v v v v v v v v v v 11 12
2 v v v v v v v
7
v v v v v v v
v v
v v
v v
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Table 2-20 shows the enhanced PLL and fast PLL features in Stratix devices.
Table 2-20. Stratix PLL Features Feature
Clock multiplication and division Phase shift Delay shift Clock switchover PLL reconfiguration Programmable bandwidth Spread spectrum clocking Programmable duty cycle Number of internal clock outputs Number of external clock outputs Number of feedback clock inputs Notes to Table 2-20:
(1) (2) (3) (4) (5) (6) The maximum count value is 1024, with a 50% duty cycle setting on the counter. The maximum count value is 512, with a non-50% duty cycle setting on the counter For fast PLLs, m, n, and post-scale counters range from 1 to 32. The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8. For degree increments, Stratix devices can shift all output frequencies in increments of at least 45 . Smaller degree increments are possible depending on the frequency and divide parameters. PLLs 7, 8, 9, and 10 have two output ports per PLL. PLLs 1, 2, 3, and 4 have three output ports per PLL. Every Stratix device has two enhanced PLLs (PLLs 5 and 6) with either eight single-ended outputs or four differential outputs each. Two additional enhanced PLLs (PLLs 11 and 12) in EP1S80, EP1S60, EP1S40 devices each have one single-ended output. Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data channel to generate txclkout. Every Stratix device has two enhanced PLLs with one single-ended or differential external feedback input per PLL.
Enhanced PLL
m/(n x post-scale counter) (1) Down to 156.25-ps increments (3), (4) 250-ps increments for 3 ns
Fast PLL
m/(post-scale counter) (2) Down to 125-ps increments (3), (4)
v v v v v
6 Four differential/eight singled-ended or one single-ended (6) 2 (8)
v
3 (5) (7)
(7) (8)
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Figure 2-49 shows a top-level diagram of the Stratix device and PLL floorplan. Figure 2-49. PLL Locations
CLK[15..12] 5 11
FPLL7CLK
7
10
FPLL10CLK
CLK[3..0]
1 2
4 3
CLK[8..11]
PLLs
FPLL8CLK
8
9
FPLL9CLK
6
12
CLK[7..4]
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Figure 2-50 shows the global and regional clocking from the PLL outputs and the CLK pins. Figure 2-50. Global & Regional Clock Connections from Side Pins & Fast PLL Outputs
RCLK1 RCLK0
FPLL7CLK l0 PLL 7 l1 g0
Note (1)
G1 G0 G2
G3 G9
G8
G10 G11
RCLK11 RCLK10
l0 l1 PLL 10 g0 FPLL10CLK
CLK0 CLK1
l0 PLL 1 l1 g0
l0 l1 PLL 4 g0
CLK10 CLK11
CLK2 CLK3
l0 2 PLL 2 l1 g0
l0 2 l1 PLL 3 g0
CLK8 CLK9
l0 PLL 8 l1 g0
l0 l1 PLL 9 g0
FPLL8CLK
FPLL9CLK
RCLK2 RCLK3
Regional Clocks Global Clocks
RCLK8 RCLK9
Regional Clocks
Notes to Figure 2-50:
(1) (2) (3) PLLs 1 to 4 and 7 to 10 are fast PLLs. PLLs 5, 6, 11, and 12 are enhanced PLLs. The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. A pin or other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL. PLLs 3, 4, 9, and 10 are used for the HSSI block in Stratix devices and are not available for this use.
Figure 2-51 shows the global and regional clocking from enhanced PLL outputs and top CLK pins.
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Figure 2-51. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs
PLL5_OUT[3..0] CLK14 (1) PLL5_FB CLK15 (2) CLK12 (1) CLK13 (2)
Note (1)
E[0..3] PLL 5 PLL 11
L0 L1 G0 G1 G2 G3
G0 G1 G2 G3 L0 L1
PLL11_OUT RCLK12 RCLK13
Regional Clocks
RCLK14 RCLK15 G12 G13 G14 G15
Global Clocks
G4 G5 G6 G7
Regional Clocks
RCLK4 RCLK5 RCLK6 RCLK7
PLL12_OUT
L0 L1 G0 G1 G2 G3 PLL 6
G0 G1 G2 G3 L0 L1 PLL 12
PLL6_OUT[3..0]
PLL6_FB CLK4 (1) CLK5 (2)
CLK6 (1)
CLK7 (2)
Notes to Figure 2-51:
(1) (2) (3) PLLs 1 to 4 and 7 to 10 are fast PLLs. PLLs 5, 6, 11, and 12 are enhanced PLLs. CLK4, CLK6, CLK12, and CLK14 feed the corresponding PLL's inclk0 port. CLK5, CLK7, CLK13, and CLK15 feed the corresponding PLL's inclk1 port.
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Enhanced PLLs
Stratix devices contain up to four enhanced PLLs with advanced clock management features. Figure 2-52 shows a diagram of the enhanced PLL. Figure 2-52. Stratix Enhanced PLL
Post-Scale Counters VCO Phase Selection Selectable at Each PLL Output Port From Adjacent PLL t Regional Clocks Clock Switch-Over Circuitry INCLK0 /n t PFD Charge Pump Loop Filter 8 VCO /g0 /l1 Phase Frequency Detector Spread Spectrum 4 t Programmable Time Delay on Each PLL Port
/l0
t
Global Clocks
INCLK1
/g1
t t t I/O Buffers (2) to I/O or general routing
(1)
t
/m
/g2
/g3 FBIN Lock Detect & Filter VCO Phase Selection Affecting All Outputs /e0
t t t t I/O Buffers (3)
/e1
4
/e2 /e3
Notes to Figure 2-52:
(1) (2) (3) (4) External feedback is available in PLLs 5 and 6. This single-ended external output is available from the g0 counter for PLLs 11 and 12. These four counters and external outputs are available in PLLs 5 and 6. This connection is only available on EP1S40 and larger Stratix devices. For example, PLLs 5 and 11 are adjacent and PLLs 6 and 12 are adjacent.
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Clock Multiplication & Division
Each Stratix device enhanced PLL provides clock synthesis for PLL output ports using m/(n x post-scale counter) scaling factors. The input clock is divided by a pre-scale divider, n, and is then multiplied by the m feedback factor. The control loop drives the VCO to match fIN x (m/n). Each output port has a unique post-scale counter that divides down the high-frequency VCO. For multiple PLL outputs with different frequencies, the VCO is set to the least common multiple of the output frequencies that meets its frequency specifications. Then, the post-scale dividers scale down the output frequency for each output port. For example, if output frequencies required from one PLL are 33 and 66 MHz, set the VCO to 330 MHz (the least common multiple in the VCO's range). There is one pre-scale divider, n, and one multiply divider, m, per PLL, with a range of 1 to 512 with any non-50% duty cycle setting. There are two post-scale dividers (l) for regional clock output ports, four counters (g) for global clock output ports, and up to four counters (e) for external clock outputs, all ranging from 1 to 1024, with a 50% duty cycle setting. The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered.
Clock Switchover
To effectively develop high-reliability network systems, clocking schemes must support multiple clocks to provide redundancy. For this reason, Stratix device enhanced PLLs support a flexible clock switchover capability. Figure 2-53 shows a block diagram of the switchover circuit. The switchover circuit is configurable, so the designer can define how to implement it. Clock-sense circuitry automatically switches from the primary to secondary clock for PLL reference when the primary clock signal is not present.
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Figure 2-53. Clock Switchover Circuitry
CLK0_BAD CLK1_BAD Active Clock SMCLKSW
Clock Sense
Switch-Over State Machine
CLKLOSS
CLKSWITCH
t INCLK0 INCLK1 MUXOUT
n Counter
PFD
FBCLK
Enhanced PLL
Note to Figure 2-53:
(1) PFD: phase frequency detector.
There are two possible ways to use the clock switch-over feature.
Designers can use automatic switch-over circuitry for switching between inputs of the same frequency. For example, in applications that require a redundant clock with the same frequency as the primary clock, the switchover state machine generates a signal that controls the multiplexer select input on the bottom of Figure 2-53. In this case, the secondary clock becomes the reference clock for the PLL. Designers can use the clkswitch input for user- or systemcontrolled switch conditions. This is possible for same-frequency switchover or to switch between inputs of different frequencies. For example, if inclk0 is 66 MHz and inclk1 is 100 MHz, the designer must control the switchover because the automatic clock-sense circuitry cannot monitor primary and secondary clock frequencies
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with a frequency difference of more than 20%. This feature is useful when clock sources can originate from multiple cards on the backplane, requiring a system-controlled switchover between frequencies of operation. The designer can use clkswitch together with the lock signal to trigger the switch from a clock that is running but becomes unstable and cannot be locked onto. During switch over, the PLL VCO continues to run and will either slow down or speed up, generating frequency drift on the PLL outputs. The clock switchover transitions without any glitches. After the switch, there is a finite resynchronization period to lock onto new clock as the VCO ramps up. The exact amount of time it takes for the PLL to relock relates to the PLL configuration and may be adjusted by using the programmable bandwidth feature of the PLL. The preliminary specification for the maximum time to relock is 100 s.
PLL Reconfiguration
The PLL reconfiguration feature enables system logic to change Stratix device enhanced PLL counters and delay elements without reloading a Programmer Object File (.pof). This provides considerable flexibility for frequency synthesis, allowing real-time PLL frequency and output clock delay variation. The designer can sweep the PLL output frequencies and clock delay in prototype environments. The PLL reconfiguration feature can also dynamically or intelligently control system clock speeds or tCO delays in end systems. Clock delay elements at each PLL output port implement variable delay. Figure 2-54 shows a diagram of the overall dynamic PLL control feature for the counters and the clock delay elements. The configuration time is less than 20 s for the enhanced PLL using a input shift clock rate of 22 MHz. The charge pump, loop filter components, and phase shifting using VCO phase taps cannot be dynamically adjusted.
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Figure 2-54. Dynamically Programmable Counters & Delays in Stratix Device Enhanced PLLs
Counters and Clock Delay Settings are Programmable All Output Counters and Clock Delay Settings can be Programmed Dynamically
fREF scandata scanclk
/n
t
PFD
Charge Pump
Loop Filter
VCO
/g
t
/m
t
scanaclr
/l
t
/e
t
PLL reconfiguration data is shifted into serial registers from the logic array or external devices. The PLL input shift data uses a reference input shift clock. Once the last bit of the serial chain is clocked in, the register chain is synchronously loaded into the PLL configuration bits. The shift circuitry also provides an asynchronous clear for the serial registers.
Programmable Bandwidth
The designer has advanced control of the PLL bandwidth using the programmable control of the PLL loop characteristics, including loop filter and charge pump. The PLL's bandwidth is a measure of its ability to track the input clock and jitter. A high-bandwidth PLL can quickly lock onto a reference clock and react to any changes in the clock. It also will allow a wide band of input jitter spectrum to pass to the output. A lowbandwidth PLL will take longer to lock, but it will attenuate all highfrequency jitter components. The Quartus II software can adjust PLL characteristics to achieve the desired bandwidth. The programmable bandwidth is tuned by varying the charge pump current, loop filter
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resistor value, high frequency capacitor value, and m counter value. Designers can manually adjust these values if desired. Bandwidth is programmable from 200 kHz to 1.5 MHz.
External Clock Outputs
Enhanced PLLs 5 and 6 each support up to eight single-ended clock outputs (or four differential pairs). See Figure 2-55.
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Figure 2-55. External Clock Outputs for PLLs 5 & 6
From IOE (1), (2) pll_out0p (3)
e0 Counter
From IOE (1) From IOE (1)
pll_out0n
pll_out1p
e1 Counter
4
From IOE (1)
pll_out1n
From IOE (1)
pll_out2p (4)
e2 Counter
pll_out2n (4) From IOE (1) From IOE (1)
pll_out3p (4)
e3 Counter
From IOE (1)
pll_out3n (4)
Notes to Figure 2-55:
(1) (2) (3) The design can use each external clock output pin as a general-purpose output pin from the logic array. These pins are multiplexed with IOE outputs. Two single-ended outputs are possible per output counter either two outputs of the same frequency and phase or one shifted 180 . EP1S10, EP1S20, and EP1S25 devices in 672-pin BGA and 484- and 672-pin FineLine BGA packages only have two pairs of external clocks (i.e., pll_out0p, pll_out0n, pll_out1p, and pll_out1n).
Any of the four external output counters can drive the single-ended or differential clock outputs for PLLs 5 and 6. This means one counter or frequency can drive all output pins available from PLL 5 or PLL 6. Each
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pair of output pins (four pins total) has dedicated VCC and GND pins to reduce the output clock's overall jitter by providing improved isolation from switching I/O pins. For PLLs 5 and 6, each pin of a single-ended output pair can either be in phase or 180 out of phase. The clock output pin pairs support the same I/O standards as standard output pins (in the top and bottom banks) as well as LVDS, LVPECL, 3.3-V PCML, HyperTransport technology, differential HSTL, and differential SSTL. Table 2-21 shows which I/O standards the enhanced PLL clock pins support. When in single-ended or differential mode, the two outputs operate off the same power supply. Both outputs use the same standards in single-ended mode to maintain performance. Designers can also use the external clock output pins as user output pins if external enhanced PLL clocking is not needed.
Table 2-21. I/O Standards Supported for Enhanced PLL Pins (Part 1 of 2) Input I/O Standard INCLK
LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI 3.3-V PCI-X 1.0 LVPECL 3.3-V PCML LVDS HyperTransport technology Differential HSTL Differential SSTL 3.3-V GTL 3.3-V GTL+ 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I
Output PLLENABLE v v EXTCLK v v v v v v v v v v v v v
FBIN v v v v v v v v v v v
v v v v v v v v v v v v v v v v v
v v v v v
v v v v v
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Table 2-21. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2) Input I/O Standard INCLK
1.8-V HSTL class II SSTL-18 class I SSTL-18 class II SSTL-2 class I SSTL-2 class II SSTL-3 class I SSTL-3 class II AGP (1x and 2x ) CTT
Output PLLENABLE EXTCLK v v v v v v v v v
FBIN v v v v v v v v v
v v v v v v v v v
Enhanced PLLs 11 and 12 support one single-ended output each (see Figure 2-56). These outputs do not have their own VCC and GND signals. Therefore, to minimize jitter, do not place switching I/O pins next to this output pin. Figure 2-56. External Clock Outputs for Enhanced PLLs 11 & 12
g0 Counter
CLK13n, I/O, PLL11_OUT or CLK6n, I/O, PLL12_OUT (1)
From Internal Logic or IOE
Note to Figure 2-56:
(1) For PLL 11, this pin is CLK13n; for PLL 12 this pin is CLK7n.
Stratix devices can drive any enhanced PLL driven through the global clock or regional clock network to any general I/O pin as an external output clock. The jitter on the output clock is not guaranteed for these cases.
Clock Feedback
The following four feedback modes in Stratix device enhanced PLLs allow multiplication and/or phase and delay shifting:
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Zero delay buffer: The external clock output pin is phase-aligned with the clock input pin for zero delay. Altera recommends using the same I/O standard on the input clock and the output clocks for optimum performance. External feedback: The external feedback input pin, FBIN, is phasealigned with the clock input, CLK, pin. Aligning these clocks allows the designer to remove clock delay and skew between devices. This mode is only possible for PLLs 5 and 6. PLLs 5 and 6 each support feedback for one of the dedicated external outputs, either one singleended or one differential pair. In this mode, one e counter feeds back to the PLL FBIN input, becoming part of the feedback loop. Altera recommends using the same I/O standard on the input clock, the FBIN pin, and the output clocks for optimum performance. Normal mode: If an internal clock is used in this mode, it is phasealigned to the input clock pin. The external clock output pin will have a phase delay relative to the clock input pin if connected in this mode. The designer defines which internal clock output from the PLL should be phase-aligned to the internal clock pin. No compensation: In this mode, the PLL will not compensate for any clock networks or external clock outputs.
Phase & Delay Shifting
Stratix device enhanced PLLs provide advanced programmable phase and clock delay shifting. These parameters are set in the Quartus II software. Phase Delay The Quartus II software automatically sets the phase taps and counter settings according to the phase shift entry. The designer enters a desired phase shift and the Quartus II software automatically sets the closest setting achievable. This type of phase shift is not reconfigurable during system operation. For phase shifting, enter a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. Designers can select phase-shifting values in time units with a resolution of 156.25 to 416.66 ps. This resolution is a function of frequency input and the multiplication and division factors (i.e., it is a function of the VCO period), with the finest step being equal to an eighth (x0.125) of the VCO period. Each clock output counter can choose a different phase of the VCO period from up to eight taps for individual fine step selection. Also, each clock output counter can use a unique initial count setting to achieve individual coarse shift selection in steps of one VCO period. The combination of coarse and fine shifts allows phase shifting for the entire input clock period.
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The equation to determine the precision of the phase shifting in degrees is: 45 / post-scale counter value. Therefore, the maximum step size is 45 , and smaller steps are possible depending on the multiplication and division ratio necessary on the output counter port. This type of phase shift provides the highest precision since it is the least sensitive to process, supply, and temperature variation. Clock Delay In addition to the phase shift feature, the ability to fine tune the t clock delay provides advanced time delay shift control on each of the four PLL outputs. There are time delays for each post-scale counter (e, g, or l) from the PLL, the n counter, and m counter. Each of these can shift in 250-ps increments for a range of 3.0 ns. The m delay shifts all outputs earlier in time, while n delay shifts all outputs later in time. Individual delays on post-scale counters (e, g, and l) provide positive delay for each output. Table 2-22 shows the combined delay for each output for normal or zero delay buffer mode where te, tg, or tl is unique for each PLL output. The tOUTPUT for a single output can range from -3 ns to +6 ns. The total delay shift difference between any two PLL outputs, however, must be less than 3 ns. For example, shifts on two outputs of -1 and +2 ns is allowed, but not -1 and +2.5 ns because these shifts would result in a difference of 3.5 ns. If the design uses external feedback, the te delay will remove delay from outputs, represented by a negative sign (see Table 2-22). This effect occurs because the te delay is then part of the feedback loop.
Table 2-22. Output Clock Delay for Enhanced PLLs Normal or Zero Delay Buffer Mode
teOUTPUT = tn -tm + te tgOUTPUT = tn -tm + tg tlOUTPUT = tn -tm + tl Note to Table 2-22:
(1)
External Feedback Mode
teOUTPUT = tn -tm -te (1) tgOUTPUT = tn -tm + tg tlOUTPUT = tn -tm + tl
te removes delay from outputs in external feedback mode.
The variation due to process, voltage, and temperature is about 15% on the delay settings. PLL reconfiguration can control the clock delay shift elements, but not the VCO phase shift multiplexers, during system operation.
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Spread-Spectrum Clocking
Stratix device enhanced PLLs use spread-spectrum technology to reduce electromagnetic interference generation from a system by distributing the energy over a broader frequency range. The enhanced PLL typically provides 0.5% down spread modulation using a triangular profile. The modulation frequency is programmable. Enabling spread-spectrum for a PLL affects all of its outputs.
Lock Detect
The lock output indicates that there is a stable clock output signal in phase with the reference clock. Without any additional circuitry, the lock signal may toggle as the PLL begins tracking the reference clock. A designer may need to gate the lock signal for use as a system control. Either a gated lock signal or an ungated lock signal from the locked port can drive the logic array or an output pin. If the input clock stops and causes the PLL to lose lock, then the PLL must be reset for correct phase shift operation. This issue is isolated to the PLL lock circuit. All other PLL components are fully functional.
f
See the Stratix FPGA Errata Sheet for more information on implementing the gated lock signal in your design.
Programmable Duty Cycle
The programmable duty cycle allows enhanced PLLs to generate clock outputs with a variable duty cycle. This feature is supported on each enhanced PLL post-scale counter (g0..g3, l0..l3, e0..e3). The duty cycle setting is achieved by a low and high time count setting for the post-scale dividers. The Quartus II software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices.
Advanced Clear & Enable Control
There are several control signals for clearing and enabling PLLs and their outputs. The designer can use these signals to control PLL resynchronization and gate PLL output clocks for low-power applications. The pllenable pin is a dedicated pin that enables/disables PLLs. When the pllenable pin is low, the clock output ports are driven by GND and all the PLLs go out of lock. When the pllenable pin goes high again, the PLLs relock and resynchronize to the input clocks. The designer can
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choose which PLLs are controlled by the pllenable signal by connecting the pllenable input port of the altpll megafunction to the common pllenable input pin. The areset signals are reset/resynchronization inputs for each PLL. The areset signal should be asserted every time the PLL loses lock to guarantee correct phase relationship between the PLL output clocks. Users should include the areset signal in designs if any of the following conditions are true:

PLL Reconfiguration or Clock switchover enables in the design. Phase relationships between output clocks need to be maintained after a loss of lock condition
The device input pins or logic elements (LEs) can drive these input signals. When driven high, the PLL counters will reset, clearing the PLL output and placing the PLL out of lock. The VCO will set back to its nominal setting (~700 MHz). When driven low again, the PLL will resynchronize to its input as it relocks. If the target VCO frequency is below this nominal frequency, then the output frequency will start at a higher value than desired as the PLL locks. If the system cannot tolerate this, the clkena signal can disable the output clocks until the PLL locks. The pfdena signals control the phase frequency detector (PFD) output with a programmable gate. If the designer disables the PFD, the VCO will operate at its last set value of control voltage and frequency with some long-term drift to a lower frequency. The system will continue running when the PLL goes out of lock or the input clock is disabled. By maintaining the last locked frequency, the system has time to store its current settings before shutting down. Designers can either use their own control signal or clkloss or gated locked status signals to trigger pdfena. The clkena signals control the enhanced PLL regional and global outputs. Each regional and global output port has its own clkena signal. The clkena signals synchronously disable or enable the clock at the PLL output port by gating the outputs of the g and l counters. The clkena signals are registered on the falling edge of the counter output clock to enable or disable the clock without glitches. Figure 2-57 shows the waveform example for a PLL clock port enable. The PLL can remain locked independent of the clkena signals since the loop-related counters are not affected. This feature is useful for applications that require a low power or sleep mode. Upon re-enabling, the PLL does not need a resynchronization or relock period. The clkena signal can also disable clock outputs if the system is not tolerant to frequency overshoot during resynchronization.
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The extclkena signals work in the same way as the clkena signals, but they control the external clock output counters (e0, e1, e2, and e3). Upon re-enabling, the PLL does not need a resynchronization or relock period unless the PLL is using external feedback mode. In order to lock in external feedback mode, the external output must drive the board trace back to the FBIN pin. Figure 2-57. extclkena Signals
COUNTER OUTPUT
CLKENA
CLKOUT
Fast PLLs
Stratix devices contain up to eight fast PLLs with high-speed serial interfacing ability, along with general-purpose features. Figure 2-58 shows a diagram of the fast PLL.
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Figure 2-58. Stratix Device Fast PLL
Post-Scale Counters diffioclk1 (2) Global or regional clock txload_en (3)
/l0 VCO Phase Selection Selectable at each PLL Output Port Phase Frequency Detector /l1
rxload_en (3) Global or regional clock diffioclk2 (2)
Global or regional clock (1)
Clock Input
PFD
Charge Pump
Loop Filter
8 VCO
/g0
Global or regional clock
/m
Notes to Figure 2-58:
(1) (2) (3) The global or regional clock input can be driven by an output from another PLL or a pin-driven global or regional clock. It cannot be driven by internally-generated global signals. In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode. This signal is a high-speed differential I/O support SERDES control signal.
Clock Multiplication & Division
Stratix device Fast PLLs provide clock synthesis for PLL output ports using m/(post scaler) scaling factors. The input clock is multiplied by the m feedback factor. Each output port has a unique post scale counter to divide down the high-frequency VCO. There is one multiply divider, m, per fast PLL with a range of 1 to 32. There are two post scale L dividers for regional and/or LVDS interface clocks, and g0 counter for global clock output port; all range from 1 to 32. In the case of a high-speed differential interface, the designer can set the output counter to 1 to allow the high-speed VCO frequency to drive the SERDES.
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External Clock Inputs
Each fast PLL supports single-ended or differential inputs for source synchronous transmitters or for general-purpose use. Sourcesynchronous receivers support differential clock inputs. The fast PLL inputs are fed by CLK[0..3], CLK[8..11], and FPLL[7..10]CLK pins, as shown in Figure 2-50 on page 2-82. Table 2-23 shows the I/O standards supported by fast PLL input pins.
Table 2-23. Fast PLL Port I/O Standards (Part 1 of 2) Input I/O Standard INCLK
LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI 3.3-V PCI-X 1.0 LVPECL 3.3-V PCML LVDS HyperTransport technology Differential HSTL Differential SSTL 3.3-V GTL 3.3-V GTL+ 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II SSTL-18 class I SSTL-18 class II SSTL-2 class I
PLLENABLE v v
v v v v v
v v v v v v v v v v v v v v
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Table 2-23. Fast PLL Port I/O Standards (Part 2 of 2) Input I/O Standard INCLK
SSTL-2 class II SSTL-3 class I SSTL-3 class II AGP (1x and 2x ) CTT
PLLENABLE
v v v v v
Table 2-24 shows the performance on each of the fast PLL clock inputs when using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology.
Table 2-24. LVDS Performance on Fast PLL Input Fast PLL Clock Input
CLK0, CLK2, CLK9, CLK11, FPLL7CLK, FPLL8CLK, FPLL9CLK, FPLL10CLK CLK1, CLK3, CLK8, CLK10 Note to Table 2-24:
(1) See "Maximum Input & Output Clock Rates" on page 4-69
Maximum Input Frequency (MHz)
717(1)
500
External Clock Outputs
Each fast PLL supports differential or single-ended outputs for sourcesynchronous transmitters or for general-purpose external clocks. There are no dedicated external clock output pins. Any I/O pin can be driven by the fast PLL global or regional outputs as an external output pin. The I/O standards supported by any particular bank determines what standards are possible for an external clock output driven by the fast PLL in that bank.
Phase Shifting
Stratix device fast PLLs have advanced clock shift capability that enables programmable phase shifts. Designers can enter a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. Designers can perform phase shifting in time units with a resolution range of 125 to 416.66 ps. This resolution is a function of the VCO period, with the finest step being equal to an eighth (x0.125) of the VCO period.
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Control Signals
The fast PLL has the same lock output, pllenable input, and areset input control signals as the enhanced PLL. If the input clock stops and causes the PLL to lose lock, then the PLL must be reset for correct phase shift operation. For more information on high-speed differential I/O support, see "HighSpeed Differential I/O Support" on page 2-132.
I/O Structure
IOEs provide many features, including:

Dedicated differential and single-ended I/O buffers 3.3-V, 64-bit, 66-MHz PCI compliance 3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance Joint Test Action Group (JTAG) boundary-scan test (BST) support Differential on-chip termination for LVDS I/O standard Programmable pull-up during configuration Output drive strength control Slew-rate control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Programmable input and output delays Open-drain outputs DQ and DQS I/O pins Double-data rate (DDR) Registers
The IOE in Stratix devices contains a bidirectional I/O buffer, six registers, and a latch for a complete embedded bidirectional single data rate or DDR transfer. Figure 2-59 shows the Stratix IOE structure. The IOE contains two input registers (plus a latch), two output registers, and two output enable registers. The design can use both input registers and the latch to capture DDR input and both output registers to drive DDR outputs. Additionally, the design can use the output enable (OE) register for fast clock-to-output enable timing. The negative edge-clocked OE register is used for DDR SDRAM interfacing. The Quartus II software automatically duplicates a single OE register that controls multiple output or bidirectional pins.
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Figure 2-59. Stratix IOE Structure
Logic Array OE Register OE D Q
OE Register D Q
Output Register Output A D Q
CLK Output Register Output B D Q Input Register D Q
Input A Input B
Input Register D Q
Input Latch D ENA Q
The IOEs are located in I/O blocks around the periphery of the Stratix device. There are up to four IOEs per row I/O block and six IOEs per column I/O block. The row I/O blocks drive row, column, or direct link interconnects. The column I/O blocks drive column interconnects. Figure 2-60 shows how a row I/O block connects to the logic array. Figure 2-61 shows how a column I/O block connects to the logic array.
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Figure 2-60. Row I/O Block Connection to the Interconnect
R4, R8 & R24 Interconnects
C4, C8 & C16 Interconnects
I/O Interconnect I/O Block Local Interconnect 16 Control Signals from I/O Interconnect (1)
16
28 Data & Control Signals from Logic Array (2) 28 Horizontal I/O Block
LAB
io_dataouta[3..0] io_dataoutb[3..0]
Direct Link Interconnect to Adjacent LAB LAB Local Interconnect
Direct Link Interconnect to Adjacent LAB io_clk[7:0]
Horizontal I/O Block Contains up to Four IOEs
Notes to Figure 2-60:
(1) (2) The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0], four clocks io_clk[3..0], and four clear signals io_bclr[3..0]. The 28 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_coe[3..0], four input clock enables io_cce_in[3..0], four output clock enables io_cce_out[3..0], four clocks io_cclk[3..0], and four clear signals io_cclr[3..0].
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Figure 2-61. Column I/O Block Connection to the Interconnect
42 Data & Control Signals from Logic Array (2)
Vertical I/O Block
Vertical I/O Block Contains up to Six IOEs
16 Control Signals from I/O Interconnect (1) I/O Block Local Interconnect
16
42 IO_datain[3:0]
io_clk[7..0]
I/O Interconnect
R4, R8 & R24 Interconnects
LAB
LAB
LAB
LAB Local Interconnect
C4, C8 & C16 Interconnects
Notes to Figure 2-61:
(1) (2) The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0], four clocks io_bclk[3..0], and four clear signals io_bclr[3..0]. The 42 data and control signals consist of 12 data out lines; six lines each for DDR applications io_dataouta[5..0] and io_dataoutb[5..0], six output enables io_coe[5..0], six input clock enables io_cce_in[5..0], six output clock enables io_cce_out[5..0], six clocks io_cclk[5..0], and six clear signals io_cclr[5..0].
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Stratix devices have an I/O interconnect similar to the R4 and C4 interconnect to drive high-fanout signals to and from the I/O blocks. There are 16 signals that drive into the I/O blocks composed of four output enables io_boe[3..0], four clock enables io_bce[3..0], four clocks io_bclk[3..0], and four clear signals io_bclr[3..0]. The pin's datain signals can drive the IO interconnect, which in turn drives the logic array or other I/O blocks. In addition, the control and data signals can be driven from the logic array, providing a slower but more flexible routing resource. The row or column IOE clocks, io_clk[7..0], provide a dedicated routing resource for low-skew, high-speed clocks. I/O clocks are generated from regional, global, or fast regional clocks (see "PLLs & Clock Networks" on page 2-71). Figure 2-62 illustrates the signal paths through the I/O block. Figure 2-62. Signal Path through the I/O Block
Row or Column io_clk[7..0] io_boe[3..0] From I/O Interconnect io_bce[3..0] io_bclk[3..0] io_bclr[3..0] To Other IOEs
To Logic Array
io_datain0 io_datain1 oe ce_in ce_out io_coe io_cce_in io_cce_out Control Signal Selection aclr/preset sclr clk_in io_cclr clk_out io_cclk io_dataout0 io_dataout1 IOE
From Logic Array
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Each IOE contains its own control signal selection for the following control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset, clk_in, and clk_out. Figure 2-63 illustrates the control signal selection. Figure 2-63. Control Signal Selection per IOE
io_bclk[3..0] Dedicated I/O Clock [7..0] I/O Interconnect [15..0] Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect io_coe io_bce[3..0] io_bclr[3..0] io_boe[3..0]
io_cclr
io_cce_out
io_cce_in
io_cclk
clk_out
ce_out
sclr/preset
clk_in
ce_in
aclr/preset
oe
In normal bidirectional operation, the input register can be used for input data requiring fast setup times. The input register can have its own clock input and clock enable separate from the OE and output registers. The output register can be used for data requiring fast clock-to-output performance. The OE register can be used for fast clock-to-output enable timing. The OE and output register share the same clock source and the same clock enable source from local interconnect in the associated LAB, dedicated I/O clocks, and the column and row interconnects. Figure 2-64 shows the IOE in bidirectional configuration.
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Figure 2-64. Stratix IOE in Bidirectional I/O Configuration
Column or Row Interconnect ioe_clk[7..0]
Note (1)
I/O Interconnect [15..0]
OE OE Register D clkout ENA CLRN/PRN OE Register tCO Delay VCCIO Q Output tZX Delay
ce_out
Output Enable Clock Enable Delay Output Clock Enable Delay
Optional PCI Clamp
VCCIO
aclr/prn
Programmable Pull-Up Resistor
Chip-Wide Reset Output Register D Q Drive Strength Control Open-Drain Output Slew Control Output Pin Delay
Logic Array to Output Register Delay sclr/preset
ENA CLRN/PRN
Input Pin to Logic Array Delay Input Pin to Input Register Delay
Bus-Hold Circuit
Input Register clkin ce_in Input Clock Enable Delay D Q
ENA CLRN/PRN
Note to Figure 2-64:
(1) All input signals to the IOE can be inverted at the IOE.
The Stratix device IOE includes programmable delays that can be activated to ensure zero hold times, input IOE register-to-logic array register transfers, or logic array-to-output IOE register transfers. A path in which a pin directly drives a register may require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay. Programmable delays exist for decreasing input-pin-to-logic-array and IOE input register delays. The Quartus II Compiler can program these delays to automatically minimize setup time while providing a zero hold time. Programmable delays can increase the register-to-pin delays for output
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and/or output enable registers. A programmable delay exists to increase the tZX delay to the output pin, which is required for ZBT interfaces. Table 2-25 shows the programmable delays for Stratix devices.
Table 2-25. Stratix Programmable Delay Chain Programmable Delays
Input pin to logic array delay Input pin to input register delay Output pin delay Output enable register tCO delay Output tZX delay Output clock enable delay Input clock enable delay Logic array to output register delay Output enable clock enable delay
Quartus II Logic Option
Decrease input delay to internal cells Decrease input delay to input register Increase delay to output pin Increase delay to output enable pin Increase tZX delay to output pin Increase output clock enable delay Increase input clock enable delay Decrease input delay to output register Increase output enable clock enable delay
The IOE registers in Stratix devices share the same source for clear or preset. The designer can program preset or clear for each individual IOE. The designer can also program the registers to power up high or low after configuration is complete. If programmed to power up low, an asynchronous clear can control the registers. If programmed to power up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of another device's active-low input upon power-up. If one register in an IOE uses a preset or clear signal then all registers in the IOE must use that same signal if they require preset or clear. Additionally a synchronous reset signal is available to the designer for the IOE registers.
Double-Data Rate I/O Pins
Stratix devices have six registers in the IOE, which support DDR interfacing by clocking data on both positive and negative clock edges. The IOEs in Stratix devices support DDR inputs, DDR outputs, and bidirectional DDR modes. When using the IOE for DDR inputs, the two input registers clock double rate input data on alternating edges. An input latch is also used within the IOE for DDR input acquisition. The latch holds the data that is present during the clock high times. This allows both bits of data to be synchronous with the same clock edge (either rising or falling). Figure 2-65 shows an IOE configured for DDR input.
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Figure 2-65. Stratix IOE in DDR Input I/O Configuration
Column or Row Interconnect ioe_clk[7..0] (1) DQS Local Bus (1), (2)
Note (1)
VCCIO To DQS Local Bus (3)
Optional PCI Clamp
VCCIO
I/O Interconnect [15..0] (1)
Programmable Pull-Up Resistor
Input Pin to Input Register Delay sclr Input Register D clkin ENA CLRN/PRN Q
Output Clock Enable Delay aclr/prn
Bus-Hold Circuit
Chip-Wide Reset Input Register D Q D Latch Q
ENA CLRN/PRN
ENA CLRN/PRN
Notes to Figure 2-65:
(1) (2) (3) All input signals to the IOE can be inverted at the IOE. This signal connection is only allowed on dedicated DQ function pins. This signal is for dedicated DQS function pins only.
When using the IOE for DDR outputs, the two output registers are configured to clock two data paths from LEs on rising clock edges. These output registers are multiplexed by the clock to drive the output pin at a x2 rate. One output register clocks the first bit out on the clock high time, while the other output register clocks the second bit out on the clock low time. Figure 2-66 shows the IOE configured for DDR output.
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Figure 2-66. Stratix IOE in DDR Output I/O Configuration
Column or Row Interconnect IOE_CLK[7..0]
Notes (1), (2)
I/O Interconnect [15..0]
OE Register D clkout ENA CLRN/PRN Output Enable Clock Enable Delay Output Clock Enable Delay aclr/prn VCCIO Q Output tZX Delay
OE Register tCO Delay
Chip-Wide Reset
OE Register D sclr ENA CLRN/PRN Q
Optional PCI Clamp
VCCIO
Used for DDR SDRAM
Programmable Pull-Up Resistor
Logic Array to Output Register Delay
Output Register D Q Output Pin Delay clk
ENA CLRN/PRN
Logic Array to Output Register Delay
Output Register D Q
Drive Strength Control Open-Drain Output Slew Control
ENA CLRN/PRN
Bus-Hold Circuit
Notes to Figure 2-66:
(1) (2) All input signals to the IOE can be inverted at the IOE. The tristate is by default active high. You can, however, design it to be active low.
The Stratix IOE operates in bidirectional DDR mode by combining the DDR input and DDR output configurations. Stratix device I/O pins transfer data on a DDR bidirectional bus to support DDR SDRAM. The negative-edge-clocked OE register holds the OE signal inactive until the falling edge of the clock. This is done to meet DDR SDRAM timing requirements.
External RAM Interfacing
Stratix devices support DDR SDRAM at up to 200 MHz (400 Mbps data rate) through dedicated phase-shift circuitry, QDR and QDRII SRAM interfaces up to 167 MHz, and ZBT SRAM interfaces at up to 200 MHz.
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Stratix devices also provide preliminary support for reduced latency DRAM at rates up to 200 MHz through the dedicated phase-shift circuitry. 1 In addition to the required signals for external memory interfacing, Stratix devices offer the optional clock enable signal. When the clock enable signal is used, the output register updates with new values. The output registers hold their old values when the clock enable signal is disabled.
f
To find out more about the DDR SDRAM specification, see the JEDEC web site (www.jedec.org). For information on memory controller megafunctions for Stratix devices, see the Altera web site (www.altera.com). Table 2-26 shows the performance specification for DDR SDRAM, RLDRAM II, and QDR SRAM interfaces with flip-chip and wire-bond packages. The pin tables define the package type in the notes section. The numbers in Table 2-26 (except the RLDRAM II numbers) have been verified with hardware characterization with third-party DDR SDRAM and QDR SRAM devices over temperature and voltage extremes.
Table 2-26. Stratix External RAM Performance Maximum Clock Rate DDR Memory Type I/O Standard -5 Speed Grade -6 Speed Grade WireBond
133 MHz N/A 167 MHz
-7 Speed Grade Flip-Chip
133 MHz N/A 133 MHz
-8 Speed Grade Flip-Chip WireBond
N/A
Flip-Chip Flip-Chip
DDR SDRAM (1) SSTL-2 RLDRAM II QDR SRAM (2)
(1) (2)
WireBond
100 MHz N/A 133 MHz
200 MHz 200 MHz 167 MHz
167 MHz N/A 167 MHz
100 MHz 100 MHz N/A
1.8-V HSTL 1.5-V HSTL
133 MHz 133 MHz
Notes to Table 2-26:
The DDR SDRAM clock rate is based on the use of the DQS phase shift circuitry. For more information on QDR SRAM, see the QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices chapter in the Stratix Handbook.
DDR SDRAM
In addition to six I/O registers and one input latch in the IOE for interfacing to these high-speed memory interfaces, Stratix devices also have dedicated circuitry for interfacing with DDR SDRAM. In every
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Stratix device, the I/O banks at the top (I/O banks 3 and 4) and bottom (I/O banks 7 and 8) of the device support DDR SDRAM up to 200 MHz. These pins support DQS signals with DQ bus modes of x8, x16, or x32. For x8 mode, there are up to 20 groups of programmable DQS and DQ pins--10 groups in I/O banks 3 and 4 and 10 groups in I/O banks 7 and 8. See Table 2-27. Each group consists of one DQS pin and a set of eight DQ pins. Each DQS pin drives the set of eight DQ pins within that group. The DQS pins are marked in the Stratix pin table as DQS[9..0]T or DQS[9..0]B, where T stands for top and B for bottom. The corresponding DQ pins are marked as DQ[9..0]T[7..0], where [9..0] indicates which DQS group the pins belong to. The numbering scheme starts from right to left on the package bottom view. For x16 mode, there are up to eight groups of programmable DQS and DQ pins--four groups in I/O banks 3 and 4, and four groups in I/O banks 7 and 8. The EP1S20 device supports seven x16 groups. The EP1S10 device does not support x16 mode. All other devices support the full eight groups. See Table 2-27. Each group consists of one DQS and 16 DQ pins. In x16 mode, DQS1T, DQS3T, DQS6T, and DQS8T pins on the top side of the device, and DQS1B, DQS3B, DQS6B, and DQS8B pins on the bottom side of the device are dedicated DQS pins. The DQS2T, DQS7T, DQS2B, and DQS7B pins are dedicated DQS pins for x32 mode. You can use any of the column I/O pins for the DM signals. 1 If the Stratix device interfaces with a x16 memory device that uses two DQS pins and each DQS pin drives eight DQ pins, the Stratix device must use two sets of x8 groups. Similarly, if the Stratix device interfaces with a x32 memory device that uses four DQS pins and each DQS pin drives eight DQ pins, the Stratix device must use four sets of the x8 groups. The Stratix device's x16 mode means that there is one DQS pin for 16 DQ pins and the Stratix device's x32 mode means that there is only one DQS pin driving all 32 DQ pins..
A compensated delay element on each DQS pin allows for either a 90 or a 72 phase shift, which automatically aligns input DQS synchronization signals with the data window of their corresponding DQ data signals. The DQS signals drive a local DQS bus within the top and bottom I/O banks. This DQS bus is an additional resource to the I/O clocks and is used to clock DQ input registers with the DQS signal. 1 The side I/O pins in I/O banks 1, 2, 5, and 6 can interface with the DDR SDRAM at up to 150 MHz. See Chapter 8, Double Data Rate I/O Signaling in Stratix & Stratix GX Devices of the Stratix Device Handbook, Volume 2.
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Table 2-27. DQS & DQ Bus Mode Support Device
EP1S10
Note (1) Number of Number of x16 Groups x32 Groups
0 0 7 7 (5) 7 (5) 8 8 8 0 4 4 4 4 4 4 4
Package
672-pin BGA 672-pin FineLine BGA 484-pin FineLine BGA 780-pin FineLine BGA
Number of x8 Groups
12 (2) 16 (3) 18 (4) 16 (3) 20 16 (3) 20 20
EP1S20
484-pin FineLine BGA 672-pin BGA 672-pin FineLine BGA 780-pin FineLine BGA
EP1S25
672-pin BGA 672-pin FineLine BGA 780-pin FineLine BGA 1,020-pin FineLine BGA
EP1S30
956-pin BGA 780-pin FineLine BGA 1,020-pin FineLine BGA 956-pin BGA 1,020-pin FineLine BGA 1,508-pin FineLine BGA 956-pin BGA 1,020-pin FineLine BGA 1,508-pin FineLine BGA 956-pin BGA 1,508-pin FineLine BGA 1,923-pin FineLine BGA
EP1S40
20
8
4
EP1S60
20
8
4
EP1S80
20
8
4
Notes to Table 2-27:
(1) (2) (3) (4) (5) See Chapter 4, Using Selectable I/O Standards in Stratix & Stratix GX Devices of the Stratix Device Handbook, Volume 2 for VREF guidelines. These packages have six groups in I/O banks 3 and 4 and six groups in I/O banks 7 and 8. These packages have eight groups in I/O banks 3 and 4 and eight groups in I/O banks 7 and 8. This package has nine groups in I/O banks 3 and 4 and nine groups in I/O banks 7 and 8. These packages have three groups in I/O banks 3 and 4 and four groups in I/O banks 7 and 8.
A single phase shifting reference circuit is located on the top and bottom of the Stratix device. This circuit is driven by a system reference clock through the CLK pins that is the same frequency as the DQS signal. Clock pins CLK12p to CLK15p feed the phase circuitry on the top of the device and clock pins CLK4p to CLK7p feed the phase circuitry on the bottom of
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the device. The phase shifting reference circuit on the top of the device controls the compensated delay elements for all ten DQS pins located at the top of the device. The phase shifting reference circuit on the bottom of the device controls the compensated delay elements for all ten DQS pins located on the bottom of the device. All ten delay elements (DQS signals) on either the top or bottom of the device shift by the same degree amount. For example, all ten DQS pins on the top of the device can be shifted by 90 and all ten DQS pins on the bottom of the device can be shifted by 72. The reference circuit requires a maximum of 256 system reference clock cycles to set the correct phase on the DQS delay elements. Figure 2-67 illustrates the phase shift reference circuit control of each DQS delay shift on the top of the device. This same circuit is duplicated on the bottom of the device. Figure 2-67. Phase Shift Reference Circuit Control of DQS Delay
CLK[15..12] DQS Pin DQS Pin DQS Pin DQS Pin DQS Pin DQS Pin DQS Pin DQS Pin DQS Pin DQS Pin Compensated Delay Element
t
t
t
t
t
Phase Shift Reference Circuit
t
t
t
t
t
DQS Bus
Note to Figure 2-67:
(1) This circuit is repeated on the bottom of the device with the CLK[4..7] pins as possible inputs to the reference circuit.
The DQS phase shift circuitry uses a DLL to generate the phase shift needed by the DQS pin. The input reference clock goes into both a phase comparator and a set of delay elements. The signal coming out of the end of the delay elements chain goes into the phase comparator. The phase comparator then issues a signal to the up/down that will adjust the delay elements so that the input reference clock and the signals coming out from the delay elements chain are in phase. Figure 2-68 shows asimplified diagram of the DQS phase shift circuitry.
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Figure 2-68. Simplified Diagram of the DQS Phase Shift Circuitry
Input Reference Clock
Phase Comparator
Up/Down Counter
Delay Chains
6
Control Signals to DQS Pins
These dedicated circuits combined with enhanced PLL clocking and phase shift ability provide a complete hardware solution for interfacing to high-speed memory. When reading from the DDR SDRAM, the DQS signal coming into the Stratix device is edge-aligned with the DQ pins. The dedicated circuitry center-aligns the DQS signal with respect to the DQ signals and the shifted DQS bus drives the clock input of the DDR input registers. The DDR input registers bring the data from the DQ signals to the device. The system clock is used to clock the DQS output enable and output paths. The -90 shifted clock is used to clock the DQ output enable and output paths. To meet 200-MHz performance for DDR SDRAM interfaces the following guidelines should be used:
Resynchronize the incoming data to the logic array clock using successive LE registers. The Stratix device can use either the rising or falling edge of the system clock to resynchronize the DQ signals. LE registers must be placed in the LAB adjacent to the DQ I/O pin column it is fed by.
The DQS and DQ pins in the Stratix devices output SSTL-2 class IIcompliant signals. Stratix devices also can drive differential SSTL-2 class II signals on the output clock pins. Figure 2-69 shows how the data is sampled using the shifted DQS signals.
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Figure 2-69. Input Timing Diagram in DDR Mode
DQ A0 B1 A1 B2 A2 B3 A3 B4
DQS Shifted 90
DQS
A'
A1
A2
A3 To Logic Array
B'
B1
B2
B3
Note to Figure 2-69
(1) DQS and DQ signals are both inputs. The DQS signal is externally edge-aligned with the data DQ signal.
When writing to the DDR SDRAM/FCRAM, the DQS signal must be center-aligned with the DQ pins. Two PLL outputs are needed to generate the DQS signal and to clock the DQ pins. The DQS are clocked by the 1x PLL output, while the DQ pins are clocked by the -90 phase-shifted 1x PLL output. Figure 2-70 shows the DQS and DQ output timing diagram.
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Figure 2-70. Output TIming Diagram in DDR Mode
CLK
DQ_CLK
DQS
A From LE Registers B B1
A2
A3
A4
B2
B3
B4
DQ
B1
A1
B2
A2
B3
A3
Figure 2-71 illustrates DDR SDRAM and FCRAM interfacing from the I/O through the dedicated circuitry to the logic array. When the DQS pin acts as an input strobe, the dedicated circuitry shifts the incoming DQS pin by either 90 and clock the DDR input registers. Due to the DDR input registers architecture in Stratix, the shifted DQS signal must be inverted. The DDR registers output is sent to two LE registers to be synchronized with the system clock. When the DQS pin acts as the output strobe, the 1x clock output from the PLL generates the DQS signal, while the shifted 1x PLL clock output clocks the DQ pins. The resynchronizing global clock in Figure 2-71 is usually the non-phase-shifted clock from the PLL output. If the PLL generating the DQ and DQS clocks uses a clock other than the 1x clock, the PLL output must go off-chip and then back onto the chip for use as the input reference clock.
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Figure 2-71. DDR SDRAM Interfacing
DQS DQ
Compensated Delay Shift
OE
DDR OE Registers
User logic/ 2 GND
2
DDR Output Registers
2
DDR Output Registers DDR Input Registers
OE t
DDR OE Registers
I/O Elements & Periphery
PLL
- 90 DQS Bus
LE Register
LE Register Resynchronizing Global Clock
Adjacent LAB LEs
f
For more information on external memory interfacing, refer to Chapter 8,
Double Data Rate I/O Signaling in Stratix & Stratix GX Devices of the Stratix Device
Handbook, Volume 2. and the DDR SDRAM Controller MegaCore Function User Guide.
RLDRAM I & II
Reduced latency DRAM (RLDRAM) I and II also use DDR signaling to transfer data into and out of the memory. RLDRAM I uses a pair of DQS pins, one at 180 degree phase shift with respect to the other. Since Stratix devices do not have differential DQS pins, the DQS# signal is ignored. The DQS itself is only used when the Stratix device reads from the RLDRAM I device because the Stratix device uses the RLDRAM clocks for writing to the RLDRAM. RLDRAM II uses two separate, free-running, unidirectional data strobes (DKx/DKx# and QKx/QKx#) for writing to, and reading from the RLDRAM II device. The QKx strobes should be routed to the DQS pins on the Stratix device. The QKx# strobes should be ignored since Stratix devices do not have differential DQS pins. The Stratix device can generate the DKx/DKx# strobes with the enhanced PLL's differential clock outputs. This implementation will give the strobes the best jitter performance.
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RLDRAM I and II use the 1.8-V HSTL I/O standard. Stratix devices support operation up to 200 MHz.
f
For more information on Stratix device support for RLDRAM I and II, contact Altera Applications.
QDR & QDR II SRAM
QDR SRAM provides independent read and write ports that eliminate bus turnaround. The memory uses two sets of clocks: K and Kn for write access, and C and Cn for read accesses, where Kn and Cn are the inverse of the K and C clocks, respectively. You can use differential HSTL I/O pins to drive the QDR SRAM clock into the Stratix device. The separate write data and read data ports permit a transfer rate up to four words on every cycle through the DDR circuitry. Stratix devices support both burst-of-2 and burst-of-4 QDR SRAM architectures, with clock cycles up to 167 MHz using the 1.5-V HSTL class I or class II I/O standard. Figure 2-72 shows the block diagram for QDR SRAM burst-of-2 architecture. Figure 2-72. QDR SRAM Block diagram for Burst-Of-2 Architecture
Discrete QDR SRAM Device
A BWSn WPSn D
18 Write Port 18 18 2 256K x 18 Memory Array 256K x 18 Memory 36 Array Data Read Port RPSn 2 C, Cn Q
36 Data
K, Kn VREF
Control Logic
Stratix devices utilize the DDR I/O circuitry for the input and output data bus and the K and Kn output clock signals. Figure 2-73 shows QDR SRAM interfacing from the I/O pin using the DDR I/O circuitry. Stratix devices also support QDR II SRAM at higher clock speeds since the timing requirements for QDR II SRAM are not as strict as QDR SRAM. Altera offers a QDR SRAM Controller Reference Design that can be modified to interface with multiple QDR SRAM devices.
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Figure 2-73. QDR SRAM Interfacing
Stratix Device
INCLK write_clk_pll WRITE_CLK_90 DDR I/O K
L1
DDR I/O
Kn
L1
DDR I/O
K_FB_OUT
L1
QDR SRAM Device
read_clk_pll DDR I/O
K_FB_IN Q
L2 L2
READ_CLK DDR I/O WRITE_CLK D, A
L1
VCC C, Cn
f
Go to www.qdrsram.com for the QDR SRAM specifications. For more information on QDR SRAM Interfaces in Stratix devices, see Chapter 2, QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices of the Stratix Device Handbook, Volume 2.
Zero Bus Turnaround SRAM Interface Support
In addition to DDR SDRAM support, Stratix device I/O pins can also interface with ZBT SRAM devices at up to 200 MHz. ZBT SRAM blocks eliminate dead bus cycles when turning a bidirectional bus around between reads and writes or between writes and reads. ZBT allows for 100% bus utilization because ZBT SRAM can be read or written on every clock cycle. Bus contention can occur when shifting from a write cycle to a read cycle or vice versa with no idle cycles in between. ZBT SRAM allows small amounts of bus contention. Bus contention will not damage Stratix device I/O drivers, but it will increase the power dissipation. To avoid bus contention, the output clock-to-low-impedance time (tZX) must be greater than the clock-to-high-impedance time (tXZ). Stratix devices can meet ZBT tCO and tSU timing requirements by controlling phase delay in clocks to the OE/output and input registers using an enhanced PLL. Figure 2-74 shows a flow-through ZBT SRAM operation where the A1 and A3 are read addresses and A2 and A4 are write addresses. For
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pipelined ZBT SRAM operation, data is delayed by another clock cycle. Stratix devices support up to 200-MHz ZBT SRAM operation using the 2.5-V or 3.3-V LVTTL I/O standard. Figure 2-74. tZX & tXZ Timing Diagram
tZX clock
addr
A1
A2
A3 tXZ
A4
dataout
Q(A1) ZBT Bus Sharing Device tZX
Q(A3)
datain
D(A3)
wren
Programmable Drive Strength
The output buffer for each Stratix device I/O pin has a programmable drive strength control for certain I/O standards. The LVTTL and LVCMOS standard has several levels of drive strength that the user can control. SSTL-3 class I and II, SSTL-2 class I and II, HSTL class I and II, and 3.3-V GTL+ support a minimum setting, the lowest drive strength that guarantees the IOH/IOL of the standard. Using minimum settings provides signal slew rate control to reduce system noise and signal overshoot.
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Table 2-28 shows the possible settings for the I/O standards with drive strength control.
Table 2-28. Programmable Drive Strength I/O Standard
3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS Notes to Table 2-28:
(1) (2) This is the Quartus II software default current setting. I/O banks 1, 2, 5, and 6 do not support this setting.
IOH / IOL Current Strength Setting (mA)
24 (1), 16, 12, 8, 4 24 (2), 12 (1), 8, 4, 2 16 (1), 12, 8, 2 12 (1), 8, 2 8 (1), 4, 2
Open-Drain Output
Stratix devices provide an optional open-drain (equivalent to an opencollector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and writeenable signals) that can be asserted by any of several devices.
Slew-Rate Control
The output buffer for each Stratix device I/O pin has a programmable output slew-rate control that can be configured for low-noise or highspeed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay to rising and falling edges. Each I/O pin has an individual slew-rate control, allowing the designer to specify the slew rate on a pin-by-pin basis. The slew-rate control affects both the rising and falling edges.
Bus Hold
Each Stratix device I/O pin provides an optional bus-hold feature. The bus-hold circuitry can weakly hold the signal on an I/O pin at its lastdriven state. Since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, you do not need an external pullup or pull-down resistor to hold a signal level when the bus is tri-stated.
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Table 2-29 shows bus hold support for different pin types.
Table 2-29. Bus Hold Support Pin Type
I/O pin
Bus Hold
v
CLK[0,2,9,11] CLK[1,3,8,10]] FCLK FPLL[7..10]CLK
v
The bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. The designer can select this feature individually for each I/O pin. The bus-hold output will drive no higher than VCCIO to prevent overdriving signals. If the bus-hold feature is enabled, the programmable pull-up option cannot be used. Disable the bus-hold feature when using open-drain outputs with the GTL+ I/O standard or when the I/O pin has been configured for differential signals. The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately 7 k to weakly pull the signal level to the last-driven state. Table 4-31 on page 4-15 gives the specific sustaining current driven through this resistor and overdrive current used to identify the nextdriven input level. This information is provided for each VCCIO voltage level. The bus-hold circuitry is active only after configuration. When going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration.
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Programmable Pull-Up Resistor
Each Stratix device I/O pin provides an optional programmable pull-up resistor during user mode. If you enable this feature for an I/O pin, the pull-up resistor (typically 25 k) weakly holds the output to the VCCIO level of the output pin's bank. Table 2-29 shows which pin types support the weak pull-up resistor feature.
Table 2-30. Programmable Weak Pull-Up Resistor Support Pin Type
I/O pins
Programmable Weak Pull-Up Resistor
v
CLK[0,2,9,11] CLK[1,3,8,10]] FCLK FPLL[7..10]CLK
Configuration pins JTAG pins Note to Table 2-30:
(1) TDO pins do not support programmable weak pull-up resistors.
v
v (1)
Advanced I/O Standard Support
Stratix device IOEs support the following I/O standards:

LVTTL LVCMOS 1.5 V 1.8 V 2.5 V 3.3-V PCI 3.3-V PCI-X 1.0 3.3-V AGP (1x and 2x) LVDS LVPECL 3.3-V PCML HyperTransport Differential HSTL (on input/output clocks only) Differential SSTL (on output column clock pins only) GTL/GTL+ 1.5-V HSTL class I and II 1.8-V HSTL Class I and II SSTL-3 class I and II SSTL-2 class I and II
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SSTL-18 class I and II CTT
Table 2-31 describes the I/O standards supported by Stratix devices.
Table 2-31. Stratix Supported I/O Standards I/O Standard
LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI 3.3-V PCI-X 1.0 LVDS LVPECL 3.3-V PCML HyperTransport Differential HSTL (1) Differential SSTL (2) GTL GTL+ 1.5-V HSTL class I and II 1.8-V HSTL class I and II SSTL-18 class I and II SSTL-2 class I and II SSTL-3 class I and II AGP (1x and 2x) CTT Notes to Table 2-31:
(1) (2) This I/O standard is only available on input and output clock pins. This I/O standard is only available on output column clock pins.
Type
Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Differential Differential Differential Differential Differential Differential Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced
Input Reference Voltage (VREF) (V)
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0.75 1.25 0.8 1.0 0.75 0.9 0.90 1.25 1.5 1.32 1.5
Output Supply Voltage (VCCIO) (V)
3.3 3.3 2.5 1.8 1.5 3.3 3.3 3.3 3.3 3.3 2.5 1.5 2.5 N/A N/A 1.5 1.8 1.8 2.5 3.3 3.3 3.3
Board Termination Voltage (VTT) (V)
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0.75 1.25 1.20 1.5 0.75 0.9 0.90 1.25 1.5 N/A 1.5
f
For more information on I/O standards supported by Stratix devices, see Chapter 4, Using Selectable I/O Standards in Stratix & Stratix GX Devices of the Stratix Device Handbook, Volume 2.
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Stratix Device Handbook, Volume 1
Stratix devices contain eight I/O banks in addition to the four enhanced PLL external clock out banks, as shown in Figure 2-75. The four I/O banks on the right and left of the device contain circuitry to support highspeed differential I/O for LVDS, LVPECL, 3.3-V PCML, and HyperTransport inputs and outputs. These banks support all I/O standards listed in Table 2-31 except PCI I/O pins or PCI-X 1.0, GTL, SSTL-18 Class II, and HSTL Class II outputs. The top and bottom I/O banks support all single-ended I/O standards. Additionally, Stratix devices support four enhanced PLL external clock output banks, allowing clock output capabilities such as differential support for SSTL and HSTL. Table 2-32 shows I/O standard support for each I/O bank.
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Figure 2-75. Stratix I/O Banks
DQS9T
PLL7
Notes (1), (2), (3)
DQS6T DQS5T 9 PLL5 10 DQS4T PLL11 DQS3T DQS2T
Bank 4 VREF4B5 VREF3B5 VREF2B5 VREF1B5 VREF4B6 VREF3B6 VREF2B6 VREF1B6
DQS8T
DQS7T
Bank 3
DQS1T
DQS0T
VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3
VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4 PLL10
VREF1B2 VREF2B2 VREF3B2 VREF4B2
LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4)
Bank 2
LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4) I/O Banks 3, 4, 9 & 10 Support All Single-Ended I/O Standards (5)
Bank 5 Bank 6
(5)
PLL1
PLL2 VREF1B1 VREF2B1 VREF3B1 VREF4B1
I/O Banks 1, 2, 5, and 6 Support All Single-Ended I/O Standards Except Differential HSTL Output Clocks, Differential SSTL-2 Output Clocks, HSTL Class II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1x/2x
PLL4
PLL3
Bank 1
(5) LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4)
I/O Banks 7, 8, 11 & 12 Support All Single-Ended I/O Standards LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4)
(5)
Bank 8
PLL8 VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8
11 DQS6B DQS5B
12 PLL12 DQS4B DQS3B
Bank 7
VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7 PLL9
DQS9B
DQS8B
DQS7B
PLL6
DQS2B
DQS1B
DQS0B
Notes to Figure 2-75:
(1) (2) (3) (4) (5) Figure 2-75 is a top view of the silicon die. This will correspond to a top-down view for non-flip-chip packages, but will be a reverse view for flip-chip packages. Figure 2-75 is a graphic representation only. Refer to the pin list and the Quartus II software for exact locations. Banks 9 through 12 are enhanced PLL external clock output banks. If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the I/O standards except HSTL class I and II, GTL, SSTL-18 Class II, PCI, PCI-X 1.0, and AGP 1x /2x . You can only place single-ended input pads four or more pads away from a differential pad. You can only place single-ended output/bidirectional pads five or more pads away from a differential pad. Use the Show Pads view in the Quartus II Floorplan Editor to locate these pads. The Quartus II software will give an error message for illegal output or bidirectional pin placement next to a high-speed differential I/O pin.
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Table 2-32 shows I/O standard support for each I/O bank.
Table 2-32. I/O Support by Bank (Part 1 of 2) I/O Standard
LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI 3.3-V PCI-X 1.0 LVPECL 3.3-V PCML LVDS HyperTransport technology Differential HSTL (clock inputs) Differential HSTL (clock outputs) Differential SSTL (clock outputs) 3.3-V GTL 3.3-V GTL+ 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II SSTL-18 class I SSTL-18 class II SSTL-2 class I SSTL-2 class II SSTL-3 class I
Top & Bottom Banks (3, 4, 7 & 8) v v v v v v v
Left & Right Banks (1, 2, 5 & 6) v v v v v
Enhanced PLL External Clock Output Banks (9, 10, 11 & 12) v v v v v v v
v v v v v v v v v v v v v v v v v v v
(1)
v v v v v v v v v v v
v v
(1)
v
(1)
v
(1)
v v v
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Table 2-32. I/O Support by Bank (Part 2 of 2) I/O Standard
SSTL-3 class II AGP (1x and 2x ) CTT Note to Table 2-32:
(1) These I/O standards are only supported for input pins.
Top & Bottom Banks (3, 4, 7 & 8) v v v
Left & Right Banks (1, 2, 5 & 6) v
(1)
Enhanced PLL External Clock Output Banks (9, 10, 11 & 12) v v v
v
Each I/O bank has its own VCCIO pins. A single device can support 1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different standard independently. Each bank also has dedicated VREF pins to support any one of the voltage-referenced standards (such as SSTL-3) independently. Each I/O bank can support multiple standards with the same VCCIO for input and output pins. Each bank can support one voltage-referenced I/O standard. For example, when VCCIO is 3.3 V, a bank can support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
Differential On-Chip Termination
Stratix devices provide differential on-chip termination (LVDS I/O standard) to reduce reflections and maintain signal integrity. Differential on-chip termination simplifies board design by minimizing the number of external termination resistors required. Termination can be placed inside the package, eliminating small stubs that can still lead to reflections. The internal termination is designed using transistors in the linear region of operation. Stratix devices support internal differential temination with a nominal resistance value of 137.5 for LVDS input receiver buffers. LVPECL signals require an external termination resistor. Figure 2-76 shows the device with differential termination.
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Figure 2-76. LVDS Input Differential On-Chip Termination
Transmitting Device Receiving Device with Differential Termination
Z0
+
RD Z0
+
I/O banks on the left and right side of the device support LVDS receiver (far-end) differential termination. Table 2-33 shows the Stratix device differential termination support.
Table 2-33. Differential Termination Supported by I/O Banks Differential Termination Support
Differential termination (1), (2) Notes to
(1) (2) Clock pin CLK0, CLK2, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential termination. Differential termination is only supported for LVDS as it requires 3.3-V VC C I O .
I/O Standard Support
LVDS
Top & Bottom Banks (3, 4, 7 & 8)
Left & Right Banks (1, 2, 5 & 6)
v
Table 2-34 shows the termination support for different pin types.
Table 2-34. Differential Termination Support Across Pin Types Pin Type
Top and bottom I/O banks (3, 4, 7, and 8) Left and right I/O banks (1, 2, 5, and 6) v v
RD
DIFFIO_RX[] CLK[0,2,9,11] CLK[1,3,8,10] FCLK FPLL[7..10]CLK
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The differential on-chip termination circuitry was designed and simulated. The differential on-chip resistence at the receiver input buffer is 118 20 %. However, there is additional resistance present between the device ball and the input of the receiver buffer as shown in Figure 2-77. This resistance is due to package trace resistance (which can be calculated as the resistance from the package ball to the pad) and the parasitic layout metal routing resistance (which is shown between the pad and the intersection of the on-chip termination and input buffer). Figure 2-77. Differential Resistance of LVDS Differential Pin Pair (RD)
0.3 RD Differential On-Chip Termination Resistor 9.3 LVDS Input Buffer
0.3 Pad Package Ball
9.3
Table 2-35 defines the specification for internal termination resistance for commercial devices.
Table 2-35. Differential On-Chip Termination Resistance Symbol
RD (2)
Description
Internal differential termination for LVDS
Conditions Min
Commercial (1), (3) Industrial (2), (3) 100
Unit Typ
135
Max
165 170
110 137.5
Notes to Table 2-35:
(1) (2) (3) Data measured over minimum conditions (Tj = 0 C, VC C I O +5%) and maximum conditions (Tj = 85 C, VC C I O = -5%). Data measured over minimum conditions (Tj = -40 C, VCCIO +5%) and maximum conditions (Tj = 100 C, VCCIO = -5%). LVDS data rate is supported for 840 Mbps using internal differential termination.
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MultiVolt I/O Interface
The Stratix architecture supports the MultiVolt I/O interface feature, which allows Stratix devices in all packages to interface with systems of different supply voltages. The Stratix VCCINT pins must always be connected to a 1.5-V power supply. With a 1.5-V VCCINT level, input pins are 1.5-V, 1.8-V, 2.5-V, and 3.3-V tolerant. The VCCIO pins can be connected to either a 1.5-V, 1.8-V, 2.5-V, or 3.3-V power supply, depending on the output requirements. The output levels are compatible with systems of the same voltage as the power supply (i.e., when VCCIO pins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems). When VCCIO pins are connected to a 3.3-V power supply, the output high is 3.3 V and is compatible with 3.3-V or 5.0-V systems. Table 2-36 summarizes Stratix MultiVolt I/O support.
Table 2-36. Stratix MultiVolt I/O Support VCCIO (V)
1.5 1.8 2.5 3.3 Notes to Table 2-36:
(1) (2) (3) (4)
Note (1) Output Signal 3.3 V v (2) v (2) v v v (4) 5.0 V 1.5 V v v (3) v (3) v (3) v v (3) v (3) v v (3) v v 1.8 V 2.5 V 3.3 V 5.0 V
Input Signal 1.5 V v v (2) 1.8 V v v 2.5 V v (2) v (2) v v (2)
To drive inputs higher than VCCIO but less than 4.1 V, disable the PCI clamping diode. However, to drive 5.0-V inputs to the device, enable the PCI clamping diode to prevent VI from rising above 4.1 V. The pin current may be slightly higher than the default value. Contact Altera Applications for details. Although VCCIO specifies the voltage necessary for the Stratix device to drive out, a receiving device powered at a different level can still interface with the Stratix device if it has inputs that tolerate the VCCIO value. Stratix devices can be 5.0-V tolerant with the use of an external resistor and the internal PCI clamp diode.
High-Speed Differential I/O Support
Stratix devices contain dedicated circuitry for supporting differential standards at speeds up to 840 Mbps. The following differential I/O standards are supported in the Stratix device: LVDS, LVPECL, HyperTransport, and 3.3-V PCML.
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There are four dedicated high-speed PLLs in the EP1S10 to EP1S25 devices and eight dedicated high-speed PLLs in the EP1S30 to EP1S80 devices to multiply reference clocks and drive high-speed differential SERDES channels. Additional high speed DIFFIO pin information for Stratix devices in Tables 2-37 to 2-41 can be found in the "Stratix Device Handbook, Volume 3". Table 2-37 shows the number of channels that each fast PLL can clock in EP1S10, EP1S20, and EP1S25 devices. Tables 2-38 through Table 2-41 show this information for EP1S30, EP1S40, EP1S60, and EP1S80 devices.
Table 2-37. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 1 of 3) Device
EP1S10
Note (1)
Package
Transmitter/ Receiver
Total Channels
20
Maximum Speed (Mbps)
840 840 (3)
Center Fast PLLs PLL 1
5 10 5 10 9 18 9 18 11 22 11 22
PLL 2
5 10 5 10 9 18 9 18 11 22 11 22
PLL 3
5 10 5 10 9 18 9 18 11 22 11 22
PLL 4
5 10 5 10 9 18 9 18 11 22 11 22
484-pin FineLine BGA Transmitter (2)
Receiver
20
840 840 (3)
672-pin FineLine BGA Transmitter (2) 672-pin BGA Receiver
36
624 (4) 624 (3)
36
624 (4) 624 (3)
780-pin FineLine BGA Transmitter (2)
44
840 840 (3)
Receiver
44
840 840 (3)
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Table 2-37. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 2 of 3) Device
EP1S20
Note (1)
Package
Transmitter/ Receiver
Total Channels
24
Maximum Speed (Mbps)
840 840 (3)
Center Fast PLLs PLL 1
6 12 5 10 12 24 13 25 17 33 17 33
PLL 2
6 12 5 10 12 24 12 25 16 33 16 33
PLL 3
6 12 5 10 12 24 12 25 16 33 16 33
PLL 4
6 12 5 10 12 24 13 25 17 33 17 33
484-pin FineLine BGA Transmitter (2)
Receiver
20
840 840 (3)
672-pin FineLine BGA Transmitter (2) 672-pin BGA Receiver
48
624 (4) 624 (3)
50
624 (4) 624 (3)
780-pin FineLine BGA Transmitter (2)
66
840 840 (3)
Receiver
66
840 840 (3)
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Table 2-37. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 3 of 3) Device
EP1S25
Note (1)
Package
Transmitter/ Receiver
Total Channels
56
Maximum Speed (Mbps)
624 (4) 624 (3)
Center Fast PLLs PLL 1
14 28 14 29 18 35 17 33 19 39 19 39
PLL 2
14 28 15 29 17 35 16 33 20 39 20 39
PLL 3
14 28 15 29 17 35 16 33 20 39 20 39
PLL 4
14 28 14 29 18 35 17 33 19 39 19 39
672-pin FineLine BGA Transmitter (2) 672-pin BGA Receiver
58
624 (4) 624 (3)
780-pin FineLine BGA Transmitter (2)
70
840 840 (3)
Receiver
66
840 840 (3)
1,020-pin FineLine BGA
Transmitter (2)
78
840 840 (3)
Receiver
78
840 840 (3)
Notes to :
(1) The first row for each transmitter or recevier reports the number of channels driven directly by the PLL. The second row below it shows the maximum channels a PLL can drive if cross bank channels are used from the adjacent center PLL. For example, in the 484-pin FineLine BGA EP1S10 device, PLL 1 can drive a maximum of five channels at 840 Mbps or a maximum of 10 channels at 840 Mbps. The Quartus II software may also merge receiver and transmitter PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive both the maximum numbers of receiver and transmitter channels. The number of channels listed includes the transmitter clock output (tx_outclock) channel. If the design requires a DDR clock, it can use an extra data channel. These channels span across two banks per side of the device. When a center fast PLL drives the opposite bank on the same side of the device, the other center fast PLL cannot drive any differential channels on the device. For example, if PLL 1 in a 484-pin FineLine BGA EP1S10 device drives 10 channels at 840 Mbps, PLL 2 cannot drive any differential channels. Similar restrictions apply to PLLs 3 and 4. 672-pin packages only support up to 624 Mbps. These values show the channels available for each PLL without crossing another bank.
(2) (3)
(4)
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Table 2-38. EP1S30 Differential Channels Package
780-pin FineLine BGA
Note (1)
Transmitter Total /Receiver Channels
Transmitter (4) Receiver 70
Maximum Center Fast PLLs Corner Fast PLLs (2), (3) Speed (Mbps) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
840 840 (5) 18 35 17 33 19 39 20 40 19 (1) 39 (1) 20 40 17 35 16 33 20 39 20 40 20 39 (1) 20 40 17 35 16 33 20 39 20 40 20 39 (1) 20 40 18 35 17 33 19 39 20 40 19 (1) 39 (1) 20 40 (6) (6) (6) (6) 20 20 19 19 20 20 19 (1) 19 (1) (6) (6) (6) (6) 20 20 20 20 20 20 20 20 (6) (6) (6) (6) 20 20 20 20 20 20 20 20 (6) (6) (6) (6) 20 20 19 19 20 20 19 (1) 19 (1)
66
840 840 (5)
956-pin FineLine BGA
Transmitter (4) Receiver
80 (7)
840 840 (5)
80 (7)
840 840 (5)
1,020-pin FineLine BGA
Transmitter (4)
80 (2) (7)
840 840 (5),(8)
Receiver
80 (2) (7)
840 840 (5),(8)
Table 2-39. EP1S40 Differential Channels (Part 1 of 2) Package
780-pin FineLine BGA
Note (1) Corner Fast PLLs (2), (3)
Transmitter/ Total Receiver Channels
Transmitter (4) Receiver 68
Maximum Speed (Mbps)
840 840 (5)
Center Fast PLLs
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
18 34 17 33 18 35 20 40 16 34 16 33 17 35 20 40 16 34 16 33 17 35 20 40 18 34 17 33 18 35 20 40 (6) (6) (6) (6) 20 20 18 18 (6) (6) (6) (6) 20 20 17 17 (6) (6) (6) (6) 20 20 17 17 (6) (6) (6) (6) 20 20 18 18
66
840 840 (5)
956-pin FineLine BGA
Transmitter (4) Receiver
80
840 840 (5)
80
840 840 (5)
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Table 2-39. EP1S40 Differential Channels (Part 2 of 2) Package
1,020-pin FineLine BGA
Note (1) Corner Fast PLLs (2), (3)
Transmitter/ Total Receiver Channels
Transmitter (4) 80 (10) (7)
Maximum Speed (Mbps)
840 840 (5), (8)
Center Fast PLLs
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
18 (2) 35 (5) 20 40 18 (2) 35 (5) 20 40 17 (3) 35 (5) 20 40 17 (3) 35 (5) 20 40 17 (3) 35 (5) 20 40 17 (3) 35 (5) 20 40 18 (2) 35 (5) 20 40 18 (2) 35 (5) 20 40 20 20 18 (2) 18 (2) 20 20 18 (2) 18 (2) 20 20 17 (3) 17 (3) 20 20 17 (3) 17 (3) 20 20 17 (3) 17 (3) 20 20 17 (3) 17 (3) 20 20 18 (2) 18 (2) 20 20 18 (2) 18 (2)
Receiver
80 (10) (7)
840 840 (5), (8)
1,508-pin FineLine BGA
Transmitter (4)
80 (10) (7)
840 840 (5), (8)
Receiver
80 (10) (7)
840 840 (5), (8)
Table 2-40. EP1S60 Differential Channels (Part 1 of 2) Package
956-pin FineLine BGA
Note (1)
Transmitter/ Total Receiver Channels
Transmitter (4) Receiver 80
Maximum Center Fast PLLs Corner Fast PLLs (2), (3) Speed PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 (Mbps)
840 840 (5), (8) 12 22 20 40 12 (2) 22 (6) 20 40 10 22 20 40 10 (4) 22 (6) 20 40 10 22 20 40 10 (4) 22 (6) 20 40 12 22 20 40 12 (2) 22 (6) 20 40 20 20 12 12 20 20 12 (8) 12 (8) 20 20 10 10 20 20 10 (10) 10 (10) 20 20 10 10 20 20 10 (10) 10 (10) 20 20 12 12 20 20 12 (8) 12 (8)
80
840 840 (5), (8)
1,020-pin FineLine BGA
Transmitter (4)
80 (12) (7)
840 840 (5), (8)
Receiver
80 (10) (7)
840 840 (5), (8)
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Table 2-40. EP1S60 Differential Channels (Part 2 of 2) Package
1,508-pin FineLine BGA
Note (1)
Transmitter/ Total Receiver Channels
Transmitter (4) 80 (36) (7)
Maximum Center Fast PLLs Corner Fast PLLs (2), (3) Speed PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 (Mbps)
840 840 (5),(8) 12 (8) 22 (18) 20 40 10 (10) 22 (18) 20 40 10 (10) 22 (18) 20 40 12 (8) 22 (18) 20 40 20 20 12 (8) 12 (8) 20 20 10 (10) 10 (10) 20 20 10 (10) 10 (10) 20 20 12 (8) 12 (8)
Receiver
80 (36) (7)
840 840 (5),(8)
Table 2-41. EP1S80 Differential Channels (Part 1 of 2) Package
956-pin FineLine BGA
Note (1)
Transmitter/ Total Receiver Channels
Transmitter (4) Receiver 80 (40) (7) 80
Maximum Center Fast PLLs Corner Fast PLLs (2) Speed (Mbps) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
840 840 (5),(8) 840 840 (5),(8) 10 20 20 40 10 (2) 20 (6) 20 40 10 20 20 40 10 (4) 20 (6) 20 40 10 20 20 40 10 (4) 20 (6) 20 40 10 20 20 40 10 (2) 20 (6) 20 40 20 20 10 10 20 20 10 (2) 10 (2) 20 20 10 10 20 20 10 (3) 10 (3) 20 20 10 10 20 20 10 (3) 10 (3) 20 20 10 10 20 20 10 (2) 10 (2)
1,020-pin FineLine BGA
Transmitter (4)
92 (12) (7)
840 840 (5),(8)
Receiver
90 (10) (7)
840 840 (5),(8)
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Table 2-41. EP1S80 Differential Channels (Part 2 of 2) Package
1,508-pin FineLine BGA
Note (1)
Transmitter/ Total Receiver Channels
Transmitter (4) 80 (72) (7)
Maximum Center Fast PLLs Corner Fast PLLs (2) Speed (Mbps) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
840 840 (5),(8) 10 (10) 20 (20) 20 40 10 (10) 20 (20) 20 40 10 (10) 20 (20) 20 40 10 (10) 20 (20) 20 40 20 (8) 20 (8) 10 (14) 10 (14) 20 (8) 20 (8) 10 (14) 10 (14) 20 (8) 20 (8) 10 (14) 10 (14) 20 (8) 20 (8) 10 (14) 10 (14)
Receiver
80 (56) (7)
840 840 (5),(8)
Notes to Tables 2-38 through 2-41.
(1) The first row for each transmitter or recevier reports the number of channels driven directly by the PLL. The second row below it shows the maximum channels a PLL can drive if cross bank channels are used from the adjacent center PLL. For example, in the 780-pin FineLine BGA EP1S30 device, PLL 1 can drive a maximum of 18 transmitter channels at 840 Mbps or a maximum of 35 transmitter channels at 840 Mbps. The Quartus II software may also merge transmitter and receiver PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive both the maximum numbers of receiver and transmitter channels. Some of the channels accessible by the center fast PLL and the channels accessible by the corner fast PLL overlap. Therefore, the total number of channels is not the addition of the number of channels accessible by PLLs 1, 2, 3, and 4 with the number of channels accessible by PLLs 7, 8, 9, and 10. For more information on which channels overlap, refer to the "Fast PLL to High-Speed I/O Connections" section in the relevant device pin table chapter of volume 3. The corner fast PLLs in this device support a data rate of 840 Mbps for channels labeled "high" speed in the device pin tables. The numbers of channels listed include the transmitter clock output (tx_outclock) channel. You can use an extra data channel if you need a DDR clock. These channels span across two banks per side of the device. When a center fast PLL drives the opposite bank on the same side of the device, the other center fast PLL cannot drive any differential channels on the device. For example, if PLL 1 in a 484-pin FineLine BGA EP1S10 device drives 10 channels at 840 Mbps, PLL 2 cannot drive any differential channels. Similar restrictions apply to PLLs 3 and 4. PLLs 7, 8, 9, and 10 are not available in this device. The number in parentheses is the number of slow-speed channels, guaranteed to operate at up to 462 Mbps. These channels are independent of the high-speed differential channels. For the location of these channels, refer to the "Fast PLL to High-Speed I/O Connections" section in the relevant device pin table chapter of volume 3. Refer to device pin-outs channels marked "high" speed are 840 MBps and "low" speed channels are 462 MBps.
(2)
(3) (4) (5)
(6) (7)
(8)
The high-speed differential I/O circuitry supports the following high speed I/O interconnect standards and applications:

UTOPIA IV SPI-4 Phase 2 (POS-PHY Level 4) SFI-4 10G Ethernet XSBI RapidIO HyperTransport
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Stratix Device Handbook, Volume 1
Dedicated Circuitry
Stratix devices support source-synchronous interfacing with LVDS, LVPECL, 3.3-V PCML, or HyperTransport signaling at up to 840 Mbps. Stratix devices can transmit or receive serial channels along with a lowspeed or high-speed clock. The receiving device PLL multiplies the clock by a integer factor W (W = 1 through 32). For example, a HyperTransport application where the data rate is 800 Mbps and the clock rate is 400 MHz would require that W be set to 2. The SERDES factor J determines the parallel data width to deserialize from receivers or to serialize for transmitters. The SERDES factor J can be set to 4, 7, 8, or 10 and does not have to equal the PLL clock-multiplication W value. For a J factor of 1, the Stratix device bypasses the SERDES block. For a J factor of 2, the Stratix device bypasses the SERDES block, and the DDR input and output registers are used in the IOE. See Figure 2-78. Figure 2-78. High-Speed Differential I/O Receiver / Transmitter Interface Example
R4, R8, and R24 Interconnect
8 840 Mbps + - 8 Data Dedicated Receiver Interface Local Interconnect Dedicated Transmitter Interface 8 + - 840 Mbps
Data
8x 105 MHz Fast PLL
rx_load_en
8x
tx_load_en Regional or global clock
An external pin or global or regional clock can drive the fast PLLs, which can output up to three clocks: two multiplied high-speed differential I/O clocks to drive the SERDES block and/or external pin, and a low-speed clock to drive the logic array. The Quartus II MegaWizard Plug-In Manager only allows you to implement up to 20 receiver or 20 transmitter channels for each fast PLL. These channels operate at up to 840 Mbps. The receiver and transmitter channels are interleaved such that each I/O bank on the left and right side of the device has one receiver channel and one transmitter channel per
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LAB row. Figure 2-79 shows the fast PLL and channel layout in EP1S10, EP1S20, and EP1S25 devices. Figure 2-80 shows the fast PLL and channel layout in the EP1S30 to EP1S80 devices. Figure 2-79. Fast PLL & Channel Layout in the EP1S10, EP1S20 or EP1S25 Devices
Up to 20 Receiver and Transmitter Channels (2) Transmitter Receiver
Note (1)
Up to 20 Receiver and Transmitter Channels (2) Transmitter Receiver
CLKIN
Fast PLL 1 (3) (3) Fast PLL 2
Fast PLL 4 Fast PLL 3
CLKIN
CLKIN
CLKIN
Transmitter Receiver Up to 20 Receiver and Transmitter Channels (2)
Transmitter Receiver Up to 20 Receiver and Transmitter Channels (2)
Notes to Figure 2-79:
(1) (2) (3) Wire-bond packages support up to 624 Mbps. See Table 2-41 for the number of channels each device supports. There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of its bank quadrant, those clocked channels support up to 840 Mbps for "high" speed channels and 462 Mbps for "Low" speed channels as labeled in the device pin tables.
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Figure 2-80. Fast PLL & Channel Layout in the EP1S30 to EP1S80 Devices
FPLL7CLK (2) Fast PLL 7
Note (1)
Fast PLL 10 FPLL10CLK (2)
Transmitter Receiver
Up to 20 Receiver and 20 Transmitter Channels in 20 Rows (3)
Transmitter Receiver
Up to 20 Receiver and 20 Transmitter Channels in 20 Rows (3) Transmitter Receiver Transmitter Receiver
CLKIN CLKIN
Fast PLL 1 Fast PLL 2
(4)
(4)
Fast PLL 4 Fast PLL 3
CLKIN CLKIN
Transmitter Receiver Up to 20 Receiver and 20 Transmitter Channels in 20 Rows (3)
Transmitter Receiver
Transmitter Receiver Up to 20 Receiver and 20 Transmitter Channels in 20 Rows (3)
Transmitter Receiver
(2) FPLL8CLK Fast PLL 8
Fast PLL 9
(2) FPLL9CLK
Notes to Figure 2-80:
(1) (2) (3) (4) Wire-bond packages support up to 624 Mbps. For EP1S80 devices, the fast PLLs located at the corners of the device support up to 840 Mbps. See Table 2-38 through 2-41 for the number of channels each device supports. There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of its bank quadrant, those clocked channels support up to 840 Mbps for "high" speed channels and 462 Mbps for "Low" speed channels as labeled in the device pin tables.
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Power Sequencing & Hot Socketing
The transmitter external clock output is transmitted on a data channel. The txclk pin for each bank is located in between data transmitter pins. For x1 clocks (e.g., 622 Mbps, 622 MHz), the high-speed PLL clock bypasses the SERDES to drive the output pins. For half-rate clocks (e.g., 622 Mbps, 311 MHz) or any other even-numbered factor such as 1/4, 1/7, 1/8, or 1/10, the SERDES automatically generates the clock in the Quartus II software. For systems that require more than four or eight high-speed differential I/O clock domains, a SERDES bypass implementation is possible using IOEs.
Byte Alignment
For high-speed source synchronous interfaces such as POS-PHY 4, XSBI, RapidIO, and HyperTransport, the source synchronous clock rate is not a byte- or SERDES-rate multiple of the data rate. Byte alignment is necessary for these protocols since the source synchronous clock does not provide a byte or word boundary since the clock is one half the data rate, not one eighth. The Stratix device's high-speed differential I/O circuitry provides dedicated data realignment circuitry for user-controlled byte boundary shifting. This simplifies designs while saving LE resources. An input signal to each fast PLL can stall deserializer parallel data outputs by one bit period. The designer can use an LE-based state machine to signal the shift of receiver byte boundaries until a specified pattern is detected to indicate byte alignment.
Power Sequencing & Hot Socketing
Because Stratix devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. Therefore, the VCCIO and VCCINT power supplies may be powered in any order. Signals can be driven into Stratix devices before and during power up without damaging the device. In addition, Stratix devices do not drive out during power up. Once operating conditions are reached and the device is configured, Stratix devices operate as specified by the user. See also "Hot Socketing" on page 4-27
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3. Configuration & Testing
S51003-1.0
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
All Stratix devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing can be performed either before or after, but not during configuration. Stratix devices can also use the JTAG port for configuration together with either the Quartus II software or hardware using either Jam Files (.jam) or Jam Byte-Code Files (.jbc). Stratix devices support IOE I/O standard setting reconfiguration through the JTAG BST chain. The JTAG chain can update the I/O standard for all input and output pins any time before or during user mode through the CONFIG_IO instruction. Designers can use this ability for JTAG testing before configuration when some of the Stratix pins drive or receive from other devices on the board using voltage-referenced standards. Since the Stratix device may not be configured before JTAG testing, the I/O pins may not be configured for appropriate electrical standards for chip-tochip communication. Programming those I/O standards via JTAG allows designers to fully test I/O connection to other devices. The enhanced PLL reconfiguration bits are part of the JTAG chain before configuration and after power-up. After device configuration, the PLL reconfiguration bits are not part of the JTAG chain. The JTAG pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O standards. The TDO pin voltage is determined by the VCCIO of the bank where it resides. The VCCSEL pin selects whether the JTAG inputs are 1.5-V, 1.8-V, 2.5-V, or 3.3-V compatible. Stratix devices also use the JTAG port to monitor the logic operation of the device with the SignalTap embedded logic analyzer. Stratix devices support the JTAG instructions shown in Table 3-1.
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Stratix Device Handbook, Volume 1
Table 3-1. Stratix JTAG Instructions JTAG Instruction Instruction Code Description
Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. Also used by the SignalTap embedded logic analyzer. Allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation. Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO. Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while holding I/O pins to a state defined by the data in the boundary-scan register. Used when configuring an Stratix device via the JTAG port with a MasterBlasterTM, ByteBlasterMVTM, or ByteBlasterTM II download cable, or when using a Jam File or Jam Byte-Code File via an embedded processor or JRunner.
SAMPLE/PRELOAD 00 0000 0101
EXTEST (1)
00 0000 0000
BYPASS
11 1111 1111
USERCODE
00 0000 0111
IDCODE HIGHZ (1)
00 0000 0110 00 0000 1011
CLAMP (1)
00 0000 1010
ICR instructions
PULSE_NCONFIG CONFIG_IO
00 0000 0001 00 0000 1101
Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is unaffected. Allows configuration of I/O standards through the JTAG chain for JTAG testing. Can be executed before, after, or during configuration. Stops configuration if executed during configuration. Once issued, the CONFIG_IO instruction will hold nSTATUS low to reset the configuration device. nSTATUS is held low until the device is reconfigured. Monitors internal device operation with the SignalTap II embedded logic analyzer.
SignalTap instructions Note to Table 3-1:
(1)
Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
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Configuration & Testing
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
The Stratix device instruction register length is 10 bits and the USERCODE register length is 32 bits. Tables 3-2 and 3-3 show the boundary-scan register length and device IDCODE information for Stratix devices.
Table 3-2. Stratix Boundary-Scan Register Length Device
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
Boundary-Scan Register Length
1,317 1,797 2,157 2,253 2,529 3,129 3,777
Table 3-3. 32-Bit Stratix Device IDCODE IDCODE (32 Bits) (2) Device Version (4 Bits)
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
(1) (2) (3)
Part Number (16 Bits)
0010 0000 0000 0001 0010 0000 0000 0010 0010 0000 0000 0011 0010 0000 0000 0100 0010 0000 0000 0101 0010 0000 0000 0110 0010 0000 0000 0111
Manufacturer Identity (11 Bits)
000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110
LSB (1 Bit) (3)
1 1 1 1 1 1 1
0000 0000 0000 0000 0000 0000 0000
Notes to Tables 3-2 and 3-3:
Contact Altera Applications for up-to-date information on this device. The most significant bit (MSB) is on the left. The IDCODE's least significant bit (LSB) is always 1.
Figure 3-1 shows the timing requirements for the JTAG signals.
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Stratix Device Handbook, Volume 1
Figure 3-1. Stratix JTAG Waveforms
TMS
TDI t JCP t JCH TCK tJPZX TDO tJSSU Signal to Be Captured Signal to Be Driven tJSH t JPCO t JPXZ t JCL t JPSU t JPH
tJSZX
tJSCO
tJSXZ
Table 3-4 shows the JTAG timing parameters and values for Stratix devices.
Table 3-4. Stratix JTAG Timing Parameters & Values Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ
Parameter
TCK clock period TCK clock high time TCK clock low time
JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Update register valid output to high impedance
Min
100 50 50 20 45
Max
Unit
ns ns ns ns ns
25 25 25 20 45 35 35 35
ns ns ns ns ns ns ns ns
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f
For more information on JTAG, see the following documents:

AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices Jam Programming & Test Language Specification
SignalTap Embedded Logic Analyzer
Stratix devices feature the SignalTap embedded logic analyzer, which monitors design operation over a period of time through the IEEE Std. 1149.1 (JTAG) circuitry. A designer can analyze internal logic at speed without bringing internal signals to the I/O pins. This feature is particularly important for advanced packages, such as FineLine BGA packages, because it can be difficult to add a connection to a pin during the debugging process after a board is designed and manufactured. The logic, circuitry, and interconnects in the Stratix architecture are configured with CMOS SRAM elements. Stratix devices are reconfigurable and are 100% tested prior to shipment. As a result, the designer does not have to generate test vectors for fault coverage purposes, and can instead focus on simulation and design verification. In addition, the designer does not need to manage inventories of different ASIC designs. Stratix devices can be configured on the board for the specific functionality required. Stratix devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers in-system programmability (ISP)-capable configuration devices that configure Stratix devices via a serial data stream. Stratix devices can be configured in under 100 ms using 8-bit parallel data at 100 MHz. The Stratix device's optimized interface allows microprocessors to configure it serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat Stratix devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy. After a Stratix device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Real-time changes can be made during system operation, enabling innovative reconfigurable computing applications.
Configuration
Operating Modes
The Stratix architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up. The process of physically loading the SRAM data into the device is called configuration. During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up,
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Configuration
Stratix Device Handbook, Volume 1
and before and during configuration. Together, the configuration and initialization processes are called command mode. Normal device operation is called user mode. SRAM configuration elements allow Stratix devices to be reconfigured incircuit by loading new configuration data into the device. With real-time reconfiguration, the device is forced into command mode with a device pin. The configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. Designers can perform in-field upgrades by distributing new configuration files either within the system or remotely. PORSEL is a dedicated input pin used to select POR delay times of 2 ms or 100 ms during power-up. When the PORSEL pin is connected to ground, the POR time is 100 ms; when the PORSEL pin is connected to VCC, the POR time is 2 ms. The nIO_PULLUP pin enables a built-in weak pull-up resistor to pull all user I/O pins to VCCIO before and during device configuration. If nIO_PULLUP is connected to VCC during configuration, the weak pullups on all user I/O pins are disabled. If connected to ground, the pull-ups are enabled during configuration. The nIO_PULLUP pin can be pulled to 1.5, 1.8, 2.5, or 3.3 V for a logic level high. VCCSEL is a dedicated input that is used to choose whether all dedicated configuration and JTAG input pins can accept 1.5 V/1.8 V or 2.5 V/3.3 V during configuration. A logic low sets 3.3 V/2.5 V, and a logic high sets 1.8 V/1.5 V. VCCSEL affects the following pins: TDI, TMS, TCK, TRST, MSEL0, MSEL1, MSEL2, nCONFIG, nCE, DCLK, PLL_ENA, CONF_DONE, nSTATUS. The VCCSEL pin can be pulled to 1.5, 1.8, 2.5, or 3.3 V for a logic level high. The VCCSEL signal does not control any of the dual-purpose pins, including the dual-purpose configuration pins. During configuration, the output buffers of dual-purpose pins will drive out a 1.5-V TTL compatible signal while the input buffers will receive 3.3-V TTL. After configuration, the dual-purpose pins inherit the I/O standards specified in the design. The VCCSEL signal does not control the dual-purpose configuration pins such as the DATA[7..0] and PPA pins (nWS, nRS, CS, nCS, and RDYnBSY). During configuration, these dual-purpose pins will drive out voltage levels corresponding to the VCCIO supply voltage that powers the I/O bank containing the pin. After configuration, the dual-purpose pins use I/O standards specified in the user design.
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Configuration & Testing
Configuration
TDO and nCEO drive out at the same voltages as the VCCIO supply that powers the I/O bank containing the pin. Users must select the VCCIO supply for bank containing TDO accordingly. For example, when using the ByteBlasterMV cable, the VCCIO for the bank containing TDO must be powered up at 3.3 V.
Configuring Stratix FPGAs with JRunner
JRunner is a software driver that configures Altera FPGAs, including Stratix FPGAs, through the ByteBlaster II or ByteBlasterMV cables in JTAG mode. The programming input file supported is in Raw Binary File (.rbf) format. JRunner also requires a Chain Description File (.cdf) generated by the Quartus II software. JRunner is targeted for embedded JTAG configuration. The source code is developed for the Windows NT operating system (OS), but can be customized to run on other platforms. For more information on the JRunner software driver, see the JRunner Software Driver: An Embedded Solution to the JTAG Configuration White Paper and the source files on the Altera web site (www.altera.com).
Configuration Schemes
Designers can load the configuration data for a Stratix device with one of five configuration schemes (see Table 3-5), chosen on the basis of the target application. Designers can use a configuration device, intelligent controller, or the JTAG port to configure a Stratix device. A configuration device can automatically configure a Stratix device at system power-up. Multiple Stratix devices can be configured in any of five configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device.
Table 3-5. Data Sources for Configuration Configuration Scheme
Configuration device Passive serial (PS) Passive parallel asynchronous (PPA) Fast passive parallel JTAG
Data Source
Enhanced or EPC2 configuration device MasterBlaster, ByteBlasterMV, or ByteBlaster II download cable or serial data source Parallel data source Parallel data source MasterBlaster, ByteBlasterMV, or ByteBlaster II download cable, a microprocessor with a Jam or JBC file, or JRunner
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Partial Reconfiguration
The enhanced PLLs within the Stratix device family support partial reconfiguration of their multiply, divide, and time delay settings without reconfiguring the entire device. Designers can use either serial data from the logic array or regular I/O pins to program the PLL's counter settings in a serial chain. This option provides considerable flexibility for frequency synthesis, allowing real-time variation of the PLL frequency and delay. The rest of the device is functional while reconfiguring the PLL. See "Enhanced PLLs" on page 2-84 for more information on Stratix PLLs.
Remote Update Configuration Modes
Stratix devices also support remote configuration using an Altera enhanced configuration device (e.g., EPC16, EPC8, and EPC4 devices) with page mode selection. Factory configuration data is stored in the default page of the configuration device. This is the default configuration which contains the design required to control remote updates and handle or recover from errors. The designer writes the factory configuration once into the flash memory or configuration device. Remote update data can update any of the remaining pages of the configuration device. If there is an error or corruption in a remote update configuration, the configuration device reverts back to the factory configuration information. There are two remote configuration modes: remote and local configuration. Designers can use the remote update configuration mode for all three configuration modes: serial, parallel synchronous, and parallel asynchronous. Configuration devices (e.g., EPC16 devices) only support serial and parallel synchronous modes. Asynchronous parallel mode allows remote updates when an intelligent host is used to configure the Stratix device. This host must support page mode settings similar to an EPC16 device.
Remote Update Mode
When the Stratix device is first powered up in remote update programming mode, it loads the configuration located at page address "000." The factory configuration should always be located at page address "000," and should never be remotely updated. The factory configuration contains the required logic to perform the following operations:

Determine the page address/load location for the next application's configuration data Recover from a previous configuration error
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Configuration & Testing
Configuration
Receive new configuration data and write it into the configuration device
The factory configuration is the default and takes control if an error occurs while loading the application configuration. While in the factory configuration, the factory-configuration logic performs the following operations:

Loads a remote update-control register to determine the page address of the new application configuration Determines whether to enable a user watchdog timer for the application configuration Determines what the watchdog timer setting should be if it is enabled
The user watchdog timer is a counter that must be continually reset within a specific amount of time in the user mode of an application configuration to ensure that valid configuration occurred during a remote update. Only valid application configurations designed for remote update can reset the user watchdog timer in user mode. If a valid application configuration does not reset the user watchdog timer in a specific amount of time, the timer updates a status register and loads the factory configuration. The user watchdog timer is automatically disabled for factory configurations. If an error occurs in loading the application configuration, the configuration logic writes a status register to specify the cause of the error. Once this occurs, the Stratix device automatically loads the factory configuration, which reads the status register and determines the reason for reconfiguration. Based on the reason, the factory configuration will take appropriate steps and will write the remote update control register to specify the next application configuration page to be loaded. When the Stratix device successfully loads the application configuration, it enters into user mode. The Stratix device then executes the main application of the user. Intellectual property (IP), such as a Nios(R) embedded processor, can help the Stratix device determine when remote update is coming. The Nios embedded processor or user logic receives incoming data, writes it to the configuration device, and loads the factory configuration. The factory configuration will read the remote update status register and determine the valid application configuration to load. Figure 3-2 shows the Stratix remote update. Figure 3-3 shows the transition diagram for remote update mode.
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Configuration
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Figure 3-2. Stratix Device Remote Update
Configuration Device
(1)
Watchdog Timer New Remote Configuration Data
Application Configuration Application Configuration
Page 7 Page 6
Stratix Device Factory Configuration Configuration Device Updates Stratix Device with Factory Configuration (to Handle Update) or New Application Configuration
Page 0
Note to Figure 3-2:
(1) When the Stratix device is configured with the factory configuration, it can handle update data from EPC16, EPC8, or EPC4 configuration device pages and point to the next page in the configuration device.
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Configuration & Testing
Configuration
Figure 3-3. Remote Update Transition Diagram
Notes (1), (2)
Power-Up
Application 1 Configuration
Configuration Error
Configuration Error
Reload an Application
Factory Configuration
Reload an Application
Configuration Error
Application n Configuration
Notes to Figure 3-3:
(1) (2) Remote update of Application Configuration is controlled by a Nios embedded processor or user logic programmed in the Factory or Application configurations. Up to seven pages can be specified allowing up to seven different configuration applications.
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Temperature Sensing Diode
Stratix Device Handbook, Volume 1
Local Update Mode
Local update mode is a simplified version of the remote update. This feature is intended for simple systems that need to load a single application configuration immediately upon power up without loading the factory configuration first. Local update designs have only one application configuration to load, so it does not require a factory configuration to determine which application configuration to use. Figure 3-4 shows the transition diagram for local update mode. Figure 3-4. Local Update Transition Diagram
Power-Up or nCONFIG
nCONFIG
Application Configuration
Configuration Error
Configuration Error
nCONFIG
Factory Configuration
Temperature Sensing Diode
Stratix devices include a diode-connected transistor for use as a temperature sensor in power management. This diode is used with an external digital thermometer device such as a MAX1617A or MAX1619 from MAXIM Integrated Products. These devices steer bias current through the Stratix diode, measuring forward voltage and converting this reading to temperature in the form of an 8-bit signed number (7 bits plus sign). The external device's output represents the package temperature of the Stratix device and can be used for intelligent power management.
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Configuration & Testing
Temperature Sensing Diode
The diode requires two pins (tempdiodep and tempdioden) on the Stratix device to connect to the external temperature-sensing device, as shown in Figure 3-5. The temperature sensing diode is a passive element and therefore can be used before the Stratix device is powered. Figure 3-5. External Temperature-Sensing Diode
Stratix Device Temperature-Sensing Device
tempdiodep
tempdioden
Table 3-6 shows the specifications for bias voltage and current of the Stratix temperature sensing diode.
Table 3-6. Temperature-Sensing Diode Electrical Characteristics Parameter
IBIAS high IBIAS low VBP - VBN VBN Series resistance
Minimum
80 8 0.3
Typical
100 10
Maximum
120 12 0.9
Unit
A A V V
0.7 3
W
The temperature-sensing diode works for the entire operating range shown in Figure 3-6.
Altera Corporation April 2003
3-13
Temperature Sensing Diode
Stratix Device Handbook, Volume 1
Figure 3-6. Temperature vs. Temperature-Sensing Diode Voltage
0.95 0.90 0.85 0.80 0.75 Voltage (Across Diode) 0.70 0.65 0.60 0.55 0.50 0.45 0.40 -55 -30 -5 20 45 70 95 120 100 A Bias Current 10 A Bias Current
Temperature ( C)
3-14
Altera Corporation April 2003
4. DC & Switching Characteristics
S51004-2.2
Operating Conditions
Stratix devices are offered in both commercial and industrial grades. Industrial devices are offered in -6 and -7 speed grades and commercial devices are offered in -5 (fastest), -6, -7, and -8 speed grades. Tables 4-1 through 4-8 provide information on absolute maximum ratings.
Table 4-1. Stratix Device Absolute Maximum Ratings Symbol
VCCINT VCCIO VI IOUT TSTG TJ DC input voltage (3) DC output current, per pin Storage temperature Junction temperature No bias
Notes (1), (2) Minimum
-0.5 -0.5 -0.5 -25 -65
Parameter
Supply voltage
Conditions
With respect to ground
Maximum
2.4 4.6 4.6 40 150 135
Unit
V V V mA C C
BGA packages under bias
Table 4-2. Stratix Device Recommended Operating Conditions (Part 1 of 2) Symbol
VCCINT VCCIO
Parameter
Supply voltage for internal logic and input buffers Supply voltage for output buffers, 3.3-V operation Supply voltage for output buffers, 2.5-V operation Supply voltage for output buffers, 1.8-V operation Supply voltage for output buffers, 1.5-V operation (4)
Conditions
Minimum
1.425 3.00 (3.135) 2.375 1.71 1.4 -0.5 0
Maximum
1.575 3.60 (3.465) 2.625 1.89 1.6 4.1 VCCIO 85 100
Unit
V V V V V V V C C
(4), (5) (4) (4) (4) (3), (6)
VI VO TJ
Input voltage Output voltage Operating junction temperature
For commercial use For industrial use
0 -40
Altera Corporation November 2003
4-1
Operating Conditions
Stratix Device Handbook, Volume 1
Table 4-2. Stratix Device Recommended Operating Conditions (Part 2 of 2) Symbol
tR tF
Parameter
Input rise time Input fall time
Conditions
Minimum
Maximum
40 40
Unit
ns ns
Table 4-3. Stratix Device DC Operating Conditions Symbol
II IOZ ICC0
Note (7) Minimum
-10 -10
Parameter
Input pin leakage current Tri-stated I/O pin leakage current VCC supply current (standby) (All memory blocks in power-down mode)
Conditions
VI = VCCIOmax to 0 V (8) VO = VCCIOmax to 0 V (8) VI = ground, no load, no toggling inputs
Typical
Maximum
10 10
Unit
A A mA
RCONF
Value of I/O pin pull- VCCIO = 3.0 V (9) up resistor before VCCIO = 2.375 V (9) and during VCCIO = 1.71 V (9) configuration
20 30 60
50 80 150
k k k
Table 4-4. LVTTL Specifications Symbol
VCCIO VI H VIL VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.0 1.7 -0.5
Maximum
3.6 4.1 0.7
Unit
V V V V
IOH = -4 to -24 mA (10) IOL = 4 to 24 mA (10)
2.4 0.45
V
4-2
Altera Corporation November 2003
DC & Switching Characteristics
Operating Conditions
Table 4-5. LVCMOS Specifications Symbol
VCCIO VIH VIL VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.0 1.7 -0.5
Maximum
3.6 4.1 0.7
Unit
V V V V
VCCIO = 3.0, IOH = -0.1 mA VCCIO = 3.0, IOL = 0.1 mA
VCCIO - 0.2 0.2
V
Table 4-6. 2.5-V I/O Specifications Symbol
VCCIO VIH VIL VOH
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage
Conditions
Minimum
2.375 1.7 -0.5
Maximum
2.625 4.1 0.7
Unit
V V V V V V
IOH = -0.1 mA IOH = -1 mA IOH = -2 to -16 mA (10)
2.1 2.0 1.7 0.2 0.4 0.7
VOL
Low-level output voltage
IOL = 0.1 mA IOL = 1 mA IOL = 2 to 16 mA (10)
V V V
Table 4-7. 1.8-V I/O Specifications Symbol
VCCIO VI H VIL VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.65 0.65 x VCCIO -0.3
Maximum
1.95 2.25 0.35 x VCCIO
Unit
V V V V
IOH = -2 to -8 mA (10) IOL = 2 to 8 mA (10)
VCCIO - 0.45 0.45
V
Altera Corporation November 2003
4-3
Operating Conditions
Stratix Device Handbook, Volume 1
Table 4-8. 1.5-V I/O Specifications Symbol
VCCIO VI H VIL VOH VOL
(1) (2)
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.4 0.65 x VCCIO -0.3 0.75 x VCCIO
Maximum
1.6 VCCIO + 0.3 0.35 x VCCIO 0.25 x VCCIO
Unit
V V V V V
IOH = -2 mA (10) IOL = 2 mA (10)
Notes to Tables 4-1 through 4-8:
See the Operating Requirements for Altera Devices Data Sheet. Conditions beyond those listed in Table 4-1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. (3) Minimum DC input is -0.5 V. During transitions, the inputs may undershoot to -2 V or overshoot to 4.6 V for input currents less than 100 mA and periods shorter than 20 ns. (4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically. (5) VCCIO maximum and minimum conditions for LVPECL, LVDS, and 3.3-V PCML are shown in parentheses. (6) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are powered. (7) Typical values are for TA = 25C, VCCINT = 1.5 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V. (8) This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO settings (3.3, 2.5, 1.8, and 1.5 V) (9) Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO. (10) Drive strength is programmable according to values in Table 2-28 on page 2-122.
Figures 4-1 and 4-2 show receiver input and transmitter output waveforms, respectively, for all differential I/O standards (LVDS, 3.3-V PCML, LVPECL, and HyperTransport technology). Figure 4-1. Receiver Input Waveforms for Differential I/O Standards
Single-Ended Waveform Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground
Differential Waveform
VID p-n=0V VID (Peak-to-Peak) VID
4-4
Altera Corporation November 2003
DC & Switching Characteristics
Operating Conditions
Figure 4-2. Transmitter Output Waveforms for Differential I/O Standards
Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VCM Ground
Differential Waveform
VOD p-n=0V VOD
Tables 4-9 through 4-32 recommend operating conditions, DC operating conditions, and capacitance for 1.5-V Stratix devices.
Table 4-9. 3.3-V LVDS I/O Specifications (Part 1 of 2) Symbol
VCCIO
Parameter
I/O supply voltage
Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465 1,000 1,000 1,000 1,000
Unit
V mV mV mV mV
VID (peak-to- Input differential voltage swing (single-ended) peak) (6)
0.1 V < VCM < 1.1 V J = 1 through 10 1.1 V VCM 1.6 V J=1 1.1 V VCM 1.6 V J = 2 through10 1.6 V < VCM < 1.8 V J = 1 through 10
300 200 100 300
Altera Corporation November 2003
4-5
Operating Conditions
Stratix Device Handbook, Volume 1
Table 4-9. 3.3-V LVDS I/O Specifications (Part 2 of 2) Symbol
VICM
Parameter
Input common mode voltage (6)
Conditions
LVDS 0.3 V < VID < 1.0 V J = 1 through 10 LVDS 0.3 V < VID < 1.0 V J = 1 through 10 LVDS 0.2 V < VID < 1.0 V J=1 LVDS 0.1 V < VID < 1.0 V J = 2 through 10
Minimum
100
Typical
Maximum
1,100
Unit
mV
1,600
1,800
mV
1,100
1,600
mV
1,100
1,600
mV
VOD (1) VOD VOCM VOCM RL
Output differential voltage (single-ended) Change in VOD between high and low Output common mode voltage Change in VOCM between high and low Receiver differential input discrete resistor (external to Stratix devices)
RL = 100 RL = 100 RL = 100 RL = 100
250
375
550 50
mV mV mV mV
1,125
1,200
1,375 50
90
100
110
4-6
Altera Corporation November 2003
DC & Switching Characteristics
Operating Conditions
Table 4-10. 3.3-V PCML Specifications Symbol
VCCIO VID (peakto-peak) VICM VOD VOD VOCM VOCM VT R1 R2
Parameter
I/O supply voltage Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Change in VOD between high and low Output common mode voltage Change in VOCM between high and low Output termination voltage Output external pull-up resistors Output external pull-up resistors
Conditions
Minimum
3.135 300 1.5 300
Typical
3.3
Maximum
3.465 600 3.465
Unit
V mV V mV mV V mV V
370
500 50
2.5
2.85
3.3 50
VCCIO 45 45 50 50 55 55

Table 4-11. LVPECL Specifications Symbol
VCCIO VID (peakto-peak) VICM VOD VOCM RL
Parameter
I/O supply voltage Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Output common mode voltage Receiver differential input resistor
Conditions
Minimum
3.135 300 1
Typical
3.3
Maximum
3.465 1,000 2
Unit
V mV V mV V
RL = 100 RL = 100
525 1.5 90
700 1.7 100
970 1.9 110
Altera Corporation November 2003
4-7
Operating Conditions
Stratix Device Handbook, Volume 1
Table 4-12. HyperTransport Technology Specifications Symbol
VCCIO VID (peakto-peak) VICM VOD VOD VOCM VOCM RL
Parameter
I/O supply voltage Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Change in VOD between high and low Output common mode voltage Change in VOCM between high and low Receiver differential input resistor
Conditions
Minimum
2.375 300 300
Typical
2.5
Maximum
2.625 900 900
Unit
V mV mV mV mV mV mV
RL = 100 RL = 100 RL = 100 RL = 100
380
485
820 50
440
650
780 50
90
100
110
Table 4-13. 3.3-V PCI Specifications Symbol
VCCIO VIH VIL VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.0 0.5 x VCCIO -0.5
Typical
3.3
Maximum
3.6 VCCIO + 0.5 0.3 x VCCIO
Unit
V V V V
IOUT = -500 A IOUT = 1,500 A
0.9 x VCCIO 0.1 x VCCIO
V
4-8
Altera Corporation November 2003
DC & Switching Characteristics
Operating Conditions
Table 4-14. PCI-X 1.0 Specifications Symbol
VCCIO VIH VIL VIPU VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input pull-up voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.0 0.5 x VCCIO -0.5 0.7 x VCCIO
Typical
Maximum
3.6 VCCIO + 0.5 0.35 x VCCIO
Unit
V V V V V
IOUT = -500 A IOUT = 1,500 A
0.9 x VCCIO 0.1 x VCCIO
V
Table 4-15. GTL+ I/O Specifications Symbol
VTT VREF VIH VIL VOL
Parameter
Termination voltage Reference voltage High-level input voltage Low-level input voltage Low-level output voltage
Conditions
Minimum
1.35 0.88 VREF + 0.1
Typical
1.5 1.0
Maximum
1.65 1.12
Unit
V V V
VREF - 0.1 IOL = 34 mA (3) 0.65
V V
Table 4-16. GTL I/O Specifications Symbol
VTT VREF VIH VIL VOL
Parameter
Termination voltage Reference voltage High-level input voltage Low-level input voltage Low-level output voltage
Conditions
Minimum
1.14 0.74 VREF + 0.05
Typical
1.2 0.8
Maximum
1.26 0.86
Unit
V V V
VREF - 0.05 IOL = 40 mA (3) 0.4
V V
Altera Corporation November 2003
4-9
Operating Conditions
Stratix Device Handbook, Volume 1
Table 4-17. SSTL-18 Class I Specifications Symbol
VCCIO VREF VTT VIH(DC) VIL(DC) VIH(AC) VIL(AC) VOH VOL
Parameter
Output supply voltage Reference voltage Termination voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.65 0.8 VREF - 0.04 VREF + 0.125
Typical
1.8 0.9 VREF
Maximum
1.95 1.0 VREF + 0.04
Unit
V V V V
VREF - 0.125 VREF + 0.275 VREF - 0.275 IOH = -6.7 mA (3) IOL = 6.7 mA (3) VTT + 0.475 VTT - 0.475
V V V V V
Table 4-18. SSTL-18 Class II Specifications Symbol
VCCIO VREF VTT VIH(DC) VIL(DC) VIH(AC) VIL(AC) VOH VOL
Parameter
Output supply voltage Reference voltage Termination voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.65 0.8 VREF - 0.04 VREF + 0.125
Typical
1.8 0.9 VREF
Maximum
1.95 1.0 VREF + 0.04
Unit
V V V V
VREF - 0.125 VREF + 0.275 VREF - 0.275 IOH = -13.4 mA (3) IOL = 13.4 mA (3) VTT + 0.630 VTT - 0.630
V V V V V
4-10
Altera Corporation November 2003
DC & Switching Characteristics
Operating Conditions
Table 4-19. SSTL-2 Class I Specifications Symbol
VCCIO VTT VREF VIH VIL VOH VOL
Parameter
Output supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 VREF - 0.04 1.15 VREF + 0.18 -0.3
Typical
2.5 VREF 1.25
Maximum
2.625 VREF + 0.04 1.35 3.0 VREF - 0.18
Unit
V V V V V V
IOH = -8.1 mA (3) IOL = 8.1 mA (3)
VTT + 0.57 VTT - 0.57
V
Table 4-20. SSTL-2 Class II Specifications Symbol
VCCIO VTT VREF VIH VIL VOH VOL
Parameter
Output supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.3 VREF - 0.04 1.15 VREF + 0.18 -0.3
Typical
2.5 VREF 1.25
Maximum
2.7 VREF + 0.04 1.35 VCCIO + 0.3 VREF - 0.18
Unit
V V V V V V
IOH = -16.4 mA (3) IOL = 16.4 mA (3)
VTT + 0.76 VTT - 0.76
V
Table 4-21. SSTL-3 Class I Specifications Symbol
VCCIO VTT VREF VIH VIL VOH VOL
Parameter
Output supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.0 VREF - 0.05 1.3 VREF + 0.2 -0.3
Typical
3.3 VREF 1.5
Maximum
3.6 VREF + 0.05 1.7 VCCIO + 0.3 VREF - 0.2
Unit
V V V V V V
IOH = -8 mA (3) IOL = 8 mA (3)
VTT + 0.6 VTT - 0.6
V
Altera Corporation November 2003
4-11
Operating Conditions
Stratix Device Handbook, Volume 1
Table 4-22. SSTL-3 Class II Specifications Symbol
VCCIO VTT VREF VIH VIL VOH VOL
Parameter
Output supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.0 VREF - 0.05 1.3 VREF + 0.2 -0.3
Typical
3.3 VREF 1.5
Maximum
3.6 VREF + 0.05 1.7 VCCIO + 0.3 VREF - 0.2
Unit
V V V V V V
IOH = -16 mA (3) IOL = 16 mA (3)
VT T + 0.8 VTT - 0.8
V
Table 4-23. 3.3-V AGP 2x Specifications Symbol
VCCIO VREF VIH VIL VOH VOL
Parameter
Output supply voltage Reference voltage High-level input voltage (4) Low-level input voltage (4) High-level output voltage Low-level output voltage
Conditions
Minimum
3.15 0.39 x VCCIO 0.5 x VCCIO 0.9 x VCCIO
Typical
3.3
Maximum
3.45 0.41 x VCCIO VCCIO + 0.5 0.3 x VCCIO
Unit
V V V V V V
IOUT = -0.5 mA IOUT = 1.5 mA
3.6 0.1 x VCCIO
Table 4-24. 3.3-V AGP 1x Specifications Symbol
VCCIO VIH VIL VOH VOL
Parameter
Output supply voltage High-level input voltage (4) Low-level input voltage (4) High-level output voltage Low-level output voltage
Conditions
Minimum
3.15 0.5 x VCCIO 0.9 x VCCIO
Typical
3.3
Maximum
3.45 VCCIO + 0.5 0.3 x VCCIO
Unit
V V V V V
IOUT = -0.5 mA IOUT = 1.5 mA
3.6 0.1 x VCCIO
Table 4-25. 1.5-V HSTL Class I Specifications (Part 1 of 2) Symbol
VCCIO VREF VTT
Parameter
Output supply voltage Input reference voltage Termination voltage
Conditions
Minimum
1.4 0.68 0.7
Typical
1.5 0.75 0.75
Maximum
1.6 0.9 0.8
Unit
V V V
4-12
Altera Corporation November 2003
DC & Switching Characteristics
Operating Conditions
Table 4-25. 1.5-V HSTL Class I Specifications (Part 2 of 2) Symbol
VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
Parameter
DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VREF + 0.1 -0.3 VREF + 0.2
Typical
Maximum
Unit
V
VREF - 0.1
V V
VREF - 0.2 IOH = 8 mA (3) IOH = -8 mA (3) VCCIO - 0.4 0.4
V V V
Table 4-26. 1.5-V HSTL Class II Specifications Symbol
VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
Parameter
Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.4 0.68 0.7 VREF + 0.1 -0.3 VREF + 0.2
Typical
1.5 0.75 0.75
Maximum
1.6 0.9 0.8
Unit
V V V V
VREF - 0.1
V V
VREF - 0.2 IOH = 16 mA (3) IOH = -16 mA (3) VCCIO - 0.4 0.4
V V V
Table 4-27. 1.8-V HSTL Class I Specifications Symbol
VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
Parameter
Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.65 0.70
Typical
1.80 0.90 VCCIO x 0.5
Maximum
1.95 0.95
Unit
V V V V
VREF + 0.1 -0.5 VREF + 0.2 VREF - 0.2 IOH = 8 mA (3) IOH = -8 mA (3) VCCIO - 0.4 0.4 VREF - 0.1
V V V V V
Altera Corporation November 2003
4-13
Operating Conditions
Stratix Device Handbook, Volume 1
Table 4-28. 1.8-V HSTL Class II Specifications Symbol
VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
Parameter
Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.65 0.70
Typical
1.80 0.90 VCCIO x 0.5
Maximum
1.95 0.95
Unit
V V V V
VREF + 0.1 -0.5 VREF + 0.2 VREF - 0.2 IOH = 16 mA (3) IOH = -16 mA (3) VCCIO - 0.4 0.4 VREF - 0.1
V V V V V
Table 4-29. 1.5-V Differential HSTL Specifications Symbol
VCCIO VDIF (DC) VCM (DC) VDIF (AC)
Parameter
I/O supply voltage DC input differential voltage DC common mode input voltage AC differential input voltage
Conditions
Minimum
1.4 0.2 0.68 0.4
Typical
1.5
Maximum
1.6
Unit
V V
0.9
V V
Table 4-30. CTT I/O Specifications Symbol
VCCIO VTT/VREF VIH VIL VOH VOL IO
Parameter
Output supply voltage Termination and input reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Output leakage current (when output is high Z)
Conditions
Minimum
3.0 1.35 VREF + 0.2
Typical
3.3 1.5
Maximum
3.6 1.65
Unit
V V V
VREF - 0.2 IOH = -8 mA IOL = 8 mA GND VOUT VCCIO -10 VREF + 0.4 VREF - 0.4 10
V V V A
4-14
Altera Corporation November 2003
DC & Switching Characteristics
Operating Conditions
Table 4-31. Bus Hold Parameters VCCIO Level Parameter Conditions 1.5 V Min
Low sustaining current VIN > VIL (maximum)
1.8 V Min
30 -30 200 -200
2.5 V Min
50 -50 300 -300
3.3 V Min
70 -70 500 -500
Unit
Max
Max
Max
Max
A A A A
High sustaining VIN < VIH current (minimum) Low overdrive current High overdrive current 0 V < VIN < VCCIO 0 V < VIN < VCCIO
Table 4-32. Stratix Device Capacitance Symbol
CIOTB CIOLR
Note (5) Minimum Typical
11.5 8.2
Parameter
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8. Input capacitance on I/O pins in I/O banks 1, 2, 5, and 6, including high-speed differential receiver and transmitter pins. Input capacitance on top/bottom clock input pins: CLK[4:7] and CLK[12:15]. Input capacitance on left/right clock inputs:
Maximum
Unit
pF pF
CCLKTB CCLKLR CCLKLR+
11.5 7.8 4.4
pF pF pF
CLK1, CLK3, CLK8, CLK10.
Input capacitance on left/right clock inputs: CLK0, CLK2, CLK9, and CLK11.
Notes to Tables 4-9 through 4-32:
(1) (2) (3) (4) (5) (6) When tx_outclock port of altlvds_tx megafunction is 717 MHz, VO D ( m i n ) = 235 mV on the output clock pin. Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO. Drive strength is programmable according to values in Table 2-28 on page 2-122. VREF specifies the center point of the switching range. Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within 0.5 pF. VIO and VCM have multiple ranges and values for J=1 through 10.
Altera Corporation November 2003
4-15
Power Consumption
Stratix Device Handbook, Volume 1
Power Consumption
Altera offers two ways to calculate power for a design: the Altera web power calculator and the PowerGaugeTM feature in the Quartus II software. The interactive power calculator on the Altera web site is typically used prior to designing the FPGA in order to get a magnitude estimate of the device power. The Quartus II software PowerGauge feature allows designers to apply test vectors against their design for more accurate power consumption modeling. In both cases, these calculations should only be used as an estimation of power, not as a specification. Stratix devices require a certain amount of power-up current to successfully power up because of the small process geometry on which they are fabricated. Table 4-33 shows the maximum power-up current (ICCINT) required to power a Stratix device. This specification is for commercial operating conditions. Measurments were performed with an isolated Stratix device on the board to characterize the power-up current of an isolated device. Decoupling capacitors were not used in this measurement. To factor in the current for decoupling capacitors, sum up the current for each capacitor using the following equation: I = C (dV/dt) If the regulator or power supply minimum output current is more than the Stratix device requires, then the device may consume more current than the maximum current listed in Table 4-33. However, the device does not require any more current to successfully power up than what is listed in Table 4-33.
Table 4-33. Stratix Power-Up Current (ICCINT) Requirements Power-Up Current Requirement Device Typ
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 250 400 500 550 650 800 1,000
Unit Max
700 1,200 1,500 1,900 2,300 2,600 3,000 mA mA mA mA mA mA mA
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Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
The exact amount of current consumed varies according to the process, temperature, and power ramp rate. Stratix devices typically require less current during power up than shown in Table 4-33. The user-mode current during device operation is generally higher than the power-up current. The duration of the ICCINT power-up requirement depends on the VCCINT voltage supply rise time. The power-up current consumption drops when the VCCINT supply reaches approximately 0.75 V.
Timing Model
The DirectDrive technology and MultiTrack interconnect ensure predictable performance, accurate simulation, and accurate timing analysis across all Stratix device densities and speed grades. This section describes and specifies the performance, internal, external, and PLL timing specifications. All specifications are representative of worst-case supply voltage and junction temperature conditions.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The Quartus II software issues an informational message during the design compilation if the timing models are preliminary. Table 4-34 shows the status of the Stratix device timing models. Preliminary status means the timing model is subject to change. Initially, timing numbers are created using simulation results, process data, and other known parameters. These tests are used to make the preliminary numbers as close to the actual timing parameters as possible.
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Final timing numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under worstcase voltage and junction temperature conditions.
Table 4-34. Stratix Device Timing Model Status Device
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
Preliminary
Final v v v v v v v
Performance
Table 4-35 shows Stratix performance for some common designs. All performance values were obtained with Quartus II software compilation of LPM, or MegaCore functions for the FIR and FFT designs.
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Table 4-35. Stratix Performance (Part 1 of 3)
Note (1) Resources Used Performance (MHz) -5 Speed Grade
354.1 254.12 422.11 325.41 317.76 319.18 290.86 290.86 290.86
Resource Used
LE
Design Size & Function
16-to-1 multiplexer (2) 32-to-1 multiplexer (2) 16-bit counter 64-bit counter
Mode
TriMatrix DSP LEs Memory Blocks Blocks
22 46 16 64 0 30 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0
-6 Speed Grade
308.92 225.52 422.11 301.65 277.62 278.86 255.55 255.55 255.55
-7 Speed Grade
279.25 196.34 390.01 262.88 241.48 242.54 222.27 222.27 222.27
-8 Speed Grade
239.80 169.26 344.23 223.26 205.21 206.14 188.89 188.89 188.89
TriMatrix memory M512 block TriMatrix memory M4K block
RAM 32 x 18 bit (2) Simple dual-port FIFO 32 x 18 bit (2) RAM 128 x 36 bit (2) RAM 256 x 18 bit (2) FIFO 128 x 36 bit (2) Simple dual-port True dualport
0 0 34
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Table 4-35. Stratix Performance (Part 2 of 3)
Note (1) Resources Used Performance (MHz) -5 Speed Grade
255.95 255.95 269.83 278.88 275.86 255.95 280.64 269.84 269.83 275.84 275.84 275.86 287.83 287.83 287.85 335.0 278.78 148.25 278.78 278.78
Resource Used
TriMatrix memory M-RAM block
Design Size & Function
RAM 4K x 144 bit (2)
Mode
TriMatrix DSP LEs Memory Blocks Blocks
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
-6 Speed Grade
223.06 233.06 237.69 243.21 223.13 223.06 254.36 237.7 237.7 244.6 244.6 244.6 253.33 253.33 253.29 293.94 237.41 134.71 237.41 237.41
-7 Speed Grade
194.06 194.06 206.82 211.49 194.02 194.06 221.17 206.7 206.7 212.7 212.7 212.7 220.29 220.29 220.36 255.68 206.52 117.16 206.52 206.52
-8 Speed Grade
164.93 164.93 164.93 179.77 164.93 164.93 188.00 175.74 175.74 180.83 180.83 180.83 187.26 187.26 187.26 217.24 175.5 99.59 175.5 175.5
Single port Simple dual-port True dualport
RAM 8K x 72 bit (2) Single port Simple dual-port True dualport RAM 16K x 36 bit (2) Single port Simple dual-port True dualport RAM 32K x 18 bit (2) Single port Simple dual-port True dualport RAM 64K x 9 bit (2) Single port Simple dual-port True dualport DSP block 9 x 9-bit multiplier (3) 18 x 18-bit multiplier (3) 36 x 36-bit multiplier (3), (5) 36 x 36-bit multiplier (4), (5) 18-bit, 4-tap FIR filter
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Table 4-35. Stratix Performance (Part 3 of 3)
Note (1) Resources Used Performance (MHz) -5 Speed Grade
148.27 271.81
Resource Used
Multiple resources
Design Size & Function
8-bit, 16-tap parallel FIR filter 8-bit, 1,024-point FFT function
Mode
TriMatrix DSP LEs Memory Blocks Blocks
58 870 0 5 (6) 4 1
-6 Speed Grade
138.19 234.19
-7 Speed Grade
115.02 206.52
-8 Speed Grade
100.05 174.03
Notes to Table 4-35:
(1) (2) (3) (4) (5) (6) These design performance numbers were obtained using the Quartus II software. This application uses registered inputs and outputs. This application uses registered input and output stages within the DSP block. This application uses registered input, pipeline, and output stages within the DSP block. This is for a signed/signed or unsigned/unsigned case. This design uses M4K TriMatrix memory blocks.
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis independent of device density. Tables 4-36 through 4-42 describe the Stratix device internal timing microparameters for LEs, IOEs, TriMatrix memory structures, DSP blocks, and MultiTrack interconnects.
Table 4-36. LE Internal Timing Microparameter Descriptions Symbol
tSU tH tCO tLUT tCLR tPRE tCLKHL
Parameter
LE register setup time before clock LE register hold time after clock LE register clock-to-output delay LE combinatorial LUT delay for data-in to data-out Minimum clear pulse width Minimum preset pulse width Minimum clock high or low time
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Table 4-37. IOE Internal Timing Microparameter Descriptions Symbol
tSU tH tCO tPIN2COMBOUT_R tPIN2COMBOUT_C tCOMBIN2PIN_R tCOMBIN2PIN_C tCLR tPRE tCLKHL
Parameter
IOE input and output register setup time before clock IOE input and output register hold time after clock IOE input and output register clock-to-output delay Row input pin to IOE combinatorial output Column input pin to IOE combinatorial output Row IOE data input to combinatorial output pin Column IOE data input to combinatorial output pin Minimum clear pulse width Minimum preset pulse width Minimum clock high or low time
Table 4-38. DSP Block Internal Timing Microparameter Descriptions Symbol
tSU tH tCO tINREG2PIPE9 tINREG2PIPE18 tPIPE2OUTREG2ADD tPIPE2OUTREG4ADD tPD9 tPD18 tPD36 tCLR tCLKHL
Parameter
Input, pipeline, and output register setup time before clock Input, pipeline, and output register hold time after clock Input, pipeline, and output register clock-to-output delay Input Register to DSP Block pipeline register in 9 x 9-bit mode Input Register to DSP Block pipeline register in 18 x 18-bit mode DSP Block Pipeline Register to output register delay in TwoMultipliers Adder mode DSP Block Pipeline Register to output register delay in FourMultipliers Adder mode Combinatorial input to output delay for 9 x 9 Combinatorial input to output delay for 18 x 18 Combinatorial input to output delay for 36 x 36 Minimum clear pulse width Minimum clock high or low time
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Table 4-39. M512 Block Internal Timing MicroparameterDescriptions Symbol
tM512RC tM512WC tM512WERESU tM512WEREH tM512DATASU tM512DATAH tM512WADDRSU tM512WADDRH tM512RADDRSU tM512RADDRH tM512DATACO1 tM512DATACO2 tM512CLKHL tM512CLR
Parameter
Synchronous read cycle time Synchronous write cycle time Write or read enable setup time before clock Write or read enable hold time after clock Data setup time before clock Data hold time after clock Write address setup time before clock Write address hold time after clock Read address setup time before clock Read address hold time after clock Clock-to-output delay when using output registers Clock-to-output delay without output registers Minimum clock high or low time Minimum clear pulse width
Table 4-40. M4K Block Internal Timing Microparameter Descriptions (Part 1 of 2) Symbol
tM4KRC tM4KWC tM4KWERESU tM4KWEREH tM4KBESU tM4KBEH tM4KDATAASU tM4KDATAAH tM4KADDRASU tM4KADDRAH tM4KDATABSU tM4KDATABH tM4KADDRBSU tM4KADDRBH
Parameter
Synchronous read cycle time Synchronous write cycle time Write or read enable setup time before clock Write or read enable hold time after clock Byte enable setup time before clock Byte enable hold time after clock A port data setup time before clock A port data hold time after clock A port address setup time before clock A port address hold time after clock B port data setup time before clock B port data hold time after clock B port address setup time before clock B port address hold time after clock
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Table 4-40. M4K Block Internal Timing Microparameter Descriptions (Part 2 of 2) Symbol
tM4KDATACO1 tM4KDATACO2 tM4KCLKHL tM4KCLR
Parameter
Clock-to-output delay when using output registers Clock-to-output delay without output registers Minimum clock high or low time Minimum clear pulse width
Table 4-41. M-RAM Block Internal Timing Microparameter Descriptions Symbol
tMRAMRC tMRAMWC tMRAMWERESU tMRAMWEREH tMRAMBESU tMRAMBEH tMRAMDATAASU tMRAMDATAAH tMRAMADDRASU tMRAMADDRAH tMRAMDATABSU tMRAMDATABH tMRAMADDRBSU tMRAMADDRBH tMRAMDATACO1 tMRAMDATACO2 tMRAMCLKHL tMRAMCLR
Parameter
Synchronous read cycle time Synchronous write cycle time Write or read enable setup time before clock Write or read enable hold time after clock Byte enable setup time before clock Byte enable hold time after clock A port data setup time before clock A port data hold time after clock A port address setup time before clock A port address hold time after clock B port setup time before clock B port hold time after clock B port address setup time before clock B port address hold time after clock Clock-to-output delay when using output registers Clock-to-output delay without output registers Minimum clock high or low time Minimum clear pulse width
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Table 4-42. Routing Delay Internal Timing Microparameter Descriptions Symbol
tR4 tR8 tR24 tC4 tC8 tC16 tLOCAL
Parameter
Delay for an R4 line with average loading; covers a distance of four LAB columns Delay for an R8 line with average loading; covers a distance of eight LAB columns Delay for an R24 line with average loading; covers a distance of 24 LAB columns Delay for an C4 line with average loading; covers a distance of four LAB rows Delay for an C8 line with average loading; covers a distance of eight LAB rows Delay for an C16 line with average loading; covers a distance of 16 LAB rows Local interconnect delay
Figure 4-3 shows the TriMatrix memory waveforms for the M512, M4K, and M-RAM timing parameters shown in Tables 4-39 through 4-41 above.
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Figure 4-3. Dual-Port RAM Timing Microparameter Waveform
wrclock tWEREH wren tWADDRSU wraddress an-1 tDATAH data-in din-1 tDATASU rdclock tWERESU rden tRC rdaddress bn b0 tDATACO1 reg_data-out doutn-2 doutn-1 tDATACO2 unreg_data-out doutn-1 doutn dout0 doutn dout0 b1 b2 b3 tWEREH din din4 din5 din6 an a0 a1 a2 a3 a4 tWADDRH a5 a6 tWERESU
Internal timing parameters are specified on a speed grade basis independent of device density. Tables 4-43 through 4-48 show the internal timing microparameters for LEs, IOEs, TriMatrix memory structures, DSP blocks, and MultiTrack interconnects.
Table 4-43. LE Internal Timing Microparameters -5 Symbol Min
tSU tH tCO tLUT tCLR tPRE tCLKHL 100 100 100 10 100 156 366 100 100 100
-6 Max Min
10 100 176 459 114 114 114
-7 Max Min
11 114 202 527 135 135 135
-8 Unit Max Min
13 135 238 621
Max
ps ps ps ps ps ps ps
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Table 4-44. IOE Internal Timing Microparameters -5 Symbol Min
tSU tH tCO tPIN2COMBOUT_R tPIN2COMBOUT_C tCOMBIN2PIN_R tCOMBIN2PIN_C tCLR tPRE tCLKHL 262 262 90 64 76 162 1,038 927 2,944 3,189 276 276 95
-6 Max Min
68 80 171 1,093 976 3,099 3,357 317 317 109
-7 Max Min
68 80 171 1,256 1,122 3,563 3,860 373 373 128
-8 Unit Max Min
68 80 171 1,478 1,320 4,193 4,542
Max
ps ps ps ps ps ps ps ps ps ps
Table 4-45. DSP Block Internal Timing Microparameters -5 Symbol Min
tSU tH tCO tINREG2PIPE9 tINREG2PIPE18 tPIPE2OUTREG2ADD tPIPE2OUTREG4ADD tPD9 tPD18 tPD36 tCLR tCLKHL 450 1,350 0 67 142 2,613 3,390 2,002 2,899 3,709 4,795 7,495 500 1,500
-6 Max Min
0 75 158 2,982 3,993 2,203 3,189 4,081 5,275 8,245 575 1,724
-7 Max Min
0 86 181 3,429 4,591 2,533 3,667 4,692 6,065 9,481 676 2,029
-8 Unit Max Min
0 101 214 4,035 5,402 2,980 4,314 5,520 7,135 11,154
Max
ps ps ps ps ps ps ps ps ps ps ps ps
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Table 4-46. M512 Block Internal Timing Microparameters -5 Symbol Min
tM512RC tM512WC tM512WERESU tM512WERH tM512DATASU tM512DATAH tM512WADDRASU tM512WADDRH tM512RADDRASU tM512RADDRH tM512DATACO1 tM512DATACO2 tM512CLKHL tM512CLR 150 170 110 34 110 34 110 34 110 34 424 3,366 167 189
-6 Max
3,340 3,138 123 38 123 38 123 38 123 38 472 3,846 192 217
-7 Max
3,816 3,590 141 43 141 43 141 43 141 43 541 4,421 225 255
-8 Unit Max
4,387 4,128 166 51 166 51 166 51 166 51 637 5,203
Min
Min
Min
Max
5,162 4,860 ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Table 4-47. M4K Block Internal Timing Microparameters (Part 1 of 2) -5 Symbol Min
tM4KRC tM4KWC tM4KWERESU tM4KWERH tM4KDATASU tM4KDATAH tM4KWADDRASU tM4KWADDRH tM4KRADDRASU tM4KRADDRH tM4KDATABSU tM4KDATABH 131 34 131 34 131 34 131 34 131 34
-6 Max
3,807 2,556 149 38 149 38 149 38 149 38 149 38
-7 Max
4,320 2,840 171 43 171 43 171 43 171 43 171 43
-8 Unit Max
4,967 3,265 202 51 202 51 202 51 202 51 202 51
Min
Min
Min
Max
5,844 3,842 ps ps ps ps ps ps ps ps ps ps ps ps
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Table 4-47. M4K Block Internal Timing Microparameters (Part 2 of 2) -5 Symbol Min
tM4KADDRBSU tM4KADDRBH tM4KDATACO1 tM4KDATACO2 tM4KCLKHL tM4KCLR 150 170 131 34 571 3,984 167 189
-6 Max Min
149 38 635 4,507 192 217
-7 Max Min
171 43 729 5,182 225 255
-8 Unit Max Min
202 51 858 6,097
Max
ps ps ps ps ps ps
Table 4-48. M-RAM Block Internal Timing Microparameters -5 Symbol Min
tMRAMRC tMRAMWC tMRAMWERESU tMRAMWERH tMRAMDATASU tMRAMDATAH tMRAMWADDRASU tMRAMWADDRH tMRAMRADDRASU tMRAMRADDRH tMRAMDATABSU tMRAMDATABH tMRAMADDRBSU tMRAMADDRBH tMRAMDATACO1 tMRAMDATACO2 tMRAMCLKHL tMRAMCLR 270 135 25 18 25 18 25 18 25 18 25 18 25 18 1,038 4,362 300 150
-6 Max
4,364 3,654 25 20 25 20 25 20 25 20 25 20 25 20 1,053 4,939 345 172
-7 Max
4,838 4,127 28 23 28 23 28 23 28 23 28 23 28 23 1,210 5,678 405 202
-8 Unit Max
5,562 4,746 33 27 33 27 33 27 33 27 33 27 33 27 1,424 6,681
Min
Min
Min
Max
6,544 5,583 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
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Routing delays vary depending on the load on that specific routing line. The Quartus II software reports the routing delay information when running the timing analysis for a design. Contact Altera Applications for more details.
External Timing Parameters
External timing parameters are specified by device density and speed grade. Figure 4-4 shows the timing model for bidirectional IOE pin timing. All registers are within the IOE. Figure 4-4. External Timing in Stratix Devices
OE Register D PRN Q
Dedicated Clock
CLRN Output Register D PRN Q
tXZ tZX tINSU tINH tOUTCO
Bidirectional Pin
CLRN
Input Register PRN D Q
CLRN
All external I/O timing parameters shown are for 3.3-V LVTTL I/O standard with the maximum current strength and fast slew rate. For external I/O timing using standards other than LVTTL or for different current strengths, use the I/O standard input and output delay adders in Tables 4-94 through 4-98.
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Table 4-49 shows the external I/O timing parameters when using fast regional clock networks.
Table 4-49. Stratix Fast Regional Clock External I/O Timing Parameters Notes (1), (2) Symbol
tINSU
Parameter
Setup time for input or bidirectional pin using column IOE input register with fast regional clock fed by FCLK pin Hold time for input or bidirectional pin using column IOE input register with fast regional clock fed by FCLK pin Clock-to-output delay output or bidirectional pin using column IOE output register with fast regional clock fed by FCLK pin Synchronous column IOE output enable register to output pin disable delay using fast regional clock fed by FCLK pin Synchronous column IOE output enable register to output pin enable delay using fast regional clock fed by FCLK pin
Conditions
tINH
tOUTCO
CLOAD = 10 pF
tXZ
CLOAD = 10 pF
tZX
CLOAD = 10 pF
Notes to Table 4-49:
(1) (2) These timing parameters are sample-tested only. These timing parameters are for column and row IOE pins. Designers should use the Quartus II software to verify the external timing for any pin.
Table 4-50 shows the external I/O timing parameters when using regional clock networks.
Table 4-50. Stratix Regional Clock External I/O Timing Parameters (Part 1 of 2) Notes (1), (2) Symbol
tINSU
Parameter
Setup time for input or bidirectional pin using column IOE input register with regional clock fed by CLK pin Hold time for input or bidirectional pin using column IOE input register with regional clock fed by CLK pin Clock-to-output delay output or bidirectional pin using column IOE output register with regional clock fed by CLK pin
Conditions
tINH tOUTCO
CLOAD = 10 pF
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Table 4-50. Stratix Regional Clock External I/O Timing Parameters (Part 2 of 2) Notes (1), (2) Symbol
tXZ
Parameter
Synchronous column IOE output enable register to output pin disable delay using regional clock fed by CLK pin Synchronous column IOE output enable register to output pin enable delay using regional clock fed by CLK pin Setup time for input or bidirectional pin using column IOE input register with regional clock fed by Enhanced PLL with default phase setting Hold time for input or bidirectional pin using column IOE input register with regional clock fed by Enhanced PLL with default phase setting Clock-to-output delay output or bidirectional pin using column IOE output register with regional clock Enhanced PLL with default phase setting Synchronous column IOE output enable register to output pin disable delay using regional clock fed by Enhanced PLL with default phase setting Synchronous column IOE output enable register to output pin enable delay using regional clock fed by Enhanced PLL with default phase setting
Conditions
CLOAD = 10 pF
tZX
CLOAD = 10 pF
tINSUPLL
tINHPLL
tOUTCOPLL
CLOAD = 10 pF
tXZPLL
CLOAD = 10 pF
tZXPLL
CLOAD = 10 pF
Notes to Table 4-50:
(1) (2) These timing parameters are sample-tested only. These timing parameters are for column IOE pins. Row IOE pins are 100- to 200-ps slower depending on device, speed grade, and the specific parameter in question. Designers should use the Quartus II software to verify the external timing for any pin.
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Table 4-51 shows the external I/O timing parameters when using global clock networks.
Table 4-51. Stratix Global Clock External I/O Timing Parameters Notes (1), (2) Symbol
tINSU
Parameter
Setup time for input or bidirectional pin using column IOE input register with global clock fed by CLK pin Hold time for input or bidirectional pin using column IOE input register with global clock fed by CLK pin Clock-to-output delay output or bidirectional pin using column IOE output register with global clock fed by CLK pin Synchronous column IOE output enable register to output pin disable delay using global clock fed by CLK pin Synchronous column IOE output enable register to output pin enable delay using global clock fed by CLK pin Setup time for input or bidirectional pin using column IOE input register with global clock fed by Enhanced PLL with default phase setting Hold time for input or bidirectional pin using column IOE input register with global clock fed by enhanced PLL with default phase setting Clock-to-output delay output or bidirectional pin using column IOE output register with global clock enhanced PLL with default phase setting Synchronous column IOE output enable register to output pin disable delay using global clock fed by enhanced PLL with default phase setting Synchronous column IOE output enable register to output pin enable delay using global clock fed by enhanced PLL with default phase setting
Conditions
tINH tOUTCO
CLOAD = 10 pF
tXZ
CLOAD = 10 pF
tZX
CLOAD = 10 pF
tINSUPLL
tINHPLL
tOUTCOPLL
CLOAD = 10 pF
tXZPLL
CLOAD = 10 pF
tZXPLL
CLOAD = 10 pF
Notes to Table 4-51:
(1) (2) These timing parameters are sample-tested only. These timing parameters are for column IOE pins using a 3.3-V LVTTL, 24-mA setting. Row IOE pins are 100- to 250-ps slower depending on device, speed grade, and the specific parameter in question. Designers should use the Quartus II software to verify the external timing for any pin.
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Tables 4-52 through 4-57 show the external timing parameters on column and row pins for EP1S10 devices.
Table 4-52. EP1S10 Column Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX 2.245 0.000 2.000 4.597 4.707 4.707
Note (1) Unit
-6 Speed Grade Min
2.332 0.000 2.000 4.920 5.036 5.036
-7 Speed Grade Min
2.666 0.000 2.000 5.635 5.767 5.767
-8 Speed Grade Min
NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns
Table 4-53. EP1S10 Column Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.035 0.000 0.500 2.629 2.739 2.739 2.114 0.000 2.000 4.728 4.838 4.838 0.941 0.000 0.500 2.769 2.885 2.885
Note (1) Unit
-6 Speed Grade Min
2.218 0.000 2.000 5.078 5.194 5.194
-7 Speed Grade Min
2.348 0.000 2.000 6.004 6.136 6.136 1.070 0.000 0.500 3.158 3.290 3.290
-8 Speed Grade
Max
Max
Max
NA NA NA NA NA NA NA NA NA NA NA NA ns ns ns ns ns ns ns ns ns ns
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Table 4-54. EP1S10 Column Pin Global Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 0.988 0.000 0.500 2.634 2.744 2.744 1.785 0.000 2.000 5.057 5.167 5.167 0.936 0.000 0.500 2.774 2.890 2.890
Note (1) -8 Speed Grade Unit Min
NA NA
-6 Speed Grade Min
1.814 0.000 2.000 5.438 5.554 5.554
-7 Speed Grade Min
2.087 0.000 2.000 6.214 6.346 6.346 1.066 0.000 0.500 3.162 3.294 3.294
Max
Max
Max
Max
ns ns NA NA NA ns ns ns ns ns NA NA NA ns ns ns
NA
NA NA NA
Table 4-55. EP1S10 Row Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX 2.194 0.000 2.000 4.956 5.193 5.193
Note (1) Unit
-6 Speed Grade Min
2.384 0.000 2.000 4.971 5.220 5.220
-7 Speed Grade Min
2.727 0.000 2.000 5.463 5.749 5.749
-8 Speed Grade Min
NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns
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Table 4-56. EP1S10 Row Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.126 0.000 0.500 2.804 3.041 3.041 2.244 0.000 2.000 4.906 5.143 5.143 1.186 0.000 0.500 2.627 2.876 2.876
Note (1) -8 Speed Grade Unit Min
NA NA
-6 Speed Grade Min
2.413 0.000 2.000 4.942 5.191 5.191
-7 Speed Grade Min
2.574 0.000 2.000 5.616 5.902 5.902 1.352 0.000 0.500 2.765 3.051 3.051
Max
Max
Max
Max
ns ns NA NA NA ns ns ns ns ns NA NA NA ns ns ns
NA
NA NA NA
Table 4-57. EP1S10 Row Pin Global Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL Note to Tables 4-52 - 4-57:
(1) Only EP1S25, EP1S30, and EP1S40 devices have the -8 speed grade.
Note (1) -8 Speed Grade Unit Min
NA NA
-6 Speed Grade Min
2.062 0.000
-7 Speed Grade Min
2.368 0.000
Max
Max
Max
Max
ns ns NA NA NA ns ns ns ns ns NA NA NA ns ns ns
1.919 0.000 2.000 5.231 5.468 5.468 1.126 0.000 0.500 2.804 3.041 3.041
2.000
5.293 5.542 5.542
2.000
5.822 6.108 6.108
NA
1.186 0.000 0.500 2.627 2.876 2.876
1.352 0.000 0.500 2.765 3.051 3.051
NA NA NA
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Tables 4-58 through 4-63 show the external timing parameters on column and row pins for EP1S20 devices.
Table 4-58. EP1S20 Column Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX 2.072 0.000 2.000 4.670 4.780 4.780
Note (1) Unit
-6 Speed Grade Min
2.296 0.000 2.000 5.000 5.116 5.116
-7 Speed Grade Min
2.624 0.000 2.000 5.728 5.860 5.860
-8 Speed Grade Min
NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns
Table 4-59. EP1S20 Column Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 0.926 0.000 0.500 2.638 2.748 2.748 1.500 0.000 2.000 5.242 5.352 5.352 0.934 0.000 0.500 2.776 2.892 2.892
Note (1) Unit
-6 Speed Grade Min
1.635 0.000 2.000 5.617 5.733 5.733
-7 Speed Grade Min
1.869 0.000 2.000 6.432 6.564 6.564 1.061 0.000 0.500 3.167 3.299 3.299
-8 Speed Grade Min
NA NA NA NA NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Altera Corporation November 2003
4-37
Timing Model
Stratix Device Handbook, Volume 1
Table 4-60. EP1S20 Column Pin Global Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 0.874 0.000 0.500 2.648 2.758 2.758 1.612 0.000 2.000 5.172 5.282 5.282 0.926 0.000 0.500 2.784 2.900 2.900
Note (1) -8 Speed Grade Unit Min
NA NA
-6 Speed Grade Min
1.699 0.000 2.000 5.553 5.669 5.669
-7 Speed Grade Min
1.943 0.000 2.000 6.358 6.490 6.490 1.052 0.000 0.500 3.176 3.308 3.308
Max
Max
Max
Max
ns ns NA NA NA ns ns ns ns ns NA NA NA ns ns ns
NA
NA NA NA
Table 4-61. EP1S20 Row Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX 2.021 0.000 2.000 4.629 4.866 4.866
Note (1) Unit
-6 Speed Grade Min
2.199 0.000 2.000 4.956 5.205 5.205
-7 Speed Grade Min
2.513 0.000 2.000 5.677 5.963 5.963
-8 Speed Grade Min
NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns
4-38
Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Table 4-62. EP1S20 Row Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.126 0.000 0.500 2.304 2.541 2.541 1.733 0.000 2.000 4.917 5.154 5.154 1.186 0.000 0.500 2.427 2.676 2.676
Note (1) -8 Speed Grade Unit Min
NA NA
-6 Speed Grade Min
1.880 0.000 2.000 5.275 5.524 5.524
-7 Speed Grade Min
2.147 0.000 2.000 6.043 6.329 6.329 1.352 0.000 0.500 2.765 3.051 3.051
Max
Max
Max
Max
ns ns NA NA NA ns ns ns ns ns NA NA NA ns ns ns
NA
NA NA NA
Table 4-63. EP1S20 Row Pin Global Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL Note to Tables 4-58 - 4-63:
(1) Only EP1S25, EP1S30, and EP1S40 devices have the -8 speed grade.
Note (1) -8 Speed Grade Unit Min
NA NA
-6 Speed Grade Min
1.951 0.000
-7 Speed Grade Min
2.232 0.000
Max
Max
Max
Max
ns ns NA NA NA ns ns ns ns ns NA NA NA ns ns ns
1.811 0.000 2.000 4.839 5.076 5.076 1.126 0.000 0.500 2.304 2.541 2.541
2.000
5.204 5.453 5.453
2.000
5.958 6.244 6.244
NA
1.186 0.000 0.500 2.427 2.676 2.676
1.352 0.000 0.500 2.765 3.051 3.051
NA NA NA
Altera Corporation November 2003
4-39
Timing Model
Stratix Device Handbook, Volume 1
Tables 4-64 through 4-69 show the external timing parameters on column and row pins for EP1S25 devices.
Table 4-64. EP1S25 Column Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX 2.418 0.000 2.000 4.524 4.634 4.634
-6 Speed Grade Min
2.618 0.000 2.000 4.834 4.950 4.950
-7 Speed Grade Min
3.014 0.000 2.000 5.538 5.670 5.670
-8 Speed Grade Unit Min
3.448 0.000 2.000 6.474 6.631 6.631
Max
Max
Max
Max
ns ns ns ns ns
Table 4-65. EP1S25 Column Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.061 0.000 0.500 2.661 2.771 2.771 1.713 0.000 2.000 5.229 5.339 5.339 1.155 0.000 0.500 2.799 2.915 2.915
-6 Speed Grade Min
1.838 0.000 2.000 5.614 5.730 5.730
-7 Speed Grade Min
2.069 0.000 2.000 6.432 6.564 6.564 1.284 0.000 0.500 3.195 3.327 3.327
-8 Speed Grade Unit Min
2.396 0.000 2.000 7.526 7.683 7.683 1.462 0.000 0.500 3.728 3.885 3.885
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
4-40
Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Table 4-66. EP1S25 Column Pin Global Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.046 0.000 0.500 2.676 2.786 2.786 1.790 0.000 2.000 5.194 5.304 5.304 1.141 0.000 0.500 2.813 2.929 2.929
-6 Speed Grade Min
1.883 0.000 2.000 5.569 5.685 5.685
-7 Speed Grade Min
2.120 0.000 2.000 6.381 6.513 6.513 1.220 0.000 0.500 3.208 3.340 3.340
-8 Speed Grade Unit Min
2.457 0.000 2.000 7.465 7.622 7.622 1.389 0.000 0.500 3.741 3.898 3.898
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-67. EP1S25 Row Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX 2.394 0.000 2.000 4.456 4.693 4.693
-6 Speed Grade Min
2.594 0.000 2.000 4.761 5.010 5.010
-7 Speed Grade Min
2.936 0.000 2.000 5.454 5.740 5.740
-8 Speed Grade Unit Min
3.425 0.000 2.000 6.365 6.702 6.702
Max
Max
Max
Max
ns ns ns ns ns
Altera Corporation November 2003
4-41
Timing Model
Stratix Device Handbook, Volume 1
Table 4-68. EP1S25 Row Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.326 0.000 0.500 2.304 2.541 2.541 1.970 0.000 2.000 4.880 5.117 5.117 1.386 0.000 0.500 2.427 2.676 2.676
-6 Speed Grade Min
2.109 0.000 2.000 5.246 5.495 5.495
-7 Speed Grade Min
2.377 0.000 2.000 6.013 6.299 6.299 1.552 0.000 0.500 2.765 3.051 3.051
-8 Speed Grade Unit Min
2.759 0.000 2.000 7.031 7.368 7.368 1.775 0.000 0.500 3.223 3.560 3.560
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-69. EP1S25 Row Pin Global Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.326 0.000 0.500 2.304 2.541 2.541 1.963 0.000 2.000 4.887 5.124 5.124 1.386 0.000 0.500 2.427 2.676 2.676
-6 Speed Grade Min
2.108 0.000 2.000 5.247 5.496 5.496
-7 Speed Grade Min
2.379 0.000 2.000 6.011 6.297 6.297 1.552 0.000 0.500 2.765 3.051 3.051
-8 Speed Grade Unit Min
2.761 0.000 2.000 7.029 7.366 7.366 1.775 0.000 0.500 3.223 3.560 3.560
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
4-42
Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Tables 4-70 through 4-75 show the external timing parameters on column and row pins for EP1S30 devices.
Table 4-70. EP1S30 Column Pin Fast Regional Clock External I/O Timing Parameters Symbol -5 Speed Grade Min
tINSU tINH tOUTCO tXZ tZX 2.509 0.000 2.000 5.013 5.123 5.123
-6 Speed Grade Min
2.687 0.000 2.000 5.413 5.529 5.529
-7 Speed Grade Min
3.059 0.000 2.000 6.202 6.334 6.334
-8 Speed Grade Min
3.575 0.000 2.000 7.259 7.416 7.416
Unit
Max
Max
Max
Max
ns ns ns ns ns
Table 4-71. EP1S30 Column Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.034 0.000 0.500 2.630 2.740 2.740 2.441 0.000 2.000 5.081 5.191 5.191 1.086 0.000 0.500 2.768 2.884 2.884
-6 Speed Grade Min
2.578 0.000 2.000 5.522 5.638 5.638
-7 Speed Grade Min
2.986 0.000 2.000 6.326 6.458 6.458 1.166 0.000 0.500 3.162 3.294 3.294
-8 Speed Grade Unit Min
3.491 0.000 2.000 7.403 7.560 7.560 1.341 0.000 0.500 3.689 3.846 3.846
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-72. EP1S30 Column Pin Global Clock External I/O Timing Parameters (Part 1 of 2) -5 Speed Grade Symbol Min
tINSU tINH tOUTCO 2.067 0.000 2.000 5.455
-6 Speed Grade Min
2.215 0.000 2.000 5.929
-7 Speed Grade Min
2.518 0.000 2.000 6.794
-8 Speed Grade Unit Min
2.941 0.000 2.000 7.953
Max
Max
Max
Max
ns ns ns
Altera Corporation November 2003
4-43
Timing Model
Stratix Device Handbook, Volume 1
Table 4-72. EP1S30 Column Pin Global Clock External I/O Timing Parameters (Part 2 of 2) -5 Speed Grade Symbol Min
tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.020 0.000 0.500 2.602 2.712 2.712
-6 Speed Grade Min Max
6.045 6.045 1.065 0.000 0.500 2.745 2.861 2.861
-7 Speed Grade Min Max
6.926 6.926 1.204 0.000 0.500 3.124 3.256 3.256
-8 Speed Grade Unit Min Max
8.110 8.110 1.378 0.000 0.500 3.652 3.809 3.809 ns ns ns ns ns ns ns
Max
5.565 5.565
Table 4-73. EP1S30 Row Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX 2.589 0.000 2.000 4.741 4.978 4.978
-6 Speed Grade Min
2.779 0.000 2.000 5.124 5.373 5.373
-7 Speed Grade Min
3.178 0.000 2.000 5.872 6.158 6.158
-8 Speed Grade Unit Min
3.732 0.000 2.000 6.870 7.207 7.207
Max
Max
Max
Max
ns ns ns ns ns
4-44
Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Table 4-74. EP1S30 Row Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.126 0.000 0.500 2.304 2.541 2.541 2.576 0.000 2.000 4.754 4.991 4.991 1.186 0.000 0.500 2.427 2.676 2.676
-6 Speed Grade Min
2.723 0.000 2.000 5.180 5.429 5.429
-7 Speed Grade Min
3.118 0.000 2.000 5.932 6.218 6.218 1.352 0.000 0.500 2.765 3.051 3.051
-8 Speed Grade Unit Min
3.662 0.000 2.000 6.940 7.277 7.277 1.575 0.000 0.500 3.223 3.560 3.560
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-75. EP1S30 Row Pin Global Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.126 0.000 0.500 2.304 2.541 2.541 2.217 0.000 2.000 5.113 5.350 5.350 1.186 0.000 0.500 2.427 2.676 2.676
-6 Speed Grade Min
2.332 0.000 2.000 5.571 5.820 5.820
-7 Speed Grade Min
2.667 0.000 2.000 6.383 6.669 6.669 1.352 0.000 0.500 2.765 3.051 3.051
-8 Speed Grade Unit Min
3.129 0.000 2.000 7.473 7.810 7.810 1.575 0.000 0.500 3.223 3.560 3.560
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Altera Corporation November 2003
4-45
Timing Model
Stratix Device Handbook, Volume 1
Tables 4-76 through 4-81 show the external timing parameters on column and row pins for EP1S40 devices.
Table 4-76. EP1S40 Column Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX 2.704 0.000 2.000 5.060 5.170 5.170
-6 Speed Grade Min
2.912 0.000 2.000 5.432 5.548 5.548
-7 Speed Grade Min
3.235 0.000 2.000 6.226 6.358 6.358
-8 Speed Grade Unit Min
3.748 0.000 2.000 7.286 7.443 7.443
Max
Max
Max
Max
ns ns ns ns ns
Table 4-77. EP1S40 Column Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.254 0.000 0.500 2.610 2.720 2.720 2.467 0.000 2.000 5.255 5.365 5.365 1.259 0.000 0.500 2.751 2.867 2.867
-6 Speed Grade Min
2.671 0.000 2.000 5.673 5.789 5.789
-7 Speed Grade Min
3.011 0.000 2.000 6.501 6.633 6.633 1.445 0.000 0.500 3.134 3.266 3.266
-8 Speed Grade Unit Min
3.485 0.000 2.000 7.609 7.766 7.766 1.632 0.000 0.500 3.658 3.815 3.815
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
4-46
Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Table 4-78. EP1S40 Column Pin Global Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.228 0.000 0.500 2.594 2.704 2.704 2.033 0.000 2.000 5.689 5.799 5.799 1.278 0.000 0.500 2.732 2.848 2.848
-6 Speed Grade Min
2.184 0.000 2.000 6.116 6.232 6.232
-7 Speed Grade Min
2.451 0.000 2.000 7.010 7.142 7.142 1.415 0.000 0.500 3.113 3.245 3.245
-8 Speed Grade Unit Min
2.830 0.000 2.000 8.204 8.361 8.361 1.594 0.000 0.500 3.636 3.793 3.793
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-79. EP1S40 Row Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX 2.450 0.000 2.000 4.880 5.117 5.117
-6 Speed Grade Min
2.662 0.000 2.000 5.241 5.490 5.490
-7 Speed Grade Min
3.046 0.000 2.000 6.004 6.290 6.290
-8 Speed Grade Unit Min
3.582 0.000 2.000 7.020 7.357 7.357
Max
Max
Max
Max
ns ns ns ns ns
Altera Corporation November 2003
4-47
Timing Model
Stratix Device Handbook, Volume 1
Table 4-80. EP1S40 Row Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.126 0.000 0.500 2.304 2.541 2.541 2.398 0.000 2.000 4.932 5.169 5.169 1.186 0.000 0.500 2.427 2.676 2.676
-6 Speed Grade Min
2.567 0.000 2.000 5.336 5.585 5.585
-7 Speed Grade Min
2.938 0.000 2.000 6.112 6.398 6.398 1.352 0.000 0.500 2.765 3.051 3.051
-8 Speed Grade Unit Min
3.450 0.000 2.000 7.152 7.489 7.489 1.575 0.000 0.500 3.223 3.560 3.560
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-81. EP1S40 Row Pin Global Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.126 0.000 0.500 2.304 2.541 2.541 1.965 0.000 2.000 5.365 5.602 5.602 1.186 0.000 0.500 2.427 2.676 2.676
-6 Speed Grade Min
2.128 0.000 2.000 5.775 6.024 6.024
-7 Speed Grade Min
2.429 0.000 2.000 6.621 6.907 6.907 1.352 0.000 0.500 2.765 3.051 3.051
-8 Speed Grade Unit Min
2.857 0.000 2.000 7.745 8.082 8.082 1.575 0.000 0.500 3.223 3.560 3.560
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
4-48
Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Tables 4-82 through 4-87 show the external timing parameters on column and row pins for EP1S60 devices.
Table 4-82. EP1S60 Column Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX 2.998 0.000 2.000 5.113 5.223 5.223
Note (1) Unit
-6 Speed Grade Min
3.289 0.000 2.000 4.892 5.608 5.608
-7 Speed Grade Min
3.737 0.000 2.000 5.694 6.426 6.426
-8 Speed Grade Min
NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns
Table 4-83. EP1S60 Column Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.161 0.000 0.500 2.603 2.713 2.713 2.712 0.000 2.000 5.441 5.551 5.551 1.168 0.000 0.500 2.142 2.858 2.858
Note (1) Unit
-6 Speed Grade Min
2.913 0.000 2.000 5.268 5.984 5.984
-7 Speed Grade Min
3.255 0.000 2.000 6.125 6.857 6.857 1.354 0.000 0.500 2.525 3.257 3.257
-8 Speed Grade Min
NA NA NA NA NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Altera Corporation November 2003
4-49
Timing Model
Stratix Device Handbook, Volume 1
Table 4-84. EP1S60 Column Pin Global Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.079 0.000 0.500 2.643 2.753 2.753 2.145 0.000 2.000 6.008 6.118 6.118 1.131 0.000 0.500 2.179 2.895 2.895
Note (1) -8 Speed Grade Unit Min
NA NA
-6 Speed Grade Min
2.312 0.000 2.000 5.869 6.585 6.585
-7 Speed Grade Min
2.617 0.000 2.000 6.814 7.546 7.546 1.259 0.000 0.500 2.569 3.301 3.301
Max
Max
Max
Max
ns ns NA NA NA ns ns ns ns ns NA NA NA ns ns ns
NA
NA NA NA
Table 4-85. EP1S60 Row Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX 3.121 0.000 2.000 4.898 5.135 5.135
Note (1) Unit
-6 Speed Grade Min
3.370 0.000 2.000 5.270 5.519 5.519
-7 Speed Grade Min
3.833 0.000 2.000 6.036 6.322 6.322
-8 Speed Grade Min
NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns
4-50
Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Table 4-86. EP1S60 Row Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.326 0.000 0.500 2.304 2.541 2.541 2.899 0.000 2.000 5.120 5.357 5.357 1.386 0.000 0.500 2.427 2.676 2.676
Note (1) -8 Speed Grade Unit Min
NA NA
-6 Speed Grade Min
3.104 0.000 2.000 5.536 5.785 5.785
-7 Speed Grade Min
3.529 0.000 2.000 6.340 6.626 6.626 1.552 0.000 0.500 2.765 3.051 3.051
Max
Max
Max
Max
ns ns NA NA NA ns ns ns ns ns NA NA NA ns ns ns
NA
NA NA NA
Table 4-87. EP1S60 Row Pin Global Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL Note to Tables 4-82 - 4-87:
(1) Only EP1S25, EP1S30, and EP1S40 devices have the -8 speed grade.
Note (1) -8 Speed Grade Unit Min
NA NA
-6 Speed Grade Min
2.457 0.000
-7 Speed Grade Min
2.786 0.000
Max
Max
Max
Max
ns ns NA NA NA ns ns ns ns ns NA NA NA ns ns ns
2.288 0.000 2.000 5.731 5.968 5.968 1.326 0.000 0.500 2.304 2.541 2.541
2.000
6.183 6.432 6.432
2.000
7.083 7.369 7.369
NA
1.386 0.000 0.500 2.427 2.676 2.676
1.552 0.000 0.500 2.765 3.051 3.051
NA NA NA
Altera Corporation November 2003
4-51
Timing Model
Stratix Device Handbook, Volume 1
Tables 4-88 through 4-93 show the external timing parameters on column and row pins for EP1S80 devices.
Table 4-88. EP1S80 Column Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX 2.297 0.000 2.000 5.072 5.182 5.182
Note (1) Unit
-6 Speed Grade Min
2.539 0.000 2.000 4.547 5.563 5.563
-7 Speed Grade Min
2.854 0.000 2.000 5.341 6.373 6.373
-8 Speed Grade Min
NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns
Table 4-89. EP1S80 Column Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 0.336 0.000 0.500 3.186 3.296 3.296 1.939 0.000 2.000 5.430 5.540 5.540 0.395 0.000 0.500 2.415 3.431 3.431
Note (1) Unit
-6 Speed Grade Min
2.088 0.000 2.000 4.954 5.970 5.970
-7 Speed Grade Min
2.439 0.000 2.000 5.807 6.839 6.839 0.531 0.000 0.500 2.797 3.829 3.829
-8 Speed Grade Min
NA NA NA NA NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
4-52
Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Table 4-90. EP1S80 Column Pin Global Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 0.321 0.000 0.500 3.243 3.353 3.353 1.225 0.000 2.000 6.186 6.296 6.296 0.331 0.000 0.500 2.479 3.495 3.495
Note (1) -8 Speed Grade Unit Min
NA NA
-6 Speed Grade Min
1.330 0.000 2.000 5.756 6.772 6.772
-7 Speed Grade Min
1.516 0.000 2.000 6.730 7.762 7.762 0.510 0.000 0.500 2.869 3.901 3.901
Max
Max
Max
Max
ns ns NA NA NA ns ns ns ns ns NA NA NA ns ns ns
NA
NA NA NA
Table 4-91. EP1S80 Row Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX 2.770 0.000 2.000 4.857 5.094 5.094
Note (1)
-6 Speed Grade Min
2.971 0.000 2.000 5.224 5.473 5.473
-7 Speed Grade Min
3.351 0.000 2.000 5.983 6.269 6.269
-8 Speed Grade Unit Min
NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns
Altera Corporation November 2003
4-53
Timing Model
Stratix Device Handbook, Volume 1
Table 4-92. EP1S80 Row Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 0.876 0.000 0.500 2.904 3.141 3.141 2.518 0.000 2.000 5.109 5.346 5.346 0.936 0.000 0.500 3.027 3.276 3.276
Note (1) -8 Speed Grade Unit Min
NA NA
-6 Speed Grade Min
2.674 0.000 2.000 5.521 5.770 5.770
-7 Speed Grade Min
3.012 0.000 2.000 6.322 6.608 6.608 1.102 0.000 0.500 3.365 3.651 3.651
Max
Max
Max
Max
ns ns NA NA NA ns ns ns ns ns NA NA NA ns ns ns
NA
NA NA NA
Table 4-93. EP1S80 Row Pin Global Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL Note to Tables 4-88 - 4-93:
(1) Only EP1S25, EP1S30, and EP1S40 devices have the -8 speed grade.
-6 Speed Grade Min
1.825 0.000
-7 Speed Grade Min
2.035 0.000
-8 Speed Grade Unit Min
NA NA
Max
Max
Max
Max
ns ns NA NA NA ns ns ns ns ns NA NA NA ns ns ns
1.718 0.000 2.000 5.909 6.146 6.146 0.876 0.000 0.500 2.904 3.141 3.141
2.000
6.370 6.619 6.619
2.000
7.299 7.585 7.585
NA
0.936 0.000 0.500 3.027 3.276 3.276
1.102 0.000 0.500 3.365 3.651 3.651
NA NA NA
4-54
Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
External I/O Delay Parameters
External I/O delay timing parameters for I/O standard input and output adders and programmable input and output delays are specified by speed grade independent of device density. Tables 4-94 through 4-99 show the adder delays associated with column and rowI/O pins for flip-chip and wire-bond packages. If an I/O standard is selected other than LVTTL 24 mA with a fast slew rate, add the selected delay to the external tCO and tSU I/O parameters shown in Tables 4-43 through 4-48.
Table 4-94. Stratix I/O Standard Column Pin Input Delay Adders -5 Speed Grade I/O Standard Min
LVCMOS 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL GTL GTL+ 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II
-6 Speed Grade Min Max
0 0 31 157 220 231 231 0 0 0 0 0 126 -32 -32 -74 -74 189 189 126 126 73 73
-7 Speed Grade Min Max
0 0 35 180 252 265 265 0 0 0 0 0 144 -37 -37 -86 -86 217 217 144 144 83 83
-8 Speed Grade Unit Min Max
0 0 42 213 298 312 312 0 0 0 0 0 170 -43 -43 -100 -100 255 255 170 170 99 99 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
0 0 30 150 210 220 220 0 0 0 0 0 120 -30 -30 -70 -70 180 180 120 120 70 70
Altera Corporation November 2003
4-55
Timing Model
Stratix Device Handbook, Volume 1
Table 4-95. Stratix I/O Standard Row Pin Input Delay Adders -5 Speed Grade I/O Standard Min
LVCMOS 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL GTL GTL+ 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II LVDS (1) LVPECL (1) 3.3-V PCML (1) HyperTransport (1)
-6 Speed Grade Min Max
0 0 31 157 220 0 231 0 0 0 0 0 84 -32 -32 -74 -74 189 0 136 0 73 73 42 -53 346 84
-7 Speed Grade Min Max
0 0 35 180 252 0 265 0 0 0 0 0 96 -37 -37 -86 -86 217 0 156 0 83 83 48 -61 397 96
-8 Speed Grade Unit Min Max
0 0 42 213 298 0 312 0 0 0 0 0 113 -43 -43 -100 -100 255 0 184 0 99 99 56 -72 468 113 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
0 0 30 150 210 0 220 0 0 0 0 0 80 -30 -30 -70 -70 180 0 130 0 70 70 40 -50 330 80
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Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Table 4-96. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2) -5 Speed Grade Standard Min
LVCMOS 2 mA 4 mA 8 mA 12 mA 24 mA 3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 24 mA 2.5-V LVTTL 2 mA 8 mA 12 mA 16 mA 1.8-V LVTTL 2 mA 8 mA 12 mA 1.5-V LVTTL 2 mA 4 mA 8 mA GTL GTL+ 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I
-6 Speed Grade Min Max
599 599 368 137 0 599 368 137 74 0 872 263 147 105 441 368 368 1,827 1,218 725 -157 -115 -241 -241 -241 -31 -31 53 95 -52 105 21 242
-7 Speed Grade Min Max
689 689 423 157 0 689 423 157 85 0 1,002 302 169 120 507 423 423 2,101 1,400 833 -181 -133 -277 -277 -277 -36 -36 61 109 -60 120 24 278
-8 Speed Grade Unit Min Max
810 810 497 184 0 810 497 184 99 0 1,179 355 199 142 596 497 497 2,472 1,648 980 -213 -156 -327 -327 -327 -43 -43 71 128 -71 142 28 327 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
570 570 350 130 0 570 350 130 70 0 830 250 140 100 420 350 350 1,740 1,160 690 -150 -110 -230 -230 -230 -30 -30 50 90 -50 100 20 230
Altera Corporation November 2003
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Timing Model
Stratix Device Handbook, Volume 1
Table 4-96. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 2 of 2) -5 Speed Grade Standard Min
SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II
-6 Speed Grade Min Max
0 399 200 399 410
-7 Speed Grade Min Max
0 459 230 459 471
-8 Speed Grade Unit Min Max
0 540 270 540 554 ps ps ps ps ps
Max
0 380 190 380 390
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Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Table 4-97. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 1 of 2) -5 Speed Grade Standard Min
LVCMOS 2 mA 4 mA 8 mA 12 mA 24 mA 3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 24 mA 2.5-V LVTTL 2 mA 8 mA 12 mA 16 mA 1.8-V LVTTL 2 mA 8 mA 12 mA 1.5-V LVTTL 2 mA 4 mA 8 mA GTL GTL+ 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I
-6 Speed Grade Min Max
599 599 368 137 0 599 368 137 74 0 872 263 147 105 1,586 441 368 1,827 1,218 725 599 -115 599 599 599 599 599 53 95 -52 105 21 242
-7 Speed Grade Min Max
689 689 423 157 0 689 423 157 85 0 1,002 302 169 120 1,824 507 423 2,101 1,400 833 689 -133 689 689 689 689 689 61 109 -60 120 24 278
-8 Speed Grade Unit Min Max
810 810 497 184 0 810 497 184 99 0 1,179 355 199 142 2,145 596 497 2,472 1,648 980 810 -156 810 810 810 810 810 71 128 -71 142 28 327 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
570 570 350 130 0 570 350 130 70 0 830 250 140 100 1,510 420 350 1,740 1,160 690 570 -110 570 570 570 570 570 50 90 -50 100 20 230
Altera Corporation November 2003
4-59
Timing Model
Stratix Device Handbook, Volume 1
Table 4-97. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 2 of 2) -5 Speed Grade Standard Min
SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II LVDS (1) LVPECL (1) PCML (1) HyperTransport Technology (1)
-6 Speed Grade Min Max
599 399 599 399 410 -21 42 -63 74
-7 Speed Grade Min Max
689 459 689 459 471 -24 48 -73 85
-8 Speed Grade Unit Min Max
810 540 810 540 554 -29 57 -85 99 ps ps ps ps ps ps ps ps ps
Max
570 380 570 380 390 -20 40 -60 70
4-60
Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Table 4-98. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 1 of 2) -5 Speed Grade I/O Standard Min
LVCMOS 2 mA 4 mA 8 mA 12 mA 24 mA 3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 24 mA 2.5-V LVTTL 2 mA 8 mA 12 mA 16 mA 1.8-V LVTTL 2 mA 8 mA 12 mA 1.5-V LVTTL 2 mA 4 mA 8 mA GTL GTL+ 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I
-6 Speed Grade Min Max
2,011 2,011 1,780 1,549 1,412 2,097 1,866 1,635 1,572 1,498 2,768 2,159 2,043 2,001 4,873 3,728 3,655 6,964 6,355 5,862 1,255 1,297 1,171 1,171 1,171 1,381 1,381 1,465 1,507 1,360 2,013 1,929 3,260
-7 Speed Grade Min Max
2,312 2,312 2,046 1,780 1,623 2,411 2,145 1,879 1,807 1,722 3,182 2,482 2,349 2,300 5,604 4,287 4,203 8,008 7,307 6,740 1,442 1,90 1,346 1,346 1,346 1,587 1,587 1,684 1,732 1,563 2,314 2,218 3,748
-8 Speed Grade Unit Min Max
2,720 2,720 2,407 2,094 1,910 2,836 2,523 2,210 2,125 2,026 3,744 2,920 2,764 2,707 6,592 5,043 4,944 9,422 8,598 7,930 1,697 1,754 1,583 1,583 1,583 1,867 1,867 1,981 2,038 1,839 2,723 2,609 4,410 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
1,911 1,911 1,691 1,471 1,341 1,993 1,773 1,553 1,493 1,423 2,631 2,051 1,941 1,901 4,632 3,542 3,472 6,620 6,040 5,570 1,191 1,231 1,111 1,111 1,111 1,311 1,311 1,391 1,431 1,291 1,912 1,832 3,097
Altera Corporation November 2003
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Timing Model
Stratix Device Handbook, Volume 1
Table 4-98. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 2 of 2) -5 Speed Grade I/O Standard Min
SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II
-6 Speed Grade Min Max
3,018 5,174 4,975 3,417 3,428
-7 Speed Grade Min Max
3,470 5,950 5,721 3,929 3,941
-8 Speed Grade Unit Min Max
4,083 7,000 6,730 4,623 4,637 ps ps ps ps ps
Max
2,867 4,916 4,726 3,247 3,257
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Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Table 4-99. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 1 of 2) -5 Speed Grade I/O Standard Min
LVCMOS 2 mA 4 mA 8 mA 12 mA 3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 2.5-V LVTTL 2 mA 8 mA 12 mA 16 mA 1.8-V LVTTL 2 mA 8 mA 12 mA 1.5-V LVTTL 2 mA 4 mA 8 mA GTL GTL+ 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I
-6 Speed Grade Min Max
2,031 2,031 1,800 1,569 2,055 1,824 1,593 1,530 2,769 2,160 2,044 2,002 4,773 3,628 3,555 6,917 6,308 5,815 2,031 1,317 2,031 2,031 2,031 2,031 2,031 1,485 1,527 1,380 1,892 1,808 2,608 2,965 3,819
-7 Speed Grade Min Max
2,335 2,335 2,069 1,803 2,363 2,097 1,831 1,759 3,183 2,483 2,350 2,301 5,489 4,172 4,088 7,954 7,253 6,686 2,335 1,513 2,335 2,335 2,335 2,335 2,335 1,707 1,755 1,586 2,175 2,079 2,998 3,409 4,391
-8 Speed Grade Unit Min Max
2,747 2,747 2,434 2,121 2,779 2,466 2,153 2,068 3,745 2,921 2,765 2,708 6,456 4,907 4,808 9,358 8,534 7,866 2,747 1,781 2,747 2,747 2,747 2,747 2,747 2,008 2,065 1,866 2,559 2,445 3,528 4,011 5,167 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
1,930 1,930 1,710 1,490 1,953 1,733 1,513 1,453 2,632 2,052 1,942 1,902 4,537 3,447 3,377 6,575 5,995 5,525 1,930 1,250 1,930 1,930 1,930 1,930 1,930 1,410 1,450 1,310 1,797 1,717 2,477 2,817 3,629
Altera Corporation November 2003
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Timing Model
Stratix Device Handbook, Volume 1
Table 4-99. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 2 of 2) -5 Speed Grade I/O Standard Min
1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II LVDS (1) LVPECL (1) 3.3-V PCML (1) HyperTransport technology (1) Note to Tables 4-94 through 4-99:
(1) These parameters are only available on row I/O pins.
-6 Speed Grade Min Max
4,019 2,765 2,776 1,411 1,474 1,369 1,506
-7 Speed Grade Min Max
4,621 3,179 3,191 1,622 1,694 1,573 1,731
-8 Speed Grade Unit Min Max
5,437 3,741 3,755 1,908 1,994 1,852 2,036 ps ps ps ps ps ps ps
Max
3,819 2,627 2,637 1,340 1,400 1,300 1,430
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Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Tables 4-100 and 4-101 show the adder delays for the column and row IOE programmable delays. These delays are controlled with the Quartus II software logic options listed in the Parameter column.
Altera Corporation November 2003
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Timing Model
Stratix Device Handbook, Volume 1
Table 4-100. Stratix IOE Programmable Delays on Column Pins -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter
Decrease input delay to internal cells
Setting Min
Off On Small Medium Large
Unit Max
3,970 3,390 2,810 212 212 3900 0 1,240 0 0 377 0 338 0 540 1,016 1,016 0 540 1,016 1,016 0 540 1,016 1,016 0 -1,112
Min
Max
4,367 3,729 3,091 224 224 4,290 0 1,364 0 0 397 0 372 0 594 1,118 1,118 0 594 1,118 1,118 0 594 1,118 1,118 0 -1,171
Min
Max
5,022 4,288 3,554 257 257 4,933 0 1,568 0 0 456 0 427 0 683 1,285 1,285 0 683 1,285 1,285 0 683 1,285 1,285 0 -1,347
Min
Max
5,908 5,045 4,181 303 303 5,804 0 1,845 0 0 538 0 503 0 804 1,512 1,512 0 804 1,512 1,512 0 804 1,512 1,512 0 -1,584 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Decrease input delay to input register Decrease input delay to output register Increase delay to output pin Increase delay to output enable pin Increase output clock enable delay
Off On Off On Off On Off On Off On Small Large
Increase input clock enable delay
Off On Small Large
Increase output enable clock enable delay
Off On Small Large
Increase tZX delay to output pin
Off On
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Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Table 4-101. Stratix IOE Programmable Delays on Row Pins -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter
Decrease input delay to internal cells
Setting Min
Off On Small Medium Large
Unit Max
3,970 3,390 2,810 164 164 3,900 0 1,240 0 0 377 0 348 0 180 260 260 0 180 260 260 0 540 1,016 1,016 0 -1,109
Min
Max
4,367 3,729 3,091 173 173 4,290 0 1,364 0 0 397 0 383 0 198 286 286 0 198 286 286 0 594 1,118 1,118 0 -1,168
Min
Max
5,022 4,288 3,554 198 198 4,933 0 1,568 0 0 456 0 441 0 227 328 328 0 227 328 328 0 683 1,285 1,285 0 -1,344
Min
Max
5,908 5,045 4,181 234 234 5,804 0 1,845 0 0 538 0 518 0 267 386 386 0 267 386 386 0 804 1,512 1,512 0 -1,580 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Decrease input delay to input register Decrease input delay to output register Increase delay to output pin Increase delay to output enable pin Increase output clock enable delay
Off On Off On Off On Off On Off On Small Large
Increase input clock enable delay
Off On Small Large
Increase output enable clock enable delay
Off On Small Large
Increase tZX delay to output pin
Off On
Altera Corporation November 2003
4-67
Timing Model
Stratix Device Handbook, Volume 1
The scaling factors for output pin timing in Table 4-102 are shown in units of time per pF unit of capacitance (ps/pF). Add this delay to the TCO or combinatorial timing path for output or bidirectional pins in addition to the "I/O Adder" delays shown in Tables 4-94 through 4-99 and the "IOE Programmable Delays" in Tables 4-100 and 4-101.
Table 4-102. Output Delay Adder for Loading on LVTTL/LVCMOS Output Buffers LVTTL/LVCMOS Standards Conditions Parameter Value
24mA 16mA 3.3-V LVTTL 15 25 30 50 60 -
Output Pin Adder Delay (ps/pF)
2.5-V LVTTL - 18 25 35 - 75 1.8-V LVTTL - - 25 40 - 120 1.5-V LVTTL - - 35 80 160 LVCMOS 8 - 15 20 30 60
Drive Strength
12mA 8mA 4mA 2mA
SSTL/HSTL Standards Conditions
SSTL-3 Class I Class II 25 25
Output Pin Adder Delay (ps/pF)
SSTL-2 25 20 SSTL-1.8 25 25 1.5-V HSTL 25 20 1.8-V HSTL 25 20
GTL+/GTL/CTT/PCI Standards Conditions Parameter
VCCIO Voltage Level
Output Pin Adder Delay (ps/pF) Value
3.3V 2.5V GTL+ 18 15 GTL 18 18 CTT 25 PCI 20 AGP 20 -
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Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Maximum Input & Output Clock Rates
Tables 4-103 through 4-108 show the maximum input clock rate for column and row pins in Stratix devices.
Table 4-103. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12] Pins in Flip-Chip Packages I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential HSTL LVDS (1) LVPECL (1) PCML (1) HyperTransport technology (1)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
422 422 422 422 422 300 300 400 400 400 400 400 400 400 400 400 400 422 422 422 422 422 300 400 645 645 300 500 422 422 422 422 422 250 250 350 350 350 350 350 350 350 350 350 350 422 422 422 422 422 250 350 645 645 275 500 390 390 390 390 390 200 200 300 300 300 300 300 300 300 300 300 300 390 390 390 390 390 200 300 622 622 275 450 390 390 390 390 390 200 200 300 300 300 300 300 300 300 300 300 300 390 390 390 390 390 200 300 622 622 275 450
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Altera Corporation November 2003
4-69
Timing Model
Stratix Device Handbook, Volume 1
Table 4-104. Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins & FPLL[10..7]CLK Pins in Flip-Chip Packages I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential HSTL LVDS (1) LVPECL (1) PCML (1) HyperTransport technology (1)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
422 422 422 422 422 300 300 400 400 400 400 400 400 400 400 400 400 422 422 422 422 422 300 400 717 717 400 717 422 422 422 422 422 250 250 350 350 350 350 350 350 350 350 350 350 422 422 422 422 422 250 350 717 717 375 717 390 390 390 390 390 200 200 300 300 300 300 300 300 300 300 300 300 390 390 390 390 390 200 300 640 640 350 640 390 390 390 390 390 200 200 300 300 300 300 300 300 300 300 300 300 390 390 390 390 390 200 300 640 640 350 640
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
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Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Table 4-105. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in Flip-Chip Packages I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential HSTL LVDS (1) LVPECL (1) PCML (1) HyperTransport technology (1)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
422 422 422 422 422 300 300 400 400 400 400 400 400 400 400 400 400 422 422 422 422 422 300 400 645 645 300 645 422 422 422 422 422 250 250 350 350 350 350 350 350 350 350 350 350 422 422 422 422 422 250 350 645 645 275 645 390 390 390 390 390 200 200 300 300 300 300 300 300 300 300 300 300 390 390 390 390 390 200 300 640 640 275 640 390 390 390 390 390 200 200 300 300 300 300 300 300 300 300 300 300 390 390 390 390 390 200 300 640 640 275 640
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Altera Corporation November 2003
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Timing Model
Stratix Device Handbook, Volume 1
Table 4-106. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12] Pins in Wire-Bond Packages Note (2) I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential HSTL LVDS (1) LVPECL (1) PCML (1) HyperTransport technology (1)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
422 422 422 422 422 250 250 300 300 300 300 300 300 300 300 300 300 422 422 422 422 422 250 300 422 422 215 422 422 422 422 422 422 250 250 300 300 300 300 300 300 300 300 300 300 422 422 422 422 422 250 300 422 422 215 422 390 390 390 390 390 200 200 250 250 250 250 250 250 180 180 180 180 390 390 390 390 390 180 180 400 400 200 400 390 390 390 390 390 200 200 250 250 250 250 250 250 180 180 180 180 390 390 390 390 390 180 180 400 400 200 400
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
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Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Table 4-107. Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins & FPLL[10..7]CLK Pins in Wire-Bond Packages Note (2) I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential HSTL LVDS (1) LVPECL (1) PCML (1) HyperTransport technology (1)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
422 422 422 422 422 250 250 350 350 350 350 350 350 350 350 350 350 422 422 422 422 422 250 350 717 717 375 717 422 422 422 422 422 250 250 350 350 350 350 350 350 350 350 350 350 422 422 422 422 422 250 350 717 717 375 717 390 390 390 390 390 200 200 300 300 300 300 300 300 300 300 300 300 390 390 390 390 390 200 300 640 640 350 640 390 390 390 390 390 200 200 300 300 300 300 300 300 300 300 300 300 390 390 390 390 390 200 300 640 640 350 640
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Altera Corporation November 2003
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Timing Model
Stratix Device Handbook, Volume 1
Table 4-108. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in Wire-Bond Packages Note (2) I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential HSTL LVDS (1) LVPECL (1) PCML (1) HyperTransport technology (1)
(1) (2)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
422 422 422 422 422 250 250 350 350 350 350 350 350 350 350 350 350 422 422 422 422 422 250 350 645 645 275 500 422 422 422 422 422 250 250 350 350 350 350 350 350 350 350 350 350 422 422 422 422 422 250 350 645 645 275 500 390 390 390 390 390 200 200 300 300 300 300 300 300 300 300 300 300 390 390 390 390 390 200 300 622 622 275 450 390 390 390 390 390 200 200 300 300 300 300 300 300 300 300 300 300 390 390 390 390 390 200 300 622 622 275 450
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Notes to Tables 4-103 through 4-108:
These parameters are only available on row I/O pins. The -5 speed grade is not available in wire-bond packages.
4-74
Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Tables 4-109 through 4-112 show the maximum output clock rate for column and row pins in Stratix devices.
Table 4-109. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins in Flip-Chip Packages I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential HSTL Differential SSTL-2 (1) LVDS (2) LVPECL (2) PCML (2) HyperTransport technology (2)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
350 350 250 225 350 200 200 167 167 200 200 150 150 250 225 250 225 350 350 350 350 350 200 225 200 500 500 350 350 300 300 250 200 300 167 167 150 150 200 200 133 133 225 200 225 200 300 300 300 300 300 200 200 200 500 500 350 350 250 300 250 200 250 125 125 133 133 167 167 133 133 200 200 200 200 250 250 250 250 250 200 200 167 500 500 350 350 250 300 250 200 250 125 125 133 133 167 167 133 133 200 200 200 200 250 250 250 250 250 200 200 167 500 500 350 350
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Altera Corporation November 2003
4-75
Timing Model
Stratix Device Handbook, Volume 1
Table 4-110. Stratix Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2, 3, 4] Pins in Flip-Chip Packages I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II HSTL class I HSTL class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential HSTL LVDS (2) LVPECL (2) PCML (2) HyperTransport technology (2)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
400 400 400 350 400 200 200 167 167 150 150 150 150 250 225 250 225 400 400 400 300 225 717 717 420 420 350 350 350 300 350 167 167 150 150 133 133 133 133 225 225 225 225 350 350 350 250 225 717 717 420 420 300 300 300 300 300 125 125 133 133 133 133 133 133 200 200 200 200 300 300 300 200 200 500 500 420 420 300 300 300 300 300 125 125 133 133 133 133 133 133 200 200 200 200 300 300 300 200 200 500 500 420 420
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
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Altera Corporation November 2003
DC & Switching Characteristics
Timing Model
Table 4-111. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins in Wire-Bond Packages Note (3) I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II HSTL class I HSTL class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential HSTL Differential SSTL-2 (1) LVDS (2) LVPECL (2) PCML (2) HyperTransport technology (2)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
175 175 175 175 175 125 125 110 133 166 133 110 110 167 167 167 167 175 175 175 125 167 110 311 311 250 311 175 175 175 175 175 125 125 110 133 166 133 110 110 167 167 167 167 175 175 175 125 167 110 311 311 250 311 150 150 150 150 150 100 100 90 125 133 100 100 100 167 133 167 133 150 150 150 100 133 100 275 275 200 275 150 150 150 150 150 100 100 90 125 133 100 100 100 167 133 167 133 150 150 150 100 133 100 275 275 200 275
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Altera Corporation November 2003
4-77
Timing Model
Stratix Device Handbook, Volume 1
Table 4-112. Stratix Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2, 3, 4] Pins in Wire-Bond Packages Note (3) I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential HSTL LVDS (2) LVPECL (1) PCML (1) HyperTransport technology (1)
(1) (2) (3)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
200 200 200 200 200 125 125 110 150 90 110 110 110 225 200 225 200 200 200 200 200 200 125 200 400 311 400 420 200 200 200 200 200 125 125 110 150 90 110 110 110 225 200 225 200 200 200 200 200 200 125 200 400 311 400 420 175 175 175 175 175 100 100 90 133 80 100 100 100 200 167 200 167 175 175 175 175 175 100 167 311 270 311 400 175 175 175 175 175 100 100 90 133 80 100 100 100 200 167 200 167 175 175 175 175 175 100 167 311 270 311 400
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Notes to Tables 4-109 through 4-112:
Differential SSTL-2 outputs are only available on column I/O pins. These parameters are only available on row I/O pins. The -5 speed grade is not available in wire-bond packages.
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Altera Corporation November 2003
DC & Switching Characteristics
High-Speed I/O Specification
High-Speed I/O Specification
Table 4-113 provides high-speed timing specifications definitions.
Table 4-113. High-Speed Timing Specifications & Terminology High-Speed Timing Specification
tC fHSCLK tRISE tFALL Timing unit interval (TUI)
Terminology
High-speed receiver/transmitter input and output clock period. High-speed receiver/transmitter input and output clock frequency. Low-to-high transmission time. High-to-low transmission time. The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency x Multiplication Factor) = tC/w). Maximum LVDS data transfer rate (fHSDR = 1/TUI). The timing difference between the fastest and slowest output edges, including tCO variation and clock skew. The clock is included in the TCCS measurement. The period of time during which the data must be valid in order for you to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window. SW = tSW (max) - tSW (min). Peak-to-peak input jitter on high-speed PLLs. Peak-to-peak output jitter on high-speed PLLs. Duty cycle on high-speed transmitter output clock. Lock time for high-speed transmitter and receiver PLLs.
fHSDR Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter (peak-to-peak) Output jitter (peak-to-peak) tDUTY tLOCK
Altera Corporation November 2003
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High-Speed I/O Specification
Stratix Device Handbook, Volume 1
Tables 4-114 and 4-115 show the high-speed I/O timing for Stratix devices.
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Altera Corporation November 2003
Altera Corporation November 2003 4-81
DC & Switching Characteristics
Table 4-114. High-Speed I/O Specifications for Flip-Chip Packages (Part 1 of 3) -5 Speed Grade Symbol
fHSCLK (Clock frequency) (LVDS, LVPECL, HyperTransport technology)
Notes (1), (2) -7 Speed Grade Min
30 37.5 42.9 75 150 300
-6 Speed Grade Min
30 37.5 42.9 75 150 300
-8 Speed Grade Unit Min
30 37.5 42.9 75 150 300
Conditions Min
W = 10 W=8 W=7 W=4 W=2 W=1 (LVDS and LVPECL only) 30 37.5 42.9 75 150 300
Typ
Max
84 105 120 210 420 717
Typ
Max
84 105 120 210 420 717
Typ
Max
62.4 78 89.14 156 231 462
Typ
Max
46.2 57.75 66.00 115.5 231 462 MHz MHz MHz MHz MHz MHz
fHSDR Device operation (LVDS, LVPECL, HyperTransport technology)
J = 10 J=8 J=7 J=4 J=2 J = 1 (LVDS and LVPECL only)
300 300 300 300 100 100
840 840 840 840 624 462
300 300 300 300 100 100
840 840 840 840 624 462
300 300 300 300 100 100
624 624 624 624 462 462
300 300 300 300 100 100
462 462 462 462 462 462
Mbps Mbps Mbps Mbps Mbps Mbps
fHSCLK (Clock frequency) (PCML)
W = 10 W=8 W=7 W=4 W=2 W=1
30 37.5 42.9 75 50 100
40 50 57.14 100 200 250
30 37.5 42.9 75 50 100
40 50 57.14 100 200 250
30 37.5 42.9 75 50 100
31.1 38.87 44.43 77.75 150 200
30 37.5 42.9 75 50 100
31.1 38.87 44.43 77.75 150 200
MHz MHz MHz MHz MHz MHz High-Speed I/O Specification
4-82 Altera Corporation November 2003
High-Speed I/O Specification
Table 4-114. High-Speed I/O Specifications for Flip-Chip Packages (Part 2 of 3) -5 Speed Grade Symbol
fHSDR Device operation (PCML)
Notes (1), (2) -7 Speed Grade Min
300 300 300 300 100 100
-6 Speed Grade Min
300 300 300 300 100 100
-8 Speed Grade Unit Min
300 300 300 300 100 100
Conditions Min
J = 10 J=8 J=7 J=4 J=2 J=1 300 300 300 300 100 100
Typ
Max
400 400 400 400 400 250 100 750 900 1,500 500 440
Typ
Max
400 400 400 400 400 250 100 750 900 1,500 500 440
Typ
Max
311 311 311 311 300 200 150 800 1,200 1,700 550 500
Typ
Max
311 311 311 311 300 200 150 800 1,200 1,700 550 500 Mbps Mbps Mbps Mbps Mbps Mbps ps ps ps ps ps ps
TCCS SW
All PCML (J = 4, 7, 8, 10) PCML (J = 2) PCML (J = 1) LVDS and LVPECL (J = 1) LVDS, LVPECL, HyperTransport technology (J = 2 through 10)
Stratix Device Handbook, Volume 1
Input jitter tolerance (peak-to-peak) Output jitter (peak-to-peak)
All
250
250
250
250
ps
All
160
160
200
200
ps
Altera Corporation November 2003 4-83
DC & Switching Characteristics
Table 4-114. High-Speed I/O Specifications for Flip-Chip Packages (Part 3 of 3) -5 Speed Grade Symbol
Output tRISE
Notes (1), (2) -7 Speed Grade Min
80 120 100 80 80 110 100 110 47.5 45
-6 Speed Grade Min
80 110 90 80 80 110 90 105 47.5 45
-8 Speed Grade Unit Min
80 120 100 80 80 110 100 110 47.5 45
Conditions Min
LVDS HyperTransport technology LVPECL PCML 80 110 90 80 80 110 90 105 47.5 45
Typ
110 170 130 110 110 170 130 140 50 50
Max
120 200 150 135 120 200 160 175 52.5 55
Typ
110 170 130 110 110 170 130 140 50 50
Max
120 200 150 135 120 200 160 175 52.5 55
Typ
110 170 135 110 110 170 135 145 50 50
Max
120 200 150 135 120 200 160 175 52.5 55
Typ
110 170 135 110 110 170 135 145 50 50
Max
120 200 150 135 120 200 160 175 52.5 55 ps ps ps ps ps ps ps ps % %
Output tFALL
LVDS HyperTransport technology LVPECL PCML
tDUTY
LVDS (J = 2 through 10) LVDS (J =1) and LVPECL, PCML, HyperTransport technology
tLOCK
(1) (2)
All
100
100
100
100
s High-Speed I/O Specification
Notes for Table 4-114:
When J = 4, 7, 8, and 10, the SERDES block is used. When J = 2 or J = 1, the SERDES is bypassed.
High-Speed I/O Specification
Stratix Device Handbook, Volume 1
Table 4-115. High-Speed I/O Specifications for Wire-Bond Packages (Part 1 of 2) -6 Speed Grade Symbol
fHSCLK (clock frequency) (LVDS,LVPECL, HyperTransport technology)
-7 Speed Grade Min
30 37.5 42.9 75 50 100 300 300 300 300 100 100
-8 Speed Grade Unit Min
30 37.5 42.9 75 50 100 300 300 300 300 100 100
Conditions Min
W = 10 W=8 W=7 W=4 W=2 W = 1 (LVDS and LVPECL only) 30 37.5 42.9 75 50 100 300 300 300 300 100 100 30 37.5 42.9 75 50 100 300 300 300 300 100 100
Typ
Max
62.4 78 89.14 156 231 311 624 624 624 624 462 311 31.1 38.87 44.43 77.75 150 200 311 311 311 311 300 200 200
Typ
Max
46 57.5 65.71 115 230 311 460 460 460 460 462 270
Typ
Max
46 57.5 65.71 115 230 311 460 460 460 460 462 270 MHz MHz MHz MHz MHz MHz Mbps Mbps Mbps Mbps Mbps Mbps MHz MHz MHz MHz
Device operation, fH S D R (LVDS,LVPECL, HyperTransport technology)
J = 10 J=8 J=7 J=4 J=2 J = 1 (LVDS and LVPECL only)
fH S C L K (clock frequency) (PCML)
W = 10 W=8 W=7 W=4 W=2 W=1
50 100
150 200
50 100
150 200
MHz MHz Mbps Mbps Mbps Mbps
Device operation, fH S D R (PCML)
J = 10 J=8 J=7 J=4 J=2 J=1
100 100
155 155 200
100 100
155 155 200
Mbps Mbps ps
TCCS
All
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Altera Corporation November 2003
DC & Switching Characteristics
High-Speed I/O Specification
Table 4-115. High-Speed I/O Specifications for Wire-Bond Packages (Part 2 of 2) -6 Speed Grade Symbol
SW
-7 Speed Grade Min Typ Max
800 1,200 1,700 550
-8 Speed Grade Unit Min Typ Max
800 1,200 1,700 550 ps ps ps ps
Conditions Min
PCML (J = 4, 7, 8, 10) only PCML (J = 2) only PCML (J = 1) only LVDS and LVPECL (J = 1) only LVDS, LVPECL, HyperTransport technology (J = 2..10) only
Typ
Max
800 1,200 1,700 550
500
500
500
ps
Input jitter tolerance (peakto-peak) Output jitter (peak-to-peak) Output tR I S E
All
250
250
250
ps
All LVDS HyperTransport technology LVPECL PCML 80 120 100 80 80 110 100 110 47.5 45 110 170 135 110 110 170 135 145 50 50
200 120 200 150 135 120 200 160 175 52.5 55 80 120 100 80 80 110 100 110 47.5 45 110 170 135 110 110 170 135 145 50 50
200 120 200 150 135 120 200 160 175 52.5 55 80 120 100 80 80 110 100 110 47.5 45 110 170 135 110 110 170 135 145 50 50
200 120 200 150 135 120 200 160 175 52.5 55
ps ps ps ps ps ps ps ps ps % %
Output tFA L L
LVDS HyperTransport LVPECL PCML
tD U T Y
LVDS (J =2..10) only LVDS (J =1) and LVPECL, PCML, HyperTransport technology
tL O C K
All
100
100
100
s
Altera Corporation November 2003
4-85
PLL Specifications
Stratix Device Handbook, Volume 1
PLL Specifications
Tables 4-116 through 4-118 describe the Stratix and Stratix GX device enhanced PLL specifications.
Table 4-116. Enhanced PLL Specifications for -5 Speed Grades Symbol
fIN fINDUTY fEINDUTY tINJITTER tEINJITTER tFCOMP fOUT fOUT_EXT tOUTDUTY tJITTER tCONFIG5,6 tCONFIG11,12 tSCANCLK tDLOCK
Parameter
Input clock frequency Input clock duty cycle External feedback clock input duty cycle Input clock period jitter External feedback clock period jitter External feedback clock compensation time (3) Output frequency for internal global or regional clock (4) Output frequency for external clock (2) Duty cycle for external clock output (when set to 50%) Period jitter for external clock output (5) Time required to reconfigure the scan chains for PLLs 5 and 6 Time required to reconfigure the scan chains for PLLs 11 and 12 scanclk frequency (4) Time required to lock dynamically (after switchover or reconfiguring any nonpost-scale counters/delays) (6) Time required to lock from end of device configuration PLL internal VCO operating range Clock skew between two external clock outputs driven by the same counter Clock skew between two external clock outputs driven by the different counters with the same settings Spread spectrum modulation frequency Percentage spread for spread spectrum frequency (9)
Min
3 (1) 40 40
Typ
Max
684 60 60 200 (2) 200 (2) 6
Unit
MHz % % ps ps ns MHz MHz % ps or mUI
9.4 0.3 45
420 526 55 100 ps for >200 MHz outclk 20 mUI for <200 MHz outclk 289/fSCANCLK 193/fSCANCLK 22 100
MHz s
tLOCK fVCO tLSKEW tSKEW
10 300 50 75
400 800 (7)
s MHz ps ps
fSS % spread
30 0.4 0.5
150 0.6
kHz %
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Altera Corporation November 2003
DC & Switching Characteristics
PLL Specifications
Table 4-117. Enhanced PLL Specifications for -6 Speed Grades Symbol
fIN fINDUTY fEINDUTY tINJITTER tEINJITTER tFCOMP fOUT fOUT_EXT tOUTDUTY tJITTER tCONFIG5,6 tCONFIG11,12 tSCANCLK tDLOCK
Parameter
Input clock frequency Input clock duty cycle External feedback clock input duty cycle Input clock period jitter External feedback clock period jitter External feedback clock compensation time (3) Output frequency for internal global or regional clock (4) Output frequency for external clock (2) Duty cycle for external clock output (when set to 50%) Period jitter for external clock output (5) Time required to reconfigure the scan chains for PLLs 5 and 6 Time required to reconfigure the scan chains for PLLs 11 and 12 scanclk frequency (4) Time required to lock dynamically (after switchover or reconfiguring any nonpost-scale counters/delays) (6) Time required to lock from end of device configuration PLL internal VCO operating range Clock skew between two external clock outputs driven by the same counter Clock skew between two external clock outputs driven by the different counters with the same settings Spread spectrum modulation frequency Percentage spread for spread spectrum frequency (9)
Min Typ
3 (1) 40 40
Max
650 60 60 200 (2) 200 (2) 6
Unit
MHz % % MHz MHz ns MHz MHz % ps or mUI
0.3 0.3 45
420 500 55 100 ps for >200 MHz outclk 20 mUI for <200 MHz outclk 289/fSCANCLK 193/fSCANCLK 22
MHz s
(8)
100
tLOCK fVCO tLSKEW tSKEW
10 300 50 75
400 800 (7)
s MHz ps ps
fSS % spread
30 0.4 0.5
150 0.6
kHz %
Altera Corporation November 2003
4-87
PLL Specifications
Stratix Device Handbook, Volume 1
Table 4-118. Enhanced PLL Specifications for -7 & -8 Speed Grade (Part 1 of 2) Symbol
fIN fINDUTY fEINDUTY tINJITTER tEINJITTER tFCOMP fOUT fOUT_EXT tOUTDUTY tJITTER tCONFIG5,6 tCONFIG11,12 tSCANCLK tDLOCK
Parameter
Input clock frequency Input clock duty cycle External feedback clock input duty cycle Input clock period jitter External feedback clock period jitter External feedback clock compensation time (3) Output frequency for internal global or regional clock (4) Output frequency for external clock (2) Duty cycle for external clock output (when set to 50%) Period jitter for external clock output (5) Time required to reconfigure the scan chains for PLLs 5 and 6 Time required to reconfigure the scan chains for PLLs 11 and 12 scanclk frequency (4) Time required to lock dynamically (after switchover or reconfiguring any nonpost-scale counters/delays) (6) Time required to lock from end of device configuration PLL internal VCO operating range Clock skew between two external clock outputs driven by the same counter Clock skew between two external clock outputs driven by the different counters with the same settings Spread spectrum modulation frequency
Min
3 (1) 40 40
Typ
Max
565 60 60 200 (2) 200 (2) 6
Unit
MHz % % MHz MHz ns MHz MHz % ps or mUI
0.3 0.3 45
420 434 55 100 ps for >200 MHz outclk 20 mUI for <200 MHz outclk 289/fSCANCLK 193/fSCANCLK 22
MHz s
(8)
100
tLOCK fVCO tLSKEW tSKEW
10 300 50 75
400 600 (7)
s MHz ps ps
fSS
30
150
kHz
4-88
Altera Corporation November 2003
DC & Switching Characteristics
PLL Specifications
Table 4-118. Enhanced PLL Specifications for -7 & -8 Speed Grade (Part 2 of 2) Symbol
% spread
Parameter
Percentage spread for spread spectrum frequency (9)
Min
0.5
Typ
Max
0.6
Unit
%
Notes to Table 4-116 and 4-118:
(1) (2) (3) (4) (5) (6) (7) (8) (9) The minimum input clock frequency to the PFD (fIN/N) must be at least 3 Mhz for Stratix and Stratix GX device enhanced PLLs. Refer to "Maximum Input & Output Clock Rates" on page 4-69. tFCOMP can also equal 50% of the input clock period multiplied by the pre-scale divider n (whichever is less). This parameter is timing analyzed by the Quartus II software because the scanclk and scandata ports can be driven by the logic array. Actual jitter performance may vary based on the system configuration. Total required time to reconfigure and lock is equal to tDLOCK + tCONFIG. If only post-scale counters and delays are changed, then tDLOCK is equal to 0. The VCO range is limited to 500 to 800 MHz when the spread spectrum feature is selected. Lock time is a function of PLL configuration and may be significantly faster depending on bandwidth settings or feedback counter change increment. Exact, user-controllable value depends on the PLL settings.
Tables 4-119 and 4-120 describe the Stratix and Stratix GX device fast PLL specifications.
Table 4-119. Fast PLL Specifications for -5 & -6 Speed Grades Symbol
fIN
Note (1) Max
717 1,000/m 1,000/m 420 717 1,000 60 200
Parameter
CLKIN frequency (for m = 1) (2), (3) CLKIN frequency (for m = 2 to 19) CLKIN frequency (for m = 20 to 32)
Min
300 300/ m 15 9.4 9.375 300 40
Unit
MHz MHz MHz MHz MHz MHz % ps % ps ps or mUI s
fOUT fOUT_EXT fVCO tINDUTY tINJITTER tDUTY tJITTER
Output frequency for internal global or regional clock (4) Output frequency for external clock (3) VCO operating frequency CLKIN duty cycle Period jitter for CLKIN pin Duty cycle for DFFIO 1x CLKOUT pin (5) Period jitter for DIFFIO clock out (5) Period jitter for internal global or regional clock
45
55 80 100 ps for >200 MHz outclk 20 mUI for <200 MHz outclk
tLOCK
Time required for PLL to acquire lock
10
100
Altera Corporation November 2003
4-89
PLL Specifications
Stratix Device Handbook, Volume 1
Table 4-119. Fast PLL Specifications for -5 & -6 Speed Grades Symbol
m l0, l1, g0
Note (1) Max
32 32
Parameter
Multiplication factors for m counter (5) Multiplication factors for l0, l1, and g0 counter (6), (7)
Min
1 1
Unit
Integer Integer
Table 4-120. Fast PLL Specifications for -7 & -8 Speed Grades Symbol
fIN
Note (1) Max
640 700/m 700/m 420 640 700 60 200
Parameter
CLKIN frequency (for m = 1) (2), (3) CLKIN frequency (for m = 2 to 19) CLKIN frequency (for m = 20 to 32)
Min
300 300/ m 15 9.375 9.4 300 40
Unit
MHz MHz MHz MHz MHz MHz % ps % ps ps or mUI s Integer Integer
fOUT fOUT_EXT fVCO tINDUTY tINJITTER tDUTY tJITTER
Output frequency for internal global or regional clock (4) Output frequency for external clock (3) VCO operating frequency CLKIN duty cycle Period jitter for CLKIN pin Duty cycle for DFFIO 1x CLKOUT pin (5) Period jitter for DIFFIO clock out (5) Period jitter for internal global or regional clock
45
55 80 100 ps for >200 MHz outclk 20 mUI for <200 MHz outclk
tLOCK m l0, l1, g0
Time required for PLL to acquire lock Multiplication factors for m counter (6) Multiplication factors for l0, l1, and g0 counter (6), (7)
10 1 1
100 32 32
Notes to Table 4-119 and 4-120:
(1) (2) (3) (4) PLLs 3, 4, 9, and 10 on Stratix GX devices are only used for the HSSI block. These PLLs are not available for generalpurpose programming. See "Maximum Input & Output Clock Rates" on page 4-69. PLLs 7, 8, 9, and 10 in the EP1S80 device support up to 717-MHz input and output. When using the SERDES, high-speed differential I/O mode supports a maximum output frequency of 210 MHz to the global or regional clocks (i.e., the maximum data rate 840 Mbps divided by the smallest SERDES J factor of 4). This parameter is for high-speed differential I/O mode only. These counters have a maximum of 32 if programmed for 50/50 duty cycle. Otherwise, they have a maximum of 16. High-speed differential I/O mode supports W = 1 to 16 and J = 4, 7, 8, or 10.
(5) (6) (7)
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Altera Corporation November 2003
5. Reference & Ordering Information
S51005-2.0
Software
Stratix devices are supported by the Altera Quartus II(R) design software, which provides a comprehensive environment for system-on-aprogrammable-chip (SOPC) design. The Quartus II software includes HDL and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis, SignalTap(R) II logic analyzer, and device configuration. See the Design Software Selector Guide for more details on the Quartus II software features. The Quartus II software supports the Windows XP/2000/NT/98, Sun Solaris, Linux Red Hat v7.1 and HP-UX operating systems. It also supports seamless integration with industry-leading EDA tools through the NativeLink(R) interface.
Device Pin-Outs
Printed Device pin-outs for Stratix devices can be found in this handbook in Section II, PCB Layout Guidelines and are also available on the Altera web site at (www.altera.com). Figure 5-1 describes the ordering codes for Stratix devices. For more information on a specific package, refer to the Chapter 8, Package Information
for Stratix Devices.
Ordering Information
Altera Corporation July 2003
5-1
Ordering Information
Stratix Device Handbook, Volume 1
Figure 5-1. Stratix Device Packaging Ordering Information
EP1S Family Signature EP1S: Stratix 80 F 1508 C 7 ES Optional Suffix Indicates specific device options or shipment method. ES: Engineering sample
Device Type 10 20 25 30 40 60 80 Speed Grade 5, 6, or 7, with 5 being the fastest
Operating Temperature C: Commercial temperature (tJ = 0 C to 85 C) I: Industrial temperature (tJ = -40 C to 100 C) Package Type Pin Count Number of pins for a particular BGA or FineLine BGA package
B: Ball-grid array (BGA) F: FineLine BGA
5-2
Altera Corporation July 2003

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