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CMOS MT9126 Quad ADPCM Transcoder Data Sheet
Features
* * Full duplex transcoder with four encode channels and four decode channels 32 kb/s, 24 kb/s and 16 kb/s ADPCM coding complying with ITU-T (previously CCITT) G.726 (without 40 kb/s), and ANSI T1.303-1989 Low power operation, 25 mW typical Asynchronous 4.096 MHz master clock operation SSI and ST-BUS interface options Transparent PCM bypass Transparent ADPCM bypass Linear PCM code No microprocessor control required Simple interface to Codec devices Pin selectable -Law or A-Law operation Pin selectable ITU-T or signed magnitude PCM coding Single 5 volt power supply
ISSUE 3
April 2002
Ordering Information MT9126AE 28 Pin Plastic DIP MT9126AS 28 Pin SOIC -40 C to +85 C
* * * * * * * * * * *
Description
The Quad ADPCM Transcoder is a low power, CMOS device capable of four encode and four decode functions per frame. Four 64 kbit/s PCM octets are compressed into four 32, 24 or 16 kbit/s ADPCM words, and four 32, 24 or 16 kbit/s ADPCM words are expanded into four 64 kbit/s PCM octets. The 32, 24 and 16 kbit/s ADPCM transcoding algorithms utilized conform to ITU-T Recommendation G.726 (excluding 40 kbit/s), and ANSI T1.303 - 1989. Switching, on-the-fly, between 32 kbit/s and 24 kbit/s ADPCM, is possible by controlling the appropriate mode select (MS1 - MS6) control pins. All optional functions of the device are pin selectable allowing a simple interface to industry standard codecs, digital phone devices and Layer 1 transceivers. Linear coded PCM is provided to facilitate external DSP functions .
Applications
* * * Pair gain Voice mail systems Wireless telephony systems
ADPCMi ADPCMo
ADPCM I/O
Full Duplex Quad Transcoder
PCM I/O
PCMo1 PCMi1
PCMo2 PCMi2 ENB1 ENB2/F0od BCLK F0i MCLK C2o EN1 EN2 Timing Control Decode
VDD VSS PWRDN IC
MS1 MS2 MS3 A/ FORMAT MS4 MS5 MS6 LINEAR SEL
Figure 1 - Functional Block Diagram
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MT9126
Data Sheet
EN1 MCLK F0i C2o BCLK PCMo1 PCMi1 VSS LINEAR ENB2/F0od ENB1 PCMo2 PCMi2 SEL
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
EN2 MS6 MS5 MS4 ADPCMo ADPCMi VDD MS3 MS2 MS1 IC PWRDN FORMAT A/
Figure 2 - Pin Connections
Pin Description
Pin # 1 Name EN1 Description Enable Strobe 1 (Output). This 8 bit wide, active high strobe is active during the B1 PCM channel in ST-BUS mode. Becomes a single bit, high true pulse when LINEAR=1. In SSI mode this output is high impedance. Master Clock (input). This is a 4.096 MHz (minimum) input clock utilized by the transcoder function; it must be supplied in both ST-BUS and SSI modes of operation. In ST-BUS mode the C4 ST-BUS clock is applied to this pin. This synchronous clock is also used to control the data I/O flow on the PCM and ADPCM input/output pins according to ST-BUS requirements. In SSI mode this master clock input is derived from an external source and may be asynchronous with respect to the 8 kHz frame. MCLK rates greater than 4.096 MHz are acceptable in this mode since the data I/O rate is governed by BCLK. 3 4 F0i C2o Frame Pulse (Input). Frame synchronization pulse input for ST-BUS operation. SSI operation is enabled by connecting this pin to VSS. 2.048 MHz Clock (Output). This ST-BUS mode bit clock output is the MCLK (C4) input divided by two, inverted, and synchronized to F0i. This output is high-impedance during SSI operation. Bit Clock (Input). 128 kHz to 4096 kHz bit clock input for both PCM and ADPCM ports; used in SSI mode only. The falling edge of this clock latches data into ADPCMi, PCMi1 and PCMi2. The rising edge clocks data out on ADPCMo, PCMo1 and PCMo2. This input must be tied to VSS for ST-BUS operation. Serial PCM Stream 1 (Output). 128 kbit/s to 4096 kbit/s serial companded/linear PCM output stream. Data are clocked out by rising edge of BCLK in SSI mode. Clocked out by MCLK divided by two in ST-BUS mode. See Figure 14. Serial PCM Stream 1 (Input). 128 kbit/s to 4096 kbit/s serial companded/linear PCM input stream. Data are clocked in on falling edge of BCLK in SSI mode. Clocked in at the 3/4 bit position of MCLK in ST-BUS mode. See Figure 14. Digital Ground. Nominally 0 volts. Linear PCM Select (Input). When tied to VDD the PCM I/O ports (PCM1,PCM2) are 16bit linear PCM. Linear PCM operates only at a bit rate of 2048 kbit/s. Companded PCM is selected when this pin is tied to VSS. See Figures 5 & 8.
2
MCLK
5
BCLK
6
PCMo1
7
PCMi1
8 9
VSS LINEAR
8-90
Data Sheet
Pin Description
Pin # 10 Name ENB2/F0od Description
MT9126
PCM B-Channel Enable Strobe 2 (Input) / Delayed Frame Pulse (Output). SSI operation: ENB2 (Input). An 8-bit wide enable strobe input defining B2 channel (AD)PCM data. A valid 8-bit strobe must be present at this input for SSI operation. See Figures 4 & 6. ST-BUS operation: F0od (Output). This pin is a delayed frame strobe output. When LINEAR=0, this becomes a delayed frame pulse output occurring 64 C4 clock cycles after F0i and when LINEAR = 1 at 128 C4 clock cycles after F0i . See Figures 7, 8, 9 & 14.
11
ENB1
PCM B-Channel Enable Strobe 1 (Input). SSI operation: An 8-bit wide enable strobe input defining B1 channel (AD)PCM data. A valid 8-bit strobe must be present at this input for SSI operation. ST-BUS operation: When tied to V SS transparent bypass of the ST-BUS D- and C- channels is enabled. When tied to V DD the ST-BUS D-channel and C-channel output timeslots are forced to a high-impedance state.
12
PCMo2
Serial PCM Stream 2 (Output). 128 kbit/s to 4096 kbit/s serial companded/linear PCM output stream. Clocked out by rising edge of BCLK in SSI mode. Clocked out by MCLK divided by two in ST-BUS mode. See Figure 14. Serial PCM Stream 2 (Input). 128 kbit/s to 4096 kbit/s serial companded/linear PCM input stream. Data bits are clocked in on falling edge of BCLK in SSI mode. Clocked in at the 3/4 bit position of MCLK in ST-BUS mode. See Figure 14. SELECT (Input). PCM bypass mode: When SEL=0 the PCM1 port is selected for PCM bypass operation and when SEL=1 the PCM2 port is selected for PCM bypass operation. See Figures 6 & 9. 16 kbit/s transcoding mode: SSI Operation - in 16 kbit/s transcoding mode, the ADPCM words are assigned to the I/O timeslot defined by ENB2 when SEL=1 and by ENB1 when SEL=0. See Figure 4. ST-BUS operation- in 16 kbit/s transcoding mode, the ADPCM words are assigned to the B2 timeslot when SEL=1 and to the B1 timeslot when SEL=0. See Figure 9.
13
PCMi2
14
SEL
15
A/
A-Law/-Law Select (Input). This input pin selects -Law companding when set to logic 0, and A-Law companding when set to logic 1. This control is for all channels .This input is ignored in Linear mode during which it may be tied to VSS or VDD. FORMAT Select (Input). Selects ITU-T PCM coding when high and Sign-Magnitude PCM coding when low. This control is for all channels.This input is ignored in Linear mode during which it may be tied to VSS or VDD. Power-down (Input). An active low reset forcing the device into a low power mode where all outputs are high-impedance and device operation is halted. Internal Connection (Input). Tie to VSS for normal operation.
16
FORMAT
17 18
PWRDN IC
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Pin Description
Pin # 19 20 21 Name MS1 MS2 MS3 Description
Data Sheet
Mode Selects 1, 2 and 3 (Inputs). Mode selects for all four encoders. MS3 MS2 MS1 MODE 0 0 0 32 kbit/s ADPCM 0 0 1 24 kbit/s ADPCM 0 1 0 16 kbit/s ADPCM in EN1/ENB1 when SEL=0 in EN2/ENB2 when SEL=1 0 1 1 ADPCM Bypass for 32 kbit/s and 24 kbit/s 1 0 0 ADPCM Bypass for 16 kbit/s 1 0 1 PCM Bypass (64 kbit/s) to PCM1 if SEL=0, PCM2 if SEL=1 1 1 0 Algorithm reset (ITU-T optional reset) 1 1 1 ADPCMo disable Positive Power Supply. Nominally 5 volts +/-10% Serial ADPCM Stream ( Input). 128 kbit/s to 4096 kbit/s serial ADPCM word input stream. Data bits are clocked in on falling edge of BCLK in SSI mode and clocked in on the 3/4 bit edge of MCLK in ST-BUS mode. Serial ADPCM Stream (Output). 128 kbit/s to 4096 kbit/s serial ADPCM word output stream. Data bits are clocked out by rising edge of BCLK in SSI mode and clocked out by MCLK divided by two in ST-BUS mode. Mode Selects 4, 5 and 6 (Inputs). Mode selects for all four decoders. MODE MS6 MS5 MS4 0 0 0 32 kbit/s ADPCM 0 0 1 24 kbit/s ADPCM 0 1 0 16 kbit/s ADPCM in EN1/ENB1 when SEL=0 in EN2/ENB2 when SEL=1 0 1 1 ADPCM Bypass for 32 kbit/s and 24 kbit/s 1 0 0 ADPCM Bypass for 16 kbit/s 1 0 1 PCM Bypass (64 kbit/s) to PCM1 if SEL=0, PCM2 if SEL=1 1 1 0 Algorithm reset (ITU-T optional reset) 1 1 1 PCMo1/2 disable Enable Strobe 2 (Output). This 8 bit wide, active high strobe is active during the B2 PCM channel in ST-BUS mode. Forced to high impedance when LINEAR=1.
22 23
VDD ADPCMi
24
ADPCMo
25 26 27
MS4 MS5 MS6
28
EN2
Notes: All unused inputs should be connected to logic low or high unless otherwise stated. All outputs should be left open circuit when not used. All inputs have TTL compatible logic levels except for MCLK which has CMOS compatible logic levels and PWRDN which has Schmitt trigger compatible logic levels. All outputs are CMOS with CMOS logic levels (See DC Electrical Characteristics).
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Data Sheet
Functional Description
The Quad-channel ADPCM Transcoder is a low power, CMOS device capable of four encode and four decode operations per frame. Four 64 kbit/s channels (PCM octets) are compressed into four 32, 24 or 16 kbit/s ADPCM channels (ADPCM words), and four 32, 24 or 16 kbit/s ADPCM channels (ADPCM words) are expanded into four 64 kbit/s PCM channels (PCM octets). The ADPCM transcoding algorithm utilized conforms to ITU-T recommendation G.726 (excluding 40 kb/s), and ANSI T1.303 - 1989. Switching on-the-fly between 32 and 24 kbit/s transcoding is possible by toggling the appropriate mode select pins (supports T1 robbed-bit signalling). All functions supported by the device are pin selectable. The four encode functions comprise a common group controlled via Mode Select pins MS1, MS2 and MS3. Similarily, the four decode functions form a second group commonly controlled via Mode Select pins MS4, MS5 and MS6. All other pin controls are common to the entire transcoder. The device requires 25 mWatts (MCLK= 4.096 MHz) typically for four channel transcode operation. A minimum master clock frequency of 4.096 MHz is required for the circuit to complete four encode channels and four decode channels per frame. For SSI operation a master clock frequency greater than 4.096 MHz and asynchronous, relative to the 8 kHz frame, is allowed. The PCM and ADPCM serial busses support both ST-BUS and Synchronous Serial Interface (SSI) operation. This allows serial data clock rates from 128 kHz to 4096 kHz, as well as compatibility with Mitel's standard Serial Telecom BUS (ST-BUS). For ST-BUS operation, on chip channel counters provide channel enable outputs as well as a 2048 kHz bit clock output which may be used by down-stream devices utilizing the SSI bus interface. Linear coded PCM is also supported. In this mode the encoders compress, four 14-bit, two's complement (S,S,S,12,...,1,0), uniform PCM channels into four 4, 3 or 2 bit ADPCM channels. Similarly, the decoder expands four 4, 3 or 2 bit ADPCM channels into four 16-bit, two's complement (S,14,...,1,0), uniform PCM channels. The data rate for both ST-BUS and SSI operation in this mode is 2048 kbit/s.
MT9126
Serial (AD)PCM Data I/O
Serial data transfer to/from the Quad ADPCM transcoder is provided through one ADPCM and two PCM ports (ADPCMi, ADPCMo, PCMi1, PCMo1, PCMi2, PCMo2). Data is transferred through these ports according to either ST-BUS or SSI requirements. The device determines the mode of operation by monitoring the signal applied to the F0i pin. When a valid ST-BUS frame pulse (244nSec low going pulse) is applied to the F0i pin the transcoder will assume ST-BUS operation. If F0i is tied continuously to VSS the transcoder will assume SSI operation. Pin functionality in each of these modes is described in the following sub-sections. ST-BUS Mode During ST-BUS operation the C2o, EN1, EN2 and F0od outputs become active and all serial timing is derived from the MCLK (C4) and F0i inputs while the BCLK input is tied to VSS. (See Figures 7, 8 & 9.) Basic Rate "D" and "C" Channels In ST-BUS mode, when ENB1 is brought low, transparent transport of the ST-BUS "Basic Rate Dand C-channels" is supported through the PCMi1 and PCMo1 pins. This allows a microprocessor controlled device, connected to the PCMi/o1 pins, to access the "D" and "C" channels of a transmission device connected to the ADPCMi/o pins. When ENB1 is brought high, the "D" and "C" channel outputs are tristated. Basic Rate "D" and "C" channels are not supported in LINEAR mode.(See Figure 7.) SSI Mode During SSI operation the BCLK, ENB1 and ENB2/ F0od inputs become active. The C2o, EN1, and EN2 outputs are forced to a high-impedance state except during LINEAR operation during which the EN1 output remains active. (See Figures 4, 5 & 6.) The SSI port is a serial data interface, including data input and data output pins, a variable rate bit clock input and two input strobes providing enables for data transfers. There are three SSI I/O ports on the Quad ADPCM; the PCMi/o1 PCM port, the PCMi/o2 PCM port, and the ADPCMi/o port. The two PCM ports may transport 8-bit companded PCM or 16-bit linear PCM. The alignment of the channels is determined by the two input strobe signals ENB1 and ENB2/F0od. The bit clock (BCLK) and input strobes (ENB1 and ENB2/F0od) are common for all
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three of the serial I/O ports. BCLK can be any frequency between 128 kHz and 4096 kHz synchronized to the input strobes. BCLK may be discontinuous outside of the strobe boundaries except when LINEAR=1. In LINEAR mode, BCLK must be 2048 kHz and continuous for 64 cycles after the ENB1 rising edge and for the duration of ENB2/ F0od. 16 kbit/s ADPCM Mode
Data Sheet
Mode Select Operation (MS1, MS2, MS3, MS4, MS5, MS6)
Mode Select pins MS1, MS2 and MS3 program different bit rate ADPCM coding, bypass, algorithmic reset and disable modes for all four encoder functions simultaneously. When 24 kbit/s ADPCM mode is selected bit 4 is unused while in 16 kb/s ADPCM mode all ADPCM channels are packed contiguously into one 8-bit octet. Mode Select pins MS4, MS5 and MS6 operate in the same manner for the four decode functions. The mode selects must be set up according to the timing constraints illustrated in Figures 16 and 17. 32 kbit/s ADPCM Mode In 32 kbit/s ADPCM mode, the 8-bit PCM octets of the B1, B2, B3 and B4 channels (PCMi1 and PCMi2) are compressed into four 4-bit ADPCM words on ADPCMo. Conversely, the 4-bit ADPCM words of the B1, B2, B3 and B4 channels from ADPCMi are expanded into four 8-bit PCM octets on PCMo1 and PCMo2. The 8-bit PCM octets (A-Law or -Law) are transferred most significant bit first starting with b7 and ending with b0. ADPCM words are transferred most significant bit first starting with I1 and ending with I4 (See Figures 4 & 7). Reference ITU-T G.726 for I-bit definitions. 24 kbit/s ADPCM Mode In 24 kbit/s mode PCM octets are transcoded into 3bit words rather than the 4-bit words utilized in 32 kbit/s ADPCM. This is useful in situations where lower bandwidth transmission is required. Dynamic operation of the mode select control pins will allow switching from 32 kbit/s mode to 24 kbit/s mode on a frame by frame basis. The 8 bit PCM octets (A-Law or -Law) are transferred most significant bit first starting with b7 and ending with b0. ADPCM words are transferred most significant bit first starting with I1 and ending with I3 (I4 becomes don't care). (See Figures 4 & 7.)
When SEL is set to 0, the 8-bit PCM octets of the B1, B2, B3 and B4 channels (PCMi1 and PCMi2) are compressed into four 2-bit ADPCM words on ADPCMo during the ENB1 timeslot in SSI mode and during the B1 timeslot in ST-BUS mode. Similarily, the four 2-bit ADPCM words on ADPCMi are expanded into four 8-bit PCM octets (on PCMo1 and PCMo2) during the ENB1/B1 timeslot. (See Figures 4 & 7.) When SEL is set to 1, The same conversion takes place as described when SEL = 0 except that the ENB2/B2 timeslots are utilized. A-Law or -Law 8-bit PCM are received and transmitted most significant bit first starting with b7 and ending with b0. ADPCM data are most significant bit first starting with I1 and ending with I2. ADPCM BYPASS (32 and 24 kbit/s) In ADPCM bypass mode the B1 and B2 channel ADPCM words are bypassed (with a two-frame delay) to/from the ADPCM port and placed into the most significant nibbles of the PCM1/2 port octets. Note that the SEL pin performs no function for these two modes (See Figures 6 & 9). LINEAR, FORMAT and A/ pins are ignored in bypass mode. In 32 kb/s ADPCM bypass mode, Bits 1 to 4 of the B1, B2, B3 and B4 channels from PCMi1 and PCMi2 are transparently passed, with a two frame delay, to the same channels on ADPCMo. In the same manner, the B1, B2, B3 and B4 channels from ADPCMi are transparently passed, with a two frame delay, to the same channels on PCMo1 and PCMo2 pins. Bits 5 to 8 are don't care. This feature allows two voice terminals, which utilize ADPCM transcoding, to communicate through a system without incurring unnecessary transcode conversions. This arrangement allows byte-wide or nibble-wide transport through a switching matrix. 24 kb/s ADPCM bypass mode is the same as 32 kb/s mode bypass excepting that only bits 1 to 3 are bypassed and bits 4 to 8 are don't care. ADPCM BYPASS (16 kbit/s) When SEL is set to 0, only bits 1 and 2 of the B1, B2, B3 and B4 PCM octets (on PCMi1 and PCMi2) are bypassed, with a two frame delay, to the same channels on ADPCMo during the ENB1 timeslot in SSI mode and during the B1 timeslot in ST-BUS
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Data Sheet
mode. Similarily, the four 2-bit ADPCM words on ADPCMi are transparently bypassed, with a two frame delay, to PCMo1 and PCMo2 during the ENB1 or B1 timeslot. Bits 3-8 are don't care. (See Figures 6 & 9.) When SEL is set to 1, the same bypass occurs as described when SEL = 0 except that the ENB2 or B2 timeslots are utilized. LINEAR, FORMAT and A/ pins are ignored in bypass mode. PCM BYPASS When SEL is set to 0, the B1 and B2 PCM channels on PCMi1 are transparently passed, with a twoframe delay, to the same channels on the ADPCMo. Simiarily, the two 8-bit words which are on ADPCMi are transparently passed, with a two-frame delay, to channels B1 and B2 of PCMo1 while PCMo2 is set to a high-impedance state.(See Figures 6 & 9.) When SEL is set to 1, the B3 and B4 channels on PCMi2 are transparently passed, with a two frame delay, to the same channels on ADPCMo. Similarily, the two 8-bit words which are on ADPCMi are transparently passed, with a two-frame delay, to channels B3 and B4 of PCMo2. In this case PCMo1 is always high-impedance if ENB1 = 0. If ENB1 = 1 during ST-BUS operation then the D and C channels are active on PCMo1. LINEAR, FORMAT and A/ pins are ignored in bypass mode. Algorithm Reset Mode While an algorithmic reset is asserted the device will incrementally converge its internal variables to the 'Optional reset values' stated in G.726. Algorithmic reset requires that the master clock (MCLK) and frame pulse (ENB1/2 or F0i) remain active and that the reset condition be valid for at least four frames. Note that this is not a power down mode; see PWRDN for this function. ADPCMo & PCMo1/2 Disable When the encoders are programmed for ADPCMo disable (MS1 to MS3 set to 1) the ADPCMo output is set to a high impedance state and the internal encode function remains active. Therefore convergence is maintained. The decode processing function and data I/O remain active.
MT9126
When the decoders are programmed for PCMo1/2 disable (MS4 to MS6 set to 1) the PCMo1/2 outputs are high impedance during the B Channel timeslots and also, during ST-BUS operation, the D and C channel timeslots according to the state of ENB1. Therefore convergence is maintained. The encode processing function and data I/O remain active. Whenever any combination of the encoders or decoders are set to the disable mode the following outputs remain active. A) ST-BUS mode: ENB2/ F0od, EN1, EN2 and C2o. Also the "D" and "C" channels from PCMo1 and ADPCMo remain active if ENB1 is set to 0. If ENB1 is brought high then PCMo1 and ADPCMo are fully tri-stated. B) SSI mode: When used in the 16-bit linear mode, only the EN1 output remains active. For complete chip power down see PWRDN.
Other Pin Controls
16 Bit Linear PCM Setting the LINEAR pin to logic one causes the device to change to 16-bit linear (uniform) PCM transmission on the PCMi/o1 and PCMi/o2 ports. The data rate for both ST-BUS and SSI operation in this mode is 2048 kbit/s and all decode and encode functions are affected by this pin. In SSI mode, the input channel strobes ENB1 and ENB2/F0od remain active for 8 cycles of BCLK for an ADPCM transfer. The EN1 output is high for one BCLK period at the end of the frame (i.e., during the 256th BCLK period). In ST-BUS mode, the output strobes EN1 and ENB2/ F0od are adjusted to accommodate the required PCM I/O streams. The EN1 output becomes a single bit high true pulse during the last clock period of the frame (i.e., the 256th bit period) while ENB2/F0od becomes a delayed, low true frame-pulse (F0od) output occuring during the 64th bit period after the EN1 rising edge. Linear PCM on PCMi1 and PCMi2, are received as 14-bit, two's complement data with three bits of sign extension in the most significant positions (i.e., S,S,S,12,...1,0) for a total of 16 bits. The linear PCM data transmitted from PCMo1 and PCmo2 are 16-bit, two's complement data with one sign bit in the most significant position (i.e., S,14,13,...1,0) 32 and 24 kbit/s ADPCM mode In 32 kbit/s and 24 kbit/s linear mode, the 16-bit uniform PCM dual-octets of the B1, B2, B3 and B4 channels (from PCMi1 and PCMi2) are compressed into four 4-bit words on ADPCMo. The four 4-bit ADPCM words of the B1, B2, B3 and B4 channels
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from ADPCMi are expanded into four 16-bit uniform PCM dual-octets on PCMo1 and PCMo2. 16-bit uniform PCM are received and transmitted most significant bit first starting with b15 and ending with b0. ADPCM data are transferred most significant bit first starting with I1 and ending with I4 for 32 kbit/s and ending with I3 for 24 kbit/s operation (i.e., I4 is don't care).(See Figures 5 & 8.) 16 kbit/sADPCM mode When SEL is set to 0, the four, 2-bit ADPCM words are transmitted/received on ADPCMo/i during the ENB1 time-slot in SSI mode and during the B1 timeslot in ST-BUS mode. When SEL is set to 1, the four, 2-bit ADPCM words are transmitted/received on ADPCMo/i during the ENB2 timeslot in SSI mode and during the B2 timeslot in ST-BUS mode. (See Figures 5 & 8.) PCM Law Control (A/, FORMAT) The PCM companding/coding law invoked by the transcoder is controlled via the A/ and FORMAT pins. ITU-T G.711 companding curves, Law and A-Law, are selected by the A/ pin (0=-Law; 1=A-Law). Per sample, digital code assignment can conform to ITU-T G.711 (when FORMAT=1) or to Sign-Magnitude coding (when FORMAT=0). Table 1 illustrates these choices. FORMAT 0 SignMagnitude A/ = 0 or 1 1111 1111 1000 0000 0000 0000 0111 1111 1 ITU-T (G.711)
MCLK ENB1
Data Sheet
and assuming that clocks are applied to the MCLK and BCLK pins, the internal clocks will still not begin to operate until the first frame alignment is detected on the ENB1 pin for SSI mode or on the F0i pin for ST-BUS mode. The C2o clock and EN1, EN2 pins will not start operation until a valid frame pulse is applied to the F0i pin. If the F0i pin remains low for longer than 2 cycles of MCLK then the C2o pin will top toggling and will stay low. If the F0i pin is held high then the C2o pin will continue to operate. In STBUS mode the EN1 and EN2 pins will stop toggling if the frame pulse (F0i) is not applied every frame.
Master Clock (MCLK)
A minimum 4096 kHz master clock is required for execution of the transcoding algorithm. The algorithm requires 512 cycles of MCLK during one frame for proper operation. For SSI operation this input, at the MCLK pin, may be asynchronous with the 8 kHz frame provided that the lowest frequency and deviation due to clock jitter still meets the strobe period requirement of a minimum of 512 tC4P 25%tC4P (see Figure 3). For example, a system producing large jitter values can be accommodated by running an over-speed MCLK that will ensure a minimum 512 MCLK cycles per frame is obtained. The minimum MCLK period is 61 nSec, which translates to a maximum frequency of 16.384 MHz. Extra MCLK cycles (>512/frame) are acceptable since the transcoder is aligned by the appropriate strobe signals each frame.
PCM Code + Full Scale + Zero - Zero - Full Scale
(A/ = 0)
(A/ = 1)
512 tC4P - 25%tC4P Minimum
1000 0000 1010 1010 1111 1111 1101 0101 0111 1111 0101 0101 0000 0000 0010 1010
Figure 3 - MCLK Minimum Requirement
Bit Clock (BCLK)
For SSI operation the bit rate, for both ADPCM and PCM ports, is determined by the clock input at BCLK. BCLK must be eight periods in duration and synchronous with the 8 kHz frame inputs at ENB1 and ENB2. Data is sampled at PCMi1/2 and at ADPCMi concurrent with the falling edge of BCLK. Data is available at PCMo1/2 and ADPCMo concurrent with the rising edge of BCLK. BCLK may be any rate between 128 kHz and 4096 kHz. For STBUS operation BCLK is ignored (tie to VSS) and the bit rate is internally set to 2048 kbit/s.
Table 1 - Companded PCM Power Down Setting the PWRDN pin low will asynchronously cause all internal operation to halt and the device to go to a power down condition where no internal clocks are running. Output pins C2o, EN1, EN2, PCMo1, PCMo2 and ADPCMo and I/O pin F0od/ ENB2 are forced to a high-impedance state. Following the reset (i.e., PWRDN pin brought high)
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Data Sheet
BCLK
MT9126
ENB1
ENB2/F0od
B1 PCMi/o1
B2
7654321076543210 B3 PCMi/o2 B4
7654321076543210
32 kb/s
ADPCM i/o
12341234 12341234 B1 B2 B3 B4
24 kb/s
123x123x 123x123x
ADPCM i/o
B1
B2
B3
B4
B1
B2
B3
B4
16 kb/s
X = undetermined logic level output; don't care input Outputs high impedance outside of channel strobe boundaries Two frame delay from data input to data output
1212 12
12121212 12
SEL = 0
SEL = 1
SEL for 16 kb/s only
Figure 4 - SSI 8-Bit Companded PCM Relative Timing
Notes: S = 3 bits sign extension
BCLK
... (2.048 MHz only)
-Law is 13 bit 2's complement data (bits 0 -12) A-Law is 12 bit 2's complement data (shifted left once and utilizing bits 1 - 12, bit 0 not defined)
EN1
ENB1
ENB2/F0od
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0 SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
PCMi/o1
B1
B2
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0 SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
PCMi/o2 32 kb/s ADPCM i/o 24 kb/s
1234 1234 1234 1234
B3
1234 1234
B4
B1
B2
B3
B4
B3
B4
123x 123x 123x 123x 12 12 12 12 12 12 12 12
123x 123x 12 12 12 12
BBBBBBBB ADPCMi/o 16 kb/s 12341234 SEL = 0 SEL = 1
BBBB 1234 SEL = 1 SEL for 16 kb/s only
X = undetermined logic level output; don't care input Outputs high impedance outside of channel strobe boundaries Two frame delay from data input to data output
Figure 5 - SSI 16-Bit Linear PCM Relative Timing
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MT9126
Data Sheet
BCLK
ENB1
ENB2/F0od
7654321076543210
PCMi/o1
B1
B2
SEL = 0
ADPCMo/i
7654321076543210
SSI PCM Bypass
SEL = 1
PCMi/o2 B3 B4
7654321076543210
1234xxxx
1234xxxx
PCMi/o1
B1
B2
32 kb/s using bits 1 2 3 4
ADPCMo/i
1 2 3 4 1 2 3 4 1 2 3 4 1 2 34
24 kb/s where bit 4 = x
PCMi/o2
B3
B4
1234xxxx1234xxxx
SSI ADPCM Bypass
12xxxxxx
12xxxxxx
PCMi/o1
B1
B2
SEL = 0
ADPCM o/i
SEL = 1
1212
12121212 1212
16 kb/s
B1
PCMi/o2 B3
B2 B3
B4
B1 B2 B3
B4
B4
12xxxxxx X = undetermined logic level output; don't care input Outputs high impedance outside of channel strobe boundaries Two frame delay from data input to data output
12xxxxxx
Figure 6 - SSI PCM and ADPCM Bypass Relative Timing
8-98
Data Sheet
MT9126
MCLK (C4)
F0i ENB2/F0od
C2o (output) EN1 (output)
EN2 (output)
PCMi1
01
7654321076 54321076543210
D
PCMo1
C
B1
B2
01
7654321076 54321076 543210
PCMi2 transparent relay of D- and C- channels when ENB1=0 PCMo2
76 54321076543210
B3
B4
76 54321076543210
ADPCMi
01
76 543210 123 41234123 41234
D
ADPCMo
C
B1
B2
B3
B4
01
76 543210 123 41234123 41234
SEL=0 32 kb/s is shown In 24 kb/s, bit 4 becomes "X" SEL=1
B1 B2 B3 B4 B1 B2 B3 B4
121 21212 121 21212
B1 B2 B3 B4 B1 B2 B3 B4
16 kb/s SEL operates for 16 kb/s only
121 21212 121 21212
outputs=High impedance inputs = don't care X = undetermined logic level output; don't care input Outputs high impedance outside of channel boundaries Two frame delay from data input to data output
Figure 7 - ST-BUS 8-bit Companded PCM Relative Timing
8-99
MT9126
Data Sheet
MCLK (C4i)
F0i
C2o
EN1 (output) F0od/ENB2
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0 SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
PCMi/o1
B1
B2
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0 SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
PCMi/o2
B3
B4
1234 1234 1234 1234
ADPCMi/o
(32/24 kb/s) bit 4 = x at 24 kbit/s
B1
B2
B3
B4
12 12 12 12 12 12 12 12
ADPCMi/o
(16 kb/s)
BBBBBBBB 12341234 SEL = 0 SEL = 1 SEL operated for 16kb/s only
outputs = High impedance inputs = don't care X = undetermined logic level output; don't care input Outputs high impedance outside of channel boundaries Two frame delay from data input to data output
Note: D &C channels not supported in this mode.
Figure 8 - ST-BUS 16-bit Linear PCM Relative Timing
8-100
Data Sheet
MT9126
MCLK F0i ENB2/F0od
C2o EN1 (output) EN2 (output)
PCMi1
01 D
76543210 C 76543210 SEL=0
76543210 B1 76543210
76543210 B2 76543210
P C M B y p a s s
PCMo1
01
PCMi2 SEL=1 PCMo2
76543210 B3 76543210
76543210 B4 76543210
ADPCMi
01 D
76543210 C 76543210
76543210 B1/B3 76543210
76543210 B2/B4 76543210
ADPCMo
01
B1 PCMi/o1 01 D 76543210 C 1234 B3 1234
B2
xxxx
1234 xxxx B4
A D P C M B y p a s s
PCMi/o2
xxxx
1234 xxxx
ADPCMi/o 32 kb/s 24 kb/s bit 4 = X
01 D
76543210 C
12341234 B1 SEL=0 B2
12341234 B3 SEL=1 B1 B2 B3 B4 B4
D ADPCMi/o (16 kb/s) 01
C 76543210
B1
B2
B3 B4
12121212 B1
12121212 B2 12 B4 12 xxxxxx xxxxxx
PCMi/o1 PCMi/o2
01 D
76543210 C
12 xxxxxx B3 12 xxxxxx
outputs = High impedance inputs = don't care X = undetermined logic level output; don't care input Outputs high impedance outside of channel boundaries Two frame delay from data input to data output
Figure 9 - ST-BUS PCM and ADPCM Bypass Relative Timing
8-101
MT9126
Processing Delay Through the Device
In order to accommodate variable rate PCM and ADPCM interfaces, the serial input and output streams require a complete frame to load internal shift registers. Internal frame alignment of the encoding/decoding functions are taken from either of the F0i or ENB1 & ENB2 input strobes depending upon the device operating mode (i.e., ST-BUS or SSI). The encoding/decoding of all channels then takes one frame to complete before the output buffers are loaded. This results in a two frame transcoding delay. The two frame delay also applies to the D and C channels and to the PCM and ADPCM bypass functions.(See Figure 10.) Note: When changing the relative positions of the ENB1 and ENB2 strobes, precaution must be taken to ensure that two conditions are met. They are: 1) There must be at least 512 master clock cycles between consecutive rising edges of ENB1. This condition also holds true for ENB2. 2) The ENB1 strobe must alternate with the ENB2 strobe. Violation of these requirements may cause noise on the output channels.
Data Sheet
Applications
Figure 11 depicts an ISDN line card utilizing the MT8910 'U' interface transciever and MT9126 ADPCM transcoder. This central office application implements the network end of a Pair-Gain system. Figure 12 shows Mitel devices used to construct the remote Pair-Gain loop terminator. Figure 13 depicts an ADPCM to linear PCM converter for applications where further, value added, functions are being performed via digital signal processor. Access to linear coded PCM reduces the overhead of the DSP by removing the need for a companded to linear conversion. The linear PCM capability of the ADPCM transcoder in conjunction with the frame alignment signal EN1 allows direct connection to the serial port of both Motorola and Texas Instruments Digital Signal Processors. Daisy-chaining via the delayed frame strobe output ensures that the ADPCM array is distributed over the complete 2048 kbit bandwidth. If the DSP has a second serial port then access to the processed PCM can be had directly. For processors with only one serial port the MT8920 connected to the DSP parallel port will provide serial access by parallel to serial conversion. The same daisychained arrangement of Quad ADPCM transcoders will provide a general system resource for PCMADPCM conversion by setting the device to nonlinear operation.
frame n-1
frame n
frame n+1
PCMi1/2
Byte "x" PCM Byte "X" latched into device during frame n-1 PCM Byte "X" processed according to MSn input states latched during frame n ADPCM Word "X" output from device during frame n+1 Word "x"
ADPCMo
ENB1 or ENB2
F0i
MS1 or 4
32 kb/s
24 kb/s
32 kb/s
Where MS2, 3, 5, 6 = 0 This diagram shows the conversion sequence from PCM to ADPCM. The same pipelining occurs in the reverse ADPCM to PCM direction. Total delay from data input to data output = 2 frames.
Figure 10 - Data Throughput
8-102
Data Sheet
MT9126
F0i
MT9126
PCMi1 PCMo1 PCMi2 PCMo2 F0i MCLK ADPCMi ADPCMo
MT8910
F0b C4b DSTo DSTi
LIN+ LINLOUTLOUT+
T 2 R
F0od
C4i F0od
1 TR
F0i F0od C4i F0i F0od C4i F0i
8 TR
F0od C4i C4i
PCMi1 PCMo1 PCMi2 PCMo2
PCMi1 PCMo1 PCMi2 PCMo2
PCMi1 PCMo1 PCMi2 PCMo2
1
2
8
F0i
F0i ST1i ST1o C4i
MT8980 DX
ST2i
ST2o
Figure 11 - ISDN Line Card with 32 kbit/s ADPCM
8-103
MT9126
8-104
MT9160 M+ 1
1 EN1
MH88622 Pair Gain SLIC 1
TIP1
VR1
RING1 2 MCLK F0i MS5 26 MS6 27
MT9126
EN2 28
VX1
RF1
5V
F0b
4 5 6 7 PCMi1 VSS LINEAR MS2 20 MS1 19 IC 18 PWRDN 17 FORMAT 16 A/ 15 ENB2/F0od ENB1 PCMo2 PCMi2 SEL MS3 21 8 9 10 11 VDD 22 PCMo1 ADPCMi 23 BCLK ADPCMo 24 C2o MS4 25
3
3
RF2
RF3
VBias VRef PWRST IC A//IRQ VSSD CS SCLK DATA1 DATA2 MVSSA HSPKR+ HSPKRVDD CLOCKin STB/F0i Din Dout
C4b DSTi DSTo
RING2 TIP2
VR2
VX2
5V 3
VDD
5V
RG1
VDD
RG2
ESTi 12 13 14
MT8910 or MT8972
VEE
ESI2
-5V 5V
VEE
-24VDC
VBAT VBAT
meter signal I/P
3
10.24 MHz
DCRI
GND
DCRI
GND
120VDC ring voltage
1 20 2 MT9160 19 3 2 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11
1 8
Pins 5,8,9,17,23,32,33,36
16
Reset
MicroController
Static Control: SLIC Functions Optional QADPCM functional control
1 2 5V
13 11 MH88622 18
Serial Micro-port Intel MCS-51 Motorola SPI Nat Semi Microwire
Pair Gain SLIC 2 19
16
20
1 20 2 MT9160 19 3 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11
16 control/status lines are: LR1/2, ESE1/2, SHK1/2, RC1/2 - 8 x 2 SLIC's
3 8
28 30
9 control lines for QADPCM, some optional 8 signals for microport are: DATA1, DATA2, SCLK, IRQ, CS1, CS2, CS3, CS4
5V
39 40 14 27
21
-5V
meter signal I/P
16 25
22 7 34 5V
-24VDC
120VDC ring voltage
3 38
15 26
4 37
1 20 2 MT9160 19 3 18 4 4 17 5 16 6 15 7 14 8 13 9 12 10 11
D-Channel access through CODEC1 Microport as well as CChannel control of MT8910/MT8972
Data Sheet
Figure 12 - Pair Gain Remote Terminal utilzing Mitel Components
Data Sheet
MT9126
System Frame pulse System 4.096MHz
MT9126 C2o PCMo1 PCMo2 PCMi1 PCMi2 EN1 LINEAR ENB2/F0od +5v F0i MCLK (C4i) ADPCMo ADPCMi
MT8920
FSR FSX IRQ0
CLKR CLKX
MT9126 C2o PCMo1 PCMo2 PCMi1 PCmi2 EN1 DX MT9126 C2o PCMo1 PCmo2 PCMi1 PCMi2 F0i MCLK (C4i) ADPCMo ADPCMi LINEAR ENB2/F0od +5v F0i MCLK (C4i) ADPCMo ADPCMi
S T P A TI DSP
DR
STPA ST-BUS port
2nd serial port if available
EN1
LINEAR ENB2/F0od
+5v
MT9126 C2o PCMo1 PCMo2 PCMi1 PCMi2 EN1 LINEAR ENB2/F0od +5v F0i MCLK (C4i) ADPCMo ADPCMi
ADPCM BUS Figure 13 - ST-BUS to DSP Platform
8-105
MT9126
Absolute Maximum Ratings*
Parameter 1 2 3 4 5 Supply Voltage Voltage on any I/O pin Continuous Current on any I/O pin Storage Temperature Package Power Dissipation Symbol VDD-VSS Vi | Vo Ii | Io TST PD -65 Min -0.3 VSS-0.3
Data Sheet
Max 7.0 VDD+ 0.3 20 150 500
Units V V mA C mW
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 5 6 Supply Voltage TTL Input High Voltage TTL Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Operating Temperature TA Sym VDD Min 4.5 2.4 VSS 4.5 VSS -40 Typ 5.0 Max 5.5 VDD 0.4 VDD 0.5 +85 Units V V V V V C 400mV noise margin 400mV noise margin Test Conditions
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12
P W R D N M C L K
Sym ICC IDD VIH VIL VIHC VILC IIH/IIL VOH VOL IOZ Co Ci V+ VH V-
Min
Typ 5
Max 100
Units A mA V
Test Conditions PWRDN = 0 PWRDN = 1, clocks active
Supply Current Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH voltage (CMOS) Input LOW voltage (CMOS) Input leakage current High level output voltage Low level output voltage High impedance leakage Output capacitance Input capacitance Positive Threshold Voltage Hysteresis Negative Threshold Voltage
2.0 0.8 3.5 1.5 0.1 2.4 0.4 1 10 8 3.7 1.0 1.3 10 10
V V V A V V A pF pF V V V VIN=VSS to VDD IOL=5.0mA IOL=5.0mA VIN=VSS to VDD
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * DC Electrical Characteristics are over recommended temperature and supply voltage.
8-106
Data Sheet
MT9126
AC Electrical Characteristics - Serial PCM/ADPCM Interfaces (see Figure 14)
Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 BCLK Clock High BCLK Clock Low BCLK Period Data Output Delay (excluding first bit) Output Active to High Z Strobe Signal Setup Strobe Signal Hold Data Input Setup Data Input Hold Strobe to Data Delay (first bit) F0i Setup F0i Hold MCLK (C4i) duty cycle F0od Delay F0od Pulse Width MCLK (C4i) period Data Output delay Data in Hold time Data in Setup time
Sym tBCH tBCL tBCP tDD tAHZ tSSS tSSH tDIS tDIH tSD tF0iS tF0iH tH/tL x100 tDFD tDFW tC4P tDSD tDSH tDSS
Min 80 80 200
Typ
Max
Units ns ns
Test Conditions
7900 60 60
ns ns ns CL=150pF//RL=1K CL=150pF//RL=1K
80 80 50 50 60 50 50 40 122 122 50
tBCL80 tBCL80
ns ns ns ns ns CL=150pF//RL=1K
150 150 60 60
ns ns % ns ns CL=150pF//RL=1K CL=150pF//RL=1K CL=150pF//RL=1K
244 61 244.2 95 50 50
ns ns ns ns
Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
8-107
MT9126
tBCP BCLK S S I tSSS ENB1 or ENB2 tBCH tBCL
Data Sheet
VIH tSSH VIL
tDIS
VIH VIL tDIH VIH
PCMi/ADPCMi tDSS tSD PCMo/ADPCMo tDSH tDD
VIL tAHZ VOH VOL tH tDSD VIHC VILC tF0iH tL tC4P VIH VIL tF0iS tDFD tDFD VOH VOL tDFW
S T B U S
MCLK
F0i
F0od
Figure 14 - Serial Port Timing
AC Electrical Characteristics - ST-BUS C2o Conversion
Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 Delay MCLK falling to C2o rising Delay MCLK falling to Enable
Sym tD1 tD2
Min
Typ 100 100
Max
Units ns ns
Test Conditions 150pF//1K Load 150pF//1K Load
F0i
VIH VIL VIHC VILC tD1 VOH VOL VOH VOL tD2 tD2
MCLK (C4i)
C2o
EN1 EN2
Figure 15 - ST-BUS Timing for External Signal Generation
8-108
Data Sheet
MT9126
AC Electrical Characteristics - Mode Select Timing (see Figures 16 & 17)
Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 Mode Select Setup Mode Select Hold
Sym tSU tHOLD
Min 500 500
Typ
Max
Units ns ns
Test Conditions MCLK=4096 kHz
Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
t
SU
t HOLD
MS1 to MS6
VIH VIL
ENB1 (input)
VIH
Figure 16 - SSI Mode Select Set-up and Hold Timing
t
SU
t HOLD
MS1 to MS6
VIH VIL
MCLK
F0i
Refer to Figure 14 for ST-BUS F0i timing.
Figure 17 - ST-BUS Mode Select Set-up and Hold Timing
8-109
MT9126
Notes:
Data Sheet
8-110
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