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| NB4N11S 3.3 V 1:2 AnyLevelTM Input to LVDS Fanout Buffer / Translator The NB4N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevelTM input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB4N11S is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications. The NB4N11S has a wide input common mode range from GND + 50 mV to VCC - 50 mV. Combined with the 50 W internal termination resistors at the inputs, the NB4N11S is ideal for translating a variety of differential or single-ended Clock or Data signals to 350 mV typical LVDS output levels. The NB4N11S is functionally equivalent to the EP11, LVEP11, SG11 or 7L11M devices and is offered in a small 3 mm X 3 mm 16-QFN package. Application notes, models, and support documentation are available at www.onsemi.com. Features http://onsemi.com MARKING DIAGRAM* 16 1 1 QFN-16 MN SUFFIX CASE 485G NB4N 11S ALYW A L Y W = Assembly Location = Wafer Lot = Year = Work Week * * * * * * * Maximum Input Clock Frequency > 2.0 GHz Maximum Input Data Rate > 2.5 Gb/s 1 ps Maximum of RMS Clock Jitter Typically 10 ps of Data Dependent Jitter 380 ps Typical Propagation Delay 120 ps Typical Rise and Fall Times Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and SG Devices *For additional marking information, refer to Application Note AND8002/D. Q0 VTD D D Q0 VOLTAGE (130 mV/div) VTD Q1 Q1 Device DDJ = 10 ps Figure 1. Logic Diagram TIME (58 ps/div) Figure 2. Typical Output Waveform at 2.488 Gb/s with PRBS 223-1 (VINPP = 400 mV; Input Signal DDJ = 14 ps) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. (c) Semiconductor Components Industries, LLC, 2005 1 December, 2005 - Rev. 0 Publication Order Number: NB4N11S/D NB4N11S Exposed Pad (EP) VCC VCC VCC VCC 16 Q0 Q0 Q1 Q1 1 2 NB4N11S 3 4 10 D 9 VTD 15 14 13 12 VTD 11 D 5 VCC 6 NC 7 VEE 8 VEE Figure 3. NB4N11S Pinout, 16-pin QFN (Top View) Table 1. PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EP Name Q0 Q0 Q1 Q1 VCC NC VEE VEE VTD D D VTD VCC VCC VCC VCC - LVPECL, CML, LVDS, LVCMOS, LVTTL LVPECL, CML, LVDS, LVCMOS, LVTTL - - - - - I/O LVDS Output LVDS Output LVDS Output LVDS Output - Description Non-inverted D output. Typically loaded with 100 W receiver termination resistor across differential pair. Inverted D output. Typically loaded with 100 W receiver termination resistor across differential pair. Non-inverted D output. Typically loaded with 100 W receiver termination resistor across differential pair. Inverted D output. Typically loaded with 100 W receiver termination resistor across differential pair. Positive Supply Voltage. No Connect. Negative Supply Voltage. Negative Supply Voltage. Internal 50 W termination pin for D. Inverted Differential Clock/Data Input (Note 1). Non-inverted Differential Clock/Data Input (Note 1). Internal 50 W termination pin for D. Positive Supply Voltage. Positive Supply Voltage. Positive Supply Voltage. Positive Supply Voltage. Exposed pad. The exposed pad (EP) on the package bottom must be attached to a heat-sinking conduit. The exposed pad may only be electrically connected to VEE. 1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage or left open, and if no signal is applied on D0/D0, D1/D1 input, then the device will be susceptible to self-oscillation. http://onsemi.com 2 NB4N11S Table 2. ATTRIBUTES Characteristics Moisture Sensitivity (Note 2) Flammability Rating ESD Protection Oxygen Index: 28 to 34 Human Body Model Machine Model Charged Device Model Value Level 1 UL 94 V-0 @ 0.125 in > 2 kV > 200 V > 1 kV 225 Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol VCC VIN IIN IOSC Parameter Positive Power Supply Positive Input Input Current Through RT (50 W Resistor) Output Short Circuit Current Line-to-Line (Q to Q) Line-to-End (Q or Q to GND) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 3) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm 1S2P (Note 3) <3 Sec @ 248C <3 Sec @ 260C QFN-16 QFN-16 QFN-16 Condition 1 GND = 0 V GND = 0 V Static Surge Q or Q to GND Q to Q QFN-16 Continuous Continuous VIN VCC Condition 2 Rating 3.8 3.8 35 70 12 24 -40 to +85 -65 to +150 41.6 35.2 4.0 265 265 C C C/W C/W C/W C Unit V V mA mA mA TA Tstg qJA qJC Tsol Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 3. JEDEC standard multilayer board - 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB4N11S Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS VCC = 3.0 V to 3.6 V, GND = 0 V, TA = -40C to +85C Symbol ICC Power Supply Current (Note 8) Characteristic Min Typ 35 Max 50 Unit mA DIFFERENTIAL INPUTS DRIVEN SINGLE-ENDED (Figures 11, 12, 16, and 18) Vth VIH VIL Input Threshold Reference Voltage Range (Note 7) Single-ended Input HIGH Voltage Single-ended Input LOW Voltage GND +100 Vth + 100 GND VCC - 100 VCC Vth - 100 mV mV mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8, 9, 10, 17, and 19) VIHD VILD VCMR VID RTIN Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Configuration) Differential Input Voltage (VIHD - VILD) Internal Input Termination Resistor 100 GND GND + 50 100 40 50 VCC VCC - 100 VCC - 50 VCC 60 mV mV mV mV W LVDS OUTPUTS (Note 4) VOD DVOD VOS DVOS VOH VOL Differential Output Voltage Change in Magnitude of VOD for Complimentary Output States (Note 9) Offset Voltage (Figure 15) Change in Magnitude of VOS for Complimentary Output States (Note 9) Output HIGH Voltage (Note 5) Output LOW Voltage (Note 6) 900 250 0 1125 0 1 1425 1075 1 450 25 1375 25 1600 mV mV mV mV mV mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 14. 5. VOHmax = VOSmax + 1/2 VODmax. 6. VOLmax = VOSmin - 1/2 VODmax. 7. Vth is applied to the complementary input when operating in single-ended mode. 8. Input termination pins open, D/D at the DC level within VCMR and output pins loaded with RL = 100 W across differential. 9. Parameter guaranteed by design verification not tested in production. http://onsemi.com 4 NB4N11S Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; (Note 10) -40C Symbol VOUTPP Characteristic Output Voltage Amplitude (@ VINPPmin) fin 1.0 GHz (Figure 4) fin= 1.5 GHz fin= 2.0 GHz Maximum Operating Data Rate Differential Input to Differential Output Propagation Delay Duty Cycle Skew (Note 11) Within Device Skew (Note 16) Device-to-Device Skew (Note 15) RMS Random Clock Jitter (Note 13) Deterministic Jitter (Note 14) fin = 1.0 GHz fin = 1.5 GHz fDATA = 622 Mb/s fDATA = 1.5 Gb/s fDATA = 2.488 Gb/s 100 Q, Q 70 120 Min 220 200 170 1.5 270 Typ 350 300 270 2.5 370 8 5 30 0.5 0.5 6 7 10 470 45 25 100 1 1 20 20 VCC- GND 170 100 70 120 Max Min 250 200 170 1.5 270 25C Typ 350 300 270 2.5 370 8 5 30 0.5 0.5 6 7 10 470 45 25 100 1 1 20 20 VCC- GND 170 100 70 120 Max Min 250 200 170 1.5 270 85C Typ 350 300 270 2.5 370 8 5 30 0.5 0.5 6 7 10 470 45 25 100 1 1 20 20 VCC- GND 170 mV ps Max Unit mV fDATA tPLH, tPHL tSKEW Gb/s ps ps tJITTER ps VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 12) Output Rise/Fall Times @ 250 MHz (20% - 80%) NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Measured by forcing VINPPmin with 50% duty cycle clock source and VCC - 1400 mV offset. All loading with an external RL = 100 W across "D" and "D" of the receiver. Input edge rates 150 ps (20%-80%). 11. See Figure 13 differential measurement of tskew = |tPLH - tPHL| for a nominal 50% differential clock input waveform @ 250 MHz. 12. Input voltage swing is a single-ended measurement operating in differential mode. 13. RMS jitter with 50% Duty Cycle clock signal at 750 MHz. 14. Deterministic jitter with input NRZ data at PRBS 223-1 and K28.5. 15. Skew is measured between outputs under identical transition @ 250 MHz. 16. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition. 400 OUTPUT VOLTAGE AMPLITUDE (mV) 350 300 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 INPUT CLOCK FREQUENCY (GHz) 85C 25C -40C Figure 4. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) and Temperature (@ VCC = 3.3 V) http://onsemi.com 5 NB4N11S VOLTAGE (63.23 mV/div) Device DDJ = 10 ps TIME (58 ps/div) Figure 5. Typical Output Waveform at 2.488 Gb/s with PRBS 223-1 and OC48 mask (VINPP = 100 mV; Input Signal DDJ = 14 ps) RC 1.25 kW Dx 50 W VTDx VTDx 50 W Dx 1.25 kW I RC 1.25 kW 1.25 kW Figure 6. Input Structure http://onsemi.com 6 NB4N11S VCC VCC VCC VCC Zo = 50 W LVPECL Driver VTD VTD Zo = 50 W NB4N11S D 50 W* 50 W* D LVDS Driver Zo = 50 W VTD VTD Zo = 50 W VTD = VTD NB4N11S D 50 W* 50 W* D VTD = VTD = VCC - 2.0 V GND GND GND GND Figure 7. LVPECL Interface Figure 8. LVDS Interface VCC VCC VCC VCC CML Driver Zo = 50 W VCC VTD VTD Zo = 50 W VTD = VTD = VCC NB4N11S D 50 W* 50 W* D HSTL Driver Zo = 50 W VTD VTD Zo = 50 W VTD = VTD = GND or VDD/2 Depending on Driver. NB4N11S D 50 W* 50 W* D GND GND GND GND Figure 9. Standard 50 W Load CML Interface Figure 10. HSTL Interface VCC VCC VCC VCC Zo = 50 W LVCMOS Driver VTD VTD NB4N11S D 50 W* 50 W* D LVTTL Driver Zo = 50 W VTD VTD NB4N11S D 50 W* 50 W* D GND GND VTD = VTD = OPEN D = GND GND GND GND VTD = OPEN D = GND GND Figure 11. LVCMOS Interface *RTIN, Internal Input Termination Resistor. Figure 12. LVTTL Interface http://onsemi.com 7 NB4N11S D VINPP = VIH(D) - VIL(D) D Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH Figure 13. AC Reference Measurement LVDS Driver Device Q Zo = 50 W 100 W D LVDS Receiver Device Q Zo = 50 W D Figure 14. Typical LVDS Termination for Output Driver and Device Evaluation QN VOS QN VOD VOH VOL Figure 15. LVDS Output D VIH Vth VIL D D D Vth Figure 16. Differential Input Driven Single-Ended Figure 17. Differential Inputs Driven Differentially VCC VCC Vthmax D Vth VIHmin D VILmin GND VIHmax VILmax VCMR VIH(MAX) VIL VIH VINPP = VIHD - VILD VIL VIH VIL(MIN) Vthmin GND Figure 18. Vth Diagram Figure 19. VCMR Diagram http://onsemi.com 8 NB4N11S ORDERING INFORMATION Device NB4N11SMNG NB4N11SMNR2G Package QFN-16, 3 X 3 mm (Pb-Free) QFN-16, 3 X 3 mm (Pb-Free) Shipping 123 Units / Rail 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 NB4N11S PACKAGE DIMENSIONS 16 PIN QFN CASE 485G-01 ISSUE B D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 --- 0.30 0.50 PIN 1 LOCATION 0.15 C 0.15 C 0.10 C TOP VIEW 16 X 0.08 C SIDE VIEW A1 C 16X L 5 NOTE 5 4 16X K 1 12 16X 0.10 C A B 0.05 C NOTE 3 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. CCC CCC D2 e 8 9 16 13 E (A3) A SEATING PLANE DIM A A1 A3 b D D2 E E2 e K L SOLDERING FOOTPRINT* 3.25 0.128 0.30 0.012 0.575 0.022 EXPOSED PAD EXPOSED PAD E2 e 3.25 0.128 1.50 0.059 b BOTTOM VIEW 0.50 0.02 0.30 0.012 SCALE 10:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 10 NB4N11S/D |
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