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| SM5901AF compression and non compression type anti-shock memory controller with built-in 1M DRAM NIPPON PRECISION CIRCUITS INC. Overview The SM5901 is a compression and non compression type anti-shock memory controller with built-in 1M DRAM LSI for compact disc players. The compression level can be set in 4 levels, and external 1M DRAM can be connected to expand the memory to 2M bits. Digital attenuator, soft mute and related functions are also incorporated. It operates from a 2.7 to 3.3 V wide supply voltage range. Features - 2-channel processing - Serial data input *2s complement, 16-bit/MSB first, rear-packed format - System clock input *384fs (16.9344 MHz) *Digital attenuator - Anti-shock memory controller - ADPCM compression method *4-level compression mode selectable pre lim 2x1M DRAM (256Kx4 bits) Internal and external 1M DRAMs 1x1M DRAM (256Kx4 bits) Only internal 1M DRAM - Compression mode selectable - Microcontroller interface *Serial command write and state read-out *Data residual quantity detector: 15-bit operation, 16-bit output 4-bit compression mode 2.78 s/Mbit 5-bit compression mode 2.22 s/Mbit 6-bit compression mode 1.85 s/Mbit Full-bit non compression mode 0.70 s/Mbit *External memory can be connected ina Full-bit setting *Soft attenuator function *Soft mute function Mute ON in 23 ms max. Direct return after soft mute release *Forced mute - Extension I/O Microcontroller interface for external control using 5 extension I/O pins - +2.7 to +3.3 V wide operating voltage range - Schmitt inputs All input pins (including I/O pins) except CLK (system clock) - Reset signal noise elimination Approximately 3.8 s or longer (65 system clock pulses) continuous LOW-level reset - 44-pin QFP package (0.8 mm pin pitch) ry Noiseless attenuation-level switching (256- step switching in 23 ms max.) SM5901AF Package dimensions (Unit: mm) 44-pin QFP 13.20 + 0.30 10.00 + 0.20 - ina ry 1.60 0.80 + 0.20 0.35 2.05 + 0.10 - 13.20 + 0.30 - 10.00 + 0.20 - 0 to 8 0.80 +0.10 0.15 - 0.05 Pinout (Top View) lim A3 A2 A1 A0 A4 A5 A6 44 43 42 41 40 39 38 NTEST3 35 2.30MAX 0.05MIN A7 37 36 A8 VDD2 UC1 UC2 UC3 UC4 34 NRAS 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 NWE D1 D0 D3 D2 NCAS2 NTEST4 YMCLK YMDATA YMLD YDMUTE SM5 9 0 1 A F pre VSS2 NTEST1 NTEST2 CLK VSS1 10 11 YSRDATA 12 13 14 15 16 17 18 19 20 21 YBLKCK NRESET ZSENSE YFCLK ZSRDATA ZLRCK YLRCK YFLAG VDD1 ZSCK YSCK 22 SM5901AF Pin description Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pine name VDD2 UC1 UC2 UC3 UC4 VSS2 NTEST1 NTEST2 CLK VSS1 YSRDATA YLRCK YSCK ZSCK ZLRCK ZSRDATA YFLAG YFCLK YBLKCK NRESET ZSENSE VDD1 I/O Ip/O Ip/O Ip/O Ip/O Ip Ip I I I I O O O I I I I Function H VDD supply pin Microcontroller interface extension I/O 1 Setting L ina ry Microcontroller interface extension I/O 3 Microcontroller interface extension I/O 4 Ground Test pin Test pin Ground 16.9344 MHz clock input Audio serial input data Audio serial input LR clock Audio serial input bit clock Left channel Audio serial output bit clock Audio serial output data Audio serial output LR clock Left channel Signal processor IC RAM overflow flag Crystal-controlled frame clock Subcode block clock signal System reset pin Microcontroller interface status output VDD supply pin Forced mute pin Mute Microcontroller interface latch clock Microcontroller interface serial data Test pin Microcontroller interface shift clock DRAM CAS control DRAM data input/output 2 DRAM data input/output 3 DRAM data input/output 0 DRAM data input/output 1 DRAM WE control DRAM RAS control Test pin DRAM address 8 DRAM address 7 DRAM address 6 DRAM address 5 DRAM address 4 DRAM address 0 DRAM address 1 DRAM address 2 DRAM address 3 Microcontroller interface extension I/O 2 Test Test Right channel Right channel Overflow lim O I I I YMLD I Ip O NCAS2 D2 D3 D0 D1 I/O I/O I/O I/O O O NWE NRAS A8 A7 A6 A5 A4 A0 A1 A2 A3 Ip O O O O O O O O O Reset YDMUTE YMDATA YMCLK NTEST4 Test pre NTEST4 Test Ip : Input pin with pull-up resistor Ip/O : Input/Output pin (With pull-up resistor when a input mode) And in case that only internal 1M DRAM is used, 28, 33, 34, 36 to 44 pin are high impedance, and 29 to 32 pin are input pull up mode. SM5901AF Absolute maximum ratings Parameter Supply voltage Input voltage Storage temperature Power dissipation Soldering temperature Soldering time Symbol VDD VI TSTG PD TSLD (VSS = 0V, VDD pin voltage = VDD) Rating Unit - 0.3 to 4.6 VSS - 0.3 to VDD + 0.3 - 55 to 125 600 255 10 V V C mW C sec tSLD (*1) Refer to pin summary on the next page. Note. Values also apply for supply inrush and switch-off. Electrical characteristics Recommended operating conditions Parameter Supply voltage Operating temperature Symbol VDD TOPR DC characteristics Standard voltage: (VDD = 2.7 to 3.3 V, VSS = 0 V, Ta = 0 to 70C) Parameter Pin Symbol IDD Condition Min Rating Typ 60 60 0.7VDD 0.3VDD 0.3 0.7VDD 0.3VDD IOH = - 0.5 mA IOL = 1 mA IOH = - 0.5 mA IOL = 1 mA VIN = VDD VIN = 0V VIN = 0V VIN = VDD VIN = 0V VOUT = VDD VOUT= 0V 15 15 1.5 30 30 3 VDD - 0.4 0.4 60 60 15 1.0 1.0 1.0 1.0 VDD - 0.4 0.4 Max mA mA V V VP-P V V V V V V A A A A A A A Unit Current consumption Input voltage pre (*2,3,4,5) (*4,6) (*5) H level L level Output voltage H level L level L level H level Input current CLK (*3,4) Input leakage current (*2,3,4,5) (*2,5) Output leakage current (*7) (*A) VDD = 3 V, CLK input frequency fXTI= 384fs = 16.9344 MHz, all outputs unloaded, SHPRF: Shock-proof, typical values are for VDD = 3 V. lim VDD CLK H level L level VIH1 VIL1 VINAC VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 IIH1 IIL1 IIL2 ILH1 ILL IZH IZL ina ry (VSS = 0V, VDD pin voltage = VDD) Rating Unit V C 2.7 to 3.3 0 to 70 (*A)SHPRF ON (*A)Through mode AC coupling SM5901AF (*1) (*2) Pin function Pin name Pin function Pin name Clock input pin (AC input) CLK Schmitt input pins YSRDATA, YLRCK, YSCK, YFLAG, YFCLK, NRESET, (*3) (*4) (*5) (*6) (*7) Pin function Pin name Pin function Pin name Pin function Pin name Pin function Pin name Pin function Pin name NCAS2, NWE, NRAS, A0, A1, A2, A3, A4, A5, A6, A7, A8 pre lim ina ry Schmitt input pin with pull-up NTEST1, NTEST2, NTEST3, NTEST4 UC1, UC2, UC3, UC4 D0, D1, D2, D3 Outputs Outputs I/O pins (Schmitt input with pull-up in input state) I/O pins (Schmitt input in input state) ZSCK, ZLRCK, ZSRDATA, ZSENSE YBLKCK, YDMUTE, YMLD, YMDATA, YMCLK SM5901AF AC characteristics Standard voltage: VDD = 2.7 to 3.3 V, VSS = 0 V, Ta = 0 to 70 C (*) Typical values are for fs = 44.1 kHz System clock (CLK pin) Clock pulsewidth (HIGH level) Clock pulsewidth (LOW level) Clock pulse cycle tCWH tCWL tCY ina ry System clock Min 26 26 Typ Max 125 125 29.5 29.5 59 384fs 56 250 Parameter Symbol Condition Rating Unit ns ns ns System clock input CLK 0.5VDD t CWH t CWL t CY Serial input (YSRDATA, YLRCK, YSCK pins) Parameter YSCK pulsewidth (HIGH level) YSCK pulsewidth (LOW level) YSCK pulse cycle YSRDATA setup time YSRDATA hold time Symbol Rating Typ Unit ns ns ns ns ns ns ns Condition Last YSCK rising edge to YLRCK edge YLRCK edge to first YSCK rising edge YLRCK pulse frequency See note below. lim tBCWH tBCWL tBCY tDS tDH tBL tLB 75 75 50 50 50 50 0 150 fs Min Max 2fs fs Memory system ON (MSON=H) Memory system OFF (MSON=L) pre operation. Note. When the memory system is OFF (through mode), the input data rate is synchronized to the system clock input (384fs), so input data needs to be at 1/384 of this frequency. But, this IC can tolerate a certain amount of jitter. For details, refer to Through-mode t BCWH t BCY t BCWL 0.5VDD YSCK t DS t DH 0.5VDD t BL t LB 0.5VDD YSRDATA YLRCK SM5901AF Microcontroller interface (YMCLK, YMDATA, YMLD, ZSENSE pins) Parameter YMCLK LOW-level pulsewidth YMCLK HIGH-level pulsewidth YMDATA setup time YMDATA hold time YMLD LOW-level pulsewidth YMLD setup time YMLD hold time Rise time Fall time ZSENSE output delay Note. tCY is the system clock cycle time (59ns typ). Symbol Min Rating Typ Max ns ns ns ns ns ns ns 30 + 2tCY 30 + 2tCY 30 + tCY 30 + tCY 30 + tCY 30 + tCY 30 + 2tCY Unit YMDATA t MDS YMCLK t MCWL YMLD t MLS lim t MLWL tf 0.7 VDD 0.3 VDD ZSENSE YMCLK YMDATA YMLD pre Reset input (NRESET pin) Parameter NRESET pulsewidth First HIGH-level after supply voltage rising edge Note. tCY is the system clock (CLK) input (384fs) cycle time. tCY = 59 ns, tNRST (min) = 3.8 s when fs = 44.1 kHz VDD NRESET t HNRST t NRST ina ry 100 100 ns ns 100 + 3tCY ns tMCWL tMCWH tMDS tMDH tMLWL tMLS tMLH tr tf tPZS 0.5VDD t MDH 0.5VDD t MCWH t MLH 0.5VDD t PZS 0.5VDD tr 0.7 VDD 0.3 VDD 0.5VDD Symbol Min Rating Typ Max 0 64 Unit tHNRST tNRST tCY (Note) tCY (Note) SM5901AF Serial output (ZSRDATA, ZLRCK, ZSCK pins) Parameter ZSCK pulsewidth ZSCK pulse cycle ZSRDATA and ZLRCK output delay time Symbol Condition Min 15 pF load 15 pF load 15 pF load 15 pF load 0 0 Rating Typ 1/96fs 1/48fs 60 60 ns ns Max Unit ZSCK ZSRDATA ZLRCK DRAM access timing (NRAS, NCAS2, NWE, A0 to A8, D0 to D3) Parameter NRAS pulsewidth Symbol Condition ina ry 0.5VDD t SCOW t SCOW t SCOY 0.5VDD t DHL t DLH Rating Typ 5 3 2 5 3 1 1 1 5 3 3 40 40 15 pF load 15 pF load Non compression 1M 6-bit compression tSCOW tSCOY tDHL tDLH Unit lim Setup time Hold time Hold time Setup time Setup time Hold time Input setup Input hold Min Max NRAS falling edge to NCAS2 falling edge NCAS2 pulsewidth NRAS NCAS2 NCAS2 NCAS2 falling edge to address falling edge to address pre rising edge to data read NWE pulsewidth NWE falling edge to NCAS2 falling edge Refresh cycle (fs = 44.1 kHz playback) Memory system ON (RDEN=H) Decode sequence operation falling edge to data write tRASL tRASH tRCD tCASH tCASL tRADS tRADH tCADS tCADH tCWDS tCWDH tCRDS tCRDH tWEL tWCS 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load tCY(note) tCY tCY tCY tCY tCY tCY tCY tCY tCY tCY ns ns 6 3 1.4 3.7 4.4 5.5 2.7 7.3 8.8 10.9 tCY tCY ms ms ms ms ms ms ms ms DRAM 5-bit compression 4-bit compression tREF 4M Non compression 6-bit compression DRAM 5-bit compression 4-bit compression Note. tCY is the system clock (CLK) input (384fs) cycle time. tCY = 59 ns when fs = 44.1 kHz SM5901AF DRAM access timing (when external DRAM is used) t RASL 5t CY NRAS t RASH 3t CY NCAS2 (DRAM2 SELECT) t RADS 1t CY A0 to A9 t CWDS 3t CY D0 to D3 (WRITE) t RADH 1t CY D0 to D3 (READ) t WCS 3t CY NWE (WRITE) pre lim ina ry t CADS 1t CY t CADH 5t CY t CWDH 3t CY t CRDS t CRDH t WEL 6t CY t RCD 2t CY t CASL 3t CY t CASH 5t CY SM5901AF Block diagram ZSRDATA ZLRCK ZSCK SM5901 YBLKCK YFCLK YFLAG Control Input 1 YMDATA YMCLK YMLD ZSENSE Microcontroller Interface lim General Port Decoder Control Input 2 NRAS CLK NCAS2 UC1 to UC4 YDMUTE NRESET NTEST 1, 2, 3, 4 pre NWE A0 to A8 D0 to D3 ina ry Output Interface Input Interface Attenuator Input Buffer Compression Mode Through Mode Encoder 1M DRAM DRAM Interface YSCK YSRDATA YLRCK SM5901AF Functional description This IC has two modes of operation; shock-proof mode and through mode. The operating sequences are controlled using commands from a microcontroller. Microcontroller interface Commands from the microcontroller are input using 3 bit serial inputs; data (YMDATA), bit clock (YMCLK) and load signal (YMLD). Write command format DATA 8bit YMDATA D7 D6 D5 D4 D3 YMCLK YMLD YMDATA YMCLK YMLD lim COMMAND 8bit B4 B3 B7 B6 B5 B2 B1 B0 COMMAND 8bit B4 B3 B2 B1 B0 B7 B6 B5 Read command format (Commands 90, 91, 93) pre YMDATA YMCLK YMLD ZSENSE ZSENSE Read command format (Command 92 (memory residual read)) ina ry COMMAND 8bit B4 B3 D2 D1 D0 B7 B6 B5 B2 B1 B0 STATUS 8bit S7 S6 S5 S4 S3 S2 S1 S0 RESIDUAL DATA 15bit S7 S6 S1 S0 M1 M2 M7 16bit RESIDUAL DATA ENTRY (lowest bit is 0) In the case of a read command from the microcontroller, bit serial data is output (ZSENSE) synchronized to the bit clock input (YMCLK). 0 SM5901AF Command table Write command summary MS command 80 B7 B6 B5 B4 Anti-shock memory system settings Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MSWREN MSWACL MSRDEN MSRACL MSDCN2 MSDCN1 WAQV MSON Function Encode sequence start/stop Write address reset Read address reset 80hex = 1000 0000 ina ry Start Reset Start Decode sequence start/stop Reset Q data valid Valid ON Memory system ON Function Output Output Output Output Function H output H output H output H output H operation Reset level MSDCN2=H, MSDCN1=H: 3-pair comparison start MSDCN2=H, MSDCN1=L: 2-pair comparison start MSDCN2=L, MSDCN1=H: Direct-connect start MSDCN2=L, MSDCN1=L: Connect operation stop Extension I/O settings 81 B7 B6 B5 B4 Extension I/O port input/output settings Bit D7 D6 D5 D4 D3 D2 D1 D0 UC4OE UC3OE UC2OE UC1OE Name 81hex = 1000 0001 H operation Reset level lim Extension I/O port UC4 input/output setting Extension I/O port UC3 input/output setting Extension I/O port UC2 input/output setting Extension I/O port UC1 input/output setting pre Bit Name D7 D6 D5 D4 D3 D2 D1 D0 UC4WD UC3WD UC2WD UC1WD Extension I/O output data settings 82 Extension port HIGH/LOW output level B7 B6 B5 B4 A port setting is invalid if that port has already been defined as an input using the 81H command above. 82hex = 1000 0010 H operation Reset level Extension I/O port UC4 output data setting Extension I/O port UC3 output data setting Extension I/O port UC2 output data setting Extension I/O port UC1 output data setting B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 L L L L L L L L L L L L L L L L SM5901AF ATT, MUTE settings 83 B7 B6 B5 B4 83hex = 1000 0011 Bit D7 D6 D5 D4 D3 D2 D1 D0 CMP12 Name ATT MUTE SOFT Function Attenuator enable Forced muting (changes instantaneously) Soft muting (changes smoothly when ON only) H operation Attenuator ON Reset level Mute ON Soft mute ina ry 12-bit comparison 12-bit comparison connect/ 16-bit comparison connect Refer to Attenuation, Soft mute, Force mute. Attenuation level settings 84 B7 B6 B5 B4 84hex = 1000 0100 H operation Reset level Bit D7 D6 D5 D4 D3 D2 D1 D0 Name K7 K6 K5 K4 K3 K2 K1 K0 Function 2 2 2 2 2 MSB 2-1 -2 -3 -4 -5 lim 2-6 -7 LSB 2 -8 Refer to Attenuation, Soft mute, Force mute Option settings 85 B7 B6 B5 B4 pre Bit Name D7 D6 D5 RAMX2 YFLGS D4 D3 D2 D1 D0 YFCKP COMPFB COMP6B COMP5B COMP4B 85hex = 1000 0101 H operation Reset level Function External DRAM select (used / no used) used FLAG6 set conditions (reset using status read command 90H) - When YFLGS=0, YFCKP=0, YFCLK input falling edge, YFLAG=L - When YFLGS=0, YFCKP=1, YFCLK input rising edge, YFLAG=L - When YFLGS=1, YFCKP=0, YFLAG=L Full-bit non compression mode 6-bit compression mode 5-bit compression mode 4-bit compression mode L L H L L - When YFLGS=1, YFCKP=1, YFLAG=H When the number of compression bits is set incorrectly (2 or more bits in D0 to D3 are set to 1 or all bits are set to 0), 6-bit compression mode is selected. B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 L L L L L H L L L L L L L L SM5901AF Read command summary Anti-shock memory status (1) 90 B7 B6 B5 B4 90hex = 1001 0000 Bit S7 S6 S5 S4 S3 S2 S1 S0 DCOMP MSWIH MSRIH Name FLAG6 MSOVF Function Signal processor IC jitter margin exceeded Write overflow (Read once only when RA exceeds WA) HIGH-level state Exceeded DRAM overflow Data compare-connect sequence operating Encode sequence stop due to internal factors Decode sequence stop due to internal factors Anti-shock memory status (2) 91 ina ry Encoding stopped Decoding stopped HIGH-level state No valid data Memory full Encoding Decoding Compare-connect sequence operating Refer to Status flag operation summary B7 B6 B5 B4 91hex = 1001 0001 Bit S7 S6 S5 S4 S3 S2 S1 S0 Name MSEMP OVFL ENCOD DECOD Function Valid data empty state (Always HIGH when RA exceeds VWA) Write overflow state (Always HIGH when WA exceeds RA) Encode sequence operating state lim Decode sequence operating state Refer to Status flag operation summary. pre B3 B2 B1 B0 B3 B2 B1 B0 SM5901AF Anti-shock memory valid data residual 92 B7 B6 B5 B4 92hex = 1001 0010 Bit S7 S6 S5 S4 S3 S2 S1 S0 M1 M2 M3 M4 M5 M6 M7 M8 ... Name AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13 AM12 AM11 AM10 AM09 AM08 AM07 AM06 AM05 to AM00 Function Valid data accumulated VWA-RA (MSB) 4M bits 2M bits 1M bits Note. The time conversion factor varies depending on the compression bit mode.(M = 1,048,576 K= 1,024) Residual time (sec) = Valid data residual (Mbits) x Time conversion value k where the Time conversion value k (sec/Mbit) = 2.786(4 bits), 2.229* (5 bits), 1.857 (6 bits) and 0.700 (Full bits). Extension I/O inputs 93 Input data entering (or output data) an extension port terminal is echoed to the microcontroller. (That is, the input data entering an I/O port configured as an input port using the 81H command, OR the output data from a pin configured as an output port using the 82H command.) Bit S7 S6 S5 S4 S3 S2 S1 S0 UC4RD UC3RD UC2RD UC1RD Name Function lim B7 B6 B5 B4 ina ry 512K bits 256K bits 128K bits 64K bits 32K bits 16K bits 8K bits 4K bits 2K bits 1K bits 512 bits 256 bits 128 to 4 bits 0 constant output HIGH-level state 93hex = 1001 0011 pre B3 B2 B1 B0 B3 B2 B1 B0 SM5901AF Status flag operation summary Flag name FLAG6 Read method READ 90H bit 7 Set Meaning - Indicates to the CD signal processor DSP (used for error correction, de-interleaving) that a disturbance has exceeded the RAM jitter margin. - Set according to the YFLAG input and the operating state of YFCKP and YFLGS. FLAG6 set conditions Reset MSOVF READ 90H bit 6 Meaning Set Reset - Indicates once only that a write to external DRAM has caused an overflow. (When reset by the 90H status read command, this flag is reset even if the overflow condition continues.) - When the write address (WA) exceeds the read address (RA) - By 90H status read - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued - After external reset DCOMP READ 90H bit 3 Meaning Set Reset - Indicates that a compare-connect sequence is operating - When a (3-pair or 2-pair) compare-connect start command is received (MSDCN2=1) - When a direct connect command is received (MSDCN2=0, MSDCN1=1) - When a (3-pair or 2-pair) comparison detects conforming data lim Meaning Set Reset Meaning Set Reset - When the connect has been performed after receiving a direct connect command - When a compare-connect stop command (MSDCN2=0, MSDCN1=0) is received received at the same time, the compare-connect command has priority.) - After external reset - Indicates that the encode sequence has stopped due to internal factors (not microcontroller commands) - When FLAG6 (above) is set - When MSOVF (above) is set - When a MSWREN=1 command is received (However, if a compare-connect command is MSWIH READ 90H bit 2 pre MSRIH READ 90H bit 1 - When conforming data is detected after receiving a compare-connect start command - When the connect has been performed after receiving a direct connect command - After external reset (not microcontroller commands) - When the valid data residual becomes 0 - By 90H status read - After external reset - When a read address clear (MSRACL) or write address clear (MSWACL) command is received - Indicates that the decode sequence has stopped due to internal factors - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued ina ry When YFLGS=0, YFCKP=0, YFCLK input falling edge, YFLAG=L When YFLGS=0, YFCKP=1, YFCLK input rising edge, YFLAG=L When YFLGS=1, YFCKP=0, YFLAG=L When YFLGS=1, YFCKP=1, YFLAG=H - By 90H status read - By 80H command when MSON=ON - After external reset SM5901AF Flag name MSEMP Read method READ 91H bit 7 Reset Meaning Set - Indicates that the valid data residual has become 0 - When the VWA (final valid data's next address) = RA (address from which the next read would take place) - Whenever the above does not apply Meaning Set Reset OVFL READ 91H bit 6 (Note: This flag is not set when WA=RA through an address initialize or reset operation.) - When the read address (RA) is advanced by the decode sequence - After external reset - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued ENCOD READ 91H bit 5 Meaning Set - Indicates that the encode sequence (input data entry, encoding, DRAM write) is operating - By the 80H command when MSWREN=1 - When conforming data is detected during compare-connect operation - When the connect has been performed after receiving a direct connect command Reset - When the FLAG6 flag=1 (above) - When the OVFL flag=1 (above) - By the 80H command when MSDCN1=1 or MSDCN2=1 (compare-connect start command) - By the 80H command when MSON=0 - After external reset DECOD READ 91H bit 4 pre lim Meaning Set Reset Note. Reset conditions have priority over set conditions. For example, if the 80H command has - Indicates that the decode sequence (read from DRAM, decoding, attenuation, data output) is operating - Whenever the above does not apply MSWREN=1 and MSDCN1=1, the ENCOD flag is reset and compare-connect operation starts. - By a new 80H command when MSRDEN=1 and the MSEMP flag=0 (above) ina ry - Indicates a write to external DRAM overflow state - When the write address (WA) exceeds the read address (RA). - By the 80H command when MSWREN=0 SM5901AF Write command supplementary information 80H (MS command) - MSWREN When 1: Encode sequence starts Invalid when MSON is not 1 within the same 80H command Invalid when FLAG6=1 Invalid when OVFL=1 -MSRACL When 1: Initializes the read address (RA) Invalid when a compare-connect start command (MSDCN2=1 or MSDCN1=1) occurs simultaneously Direct connect if a compare-connect sequence is already operating When 0: Encode sequence stops - MSWACL When 1: Initializes the write address (WA) When 0: No operation - MSRDEN When 1: Decode sequence starts Does not perform decode sequence if MSON=1.If there is no valid data, decode sequence temporarily stops. But, because the MSRDEN flag setting is maintained as is, the sequence automatically re-starts when valid data appears. When 0: Decode sequence stops 81H (I/O setting on extension I/O) pre 82H (Setting output data on extension I/O) lim ina ry - MSDCN2, MSDCN1 - WAQV When 0: No operation - MSON When 0: No operation When 1 and 1: 3-pair compare-connect sequence starts When 1 and 0: 2-pair compare-connect sequence starts When 0 and 1: Direct connect sequence starts When 0 and 0: Compare-connect sequence stops. No operation if a compare-connect sequence is not operating. When 1: The immediately preceding YBLKCK falling-edge timing WA (write address) becomes the VWA (valid write address). When 1: Memory system turns ON and compression-type shock-proof operation starts When 0: Memory system turns OFF and throughmode playback starts. (In this mode, the attenuator is still active.) SM5901AF 83H (ATT, MUTE settings) - ATT (attenuator enable) When 1: Attenuator settings become active (84H command) When 0: Attenuator settings become inactive, and output continues without attenuation - MUTE (forced muting) - SOFT (soft muting) When 1: Outputs are smoothly muted to 0. When 0: No muting. Soft mute release occurs instantaneously to either the value set by the 84H command (When ATT=1) or 0dB (When ATT=0) When 1: Outputs are instantaneously muted to 0.(note 1) Same effect as taking the YDMUTE pin HIGH. When 0: No muting(note 1) (note1) Effective at the start of a Left-channel output data. 85H (option settings) - RAMX2 When 1: External DRAM is used When 0: External DRAM is no used - YFLGS, YFCKP see 9-2-3. pre When 0 and 0: Sets FLAG6 on the falling edge of YFCLK when YFLAG=0 When 0 and 1: Sets FLAG6 on the rising edge of YFCLK when YFLAG=0 When 1 and 0: Sets FLAG6 when YFLAG=0 When 1 and 1: Sets FLAG6 when YFLAG=1 lim ina ry - MUTE, SOFT, YDMUTE relationship - CMP12 (12-bit comparison connection) When all mute inputs are 0, mute is released. When 1: Performs comparison connection using only the most significant 12 bits of input data. When 0: Performs comparison connection using all 16 bits of input data. - COMPFB, COMP6B, COMP5B, COMP4B When 0, 0, 0 and 1: Selects 4-bit compression mode When 0, 0, 1 and 0: Selects 5-bit compression mode When 1, 0, 0 and 0: Selects full-bit compression mode In all other cases: Selects 6-bit compression mode Changing mode without initialize in operation is possible. SM5901AF Shock-proof operation overview Shock-proof mode is the mode that realizes shockproof operation using external DRAM. Shock-proof mode is invoked by setting MSON=H in microcontroller command 80H. This mode comprises the following 3 sequences. 1. Input data from a signal processor IC is stored in internal buffers. 2. Encoder starts after a fixed number of data have been received. - Decode sequence 1. Reads compressed data stored in external buffer RAM at rate fs. 2. Decoder starts, using the predicting filter type and quantization levels used when encoded. - Compare-connect sequence 2. Then, using microcontroller command 80H, the compare-connect start command is executed and compare-connect sequence starts. pre lim 1. Encoding immediately stops when either external buffer RAM overflows or when a CD read error occurs due to shock vibrations. ina ry 4. Outputs the result. - Encode sequence 3. The encoder, after the most suitable predicting filter type and quantization steps have been determined, performs APC encoding and then writes to external DRAM. 3. Performs attenuation operation (including muting operation) 3. Compares data re-read from the CD with the processed final valid data stored in RAM (confirms its correctness). 4. As soon as the comparison detects conforming data, compare-connect sequence stops and encode sequence re-starts, connecting the data directly behind previous valid data. SM5901AF RAM addresses SM5901 has an 1M DRAM as the internal buffer. and an external 1M DRAM can be also connected to expand the memory to 2M bits. Three kinds of addresses are used for external RAM control. WA (write address) RA (read address) VWA (valid write address) Among these, VWA is the write address for conforming data whose validity has been confirmed. Determination of the correctness of data read from the CD is delayed relative to the encode write processing, so VWA is always delayed relative to WA. Connect data work area RA WA The region available for valid data is the area between VWA-RA. - Connect data work area This is an area of memory reserved for connect data. This area is 2Kbits. VWA (valid write address) The VWA is determined according to the YBLKCK pin and WAQV command. Refer to the timing chart below. 1.YBLKCK is a 75 Hz clock(HIGH) when used for normal read mode and it is a 150Hz clock when used for double-speed read mode. Both modes clock are synchronized to the CD format block end timing. pre YBLKCK Microcontroller data set Refer to Microcontroller interface When this clock goes LOW, WA which is the write address of internal encode sequence, is stored (see note 2). lim VWA VWA(x) Values shown are for rate fs. The values are 1/2 those shown at rate 2fs. Fig 2. YBLKCK and VWA relationship ina ry VWA Valid data area Fig1. RAM addresses 2.The microcontroller checks the subcode and, if confirmed to be correct, generates a WAQV command (80H). 3.When the WAQV command is received, VWA is updated according to the previously latched WA. (note 2) Actually, there is a small time difference, or gap, between the input data and YBLKCK. This gap serves to preserves the preceding WA to protect against incorrect operation. 13.3ms VWA latch set WAQV set VWA(x + 1) SM5901AF YFLAG, YFCLK, FLAG6 Correct data demodulation becomes impossible for the CD signal processor IC when a disturbance exceeding the RAM jitter margin occurs. The YFLAG signal input pin is used to indicate when such a condition has occurred. The YFLAG signal is a 7.35 kHz clock synchronized to the CD format frame 1. The IC checks the YFLAG input and stops the encode sequence when such a disturbance has occurred, and then makes FLAG6 active. The YFLAG check method used changes depending on the YFLGS flag and YFCKP flag (85H command). See table1. If YFLAGS is set to 1, then YFCLK should be tied either High or Low. 85H command YFLGS 1 2 3 4 1 0 YFCKP 0 1 0 1 When YFLAG=LOW on YFCLK input falling edge When YFLAG=LOW on YFCLK input rising edge When YFLAG=LOW When YFLAG=HIGH Table1. YFLAG signal check method pre lim ina ry FLAG6 set conditions YFCLK be tied either High or Low - After system reset FLAG6 reset conditions - When MSON=LOW - By status read (90H command) SM5901AF Compare-connect sequence The SM5901 supports three kinds of connect modes; 3-pair compare-connect, 2-pair compareconnect and direct connect. Note that the SM5901 can also operate in 12-bit comparison connect mode using only the most significant 12 bits of data for connection operation. In 3-pair compare-connect mode, the final 6 valid data (3 pairs of left- and right-channel data input before encode processing) and the most recently input data are compared until three continuous data pairs all conform. At this point, the encode sequence is re-started and data is written to VWA. In 2-pair compare-connect mode, comparison occurs just as for 3-pair comparison except that only 2 pairs from the three compared need to conform with the valid data. At this point, the encode sequence is re-started and data is written to VWA. In direct-connect mode, comparison is not performed at all, and encode sequence starts and data is written to the VWA. This mode is for systems that cannot perform compare-connect operation. - Compare-connect preparation time 1. Comparison data preparation time 2. After the above preparation is finished, data is input beginning from the left-channel data and comparison starts. - Compare-connect sequence stop pre If a compare-connect stop command (80H with MSDCN1= 1, MSDCN2= 0) is input from the microcontroller, compare-connect sequence stops. lim Internally, when the compare-connect start command is issued, a sequence starts to restore the data for comparison. The time required for this preparation after receiving the command is approximately 2.5 x (1/fs). (approximately 60 s when fs = 44.1 kHz) ina ry 3. If the compare-connect command is issued again, the preparation time above is not necessary and operation starts from step 2. 4. The same sequence takes place in direct-connect mode also. However, at the point when 3 words have been input, all data is directly connected as if comparison and conformance had taken place. If compare-connect sequence was not operating, the compare-connect stop command performs no operation. However, make sure that the other bit settings within the same 80H command are valid. SM5901AF Encode sequence temporary stop - When RAM becomes full, MSWREN is set LOW using the 80H command and encode sequence stops. (For details of the stop conditions, refer to the description of the ENCOD flag.) - Then, if MSWREN is set HIGH without issuing a compare-connect start command, the encode sequence re-starts. At this time, newly input data is written not to VWA, but to WA. In this way, the data already written to the region between VWA and WA is not lost. - But if the MSWREN is set HIGH (80H command) after using the compare-connect start command even only once, data is written to VWA. If data is input before comparison and conformance is detected, the same operation as direct-connect mode takes place when the command is issued. After comparison and conformance are detected, no operation is performed because the encode sequence has already been started. However, make sure that the other bit settings within the same 80H command are valid. DRAM refresh - DRAM initialization refresh A 15-cycle RAS-only refresh is carried out for DRAM initialization under the following condition. When from MSON=1, MSRDEN=0 and MSWREN=0 states only MSWREN changes to 1. In this case, encode sequence immediately starts and initial data is written (at 2fs rate input) after a delay of 0.7ms. - Refresh during Shock-proof mode operation pre Data compression mode 4 bit 5 bit 6 bit Full bit In this IC, a data access operation to any address also serves as a data refresh. Accordingly, there are no specific refresh cycles other than the initialization refresh cycle (described above). lim When MSON changes from 0 to 1 in command 80H. Table 2. Decode sequence refresh rate ina ry 1M DRAM (256Kx4 bits) 5.44 ms 4.35 ms 3.63 ms 1.36 ms This has the resulting effect of saving on DRAM power dissipation. A data access to DRAM can occur in an encode sequence write operation or in a decode sequence read operation. In an encode sequence write operation the connect operation is stopped, while in a decode sequence read operation the data is always output to the D/A converter in a fixed manner. The refresh rate for each DRAM during decode sequence is shown in the table below. The decode sequence, set by MSON=1 and MSRDEN=1, operates when valid data is in DRAM (when MSEMP=0). - When MSON=0 or both ENCOD and DECOD=0 (both encode sequence and decode sequence are stopped), DRAM is not refreshed because no data is being accessed. SM5901AF Selecting compression mode Even when the compression mode in selected with the 85H command during shock-proof operation,no malfunction occurs. The compression mode change is not performed immediately after input of the 85H command, but it is performed at the following timing. After changing the mode, zero data of one block is output. YMLD When 85H generated WA CAS 3FE 3FF RA CAS Encode compression mode 3FD A Decode compression mode ZSRDATA (note) CAS-000 is connect data. pre lim ina ry 001 002 003 004 005 3FE 3FF 001 002 B A B SM5901AF Through-mode operation If MSON is set LOW (80H command), an operating mode that does not perform shock-proof functions becomes active. In this case, input data is passed as-is (after attenuator and mute operations) to the output. External DRAM is not accessed. - In this case, input data needs to be at a rate fs and the input word clock must be synchronized to the CLK input (384fs). However, short range jitter can be tolerated (jitter-free system). - Jitter-free system timing starts from the first YLRCK rising edge after either (A) a reset (NESET= 0) release by taking the reset input from LOW to HIGH or (B) by taking MSON from HIGH to LOW. Accordingly, to provide for the largest possible jitter margin, it is necessary that the YLRCK clock be at rate fs by the time jitter-free timing starts. The jitter margin is 0.2/ fs. Attenuation - The attenuation register is set by the 84H command. - The attenuation register set value becomes active when the 83H command sets the ATT flag to 1. When the ATT flag is 0, the attenuation register value is considered to be the equivalent of 256 for a maximum gain of 0 dB. - The gain (dB) is given from the set value (Datt) by the following equation. Gain = 20 x log(Datt/256) [dB]; left and right channels pre set 1 Gain set 2 - For the maximum attenuation register set value (Datt = 255), the corresponding gain is -0.03 dB. But when the ATT flag is 0 (Datt = 256), there is no attenuation. lim set 3 Fig 3 Attenuation operation example ina ry set 5 set 4 time This jitter margin is the allowable difference between the system clock (CLK) 1/ 384 divided, fs rate clock and the YLRCK input clock. If the timing difference exceeds the jitter margin, irregular operation like data being output twice or conversely complete "1" data output may occur. In the worst case, a click noise will also be generated. - After a system reset initialization, the attenuation register is set to 64 (-12 dB). However, because the ATT flag is reset to 0, there is no attenuation. - When the attenuation register setting changes or when the ATT flag changes, the gain changes smoothly from the previous set gain towards the new set value. If a new value for the attenuation level is set before the previously set level is reached, the gain changes smoothly towards the latest setting. The gain changes at a rate of 4 x (1/fs) per step. A full-scale change (255 steps) takes approximately 23.3 ms (when fs = 44.1 kHz). See fig 3. SM5901AF Soft mute Soft mute operation is controlled by the SOFT flag using a built-in attenuation counter. Mute is ON when the SOFT flag is 1. When ON, the attenuation counter output decrement by 1 step at a time, thereby reducing the gain. Complete mute takes 1024/fs (or approximately 23.2 ms for fs = 44.1 kHz). Conversely, mute is released when the SOFT flag is 0. In this case, the attenuation counter instantaneously increases. The attenuation register takes on the value when the ATT flag was 1. If the ATT flag was 0, the new set value is 256 (0 dB). SOFT Attenation level or full scale (Gain) - Fig 4. Soft mute operation example Force mute Serial output data is muted by setting the YDMUTE pin input HIGH or by setting the MUTE flag to 1. Mute starts and finishes on the leading left-channel bit. 12-bit comparison connection pre When the CMP12 flag is set to 1, the least significant 4 bits of the 16-bit comparison connection input data are discarded and comparison connection is performed using the remaining 12 bits. lim ina ry 256 step / 1024TS When MSON is HIGH and valid data is empty (MSEMP=H), the output is automatically forced into the mute state. Note that if the CMP12 flag is set to 1 during a comparison connection operation, only the most significant 12 bits are used for comparison connection from that point on. SM5901AF Timing charts Input timing (YSCK, YSRDATA, YLRCK) 16 16 YSCK LSB ina ry L channel R channel MSB LSB MSB LSB YSRDATA YLRCK 1/2fs Output timing (ZSCK, ZSRDATA, ZLRCK) 1 9 24 33 48 ZSCK ZSRDATA ZLRCK lim L channel MSB LSB LSB R channel MSB LSB 1/fs pre SM5901AF DRAM write timing (NRAS, NCAS2, NWE, A0 to A8, D0 to D3) Write timing (when external DRAM is used) t RASL NRAS t RASH NCAS2 (DRAM2 SSELECT) tRADS A0 to A8 t RADH t CWDS D0 to D3 (WRITE) NWE DRAM read timing (NRAS, NCA2, NWE, A0 to A8, D0 to D3) Read timing (when external DRAM is used) lim t RASL t RCD t RADS tRADH t CADS NRAS NCAS2 (DRAM2 SSELECT) pre D0 to D3 (READ) NWE A0 to A8 ina ry t RCD t CASL t CASH t CADS t CADH t CWDH t WEL t RASH t CASL t CASH t CADH t CRDS t CRDH SM5901AF Connection example SM5901 Microcontroller YMDATA YMCLK YMLD ZSENSE UC1 to UC4 DRAM 2 DSP Matsushita MN662740 YBLKCK YFLAG YFCLK YLRCK YSCK YSRDATA D/A converter ZLRCK ZSCK ZSRDATA CLK NRESET YDMUTE lim Microcontroller YMDATA YMCLK YMLD ZSENSE SCOR XROF DSP SONY CXD2517 YBLKCK YFLAG YFCLK pre D/A converter GND YLRCK YSCK YSRDATA ZLRCK ZSCK ZSRDATA CLK NRESET YDMUTE note1 - When external DRAM is used, the DRAM OE pins should be tied LOW. note 2 When CXD 2517 (Sony) is used Set 85H of microcontroller comand (option setting) as setting YFLAG take in; D5: YFLAGS= 1 D4: YFCKP= 0 ina ry NRAS NWE A0 to A8 D0 to D3 NCAS RAS WE A0 to A8 D0 to D3 CAS OE GND SM5901 UC1 to UC4 DRAM 2 RAS WE A0 to A8 D0 to D3 CAS OE GND NRAS NWE A0 to A8 D0 to D3 NCAS SM5901AF pre NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. lim NIPPON PRECISION CIRCUITS INC. 4-3, 2-chome Fukuzumi, Koto-ku Tokyo, 135 -8430, JAPAN Telephon: 03-3642-6661 Facsimile: 03-3642-6698 NC9607BE 1996.8 ina ry |
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