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(R)
VNQ05XSP16
QUAD CHANNEL HIGH SIDE SOLID STATE RELAY
TYPE VNQ05XSP16
(*) Per each channel
s s
RON(*) 110m
IOUT 5A (*)
VCC 36 V
OUTPUT CURRENT (CONTINUOUS): 5A CMOS COMPATIBLE INPUTS s MULTIPLEXED PROPORTIONAL LOAD CURRENT SENSE s UNDERVOLTAGE & OVERVOLTAGE SHUT- DOWN s OVERVOLTAGE CLAMP s THERMAL SHUT DOWN s CURRENT LIMITATION s VERY LOW STAND-BY POWER DISSIPATION s PROTECTION AGAINST: n LOSS OF GROUND & LOSS OF VCC s REVERSE BATTERY PROTECTION (**) DESCRIPTION The VNQ05XSP16 is a monolithic device designed in STMicroelectronics VIPower M0-3
PowerSO-16TM ORDER CODES
PACKAGE TUBE T&R PowerSO-16TM VNQ05XSP16 VNQ05XSP1613TR
Technology. It is intended for driving any type of multiple loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device has four independent channels and one multiplexed analog sense output which deliver a current proportional to the selected output current. SenseEnable pin allows to connect any number of VNQ05XSP16 on the same Current Sense line. Active current limitation combined with thermal shut-down and automatic restart protect the device against overload. Device automatically turns off in case of ground pin disconnection.
Value 41 -0.3 Internally limited -5 +/- 10 -3 +15 -200 4000 2000 5000 5000 78 76 Internally limited - 40 to 150 -55 to 150 Unit V V A A mA V V mA V V V V W mJ C C C
ABSOLUTE MAXIMUM RATING
Symbol VCC -VCC IOUT IR IIN VCSENSE IGND Parameter Supply voltage (continuous) Reverse supply voltage (continuous) Output current (continuous), for each channel Reverse output current (continuous), for each channel Input current (IN1,IN2,IN3,IN4,SELA,SELB,SENSENABLE) Current sense maximum voltage Ground current at Tcase<25C (continuous) Electrostatic Discharge (Human Body Model: R=1.5; C=100pF) - INPUT VESD - CURRENT SENSE - OUTPUT Ptot EMAX Tj Tc TSTG - VCC Power dissipation at Tcase=25C Maximum Switching Energy (L=1.72mH; RL=0; Vbat=13.5V; Tjstart=150C; IL=7.5A) Junction operating temperature Case Operating Temperature Storage temperature
(**) See application schematic at page 9
March 2003
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VNQ05XSP16
BLOCK DIAGRAM
VCC
OVERVOLTAGE UNDERVOLTAGE
INPUT 1 INPUT 2 INPUT 3 INPUT 4 OVERTEMP. 1 OVERTEMP. 2 OVERTEMP. 3 OVERTEMP. 4 SELECT A SELECT B SENSE ENABLE DIAG LOGIC
DRIVER 1
DEMAG 1 LOGIC ILIM 1 VdsLIM 1 Ot1 CS1 K IOUT1 OUTPUT 1
Same structure for the channels2,3,4
OUTPUT 2 OUTPUT 3 OUTPUT 4
GND QUAD ANALOG Mux
CURRENT SENSE
CS1 CS2 CS3 CS4
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VNQ05XSP16
CURRENT AND VOLTAGE CONVENTIONS
IS VCC VCC IIN1 VIN1 VIN2 VIN3 VIN4 VSENSE VSELA IIN2 IIN3 IIN4 ISENSE ISELA ISELB INPUT1 INPUT2 INPUT3 INPUT4 SENSE SELA SELB SENSENABLE GND IGND OUTPUT4 OUTPUT2 IOUT3 OUTPUT3 IOUT4 VOUT4 VOUT3 VOUT2 OUTPUT1 IOUT2 VOUT1 IOUT1
VSELB ISENSENABLE VSENSENABLE
CONNECTION DIAGRAM (TOP VIEW)
INPUT 1 INPUT 2 INPUT 3 INPUT 4 C.SENSE SENSENABLE SELA SELB
9 10 11 12 13 14 15 16 17 VCC
8 7 6 5 4 3 2 1
GROUND N.C. OUTPUT 1 OUTPUT 2 N.C. OUTPUT 3 OUTPUT 4 VCC
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VNQ05XSP16
THERMAL DATA Symbol Rthj-case Rthj-amb Parameter Thermal resistance junction-case Thermal resistance junction-ambient (MAX) (MAX) Value 1.6 51.6 (*) Unit C/W C/W
(*) When mounted on FR4 printed circuit board with 0.5 cm of copper area (at least 35 m thick) connected to all VCC pins ELECTRICAL CHARACTERISTICS (8VIOUT1,2,3,4=1A; Tj=25C IOUT1,2,3,4=1A; Tj=150C IOUT1,2,3,4=0.5A; VCC=6V ICC=20mA (See note 1) Off state; Inputs=n.c.; VCC=13V On state; VIN=5V; VCC=13V; IOUT=0A; RSENSE=3.9k VIN=VOUT=0V VIN=0V; VOUT=3.5V VIN=VOUT=0V; Vcc=13V; Tj=125C VIN=VOUT=0V; Vcc=13V; Tj=25C
SWITCHING (VCC=13V) Symbol td(on) td(off) (dVOUT/ dt)on (dVOUT/ dt)off Parameter Turn-on delay time Turn-off delay time Turn-on voltage slope Test Conditions RL=2.6 channels 1,2,3,4 (see figure 2) RL=2.6 channels 1,2,3,4 (see figure 2) RL=2.6 channels 1,2,3,4 (see figure 2) Min Typ 40 40 See relative diagram See relative diagram Max Unit s s V/s
Turn-off voltage slope
RL=2.6 channels 1,2,3,4 (see figure 2)
V/s
PROTECTIONS Symbol Ilim TTSD TR THYST Vdemag VON Parameter DC short circuit current Thermal shut down temperature Thermal reset temperature Thermal hysteresis Turn-off output voltage clamp Output voltage drop limitation VCC=13V 5.5VVCC-41 VCC-48 VCC-55 50
Note 1: Vclamp and VOV are correlated. Typical difference is 5V.
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VNQ05XSP16
CURRENT SENSE (9V< VCC <16V)
Symbol K1 dK1/K1 K2 dK2/K2 K3 dK3/K3 Parameter IOUT/ISENSE Test Conditions IOUT=0.1A; VSENSE=0.5V Min 650 -10 800 -8 850 -6 1000 1000 Typ 950 Max 1200 +10 1200 +8 1150 +6 % A % % Unit
Tj=-40...+150C Current Sense Ratio IOUT=0.1A; VSENSE=0.5V; Drift Tj= -40C...+150C IOUT=1.0A, VSENSE=4V IOUT/ISENSE Tj=-40...+150C Current Sense Ratio IOUT=1.0A; VSENSE=4V; Drift Tj=-40C...+150C IOUT/ISENSE IOUT=2.0A, VSENSE=4V Tj=-40...+150C Current Sense Ratio IOUT=2.0A; VSENSE=4V; Drift Tj=-40C...+150C Analog Sense Leakage Current VCC=6...16V; IOUT=0A;VSENSE=0V; Tj=-40C...+150C VCC=5.5V, IOUT1,2,3,4=1.0A RSENSE=10k VCC>8V, IOUT1,2,3,4=2.0A RSENSE=10k
ISENSEO
0
10
VSENSE1,2,3,4
Max analog sense output voltage
2 4 5.5
V V V
VSENSEH
RVSENSEH
tDSENSE
Analog sense output voltage in VCC=13V; RSENSE= 3.9k overtemperature condition Analog sense output VCC=13V; Tj>TTSD; impedance in overtemperature All Channels Open condition VCC=13V; RSENSE=3.9k Current sense delay (see note 2)
400
300
500
s
LOGIC CHARACTERISTICS (Inputs, Sela&b, Sensenable)
Symbol VIL VIH VI(hyst) IIL IIN VICL Parameter Input low level voltage Input high level voltage Input hysteresis voltage Low level input current High level input current Input clamp voltage Test Conditions Min Typ Max 1.25 3.25 0.5 VIN=1.25V VIN=3.25V IIN=1mA IIN=-1mA 6 6.8 -0.7 1 10 8 Unit V V V A A V V
Note 2: current sense signal delay after positive input slope. Note: Sense pin doesn't have to be left floating.
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VNQ05XSP16
TRUTH TABLE
CONDITIONS Normal operation Overtemperature Undervoltage Overvoltage INPUT L H L H L H L H L H H L H L OUTPUT L H L L L L L L L L L H H L SENSE 0 Nominal 0 VSENSEH 0 0 0 0 0 (TjTTSD) VSENSEH 0 < Nominal 0
Short circuit to GND
Short circuit to VCC Negative output voltage clamp
TRUTH TABLE
SENSENABLE L H H H H Figure 1: IOUT/ISENSE versus IOUT SELB X L L H H SELA X L H L H SENSE High Impedance ISENSE=IOUT1/K ISENSE=IOUT2/K ISENSE=IOUT3/K ISENSE=IOUT4/K
IOUT/ISENSE
1500 1400 1300 1200 1100 1000 900 800 700 600 500 0 1 2 3 4 5 6 7 8 9 10 min. Tj=-40C<<150C max. Tj=-40C<<150C typical value
IOUT (A)
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VNQ05XSP16
ELECTRICAL TRANSIENT REQUIREMENTS
ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 Class C E Test Levels I -25V +25V -25V +25V -4V +26.5V Test Levels II -50V +50V -50V +50V -5V +46.5V Test Levels III -75V +75V -100V +75V -6V +66.5V Test Levels IV -100V +100V -150V +100V -7V +86.5V Test Levels Result III C C C C C E Test Levels Delays and Impedance 2ms, 10 0.2ms, 10 0.1s, 50 0.1s, 50 10ms, 0.01 400ms, 2 Test Levels Result IV C C C C C E
Test Levels Result I C C C C C C
Test Levels Result II C C C C C E
Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device.
Figure 2: Switching Characteristics (Resistive load RL=1.3)
VOUT
80% dVOUT/dt(on) tr ISENSE 90% 10%
90% dVOUT/dt(off) tf t
INPUT
tDSENSE
t td(off)
td(on)
t
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VNQ05XSP16
Figure 3: Waveforms
NORMAL OPERATION (for example: Channel1 is ON) INPUT1 LOAD CURRENT1 SENSE1 SENSEN UNDERVOLTAGE VCC INPUT1 LOAD CURRENT1 SENSE1 SENSEN OVERVOLTAGE
VOV VUSD VUSDhyst
VCC INPUT1 LOAD CURRENT1 SENSE1 SENSEN
VCC < VOV
VCC > VOV
SHORT TO GROUND INPUT1 LOAD CURRENT1 LOAD VOLTAGE1 SENSE1 SENSEN SHORT TO VCC INPUT1 LOAD VOLTAGE1 LOAD CURRENT1 SENSE1 SENSEN OVERTEMPERATURE Tj INPUT1 LOAD CURRENT1 SENSE1 SENSEN
ISENSE= VSENSEH RSENSE TTSD TR
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VNQ05XSP16
APPLICATION SCHEMATIC
+5V Rprot INPUT1 VCC Dld Rprot INPUT2 Rprot INPUT3 C Rprot INPUT4 OUTPUT2 Rprot SELA Rprot SESB Rprot SENSENABLE OUTPUT4 A/D CFILTER CPAR RSENSE RGND DGND VGND Rprot C. SENSE GND OUTPUT3 OUTPUT1
Notes: Input1,2,3,4, SELA, SELB, SENSENABLE have the same structure. RSENSE x CPAR <10s
GND PROTECTION REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / (IS(on)max). 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device's datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below).
Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table.
C I/Os PROTECTION:
If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended Rprot value is 10k.
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VNQ05XSP16
Off State Output Current
IL(off) (A)
5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
High Level Input Current
Iih (A)
5 4.5
Off state Vcc=36V Vin=Vout=0V
Vin=3.25V
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Input Clamp Voltage
Vicl (V)
8 7.75
Input High Level
Vih (V)
3.6 3.4
Iin=1mA
7.5 7.25 7 6.75 6.5 6.25 6 -50 -25 0 25 50 75 100 125 150 175 3.2 3 2.8 2.6 2.4 2.2 2 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Overvoltage Shutdown
Vov (V)
50 47.5 45 42.5 40 37.5 35 32.5 30 -50 -25 0 25 50 75 100 125 150 175
ILIM Vs Tcase
Ilim (A)
20 17.5
Vcc=13V
15 12.5 10 7.5 5 2.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
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VNQ05XSP16
Turn-on Voltage Slope
dVout/dt(on) (V/ms)
500 450 400 350 300 250 200 150 100 50 0 -50 -25 0 25 50 75 100 125 150 175
Turn-off Voltage Slope
dVout/dt(off) (V/ms)
600 550
Vcc=13V Rl=2.6Ohm
500 450 400 350 300 250 200 150 100 50 0 -50
Vcc=13V Rl=2.6Ohm
-25
0
25
50
75
100
125
150
175
Tc (C)
Tc (C)
On State Resistance Vs Tcase
Ron (mOhm)
250 225 200 175 150 125 100 75
On State Resistance Vs VCC
Ron (mOhm)
200 175
Iout=1A Vcc=8V & 36V
Tc=150C
150
Iout=1A
125 100 75 50
Tc=25C Tc=-40C
50 25 0 -50 -25 0 25 50 75 100 125 150 175
25 0 5 10 15 20 25 30 35 40
Tc (C)
Vcc (V)
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VNQ05XSP16
Maximum turn off current versus load inductance
ILMAX (A) 100
10
A B C
1 0.01
A = Single Pulse at TJstart=150C B= Repetitive pulse at TJstart=100C C= Repetitive Pulse at TJstart=125C Conditions: VCC=13.5V Values are generated with RL=0 In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization
0.1 L(mH)
1
10
t
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VNQ05XSP16
PowerSO-16TM THERMAL DATA
PowerSO-16TM PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 60mm x 60mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: 6cm2).
Rthj-amb Vs PCB copper area in open box free air condition
RTHj_amb (C/W)
55
Tj-Tamb=50C
50 45 40 35 30
0 2 4 6 8 10
PCB Cu heatsink area (cm^2)
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VNQ05XSP16
Thermal Impedance Junction Ambient Single Pulse
ZT H (C/W) 1000
100
Footprint 6 cm2
10
1
0.1 0.0001 0.001 0.01 0.1 1 T ime (s) 10 100 1000
Thermal fitting model of a quad HSD in PowerSO-16
Pulse calculation formula
Z TH = R TH + ZTHtp ( 1 - )
where
Tj_1
C1
C2
C3
C4
C5
C6
= tp T
Footprint 0.18 0.8 0.7 0.8 13 37 0.0006 1.50E-03 1.75E-02 0.4 0.75 3 6
R1 Pd1 C13
R2
R3
R4
R5
R6
Thermal Parameter
Area/island (cm2) R1 (C/W) R2 (C/W) R3 ( C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1 (W.s/C) C2 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C)
Tj_2
C14
R13 Pd2
R14
R17
R18
Tj_3
C7
C8
C9
C10
C11
C12
22
R7 Pd3 C15
R8
R9
R10
R11
R12
Tj_4
C16
R15 Pd4
R16
T_amb
5
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VNQ05XSP16
POWERSO-16TM MECHANICAL DATA
DIM. A1 A2 A3 A4 a b c D D1 d E (1) E1 E2 E3 e e1 F G L R1 R2 T T1 T2 Package Weight MIN. 0 3.4 1.2 0.15 0.27 0.23 9.4 7.4 0 13.85 9.3 7.3 5.9 mm. TYP 0.05 3.5 1.3 0.2 0.2 0.35 0.27 9.5 7.5 0.05 14.1 9.4 7.4 6.1 0.8 5.6 0.5 1.2 1 0.8 5 6 (typ.) 10 (typ.) (typ.) MAX. 0.1 3.6 1.4 0.25 0.43 0.32 9.6 7.6 0.1 14.35 9.5 7.5 6.3
0.8
1.1 0.25 8
2
P013Q
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VNQ05XSP16
PowerSO-16TM SUGGESTED PAD LAYOUT
0.8 +/- 0.1 2 +/- 0.14
TUBE SHIPMENT (no suffix)
0.5 +/- 0.1
A
C
7.4 +/- 0.1
10 +/- 0.1
B
All dimensions are in mm. Base Q.ty Bulk Q.ty Tube length ( 0.5) 50 1000 532 A B C ( 0.1) 0.8
4.9 17.2
10.5 +/- 0.1
TAPE AND REEL SHIPMENT (suffix "13TR")
REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 24 4 24 1.5 1.5 11.5 6.5 2
End
All dimensions are in mm.
Start Top cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min No components Components No components
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VNQ05XSP16
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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