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A-Data
Revision History Revision 1 ( Dec. 2001 )
1.Fister release.
ADD8616A8A
Revision 2 ( Apr. 2002 )
1. Changed module current specification. 2. Add Performance range. 3. Changed AC Characteristics. 4. Changed typo size on module PCB in package dimensions.
Rev 2 April, 2002
1
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Double Data Rate SDRAM General Description
The ADD8616A8A are four-bank Double Data Rate(DDR) Synchronous DRAMs organized as 4,194,304 words x 16 bits x 4 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Data outputs occur at both rising edges of CK and /CK. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications
ADD8616A8A
4M x 16 Bit x 4 Banks Features
*2.5V for VDDQ power supply *SSTL_2 interface *MRS Cycle with address key programs -CAS Latency (2, 2.5) -Burst Length (2,4 &8) -Burst Type (sequential & Interleave) *4 banks operation *Differential clock input (CK, /CK) operation *Double data rate interface *Auto & Self refresh *8192 refresh cycle *DQM for masking *Package:66-pins 400 mil TSOP-Type II
Ordering Information.
Part No. VDD8608A8A-75BA ADD8616A8A-75B Frequency 133Mhz(7.5ns /CL=2) 133Mhz(7.5ns /CL=2.5) Interface SSTL_2 Package 400mil 66pin TSOPII
Pin Assignment
VD D D Q0 VDD Q NC DQ1 VSSQ NC DQ2 VDD Q NC DQ3 VSSQ NC NC V DQ D NC NC
VD D NC
NC
WE CAS RAS CS NC BA0
BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
VS S DQ7 V S SQ NC DQ6 VDDQ NC DQ5 V S SQ NC DQ4 VDD Q NC NC VS S Q DQS NC VR E F VS S DM
CK CK CKE NC NC A11 A9 A8 A7
A6 A5 A4 VS S
66-pin plastic TSOP II 400 mil
Rev 2 April, 2002
2
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Pin Description
PIN CK, /CK CKE NAME System Clock Clock Enable Differential clock input. FUNCTION
ADD8616A8A
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least on cycle prior new command. Disable input buffers for power down in standby
/CS A0~A12
Chip Select Address
Disables or Enables device operation by masking or enabling all input except CK, CKE and DQ Row / Column address are multiplexed on the same pins. Row address : A0~A12 Column address : A0~A9
BS0~BS1
Banks Select
Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. Data inputs / outputs are multiplexed on the same pins. Latches row addresses on the positive edge of the CLK with /RAS low Latches Column addresses on the positive edge of the CLK with /CAS low Enables write operation and row recharge. Power and Ground for the input buffers and the core logic. Power supply for output buffers. Reference voltage for inputs for SSTL interface. This pin is recommended to be left No Connection on the device.
DQ0~DQ15 Data /RAS /CAS /WE VDD/VSS VREF NC Row Address Strobe Column Address Strobe Write Enable Power Supply/Ground Reference Voltage No Connection
VDDQ/VSSQ Data Output Power/Ground
Block Diagram
CK CKE Address
Clock Generator
Bank3 Bank2 Bank1
Row Decoder
Mode Register
Address Buffer & Refresh Counter
Bank0
Amplifier
Command Decoder
/RAS /CAS /WE
Control Logic
/CS
Data Latch
Column Address Buffer & Refresh Counter
Column Decoder
DQM DQS
Data Control Circuit
DQ0~DQn
Rev 2 April, 2002
3
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Absolute Maximum Ratings
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, Vout VDD, VDDQ TSTG PD IOUT Value -0.3 ~ VDDQ+0.3 -0.3 ~ 3.6 -55 ~ +150 1 50
ADD8616A8A
Unit V V W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 Parameter Supply voltage Supply voltage Input logic high voltage Input logic low voltage Differential Clock DC Input voltage Input Differential CLK&/CLK voltage Input leakage current Output leakage current Reference Voltage Termination Voltage Symbol VDD VDDQ VIH VIL VICK VID IIL IOL VREF VTT Min 2.3 2.3 VREF+0.15 -0.3 -0.3 0.7 -5 -5 0.49* VDDQ VREF-0.04 Max 2.7 VDD VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6 5 5 0.51* VDDQ VREF+0.04 V V V V uA uA V V 5 3 4 2 Unit V 1 Note
Note : 1. VDDQ must not exceed the level of VDDQ. 2.VIL(min)=-0.9V with a pulse width 5ns . 3.Any input 0V VIN 3.6V, all other pins are not under test = 0V. 4.Dout is disabled, 0V VOUT 2.7V. 5. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on VREF may not exceed 2% of the DC value.
Rev 2 April, 2002
4
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AC Test Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 Parameter AC input high level voltage AC input low level voltage Input Reference Voltage Termination Voltage Input Signal Peak to Peak Swing Input Difference Voltage. CLK and /CLK Inputs Symbol VIH VIL VREF VTT VSWING VID Value VREF+0.31 VREF-0.31 0.5xVDDQ 0.5xVDDQ 1.0 1.5
ADD8616A8A
Unit V V V V V V
Note
Capacitance
TA=25, f-=1Mhz Parameter Input capacitance CK, /CK A0~A12,BS0,BS1,CKE,/CS,/RAS, /CAS,/WE,DQM Data input / output capacitance DQM CI/O 4 5 pF Pin Symbol Cl1 Cl2 Min 2 2 Max 3.0 3.0 Unit pF pF
Output load circuit
Vtt=0.5*VDDQ
RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*V DDQ
Output Load Circuit (SSTL_2)
Rev 2 April, 2002
5
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DC Characteristics II
Speed Parameter Symbol Test condition -75BA/ -75B Burst length=2, One bank active Operating Current Precharge standby current in power down mode IDD2P CKEVIL(max), tCK=min 20 IDD1 Trc=tRC(min),IOUT=0mA 110
ADD8616A8A
Unit
Note
mA
1
mA
Precharge standby current in Non power IDD2N down mode
CKEVIH(min), /CSVIH(min), tCK= tCK min input signals are changed one time during 2clks. 40 mA
Active standby current in power down mode IDD3P CKEVIL(max), tCK= tCK min 20 mA
Active standby current in Non power IDD3N down mode
CKEVIH(min), /CSVIH(min), tCK=min input signals are changed one time during 2clks. 65 mA
Burst mode operating IDD4R current Auto refresh current Self refresh current IDD5
tCKtCK(min),IOUT=0 mA 155 All banks active tRRCtRRC(min), All banks 190 active IDD6 CKE0.2V 3 mA mA 2 mA 1
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRRC is shown at AC characteristics.
Rev 2 April, 2002
6
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AC Characteristics
-75BA Parameter System clock /CAS Latency = 2.5 Cycle time /CAS Latency = 2 Symbol Min tCK2.5 tCK2 tCHW tCLW tAC tDQSCK tDQSS tRC tRCD tRAS tRP tRRD tCCD tDS tDH tDSS 7.5 7.5 0.45 0.45 -0.75 -0.75 0.75 65 20 45 20 15 1 0.5 0.5 0.2 0.2 0.9 0.9 0.35 0.35 0 0.4 Max 12 12 0.55 0.55 0.75 0.75 1.25 120K 06 0.5 15 0.9 1.1 15 0.9 1.1 Min 7.5 10 0.45 0.45 -0.75 -0.75 0.75 65 20 45 20 15 1 0.5 0.5 0.2 0.2 0.9 0.9 0.35 0.35 0 0.4 Max 12 12 0.55 0.55 0.75 0.75 1.25 120K 06 0.5 -75B
ADD8616A8A
Unit
ns CLK CLK ns ns CLK ns ns ns ns ns CLK ns ns CLK CLK ns ns CLK CLK ns CLK ns
Clock high pulse width Clock low pulse width Access time form CK to /CK Data strobe edge to clock edge Clock to first rising edge of DQS delay /RAS cycle time /RAS to /CAS delay /RAS active time /RAS precharge time /RAS to /RAS bank active delay /CAS to /CAS delay Data-in setup time (to DQS) Data-in hold time (to DQS) DQS Falling Edge to CLK Setup Time
DQS Falling Edge Hold Time from CLK tDSH Input setup time Input hold time DQS-in high level width DQS-in low level width tIS tIH tDSH tDSL
Clock to DQS write preamble setup time tWPRES Write preamble Data strobe edge to output data edge Mode register set cycle time DQS read preamble tWPST tDQSQ tMRD tRPRE
CLK
Rev 2 April, 2002
7
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Command Truth-Table
SYM. MRS NOP ACT READ Command Mode Register Set No Operation Bank Active Read H X L H L H X CKEn-1 CKEn /CS /RAS /CAS /WE H H H X X X L L L L H L L H H L H H
ADD8616A8A
DM ADDR A10/AP X X X V H V L CA CA X
BS L
V V
READA Read with Auto Precharge WRIT Write
WRITA Write with Auto Precharge PREA BST AREF SELF SELEX Self Refresh Exit PD Entry Precharge Power down PDEX WDE WDD Data write Disable H Exit L H L Precharge All Bank Burst Stop Auto Refresh Entry H
H
X
L
H
L
L
X
V
L H
V
H H H L H
X X H L H L H
L L L L X H X H X H X X
L H L L X H X H X H X X
H H L H X
L L H X
X X X
X
H X X
X
X X
H X X H X X X X X L X H X
L L H H L
Enable
H
X X
X X
Rev 2 April, 2002
8
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Package Information
ADD8616A8A
66
34
1
33
SYMBOL A A1 A2 B c D HE E e L L1
MIN. 0.05 0.95 0.17 0.09 11.74 10.15 0.65 BSC 0.40
MILLIMETER NOM. 1.00 0.24 0.145 22.62 BSC 11.76 10.16 0.50 0.80 REF 0.71 REF -
MAX. 1.20 0.15 1.05 0.32 0.2 11.78 10.17 0.60
MIN. 0.002 0.037 0.007 0.004 0.462 0.3996 0.026 0.016
INCH NOM. 0.039 0.009 0.0006 0.891 BSC 0.463 0.400 0.020 0.031 REF 0.028 REF -
MAX. 0.047 0.006 0.041 0.013 0.008 0.464 0.4004 0.024
S
0
8
0
8
400mil 66pin TSOP II Package
Rev 2 April, 2002
9

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