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HM5117805 Series
2,097,152-word x 8-bit Dynamic RAM
ADE-203-630 C (Z) Rev. 3.0 Feb. 25, 1997
Description
The Hitachi HM5117805 is a CMOS dynamic RAM organized 2,097,152-word x 8-bit. It employs the most advanced CMOS technology for high performance and low power. The HM5117805 offers Extended Data Out (EDO) Page Mode as a high speed access mode. Multiplexed address input permits the HM5117805 to be packaged in standard 28-pin plastic SOJ and 28-pin TSOP.
Features
* * * Single 5 V (10%) Access time: 50 ns/60 ns/70 ns (max) Power dissipation Active mode: 605 mW/550 mW/495 mW (max) Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) EDO page mode capability Long refresh period 2048 refresh cycles : 32 ms : 128 ms (L-version) 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) Battery backup operation (L-version)
* *
*
*
HM5117805 Series
Ordering Information
Type No. HM5117805J-5 HM5117805J-6 HM5117805J-7 HM5117805LJ-5 HM5117805LJ -6 HM5117805LJ -7 HM5117805S-5 HM5117805S-6 HM5117805S-7 HM5117805LS-5 HM5117805LS-6 HM5117805LS-7 HM5117805TT-5 HM5117805TT-6 HM5117805TT-7 HM5117805LTT-5 HM5117805LTT-6 HM5117805LTT-7 HM5117805TS-5 HM5117805TS-6 HM5117805TS-7 HM5117805LTS-5 HM5117805LTS-6 HM5117805LTS-7 Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 300-mil 28-pin plastic TSOP II (TTP-28DB) 400-mil 28-pin plastic TSOP II (TTP-28DA) 300-mil 28-pin plastic SOJ (CP-28DNA) Package 400-mil 28-pin plastic SOJ (CP-28DA)
2
HM5117805 Series
Pin Arrangement
HM5117805J/LJ Series HM5117805S/LS Series
VCC I/O0 I/O1 I/O2 I/O3 WE RAS NC A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS I/O7 I/O6 I/O5 I/O4 CAS OE A9 A8 A7 A6 A5 A4 VSS
HM5117805TT/LTT Series HM5117805TS/LTS Series VCC I/O0 I/O1 I/O2 I/O3 WE RAS NC A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top view) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS I/O7 I/O6 I/O5 I/O4 CAS OE A9 A8 A7 A6 A5 A4 VSS
(Top view)
Pin Description
Pin name A0 to A10 Function Address input -- Row/Refresh address A0 to A10 -- Column address A0 to A9 Data input/Data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground No connection
I/O0 to I/O7 RAS CAS WE OE VCC VSS NC
3
HM5117805 Series
Block Diagram
RAS CAS WE OE
Timing and control
A0 A1 to A9 Row decoder * * * Column address buffers
Column decoder 2M array 2M array 2M array 2M array 2M array 2M array 2M array 2M array I/O buffers I/O0 to I/O7
* * *
Row address buffers
A10
4
HM5117805 Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Input high voltage Input low voltage Note: Symbol VCC VIH VIL Min 4.5 2.4 -1.0 Typ 5.0 -- -- Max 5.5 6.5 0.8 Unit V V V Note 1 1 1
1. All voltage referred to VSS .
5
HM5117805 Series
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)
HM5117805 -5 Parameter Operating current* * Standby current
1, 2
-6
-7 Test conditions tRC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z tRC = min RAS = VIH CAS = VIL Dout = enable tRC = min tHPC = min CMOS interface Dout = High-Z CBR refresh: tRC = 62.5 s tRAS 0.3 s CMOS interface RAS, CAS 0.2V Dout = High-Z 0 V Vin 7 V 0 V Vout 7 V Dout = disable High Iout = -2 mA Low Iout = 2 mA
Symbol ICC1 ICC2
Min Max Min Max Min Max Unit -- -- 110 -- 2 -- 100 -- 2 -- 90 2 mA mA
--
1
--
1
--
1
mA
Standby current (L-version) RAS-only refresh current*2 Standby current*
1
ICC2
--
150 --
150 --
150 A
ICC3 ICC5
-- --
110 -- 5 --
100 -- 5 --
90 5
mA mA
CAS-before-RAS refresh current EDO page mode current*1, *3 Battery backup current*4 (Standby with CBR refresh) (L-version)
ICC6 ICC7 ICC10
-- -- --
110 -- 100 -- 500 --
100 -- 90 --
90 85
mA mA
500 --
500 A
Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage
ICC11
--
300 --
300 --
300 A
ILI ILO VOH VOL
-10 10 -10 10 2.4 0
-10 10 -10 10
-10 10 -10 10 VCC 0.4
A A V V
VCC 2.4 0.4 0
VCC 2.4 0.4 0
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L ( 0.2 V) while RAS = L ( 0.2 V).
6
HM5117805 Series
Capacitance (Ta = 25C, VCC = 5 V 10%)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *2, *18
Test Conditions * * * * * Input rise and fall time: 2 ns Input levels: VIL = 0 V, V IH = 3 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
7
HM5117805 Series
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5117805 -5 Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Symbol tRC tRP tCP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tOED tDZO tDZC tT Min 84 30 7 50 7 0 7 0 7 11 9 10 35 5 13 0 0 2 Max -- -- -- -6 Min 104 40 10 Max -- -- -- -7 Min 124 50 13 Max -- -- -- Unit ns ns ns Notes
10000 60 10000 10 -- -- -- -- 37 25 -- -- -- -- -- -- 50 0 10 0 10 14 12 13 40 5 15 0 0 2
10000 70 10000 13 -- -- -- -- 45 30 -- -- -- -- -- -- 50 0 10 0 13 14 12 13 45 5 18 0 0 2
10000 ns 10000 ns -- -- -- -- 52 35 -- -- -- -- -- -- 50 ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 3 4
8
HM5117805 Series
Read Cycle
HM5117805 -5 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time RAS next CAS delay time Symbol tRAC tCAC tAA tOEA tRCS tRCH Min -- -- -- -- 0 0 50 0 25 15 0 3 3 -- -- 13 3 -- -- 13 13 50 Max 50 13 25 13 -- -- -- -- -- -- -- -- -- 13 13 -- -- 13 13 -- -- -- -6 Min -- -- -- -- 0 0 60 0 30 18 0 3 3 -- -- 15 3 -- -- 15 15 60 Max 60 15 30 15 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -- -7 Min -- -- -- -- 0 0 70 0 35 23 0 3 3 -- -- 18 3 -- -- 18 18 70 Max 70 18 35 18 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 20 13 5 20 20 20 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9
Read command hold time from RAS tRCHR tRRH tRAL tCAL tCLZ tOH tOHO tOFF tOEZ tCDD tOHR tOFR tWEZ tWED tRDD tRNCD
9
HM5117805 Series
Write Cycle
HM5117805 -5 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol tWCS tWCH tWP tRWL tCWL tDS tDH Min 0 7 7 7 7 0 7 Max -- -- -- -- -- -- -- -6 Min 0 10 10 10 10 0 10 Max -- -- -- -- -- -- -- -7 Min 0 13 10 13 13 0 13 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 15 15 Notes 14
Read-Modify-Write Cycle
HM5117805 -5 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol tRWC tRWD tCWD tAWD tOEH Min 111 67 30 42 13 Max -- -- -- -- -- -6 Min 135 79 34 49 15 Max -- -- -- -- -- -7 Min 161 92 40 57 18 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes
Refresh Cycle
HM5117805 -5 Parameter CAS hold time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol Min 5 7 0 7 5 Max -- -- -- -- -- CAS setup time (CBR refresh cycle) tCSR tCHR WE setup time (CBR refresh cycle) tWRP tWRH tRPC -6 Min 5 10 0 10 5 Max -- -- -- -- -- -7 Min 5 10 0 10 5 Max -- -- -- -- -- Unit ns ns ns ns ns Notes
10
HM5117805 Series
EDO Page Mode Cycle
HM5117805 -5 Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge Symbol tHPC tRASP tCPA Min Max 20 -- -- 28 3 7 5 28 -- -6 Min Max 25 -- -7 Min Max 30 -- Unit ns Notes 19 16 9, 17
100000 -- 28 -- -- -- -- -- -- 35 3 10 5 35
100000 -- 35 -- -- -- -- -- -- 40 3 13 5 40
100000 ns 40 -- -- -- -- -- ns ns ns ns ns ns
RAS hold time from CAS precharge tCPRH Output data hold time from CAS low tDOH CAS hold time referred OE CAS to OE setup time tCOL tCOP
9, 17
Read command hold time from CAS tRCHC precharge
EDO Page Mode Read-Modify-Write Cycle
HM5117805 -5 Parameter Symbol Min 57 45 Max -- -- -6 Min 68 54 Max -- -- -7 Min 79 62 Max Unit ns ns 14 Notes
EDO page mode read- modify-write tHPRWC cycle time WE delay time from CAS precharge tCPW
Refresh
Parameter Refresh period Refresh period (L-version) Symbol tREF tREF Max 32 128 Unit ms ms Note 2048 cycles 2048 cycles
11
HM5117805 Series
Self Refresh Mode (L-version)
HM5117805L -5 Parameter RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Symbol tRASS tRPS tCHS Min 100 90 -50 Max -- -- -- -6 Min 100 110 -50 Max -- -- -- -7 Min 100 130 -50 Max -- -- -- Unit s ns ns Notes
Notes: 1. AC measurements assume tT = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either tOED or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that tRCD tRCD (max) and tRAD tRAD (max). 11. Assumes that tRCD tRCD (max) and tRAD tRAD (max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. tWCS , tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. tRASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among tAA , tCAC and tCPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device.
12
HM5117805 Series
19. tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified tHPC (min) value.The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 20. Data output turns off and becomes high impedance from later rising edge of RAS and CAS . Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between tOHR and tOH and between tOFR and tOFF. 21. Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If tRASS 100 s, then RAS precharge time should use tRPS instead of tRP. 22. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycles, 2048 cycles of distributed CBR refresh with 15.6 s interval should be executed within 32 ms immediately after exiting from and before entering into the self refresh mode. 23. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 24. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 25. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
13
HM5117805 Series
Timing Waveforms*25
Read Cycle
t RC t RAS t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS
t RAD t ASR t ASC t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCHR t RCS t RCH
WE t WED t DZC t CDD t RDD Din High-Z
t DZO
t OEA
t OED
OE t OEZ t OHO t OFF t OH t OFR t OHR t WEZ Dout Dout
t CAC t AA t RAC t CLZ
14
HM5117805 Series
Early Write Cycle
t RC t RAS t RP
RAS t CSH t RCD tT CAS t RSH t CAS t CRP
t ASR
t RAH
t ASC
t CAH
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z* * t WCS t WCS (min)
15
HM5117805 Series
Delayed Write Cycle*18
t RC t RAS
t RP
RAS t CSH t RCD tT CAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP
Address
Row
Column t CWL t RCS t RWL t WP
WE
t DZC
t DS
t DH
Din
High-Z
Din t OEH t OED
t DZO

OE t OEZ t CLZ Dout High-Z Invalid Dout 16
HM5117805 Series
Read-Modify-Write Cycle*18
t RWC t RAS
t RP
RAS tT t RCD t CAS t CRP
CAS t RAD t ASR t RAH t ASC t CAH
Address
Row t RCS
Column t CWD t AWD t RWD tCWL t RWL t WP
WE t DZC t DS Din
High-Z Din
t DH
t DZO
t OED t OEA
t OEH
OE t CAC t AA t RAC t OEZ t OHO
High-Z
Dout t CLZ
Dout
17
HM5117805 Series
RAS-Only Refresh Cycle
t RC t RAS RAS tT t CRP CAS t RPC t CRP t RP
t ASR Address t OFR t OFF Dout Row
t RAH
High-Z
18
HM5117805 Series
CAS-Before-RAS Refresh Cycle
t RC t RP RAS t RPC CAS t CSR tT t CHR t RPC t CRP t RAS t RP
,
t CP t WRP t WRH t CP WE Address t OFR t OFF Dout High-Z 19
HM5117805 Series
Hidden Refresh Cycle
t RC t RAS t RP
t RC t RAS t RP t RAS
t RC t RP
RAS tT t RSH t RCD
CAS
t CHR
t CRP
t RAD t ASR t RAH Address Row t ASC
t RAL t CAH
Column t RRH t RCH

WE t DZC High-Z Din t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout
t RCS
t RRH
t WRH t WRP
t WRP
tWRH
t WED t CDD t RDD
t OED
t OFF t OH
t OEZ t WEZ t OHO
t OFR t OHR
20
HM5117805 Series
EDO Page Mode Read Cycle
t RP t RASP t CP t CAS t RCS
WE
t RNCD
RAS
t HPC t HPC tCAS t RCHC t CPRH t CP t t CRP
tT
CAS
t CSH
t HPC t CAS
t CP
RSH
tCAS t RRH t RCH
t RCHR
t RCH t RCS
tASR
Address
tRAH tASC Row
tCAH
t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL tDZC
t CAL tRDD tCDD
Din
High-Z tDZO tCOL tCOP tOED

OE
tOEA
tCPA
tCPA
tCAC tAA
tAA tCAC
tOEZ
tWEZ
tOHO
tCPA tAA tCAC
tAA
tOEZ
tOFR tOHR tOEZ
tCAC
tRAC
tOEA
tDOH
tOHO
tOEA
tOHO tOFF tOH
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
21
HM5117805 Series
EDO Page Mode Early Write Cycle
t RASP t RP
RAS tT t CSH t RCD t CAS CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
t ASR t RAH
t ASC
t CAH
t ASC
tCAH
t ASC t CAH
Address
Row
Column 1
Column 2
Column N
t WCS
t WCH
t WCS
t WCH
t WCS
t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z* * t WCS t WCS (min)
22
HM5117805 Series
EDO Page Mode Delayed Write Cycle*18
t RASP t RP RAS tT t CSH t RCD
CAS
t CP t CAS t HPC t CAS
t CP t RSH t CAS
t CRP
t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL

t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z
Invalid Dout Invalid Dout Invalid Dout
23
HM5117805 Series
EDO Page Mode Read-Modify-Write Cycle*18
t RASP t RP RAS tT t CP t RCD
CAS
t HPRWC t CP t CAS t CAS
t RSH t CAS
t CRP
t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO
t OED
t ASC t CAH Column 2 t CWL t RCS t CPW t AWD t CWD t RCS t CWL
t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
t WP t DZC t DS t DH Din 2 t OED t OEH t DZO t OED
t WP t DZC t DS t DH Din N
Din 1 t DZO t OEH
t OEH
*
OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
High-Z
Dout
Dout 1
Dout 2
Dout N
24
HM5117805 Series
EDO Page Mode Mix Cycle (1)
t RP
RAS
t RASP t CRP tCAS tRSH t RCS tCPW tAWD t ASC tRAH Row tCAH t ASC t CAH Column 2 t CAL tASC t CAH Column 3 t CAL t DS High-Z tOED t DH Din 3 tWED tWP t RAL t CAH Column 4 t CAL tRDD tCDD t RCS t RRH t RCH
tT
CAS
t CP t CAS t CSH t RCD t WCS t WCH t CAS
t CP tCAS
t CP
WE
tASR
Address
tASC
Column 1 t CAL
t DS
Din
t DH Din 1

OE
tCPA tAA tOEA
tCPA
tCPA tAA
t OEZ
tAA
tOFR tWEZ tOEZ
tCAC
tOHO tOFF tOH
tCAC
t DOH
tCAC t OHO
tOEA
Dout
Dout 2
Dout 3
Dout 4
25
HM5117805 Series
EDO Page Mode Mix Cycle (2)
t RNCD
RAS
t RP t RASP
tT
CAS
t CSH t CAS t RCD t RCS t RCHR t RCH tWCS t WCH t RCS t CAS
t CP tCAS
t CP tCAS t RCS tCPW tWP t RAL tASC t CAH Column 4 t CAL t DS t DH Din 3 tOED tCOP tRSH
t CRP
t RRH t RCH
WE
tASR
Address
tRAH Row
t ASC
tCAH
t ASC t CAH Column 2 t CAL t DS t DH Din 2 tOED tCOL
t ASC t CAH Column 3 t CAL
Column 1 t CAL
tRDD tCDD
Din
High-Z
tWED
OE
tAA tOEA tCAC tRAC t OHO
Dout
t OEA tOEZ tCPA tAA tCAC tOEZ t OHO
Dout 3
tCPA tAA tCAC tOEA
tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4
Dout 1
26
HM5117805 Series
Self Refresh Cycle (L-version) *21, 22, 23, 24
t RP
t RASS
t RPS
RAS t RPC tT t CRP t CHS
, ,
t CP t CSR CAS t WRP WE t OFR t OFF Dout 27
t WRH
, + & $
High-Z
HM5117805 Series
Package Dimensions
HM5117805J/LJ Series (CP-28DA)
Unit: mm
18.17 18.54 Max
28
15 10.16 0.13 11.18 0.13
1
3.50 0.26
1.30 Max
0.43 0.10
1.27 0.10
0.80
9.40 0.25
HM5117805S/LS Series (CP-28DNA)
2.85 0.12
0.74
14
+0.25 -0.17
Unit: mm
18.41 18.84 Max
28
15 7.62 0.12 8.51 0.12
1
3.50 0.26
1.165 Max
0.43 0.10
1.27 0.10
0.64 Min
6.79 0.18
2.45 0.12
0.74
14
28
HM5117805 Series
HM5117805TT/LTT Series (TTP-28DA)
Unit: mm
18.41 18.81 Max 28 15
1 0.40 0.10
1.27 0.21 M
14 11.76 0.2 0 - 5 0.08 Min 0.18 Max
1.20 Max
0.10 1.15 Max
0.145
+0.075 -0.025
10.16
0.68 0.50 0.10
HM5117805TS/LTS Series (TTP-28DB)
Unit: mm
18.41 18.81 Max 28 15
1 0.40 0.10
1.27 0.21 M
14 9.22 0.2 0 - 5 0.08 Min 0.18 Max
1.20 Max
0.10 1.15 Max
0.145 -0.025
+0.075
7.62
0.63 0.50 0.10
29
HM5117805 Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
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HM5117805 Series
Revision Record
Rev. 1.0 2.0 Date Oct. 1, 1996 Nov. 8, 1996 Contents of Modification Initial issue Addition of HM5117805-5 Series Addition of HM5117805S/LS Series (CP-28DNA) Addition of HM5117805TS/LTS Series (TTP-28DB) Power dissipation (active) 660/605 mW(max) to 605/550/495 mW (max) DC Characteristics ICC1 max: ICC3 max: ICC6 max: ICC7 max: 120/110 mA to 110/100/90 mA 120/110 mA to 110/100/90 mA 120/110 mA to 110/100/90 mA 120/110 mA to 100/90/85 mA Drawn by Y. Kasama Y. Kasama Approved by M. Mishima Y. Matsuno
AC Characteristics tRCD min: 20/20 ns to 11/14/14 ns tRAD min: 15/15 ns to 9/12/12 ns tRSH min: 15/18 ns to 10/13/13 ns tRRH min: 0/0 ns to 5/5/5 ns tRWC min: 149/175 ns to 111/135/161 ns tRWD min: 82/95 ns to 67/79/92 ns tCWD min: 37/43 ns to 30/34/40 ns tAWD min: 52/60 ns to 42/49/57 ns tRPC min: 0/0 ns to 5/5/5 ns tHPRWC min: 79/90 ns to 57/68/79 ns Timing Waveforms Addition of tRNCD timing to EDO page mode mix cycle (2) 3.0 Feb. 25, 1997 AC Characteristics tRRH min: 5/5/5 ns to 0/0/0 ns
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