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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843022
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
FEATURES
* 1 differential 3.3V LVPECL output * Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal * Output frequencies: 125MHz or 62.5MHz (selectable) * RMS phase jitter @ 125MHz, using a 25MHz crystal (12KHz - 20MHz): 0.62ps (typical) * RMS phase noise at 125MHz (typical) Offset Noise Power 100Hz ............... -94.6 dBc/Hz 1KHz .............. -122.8 dBc/Hz 10KHz .............. -132.2 dBc/Hz 100KHz .............. -132.0 dBc/Hz * 3.3V operating supply * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS843022 is a Fibre Channel Clock Generator and a member of the HiPerClocksTM family of high HiPerClockSTM performance devices from ICS. The ICS843022 uses a 25MHz crystal to synthesize 125MHz or 62.5MHz. The ICS843022 has excellent phase jitter performance, over the 12KHz - 20MHz integration range. The ICS843022 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
ICS
FUNCTION TABLE
Inputs FREQ_SEL 0 1 Output Frequencies (with a 25MHz crystal) 125MHz 62.5MHz
BLOCK DIAGRAM
PIN ASSIGNMENT
VCCA VEE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VCC Q0 nQ0 FREQ_SEL
XTAL_IN
OSC
XTAL_OUT
Output Divider
nQ0 Q0
ICS843022
8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
FREQ_SEL
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843022AG www.icst.com/products/hiperclocks.html REV. A NOVEMBER 30, 2004
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843022
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Type Power Power Input Input Description Analog supply pin. Negative supply pin. Crystal oscillator interface. XTAL_in is the input, XTAL_OUT is the output. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels. Core supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 4 5 6, 7 8 Name VCCA V EE XTAL_OUT, XTAL_IN FREQ_SEL nQ0, Q0 VCC
Output Power
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF K
843022AG
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843022
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5V 50mA 100mA 101.7C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA=0C TO 70C
Symbol VCC VCCA I EE Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 85 Units V V mA
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V5%, TA=0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current FREQ_SEL FREQ_SEL VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V -5 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 Units V V A A
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, TA=0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Test Conditions Minimum Typical Fundamental 25 50 7 MHz pF Maximum Units
843022AG
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843022
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Test Conditions Minimum Typical 125 62.5 125MHz, Integration Range: 12KHz - 20MHz 62.5MHz, Integration Range: 12KHz - 20MHz 20% to 80% 0.62 0.63 400 50 Maximum Units MHz MHz ps ps ps %
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V5%, TA=0C TO 70C
Symbol fOUT Parameter Output Frequency
tjit(O)
tR / tF
RMS Phase Jitter; NOTE 1 Output Rise/Fall Time
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot.
843022AG
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843022
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 125MHZ
0 -10 -20 -30 -40 -50
Fibre Channel Filter
125MHz
RMS Phase Jitter (Random) 12KHz to 20MHz = 0.62ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110
Raw Phase Noise Data
-120 -130 -140 -150 -160 -170 -180 -190 100 1k
Phase Noise Result by adding Fibre Channel Filter to raw data
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843022AG
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843022
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
Phase Noise Plot
Noise Power
VCC
Qx
SCOPE
LVPECL
nQx
Phase Noise Mask
VEE
f1 Offset Frequency f2
-1.3V 0.165V
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ0 Q0
Pulse Width t
PERIOD
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
843022AG
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843022
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843022 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F 10
V CCA .01F
10 F
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843022 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p
Figure 2. CRYSTAL INPUt INTERFACE
843022AG
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843022
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
output frequency. The C1 = 27pF and C2 = 33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy.
APPLICATION SCHEMATIC
Figure 3A shows a schematic example of the ICS843022. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18pF parallel resonant 25MHz crystal is used for generating 125MHz
VCC
VCCA
VCC
VCC
R2 10
C3 10uF
C4 0.1u
U1
R1 1K
R3 133
Zo = 50 Ohm
Q
R5 133
XTAL2 XTAL_OUT
C2 33pF
X1 25MHz 18pF
XTAL_IN XTAL1
1 2 3 4
VCCA VEE XTAL_OUT XTAL2 XTAL_IN XTAL1
VCC Q0 nQ0 FREQ_SEL
ICS843022
8 7 6 5
VCC
+
Zo = 50 Ohm
nQ
-
C1 27pF
C5 0.1u
R4 82.5
R6 82.5
FIGURE 3A. ICS843022 SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of P.C. board layout. The crystal X1 footprint in this example allows either surface mount (HC49S) or through hole (HC49) package. C3 is 0805. C1 and C2 are
0402. Other resistors and capacitors are 0603. This layout assumes that the board has clean analog power and ground planes.
FIGURE 3B. ICS843022 PC BOARD LAYOUT EXAMPLE
843022AG
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843022
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843022. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS843022 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 85mA = 294.5mW Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 294.5mW + 30mW = 324.5mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.325W * 90.5C/W = 99.4C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
8-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
843022AG
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4.
VCC
ICS843022
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Q1
VOUT RL 50 VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CC_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V
OH_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843022AG
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843022
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 7.
JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
JA by Velocity (Meters per Second)
0 1
90.5C/W
2.5
89.8C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
TRANSISTOR COUNT
The transistor count for ICS843022 is: 1928
843022AG
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843022
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
8 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
843022AG
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843022
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Marking 3022A 3022A Package 8 lead TSSOP 8 lead TSSOP on Tape and Reel Count 100 per tube 2500 Temperature 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS843022AG ICS843022AGT
The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843022AG
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REV. A NOVEMBER 30, 2004

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