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Integrated Circuit Systems, Inc.
ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
FEATURES
* 5 differential HSTL outputs * Selectable differential CLKx, nCLKx input pairs * CLKx, nCLKx pairs can accept the following differential input levels: LVDS, LVPECL, HSTL, SSTL, HCSL * Output frequency range: 31.25MHz to 630MHz * Input frequency range: 31.25MHz to 630MHz * VCO range: 250MHz to 630MHz * External feedback for "zero delay" clock regeneration with configurable frequencies * Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 * Static phase offset: 30ps 125ps * Cycle-to-cycle jitter: 35ps (maximum) * Output skew: 50ps (maximum) * 3.3V core, 1.8V output operating supply * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS8725I-01 is a highly versatile 1:5 Differential-to-HSTL Clock Generator and a member HiPerClockSTM of the HiPerClockSTMfamily of High Performance Clock Solutions from ICS. The ICS8725I-01 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 630MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.
ICS
BLOCK DIAGRAM
PLL_SEL Q0 nQ0 Q1 nQ1
PIN ASSIGNMENT
PLL_SEL SEL3 GND VDDO
VDDA
nQ4
VDD
Q4
CLK0 nCLK0 CLK1 nCLK1 CLK_SEL FB_IN nFB_IN
/1, /2, /4, /8, /16, /32, /64
0
0
Q2 nQ2
SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR 1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 VDDO Q3 nQ3 Q2 nQ2 Q1 nQ1 VDDO
1
1
Q3 nQ3
PLL
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Q4 nQ4
ICS8725I-01
21 20 19 18 17
9 10 11 12 13 14 15 16
VDD nFB_IN FB_IN SEL2 GND nQ0 Q0 VDDO
SEL0 SEL1 SEL2 SEL3 MR
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
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8725AYI-01
Integrated Circuit Systems, Inc.
ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Type Description Determines output divider values in Table 3. Pulldown LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects CLK1, nCLK1. Pulldown When LOW, selects CLK0, nCLK0. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go Pulldown high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Core supply pins. Pullup Feedback input to phase detector for regenerating clocks with "zero delay". Power supply ground. Differential output pair. HSTL interface levels. Output supply pins. Differential output pair. HSTL interface levels. Differential output pair. HSTL interface levels. Differential output pair. HSTL interface levels. Differential output pair. HSTL interface levels. Analog supply pin. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS/LVTTL interface levels. Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
TABLE 1. PIN DESCRIPTIONS
Number 1, 2, 12, 29 3 4 5 6 7 Name SEL0, SEL1, SEL2, SEL3 CLK0 nCLK0 CLK1 nCLK1 CLK _ S E L
Input Input Input Input Input Input
8 9, 32 10 11 13, 28 14, 15 16, 17, 24, 25 18, 19 20, 21 22, 23 26, 27 30 31
MR VDD nFB_IN FB_IN GN D nQ0, Q0 VDDO nQ1, Q1 nQ2, Q2 nQ3, Q3 nQ4, Q4 VDDA PLL_SEL
Input Power Input Input Power Output Power Output Output Output Output Power Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
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ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Outputs PLL_SEL = 1 PLL Enable Mode Q0:Q4, nQ0:nQ4 /1 /1 /1 /1 /2 /2 /2 /4 /4 /8 x2 x2 x2 x4 x4 x8
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S E L1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference Frequency Range (MHz)* 250 - 630 125 - 315 62.5 - 157.5 31.25 - 78.75 250 - 630 125 - 315 62.5 - 157.5 250 - 630 125 - 315 250 - 630 125 - 315 62.5 - 157.5 31.25 - 78.75 62.5 - 157.5 31.25 - 78.75 31.25 - 78.75
*NOTE: VCO frequency range for all configurations above is 250MHz to 630MHz.
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
8725AYI-01
SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
S E L1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Outputs PLL_SEL = 0 PLL Bypass Mode Q0:Q4, nQ0:nQ4 /4 /4 /4 /8 /8 /8 / 16 / 16 / 32 / 64 /2 /2 /4 /1 /2 /1
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Integrated Circuit Systems, Inc.
ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5V 50mA 100mA 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current No Load 0 Test Conditions Minimum 3.135 3.135 1.6 Typical 3.3 3.3 1.8 Maximum 3.465 3.465 2.0 137 17 Units V V V mA mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage CLK_SEL, MR, SEL0, SEL1, SEL2, SEL3 PLL_SEL CLK_SEL, MR, SEL0, SEL1, SEL2, SEL3 PLL_SEL VDD = VIN = 3.465V VDDO = 2V VDD = VIN = 3.465V VDDO = 2V VDD = 3.465V, VDDO = 2V, VIN = 0V VDD = 3.465V, VDDO = 2V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 Units V V A A A A
Input High Current
IIL
Input Low Current
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol Parameter IIH IIL VPP Input High Current Input Low Current CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.15 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 0.5 VCMR NOTE 1: For single ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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REV. A SEPTEMBER 29, 2003
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ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Test Conditions Minimum 1 0 40% x (VOH - VOL) + VOL 0.6 Typical Maximum 1.4 0.4 60% x (VOH - VOL) + VOL 1.1 Units V V V V
TABLE 4D. HSTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol Parameter Output High Voltage; VOH NOTE 1 Output Low Voltage; VOL NOTE 1 VOX Output Crossover Voltage
Peak-to-Peak VSWING Output Voltage Swing NOTE 1: Outputs terminated with 50 to ground.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol fIN Parameter Input Frequency CLK0, nCLK0, CLK1, nCLK1 Test Conditions PLL_SEL = 1 PLL_SEL = 0 Minimum 31.25 Typical Maximum 630 630 Units MHz MHz
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C
Symbol fMAX t PD t(O) t sk(o) t jit(cc) t jit(O) tL tR / tF tPW Parameter Output Frequency Propagation Delay; NOTE 1 Static Phase Offset; NOTE 2, 5 Output Skew; NOTE 3, 5 Cycle-to-Cycle Jitter; NOTE 5, 6 Phase Jitter; NOTE 4, 5, 6 PLL Lock Time Output Rise/Fall Time Output Pulse Width 20% to 80% 300 tPERIOD/2 - 85 tPERIOD/2 PLL_SEL = 0V 630MHz PLL_SEL = 3.3V 3.4 -95 3.9 30 Test Conditions Minimum Typical Maximum 630 4.5 155 50 35 50 1 700 tPERIOD/2 + 85 Units MHz ns ps ps ps ps ms ps ps
All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across alll conditions, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz.
8725AYI-01
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REV. A SEPTEMBER 29, 2003
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ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.8V 0.2V 3.3V 5% VDD
VDD, VDDA
Qx
SCOPE
nCLK0, nCLK1
VDDO
HSTL
GND
nQx
V
CLK0, CLK1
PP
Cross Points
V
CMR
GND 0V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx nQ nQy Qy
nQ0:nQ4 Q0:Q4
tcycle
n
tsk(o)
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
OUTPUT SKEW
nCLK0, nCLK1 CLK0, CLK1 nFB_IN FB_IN
t(O) VOH VOL
CYCLE-TO-CYCLE JITTER
80%
VOH VOL
Clock Outputs
20% tR tF
tjit(O) = t(O) -- t(O) mean = Phase Jitter t(O) mean = Static Phase Offset (where t(O) is any random sample, and t(O) mean is the average of the sampled cycles measured on controlled edges)
PHASE JITTER
nQ0:nQ4 Q0:Q4
AND
STATIC PHASE OFFSET
OUTPUT RISE/FALL TIME
nCLK0, nCLK1
Pulse Width t
PERIOD
CLK0, CLK1 nQ0:nQ4 Q0:Q4
tPD
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
8725AYI-01
PROPAGATION DELAY
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tcycle n+1
80% VOD 20%
Integrated Circuit Systems, Inc.
ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR APPLICATIONS INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8725I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V VDD .01F V DDA .01F 10 F 10
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
8725AYI-01
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REV. A SEPTEMBER 29, 2003
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ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS HSTL drivers. If you are using an HSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS HSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
LVDS_Driv er
Zo = 50 Ohm
CLK
R1 100
Zo = 50 Ohm
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
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REV. A SEPTEMBER 29, 2003
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ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
depend on the selected component types, the density of the components, the density of the traces, and the stacking of the P.C. board.
LAYOUT GUIDELINE
The schematic of the ICS8725I-01 layout example is shown in Figure 4A. The ICS8725I-01 recommended PCB board layout for this example is shown in Figure 4B. This layout example is used as a general guideline. The layout in the actual system will
VDD
SP = Space (i.e. not intstalled)
R7 RU2 SP RU3 1K RU4 1K RU5 SP RU6 1K RU7 SP CLK_SEL PLL_SEL SEL0 SEL1 SEL2 SEL3 PLL_SEL SEL3 VDDA 10 C11 0.01u C16 10u Zo = 50 Ohm + VDD
(155.5 MHz)
RD2 1K
RD3 SP
RD4 SP
RD5 1K
RD6 SP
RD7 1K
VDD
VDDO Zo = 50 Ohm
-
LVHSTL_input
U1 3.3V
32 31 30 29 28 27 26 25
(155.5 MHz)
Zo = 50 Ohm SEL0 SEL1 1 2 3 4 5 6 7 8
VDD PLL_SEL VDDA SEL3 GND Q4 nQ4 VDDO
R4A 50 VDDO Q3 nQ3 Q2 nQ2 Q1 nQ1 VDDO 24 23 22 21 20 19 18 17
R4B 50
Zo = 50 Ohm CLK_SEL 3.3V PECL Driver R8 50 R9 50
VDD nFB_IN FB_IN SEL2 GND nQ0 Q0 VDDO
SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR
VDD=3.3V VDDO=1.8V
9 10 11 12 13 14 15 16
8725_01
R10 50
SEL2
SEL[3:0] = 0101, Divide by 2
R2B 50
R2A 50
Bypass capacitors located near the power pins
(U1-9) VDD
C1 0.1uF
(U1-32)
C6 0.1uF
(U1-16)
C2 0.1uF
VDDO
(U1-17)
C4 0.1uF
(U1-24)
C5 0.1uF
(U1-25)
C7 0.1uF
FIGURE 4A. ICS8725I-01 HSTL ZERO DELAY BUFFER SCHEMATIC EXAMPLE
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The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. * The differential 50 output traces should have same length. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. * Make sure no other signal traces are routed between the clock trace pair. * The matching termination resistors should be located as close to the receiver input pins as possible.
POWER
AND
GROUNDING
Place the decoupling capacitors C1, C6, C2, C4, and C5, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible.
CLOCK TRACES
AND
TERMINATION
Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the
GND
R7 C16 C11 C7 C6 C5
VDDO
U1
Pin 1
VDD
VDDA
VIA
50 Ohm Traces
C4 C1 C2
FIGURE 4B. PCB BOARD LAYOUT FOR ICS8725I-01
8725AYI-01
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REV. A SEPTEMBER 29, 2003
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ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8725I-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8725I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (137mA + 17mA) = 499mW Power (outputs)MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 32.8mW = 164mW
Total Power_MAX (3.465V, with all outputs switching) = 499mW + 164mW = 663mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.663W * 42.1C/W = 113C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
Table 7. Thermal Resistance JA for 32-pin LQFP, Forced Convection
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 5.
VDD
Q1
VOUT RL 50
FIGURE 5. HSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MIN
/R ) * (V
L DD_MAX
-V
OH_MIN
) )
Pd_L = (V
OL_MAX
/R ) * (V
L DD_MAX
-V
OL_MAX
Pd_H = (1V/50) * (2V - 1V) = 20mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
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ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8725I-01 is: 2969
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1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
PACKAGE OUTLINE - Y SUFFIX
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Marking ICS8725AYI-01 ICS8725AYI-01 Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS8725AYI-01 ICS8725AYI-01T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8725AYI-01
www.icst.com/products/hiperclocks.html
15
REV. A SEPTEMBER 29, 2003

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