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Integrated Circuit Systems, Inc.
ICS94241
Programmable TCHTM for Differential PIIITM Processor
Recommended Application: VIA PL133-T style chipset with Intel differential PIII processor Output Features: * 2 - CPUs @2.5V * 13 - SDRAM @ 3.3V * 7 - PCI @3.3V, * 1 - 48MHz, @3.3V * 1 - 24MHz @ 3.3V * 2 - REF @3.3V, 14.318MHz. Features: * Programmable ouput frequency * Programmable ouput rise/fall time * Programmable output to output skew * Programmable spread spectrum for EMI control * Real time system reset output * Watchdog timer technology to reset system if over-clocking causes malfunction * Uses external 14.318MHz crystal Key Specifications: * CPU - CPU: <175ps * SDRAM - SDRAM: <500ps * PCI - PCI: <500ps * CPU-SDRAM: <500ps * CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
Pin Configuration
VDDREF GNDREF X1 X2 VDDPCI *FS4/PCICLK0 *FS3/PCICLK1 GNDPCI PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 VDDPCI BUFFER_IN GNDSDR SDRAM12 SDRAM11 VDDSDR SDRAM10 SDRAM9 GND48 SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VTT_PWRGD# REF0 1 REF1/FS2** GNDCPU CPUCLK_CS CPUCLK0 VDDLCPU RESET# SDRAM0 GNDSDR SDRAM1 SDRAM2 VDDSDR SDRAM3 SDRAM4 GNDSDR SDRAM5 SDRAM6 VDDSDR SDRAM7 SDRAM8 AVDD48 48MHz/FS0** 24MHz/FS1**
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD ** Internal Pull-down resistor of 120K to GND 1. This output has 1.5 to 2X drive strength
Block Diagram
Functionality
Bit2 Bit7 Bit6 Bit5 Bit4 CPUCLK PCICLK Spread Percentage FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 66.67 33.33 +/- 0.25 Center Spread 0 0 0 0 1 66.67 33.33 0 to -0.5% Down Spread 0 0 0 1 0 68.67 34.33 0.25 Center Spread 0 0 0 1 1 71.34 35.66 +/- 0.25 Center Spread 0 1 0 0 0 100.00 33.33 +/- 0.25 Center Spread 0 1 0 0 1 100.00 33.33 0 to -0.5% Down Spread 0 1 0 1 0 103.00 34.33 +/- 0.25 Center Spread 0 1 0 1 1 107.00 35.67 +/- 0.25 Center Spread 1 0 0 0 0 200.00 33.33 +/- 0.25 Center Spread 1 0 0 0 1 200.00 33.33 0 to -0.5% Down Spread 1 0 0 1 0 206.00 34.33 +/- 0.25 Center Spread 1 0 0 1 1 214.00 35.67 +/- 0.25 Center Spread 1 1 0 0 0 133.33 33.33 +/- 0.25 Center Spread 1 1 0 0 1 133.33 33.33 0 to -0.5% Down Spread 1 1 0 1 0 137.33 34.33 +/- 0.25 Center Spread 1 1 0 1 1 142.67 35.67 +/- 0.25 Center Spread
For additional margin testing frequencies refer to pg 5 frequency table.
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ICS94241
ICS94241
General Description
The ICS94241 is a single chip timing control hub for desktop designs using VIA PL133-T style chipset with Intel differential PIII processor. It provides all necessary clock signals for such a system. The ICS94241 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part incorporates ICS's newest clock technology which more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology in having a frequency reset feature to provide a safe setting under unstable system conditions.
Pin Configuration
PIN NUMBER 1, 5, 14, 19, 30, 36 2, 8, 16, 22, 33, 39, 45 3 4 6 PIN NAME VDD GND X1 X2 FS41,3 PCICLK0 FS31,3 7 13, 12, 11, 10, 9 15 17, 18, 20, 21, 28, 29, 31, 32, 34, 34, 35, 37, 38, 40 23 24 25 26 27 41 42 43 44 46 47 48 PCICLK1 PCICLK (6:2) BUFFER IN SDRAM (12:0) SDATA SCLK FS1
2,3
TYPE PWR PWR IN OUT IN OUT IN OUT OUT IN OUT I/O IN IN OUT OUT IN PWR OUT PWR OUT OUT IN OUT OUT IN
DESCRIPTION Power supply, nominal 3.3V Ground Cr ystal input, has inter nal load cap (36pF) and feedback resistor from X2 Cr ystal output, nominally 14.318MHz. Has inter nal load cap (36pF) Frequency select pin. Latched Input. Internal Pull-down to GND PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew (CPU early) Frequency select pin. Latched Input. Internal Pull-down to GND PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew (CPU early) PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew (CPU early) Input to Fanout Buffers for SDRAM outputs. SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset) Data pin for I2C circuitr y 5V tolerant Clock pin of I2C circuitr y 5V tolerant Frequency select pin. Latched Input. 24MHz output clock 48MHz output clock Frequency select pin. Latched Input Analog power for 48MHz outputs Real time system reset signal for frequency ratio change or watchdog timmer timeout. This signal is active low. Supply for CPU clocks 2.5V nominal CPU clock outputs CPU clock output for chipset host clock Frequency select pin. Latched Input 14.318 MHz reference clock. 14.318 Mhz reference clock. This 3.3V LVTTL input is a level sensitive strobe used to determine when FS inputs are valid and are ready to be sampled (active low)
24MHz 48MHz FS02,3 AVDD48 RESET VDDLCPU CPUCLK0 CPUCLK_CS FS22,3 REF1 REF0 VTT_PWRGD#
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Internal Pull-down to GND on indicated inputs 3: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS94241
General I2C serial interface information for the ICS94241 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending Byte 0 through Byte 20 (see Note) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends Byte 0 through byte 8 (default) ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). * Controller (host) will need to acknowledge each byte * Controller (host) will send a stop bit * * * * * * *
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK If 7H has been written to B6 ACK Byte 7
Byte 18 ACK Byte 19 ACK Byte 20 ACK Stop Bit
*See notes on the following page.
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If 12H has been written to B6 ACK If 13H has been written to B6 ACK If 14H has been written to B6 ACK Stop Bit
Byte18 Byte 19 Byte 20
3
ICS94241
Brief I2C registers description for ICS94241 Programmable System Frequency Generator
Register Name Functionality & Frequency Select Register Output Control Registers Byte 0 Description Output frequency, hardware / I2C frequency select, spread spectrum & output enable control register. Active / inactive output control registers/latch inputs read back. Byte 7 bit (7:4) is ICS vendor id 001. Other bits in this register designate device revision ID of this part. Writing to this register will configure byte count and how many byte will be read back. Do not write 00H to this byte Writing to this register will configure the number of seconds for the watchdog timer to reset. Watchdog enable, watchdog status and programmable 'safe' frequency' can be configured in this register. This bit select whether the output frequency is control by hardware/byte 0 configurations or byte 11&12 programming. These registers control the dividers ratio into the phase detector and thus control the VCO output frequency. These registers control the spread percentage amount. Increment or decrement the group skew amount as compared to the initial skew. These registers will control the output rise and fall time. PWD Default See individual byte description See individual byte description See individual byte description
1-6
Vendor ID & Revision ID Registers
7
Byte Count Read Back Register Watchdog Timer Count Register
8
08H
9
10H
Watchdog Control Registers
10 Bit [6:0]
000,0000
VCO Control Selection Bit
10 Bit [7]
0
VCO Frequency Control Registers Spread Spectrum Control Registers Group Skews Control Registers Output Rise/Fall Time Select Registers
11-12
Depended on hardware/byte 0 configuration Depended on hardware/byte 0 configuration See individual byte description See individual byte description
13-14
15-16
17-20
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing to byte 8. When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
2. 3. 4. 5. 6.
7.
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ICS94241
Byte 0: Functionality and frequency select register (Default=0)
Bit
Bit 2, (7:4)
Bit 3 Bit 1 Bit 0
Description Bit2 Bit7 Bit6 Bit5 Bit4 CPUCLK PCICLK Spread Percentage FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 66.67 33.33 Center Spread +/- 0.25% 0 0 0 0 1 66.67 33.33 Down Spread 0 to - 0.5% 0 0 0 1 0 68.67 34.33 Center Spread +/- 0.25% 0 0 0 1 1 71.34 35.66 Center Spread +/- 0.25% 0 0 1 0 0 73.34 36.66 Center Spread +/- 0.25% 0 0 1 0 1 76.67 38.33 Center Spread +/- 0.25% 0 0 1 1 0 150.00 30.00 Center Spread +/- 0.25% 0 0 1 1 1 166.67 33.33 Center Spread +/- 0.25% 0 1 0 0 0 100.00 33.33 Center Spread +/- 0.25% 0 1 0 0 1 100.00 33.33 Down Spread 0 to - 0.5% 0 1 0 1 0 103.00 34.33 Center Spread +/- 0.25% 0 1 0 1 1 107.00 35.67 Center Spread +/- 0.25% 0 1 1 0 0 110.00 36.67 Center Spread +/- 0.25% 0 1 1 0 1 115.00 38.33 Center Spread +/- 0.25% 0 1 1 1 0 100.90 33.63 Center Spread +/- 0.25% 0 1 1 1 1 90.00 30.00 Center Spread +/- 0.25% 1 0 0 0 0 200.00 33.33 Center Spread +/- 0.25% 1 0 0 0 1 200.00 33.33 Down Spread 0 to - 0.5% 1 0 0 1 0 206.00 34.33 Center Spread +/- 0.25% 1 0 0 1 1 214.00 35.67 Center Spread +/- 0.25% 1 0 1 0 0 220.00 36.67 Center Spread +/- 0.25% 1 0 1 0 1 230.00 38.33 Center Spread +/- 0.25% 1 0 1 1 0 201.80 33.63 Center Spread +/- 0.25% 1 0 1 1 1 180.00 30.00 Center Spread +/- 0.25% 1 1 0 0 0 133.33 33.33 Center Spread +/- 0.25% 1 1 0 0 1 133.33 33.33 Down Spread 0 to - 0.5% 1 1 0 1 0 137.33 34.33 Center Spread +/- 0.25% 1 1 0 1 1 142.67 35.67 Center Spread +/- 0.25% 1 1 1 0 0 146.67 36.67 Center Spread +/- 0.25% 1 1 1 0 1 153.33 38.33 Center Spread +/- 0.25% 1 1 1 1 0 133.90 33.48 Center Spread +/- 0.25% 1 1 1 1 1 120.00 30.00 Center Spread +/- 0.25% 0=Frequency selected by hardware; 1=Frequency selected by Bit2, (7:4) 0=Spread off; 1=Spread Spectrum Enable 0=Running; 1=Tristate
PWD
Note 1
0 1 0
Notes: 1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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ICS94241
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
40 43 44
PWD
X 1 1 1 1 1 1 1
DESCRIPTION
Latched FS2# (Reserved) (Reserved) (Reserved) SDRAM0 (Reserved) CPUCLK0 CPUCLK_CS
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
6 13 12 11 10 9 7
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
(Reserved) PCICLK0 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1
Byte 3: SDRAM, Active/Inactive Register (1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
26 25 17, 18, 20, 21 28, 29, 31, 32 34, 35, 37, 38
PWD
1 X 1 1 1 1 1 1
DESCRIPTION
(Reserved) Latched FS0# 48MHz 24 MHz (Reserved) SDRAM (12:9) SDRAM (8:5) SDRAM (4:1)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
1 1 1 1 X X X 1
DESCRIPTION
(Reserved) (Reserved) (Reserved) (Reserved) Latched FS1# Latched FS4# Latched FS3# (Reserved)
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes:
PIN# PWD
46 47 1 1 1 1 1 1 1 1
DESCRIPTION
(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) REF1 REF0
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD 0 1 X X X X X X
DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. 0453C--10/26/04
Note: This is an unused register writing to this register will not affect device performance or functinality.
6
ICS94241
Byte 7: Vendor ID and Revision ID Register
Byte 8: Byte Count and Read Back Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 1 X X X X X
Description Vendor ID Vendor ID Vendor ID Revision ID Revision ID Revision ID Revision ID Revision ID
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 1 0 0 0
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Byte 9: Watchdog Timer Count Register
Byte 10: VCO Control Selection Bit & Watchdog Timer Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 1 0 0 0 0
Description The decimal representation of these 8 bits correspond to 290ms or 1ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 16X 290ms = 4.6 seconds.
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 1 1 0 0 0
Description 0=Hw/B0 freq / 1=B11&12 freq WD Enable 0=disable / 1=enable WD Status 0=normal / 1=alarm WD Safe Frequency, FS4 WD Safe Frequency, FS3 WD Safe Frequency, FS2 WD Safe Frequency, FS1 WD Safe Frequency, FS0
Note: FS values in bit (4:0) will correspond to Byte 0 FS values. Default safe frequency is same as 00000 entry in byte0.
Byte 11: VCO Frequency Control Register
Byte 12: VCO Frequency Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description VCO Divider Bit0 REF Divider Bit6 REF Divider Bit5 REF Divider Bit4 REF Divider Bit3 REF Divider Bit2 REF Divider Bit1 REF Divider Bit0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description VCO Divider Bit8 VCO Divider Bit7 VCO Divider Bit6 VCO Divider Bit5 VCO Divider Bit4 VCO Divider Bit3 VCO Divider Bit2 VCO Divider Bit1
Note: The decimal representation of these 7 bits (Byte 11 [6:0]) + 2 is equal to the REF divider value .
Notes: 1. PWD = Power on Default
Note: The decimal representation of these 9 bits (Byte 12 bit [7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO divider value. For example if VCO divider value of 36 is desired, user need to program 36 - 8 = 28, namely, 0, 00011100 into byte 12 bit & byte 11 bit 7.
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ICS94241
Byte 13: Spread Sectrum Control Register
Byte 14:
Spread Sectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Spread Spectrum Bit7 Spread Spectrum Bit6 Spread Spectrum Bit5 Spread Spectrum Bit4 Spread Spectrum Bit3 Spread Spectrum Bit2 Spread Spectrum Bit1 Spread Spectrum Bit0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit12 Spread Spectrum Bit11 Spread Spectrum Bit10 Spread Spectrum Bi 9 Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD Description 0 1 PCICLK0 Skew Control 1 0 0 1 PCICLK (6:1) Skew Control 1 0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 0 0 0 0
Description SDRAM (12:1) Skew Control CPUCLK_CS Skew Control CPUCLK0 Skew Control SDRAM0 Skew Control
Byte 17: Output Rise/Fall Time Select Register
Byte 18: Output Rise/Fall Time Select Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 1 0 1 0 1 0 1 0
Description CPUCLK_CS Slew Rate Control CPUCLK0 Slew Rate Control SDRAM0 Slew Rate Control SDRAM (12:1) Slew Rate Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 1 0 1 0 1 0 1 0
Description PCICLK (6:1) Slew Rate Control PCICLK0 Slew Rate Control 48MHz Slew Rate Control 24MHz Slew Rate Control
Notes: 1. PWD = Power on Default 2. The power on default for byte 13-20 depends on the harware (latch inputs FS[0:4]) or I2C (Byte 0 bit [1:7]) setting. Be sure to read back and re-write the values of these 8 registers when VCO frequency change is desired for the first pass.
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ICS94241
Byte 19: Reserved Register
Byte 20: Reserved Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Note: Byte 19 and 20 are reserved registers, these VCO Programming Constrains VCO Frequency ...................... 150MHz to 500MHz VCO Divider Range ................ 8 to 519 REF Divider Range ................. 2 to 129 Phase Detector Stability .......... 0.3536 to 1.4142 Useful Formula VCO Frequency = 14.31818 x VCO/REF divider value Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5 To program the VCO frequency for over-clocking. 0. Before trying to program our clock manually, consider using ICS provided software utilities for easy programming. 1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by writing to byte 0, or using initial hardware power up frequency. 2. Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20). 3. Read back byte 11-20 and copy values in these registers. 4. Re-initialize the write sequence. 5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values. 6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew rate. 7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be changed again, user only needs to write to byte 11 and 12 unless the system is to reboot. Note: 1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew relation programmed into bytes 13-16 could be unstable. Step 3 & 7 assure the correct spread and skew relationship. 2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly. 3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz). 4. ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program the VCO frequency. 5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spread amount desired. See Application note for software support.
0453C--10/26/04
are unused registers writing to these registers will not affect device performance or functionality.
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ICS94241
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . 7.0 V GND -0.5 V to VDD +0.5 V 0C to +70C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD, VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Input frequency Input Capacitance1 Clk Stabilization1
1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP66 IDD3.3OP100 Fi CIN CINX TSTAB
CONDITIONS
MIN 2 VSS - 0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with no pull-up resistors CL = 0 pF; Select @ 66MHz CL = 0 pF; Select @ 100MHz VDD = 3.3 V Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% target Freq.
MAX VDD + 0.3 0.8 5
UNITS V V mA mA mA mA MHz pF pF ms
90 90 12 27
180 16 5 45 3
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX Operating IDD2.5OP66 CL = 0 pF; Select @ 66.8 MHz 10 72 CL = 0 pF; Select @ 100 MHz 15 100 Supply Current IDD2.5OP100 1 Skew tCPU-PCI VT = 1.5 V; VTL = 1.25 V 1.5 4
1
UNITS mA ns
Guaranteed by design, not 100% tested in production.
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ICS94241
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Cycle-to-cycle
1
SYMBOL VOH2B VOL2B IOH2B IOL2B tr2B1 tf2B1 1 dt2B 1 tsk2B tjcyc-cyc2B1
CONDITIONS IOH = -12.0mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.5V, VOH = 2.0 V VOH = 2.0V, VOL = 0.5 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 2
TYP
MAX 0.4 -19
19 0.95 0.95 45 49 145 225 1.3 1.3 55 175 250
UNITS V V mA mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
T A = 0 - 70C; V DD = 3.3 V +/-5% , V DDL = 2.5 V +/-5% ; CL = 30 pF (unless otherwise stated) PARAMETER
Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time 1 Fall Time Skew 1 Jitter, Cycle-to-cycle
1
1 1
SYMBOL
V OH1 V OL1 IOH1 IOL1 tr1 tf1 d t1 tsk1 tjcyc-cyc2B1
CONDITIONS
IOH = -11 mA IOL = 9.4 mA V OH = 2.0 V V OL = 0.8 V V OL = 0.4 V,V OH = 2.4 V V OH = 2.4 V,V OL = 0.4 V V T = 1.5 V V T = 1.5 V V T = 1.5 V
MIN
2.4
TYP
MAX
0.4 -22
UNITS
V V mA mA ns ns % ps ps
25 1.6 1.9 45 52 50 240 2 2 55 500 250
Duty Cycle
Guaranteed by design, not 100% tested in production.
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ICS94241
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew1 Propagation Delay SYMBOL VOH3 VOL3 IOH3 IOL3 Tr31 Tf31 Dt31 Tsk1 Tprop CONDITIONS IOH = -28mA IOL = 23 mA VOH = 2.0 V VOH = 0.8 V VOL = 0.4V, VOH = 2.4 V VOH = 2.4V, VOL= 0.4 V VT= 1.5 V VT= 1.5 V VT= 1.5 V MIN 2.4 TYP MAX 0.4 -54 41 0.85 0.85 50 200 2 2 55 500 5 UNITS V V mA mA ns ns % ps ns
45
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz, REF
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current 1 Rise Time Fall Time1 Duty Cycle
1
1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 tjcyc-cyc2B1
CONDITIONS IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 2.4
TYP
MAX 0.4 -22
16 1.5 1.5 45 53 250 4 4 55 500
UNITS V V mA mA ns ns % ps
Jiter, Cycle-to-cycle (24, 48MHz)
Guaranteed by design, not 100% tested in production.
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ICS94241
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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ICS94241
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz CPU 100MHz CPU 133MHz
SDRAM 100MHz SDRAM 133MHz
3.5V 66MHz PCI 33MHz APIC 33MHz REF 14.318MHz USB 48MHz
Group Offset Waveforms
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ICS94241
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
a
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS94241yFLF-T
Example:
ICS XXXX y F LF - T
Designation for tape and reel packaging
Lead Free (optional)
Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS, AV = Standard Device
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ICS94241
Revision History
Rev. C Issue Date Description 10/26/2004 Added Lead Free Ordering Information Page # 15
0453C--10/26/04
16

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