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ISL6326
Data Sheet April 21, 2006 FN9262.0
4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision DCR Differential Current Sensing
The ISL6326 controls microprocessor core voltage regulation by driving up to 4 synchronous-rectified buck channels in parallel. Multiphase buck converter architecture uses interleaved timing to multiply channel ripple frequency and reduce input and output ripple currents. Lower ripple results in fewer components, lower component cost, reduced power dissipation, and smaller implementation area. Microprocessor loads can generate load transients with extremely fast edge rates. The ISL6326 utilizes Intersil's proprietary Active Pulse Positioning (APP) and Adaptive Phase Alignment (APA) modulation scheme to achieve the extremely fast transient response with fewer output capacitors. Today's microprocessors require a tightly regulated output voltage position versus load current (droop). The ISL6326 senses the output current continuously by utilizing patented techniques to measure the voltage across the dedicated current sense resistor or the DCR of the output inductor. Current sensing provides the needed signals for precision droop, channel-current balancing, and overcurrent protection. A programmable integrated temperature compensation function is implemented to effectively compensate for the temperature coefficient of the current sense element. The current limit function provides the overcurrent protection for the individual phase. A unity gain, differential amplifier is provided for remote voltage sensing. Any potential difference between remote and local grounds can be completely eliminated using the remote-sense amplifier. Eliminating ground differences improves regulation and protection accuracy. The thresholdsensitive enable input is available to accurately coordinate the start up of the ISL6326 with any other voltage rail. Dynamic-VIDTM technology allows seamless on-the-fly VID changes. The offset pin allows accurate voltage offset settings that are independent of VID setting.
Features
* Proprietary Active Pulse Positioning and Adaptive Phase Alignment Modulation Scheme * Precision Multiphase Core Voltage Regulation - Differential Remote Voltage Sensing - 0.5% System Accuracy Over Life, Load, Line and Temperature - Adjustable Precision Reference-Voltage Offset * Precision resistor or DCR Current Sensing - Accurate Load-Line Programming - Accurate Channel-Current Balancing - Differential Current Sense * Microprocessor Voltage Identification Input - Dynamic VIDTM Technology - 8-Bit VID Input with Selectable VR11 Code and Extended VR10 Code at 6.25mV Per Bit * Thermal Monitoring * Integrated Programmable Temperature Compensation * Overcurrent Protection and Channel Current Limit * Overvoltage Protection * 2, 3 or 4 Phase Operation * Adjustable Switching Frequency up to 1MHz Per Phase * Package Option - QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - QFN Near Chip Scale Package Footprint; Improves PCB Efficiency, Thinner in Profile
*
Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER (Note) ISL6326CRZ ISL6326IRZ PART MARKING ISL6326CRZ TEMP. (C) 0 to70 PACKAGE (Pb-free) PKG. DWG. #
40 Ld 6x6 QFN L40.6x6
ISL6326IRZ -40 to 85 40 Ld 6x6 QFN L40.6x6
Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6326 Pinout
ISL6326 (40 LD QFN) TOP VIEW
EN_PWR 32 VR_HOT VR_RDY VR_FAN EN_VTT
VID7
TM
SS
40 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VRSEL OFS DAC 1 2 3 4 5 6 7 8 9 10 11 REF
39
38
37
36
35
34
FS
33
31 30 ISEN3+ 29 28 ISEN3ISEN2-
PWM3 27 ISEN2+ 26 PWM2 25 PWM4 24 ISEN4+ 23 ISEN422 21 ISEN1ISEN1+ 20 PWM1
GND
12 COMP
13 FB
14 IDROOP
15 VDIFF
16 RGND
17 VSEN
18 TCOMP
19 VCC
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ISL6326 ISL6326CR Block Diagram
VDIFF VR_RDY FS
RGND VSEN
X1 +
CLOCK AND RAMP GENERATOR N
POWER-ON RESET (POR)
+
0.875
EN_VTT
0.875
+ +
OVP SOFTSTART AND FAULT LOGIC
EN_PWR
-
+175mV APP and APA MODULATOR
PW M1
SS VRSEL VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 DAC
Dynamic VID D/A APP and APA MODULATOR
PW M2
APP and APA MODULATOR
PW M3
APP and APA MODULATOR OFFSET
PW M4
OFS REF FB COMP
+
E/A
-
CHANNEL CURRENT BALANCE AND PEAK CURRENT LIMIT I_TRIP
CHANNEL DETECT
N
OCP
ISEN1+ ISEN1ISEN2+
+ IDROOP
1 N
TEMPERATURE COMPENSATION
CHANNEL CURRENT SENSE
ISEN2ISEN3+ ISEN3ISEN4+ ISEN4-
VR_HOT
THERMAL MONITOR
VR_FAN
TEMPERATURE COMPENSATION GAIN ADJUST
TM
TCOMP
GND
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ISL6326 Typical Application - 4-Phase Buck Converter with External Temperature Compensation
+12V THERMISTOR NTC
o
VIN BOOT
PVCC +5V VCC UGATE PHASE
C
ISL6612 DRIVER
FB COMP VCC DAC REF PWM LGATE GND
IDROOP VDIFF VSEN RGND VTT VR_RDY VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VRSEL VR_FAN VR_HOT VIN EN_VTT
PWM1 ISEN1ISEN1+
+12V PVCC VCC
VIN BOOT
UGATE PHASE
ISL6326
PWM2 ISEN2ISEN2+ +12V PWM3 ISEN3ISEN3+ VCC PVCC PWM
ISL6612 DRIVER
LGATE GND
VIN BOOT uP LOAD UGATE PHASE
ISL6612
EN_PWR GND PWM4 ISEN4TCOMP TM +5V OFS FS ISEN4+ SS +12V PVCC VCC UGATE PHASE
o
DRIVER
PWM
LGATE GND
VIN BOOT
C
ISL6612 DRIVER
PWM LGATE GND
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ISL6326 Typical Application - 4-Phase Buck Converter with Integrated Temperature Compensation
+5V
+12V VCC BOOT1
VIN
UGATE1 PHASE1 FB COMP VCC DAC REF LGATE1 VDIFF VSEN RGND VTT VR_RDY VID7 VID6 VID5 VID4 VID3 VID2 VID1 ISEN3+ VID0 VRSEL VR_FAN VR_HOT VIN UGATE1 EN_PWR PWM4 GND ISEN4ISEN4+ GND LGATE1 PHASE1 ISEN2+ ISEN2PWM2 +12V VCC BOOT1 VIN uP LOAD PWM3 ISEN3PWM2 PWM1 EN_VTT ISEN1+ ISEN1PWM1 UGATE2 PHASE2 GND IDROOP
ISL6614 DRIVER
PVCC BOOT2
5V To 12V
VIN
ISL6326
LGATE2 PGND
ISL6614
TCOMP TM +5V +5V PWM1 OFS FS SS
PVCC BOOT2
DRIVER
5V To 12V
VIN
UGATE2 PHASE2
NTC LGATE2 PWM2 PGND
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ISL6326
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V All Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to VCC + 0.3V ESD (Human body model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV ESD (Machine model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200V ESD (Charged device model) . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV
Thermal Information
Thermal Resistance (Notes 1, 2) JA (C/W) JC (C/W) QFN Package. . . . . . . . . . . . . . . . . . . . 32 3.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5% Ambient Temperature (ISL6326CRZ) . . . . . . . . . . . . . . 0C to 70C Ambient Temperature (ISL6326IRZ) . . . . . . . . . . . . . .-40C to 85C
CAUTION: Stress above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER VCC SUPPLY CURRENT Nominal Supply Shutdown Supply
Operating Conditions: VCC = 5V, Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS
VCC = 5VDC; EN_PWR = 5VDC; RT = 100k, ISEN1 = ISEN2 = ISEN3 = ISEN4 = -70A VCC = 5VDC; EN_PWR = 0VDC; RT = 100k
-
18 14
26 21
mA mA
POWER-ON RESET AND ENABLE POR Threshold VCC Rising VCC Falling EN_PWR Threshold Rising Hysteresis Falling EN_VTT Threshold Rising Hysteresis Falling REFERENCE VOLTAGE AND DAC System Accuracy of ISL6326CRZ (VID = 1V-1.6V, TJ = 0C to 70C) System Accuracy of ISL6326CRZ (VID = 0.5V-1V, TJ = 0C to 70C) System Accuracy of ISL6326IRZ (VID = 1V-1.6V, TJ = -40C to 85C) System Accuracy of ISL6326IRZ (VID = 0.5V-1V,TJ = -40C to 85C) VID Pull Up VID Input Low Level VID Input High Level VRSEL Input Low Level VRSEL Input High Level DAC Source Current (Note 3) (Note 3) (Note 3) (Note 3) -0.5 -0.9 -0.6 -1 -60 0.8 0.8 -40 4 0.5 0.9 0.6 1 -20 0.4 0.4 7 %VID %VID %VID %VID A V V V V mA 4.3 3.7 0.850 0.720 0.850 0.720 4.5 3.9 0.875 130 0.745 0.875 130 0.745 4.7 4.2 0.910 0.775 0.910 0.775 V V V mV V V mV V
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ISL6326
Electrical Specifications
PARAMETER DAC Sink Current REF Source Current REF Sink Current PIN-ADJUSTABLE OFFSET Voltage at OFS Pin Offset resistor connected to ground Voltage below VCC, offset resistor connected to VCC OSCILLATORS Accuracy of Switching Frequency Setting RT = 100k 225 0.08 0.625 250 1.563 275 1.0 6.25 kHz MHz mV/s mV/s 380 1.55 400 1.600 420 1.65 mV V Operating Conditions: VCC = 5V, Unless Otherwise Specified (Continued) TEST CONDITIONS MIN 45 45 TYP 50 50 MAX 300 55 55 UNITS A A A
Adjustment Range of Switching Frequency (Note 4) Soft-Start Ramp Rate RS = 100k (Notes 5, 6)
Adjustment Range of Soft-Start Ramp Rate (Note 4) PWM GENERATOR Sawtooth Amplitude ERROR AMPLIFIER Open-Loop Gain Open-Loop Bandwidth Slew Rate Maximum Output Voltage Output High Voltage @ 2mA Output Low Voltage @ 2mA REMOTE-SENSE AMPLIFIER Bandwidth Output High Current Output High Current PWM OUTPUT PWM Output Voltage LOW Threshold PWM Output Voltage HIGH Threshold Iload = 500A Iload = 500A (Note 4) VSEN - RGND = 2.5V VSEN - RGND = 0.6 RL = 10k to ground (Note 4) (Note 4) (Note 4)
-
1.25
-
V
3.8 3.6 -
96 80 25 4.3 -
4.9 1.8
dB MHz V/s V V V
-500 -500
20 -
500 500
MHz A A
4.3
-
0.5 -
V V
CURRENT SENSE AND OVERCURRENT PROTECTION Sensed Current Tolerance (IDROOP) Overcurrent Trip Level for Average Current Peak Current Limit for Individual Channel THERMAL MONITORING AND FAN CONTROL TM Input Voltage for VR_FAN Trip TM Input Voltage for VR_FAN Reset TM Input Voltage for VR_HOT Trip TM Input Voltage for VR_HOT Reset Leakage Current of VR_FAN VR_FAN Low Voltage With externally pull-up resistor connected to VCC IVR_FAN = 4mA 1.55 1.85 1.3 1.55 1.65 1.95 1.4 1.65 1.75 2.05 1.5 1.75 30 0.4 V V V V A V ISEN1 = ISEN2 = ISEN3 = ISEN4 = 60A 57 72 100 60 85 120 63 98 140 A A A
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ISL6326
Electrical Specifications
PARAMETER Leakage Current of VR_HOT VR_HOT Low Voltage Operating Conditions: VCC = 5V, Unless Otherwise Specified (Continued) TEST CONDITIONS With externally pull-up resistor connected to VCC IVR_HOT = 4mA MIN TYP MAX 30 0.4 UNITS A V
VR READY AND PROTECTION MONITORS Leakage Current of VR_RDY VR_RDY Low Voltage Undervoltage Threshold VR_RDY Reset Voltage Overvoltage Protection Threshold With externally pull-up resistor connected to VCC IVR_RDY = 4mA VDIFF Falling VDIFF Rising Before valid VID After valid VID, the voltage above VID Overvoltage Protection Reset Hysteresis NOTES: 3. These parts are designed and adjusted for accuracy with all errors in the voltage loop included. 4. Spec guaranteed by design. 5. During soft-start, VDAC rises from 0 to 1.1V first and then ramp to VID voltage after receiving valid VID. 6. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle. 48 58 1.250 150 50 60 1.275 175 100 30 0.4 52 62 1.300 200 A V %VID %VID V mV mV
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ISL6326 Functional Pin Description
VCC - Supplies the power necessary to operate the chip. The controller starts to operate when the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below the falling POR threshold. Connect this pin directly to a +5V supply. GND - Bias and reference ground for the IC. The bottom metal base of ISL6326 is the GND. EN_PWR - This pin is a threshold-sensitive enable input for the controller. Connecting the 12V supply to EN_PWR through an appropriate resistor divider provides a means to synchronize power-up of the controller and the MOSFET driver ICs. When EN_PWR is driven above 0.875V, the ISL6326 is active depending on status of EN_VTT, the internal POR, and pending fault states. Driving EN_PWR below 0.745V will clear all fault states and prime the ISL6326 to soft-start when re-enabled. EN_VTT - This pin is another threshold-sensitive enable input for the controller. It's typically connected to VTT output of VTT voltage regulator in the computer mother board. When EN_VTT is driven above 0.875V, the ISL6326 is active depending on status of EN_PWR, the internal POR, and pending fault states. Driving EN_VTT below 0.745V will clear all fault states and prime the ISL6326 to soft-start when re-enabled. FS - Use this pin to set up the desired switching frequency. A resistor, placed from FS to ground will set the switching frequency. The relationship between the value of the resistor and the switching frequency will be described by an approximate equation. SS - Use this pin to set up the desired start-up oscillator frequency. A resistor, placed from SS to ground will set up the soft-start ramp rate. The relationship between the value of the resistor and the soft-start ramp up time will be described by an approximate equation. VID7, VID6, VID5, VID4, VID3, VID2, VID1 and VID0 These are the inputs to the internal DAC that generates the reference voltage for output regulation. Connect these pins either to open-drain outputs with or without external pull-up resistors or to active pull-up outputs. All VID pins have 40A internal pull-up current sources that diminish to zero as the voltage rises above the logic-high level. These inputs can be pulled up externally as high as VCC plus 0.3V. VRSEL - use this pin to select internal VID code. When it is connected to GND, the extended VR10 code is selected. When it's floated or pulled to high, VR11 code is selected. This input can be pulled up as high as VCC plus 0.3V. VDIFF, VSEN, and RGND - VSEN and RGND form the precision differential remote-sense amplifier. This amplifier converts the differential voltage of the remote output to a single-ended voltage referenced to local ground. VDIFF is the amplifier's output and the input to the regulation and protection circuitry. Connect VSEN and RGND to the sense pins of the remote load. FB and COMP - Inverting input and output of the error amplifier respectively. FB can be connected to VDIFF through a resistor. A properly chosen resistor between VDIFF and FB can set the load line (droop), when IDROOP pin is tied to FB pin. The droop scale factor is set by the ratio of the ISEN resistors and the inductor DCR or the dedicated current sense resistor. COMP is tied back to FB through an external R-C network to compensate the regulator. DAC and REF - The DAC pin is the output of the precision internal DAC reference. The REF pin is the positive input of the Error Amp. In typical applications, a 1k, 1% resistor is used between DAC and REF to generate a precision offset voltage. This voltage is proportional to the offset current determined by the offset resistor from OFS to ground or VCC. A capacitor is used between REF and ground to smooth the voltage transition during Dynamic VIDTM operations. PWM1, PWM2, PWM3, PWM4 - Pulse width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM3 and PWM4. Tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to configure for 3-phase operation. ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-; ISEN4+, ISEN4- - The ISEN+ and ISEN- pins are current sense inputs to individual differential amplifiers. The sensed current is used for channel current balancing, overcurrent protection, and droop regulation. Inactive channels should have their respective current sense inputs left open (for example, open ISEN4+ and ISEN4- for 3-phase operation). For DCR sensing, connect each ISEN- pin to the node between the RC sense elements. Tie the ISEN+ pin to the other end of the sense capacitor through a resistor, RISEN. The voltage across the sense capacitor is proportional to the inductor current. Therefore, the sense current is proportional to the inductor current, and scaled by the DCR of the inductor and RISEN. To match the time delay of the internal circuit, a capacitor is needed between each ISEN+ pin and GND, as described in the Current Sensing section. VR_RDY - VR_RDY indicates that soft-start has completed and the output voltage is within the regulated range around VID setting. It is an open-drain logic output. When OCP or OVP occurs, VR_RDY will be pulled to low. It will also be pulled low if the output voltage is below the undervoltage threshold. OFS - The OFS pin can be used to program a DC offset current which will generate a DC offset voltage between the REF and DAC pins. The offset current is generated via an
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external resistor and precision internal voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no offset, the OFS pin should be left unterminated. TCOMP - Temperature compensation scaling input. The voltage sensed on the TM pin is utilized as the temperature input to adjust ldroop and the overcurrent protection limit to effectively compensate for the temperature coefficient of the current sense element. To implement the integrated temperature compensation, a resistor divider circuit is needed with one resistor being connected from TCOMP to VCC of the controller and another resistor being connected from TCOMP to GND. Changing the ratio of the resistor values will set the gain of the integrated thermal compensation. When integrated temperature compensation function is not used, connect TCOMP to GND. IDROOP - IDROOP is the output pin of the sensed average channel current which is proportional to the load current. In the application which does not require loadline, this pin can be connected to GND through a resistor to generate a voltage signal, which is proportional the load current and the resistor value. In the application which requires load line, connect this pin to FB so that the sensed average current will flow through the resistor between FB and VDIFF to create a voltage drop which is proportional to load current. Tie this pin to GND if not used. TM - TM is an input pin for the VR temperature measurement. Connect this pin through an NTC thermistor to GND and a resistor to VCC of the controller. The voltage at this pin is reverse proportional to the VR temperature. ISL6326 monitors the VR temperature based on the voltage at the TM pin and outputs VR_HOT and VR_FAN signals. VR_HOT - VR_HOT is used as an indication of high VR temperature. It is an open-drain logic output. It will be pulled low if the measured VR temperature is less than a certain level, and open when the measured VR temperature reaches a certain level. A external pull-up resistor is needed. VR_FAN - VR_FAN is an output pin with open-drain logic output. It will be pulled low if the measured VR temperature is less than a certain level, and open when the measured VR temperature reaches a certain level. A external pull-up resistor is needed.
Operation
Multiphase Power Conversion
Microprocessor load current profiles have changed to the point that the advantages of multiphase power conversion are impossible to ignore. The technical challenges associated with producing a single-phase converter which is both cost-effective and thermally viable have forced a change to the cost-saving approach of multiphase. The ISL6326 controller helps reduce the complexity of implementation by integrating vital functions and requiring minimal output components. The block diagrams on pages 3, 4, and 5 provide top level views of multiphase power conversion using the ISL6326 controller.
Interleaving
The switching of each channel in a multiphase converter is timed to be symmetrically out of phase with each of the other channels. In a 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. As a result, the three-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phase. In addition, the peak-topeak amplitude of the combined inductor currents is reduced in proportion to the number of phases (Equations 1 and 2). Increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification. Figure 1 illustrates the multiplicative effect on output ripple frequency. The three channel currents (IL1, IL2, and IL3) combine to form the AC ripple current and the DC load current. The ripple component has three times the ripple frequency of each individual channel current. Each PWM pulse is terminated 1/3 of a cycle after the PWM pulse of the previous phase. The DC components of the inductor currents combine to feed the load.
IL1 + IL2 + IL3, 7A/DIV
IL1, 7A/DIV PWM1, 5V/DIV IL2, 7A/DIV PWM2, 5V/DIV IL3, 7A/DIV PWM3, 5V/DIV 1s/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR 3-PHASE CONVERTER
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To understand the reduction of ripple current amplitude in the multiphase circuit, examine the equation representing an individual channel's peak-to-peak inductor current.
( V IN - V OUT ) V OUT I PP = ----------------------------------------------------L fS V
IN
RMS input capacitor current. The single-phase converter must use an input capacitor bank with twice the RMS current capacity as the equivalent three-phase converter. Figures 18, 19 and 20 in the section entitled Input Capacitor Selection can be used to determine the input-capacitor RMS current based on load current, duty cycle, and the number of channels. They are provided as aids in determining the optimal input capacitor solution. Figure 21 shows the single phase input-capacitor RMS current for comparison.
(EQ. 1)
In Equation 1, VIN and VOUT are the input and output voltages respectively, L is the single-channel inductor value, and fS is the switching frequency.
INPUT-CAPACITOR CURRENT, 10A/DIV
PWM Modulation Scheme
The ISL6326 adopts Intersil's proprietary Active Pulse Positioning (APP) modulation scheme to improve transient performance. APP control is a unique dual-edge PWM modulation scheme with both PWM leading and trailing edges being independently moved to give the best response to transient loads. The PWM frequency, however, is constant and set by the external resistor between the FS pin and GND. To further improve the transient response, the ISL6326 also implements Intersil's proprietary Adaptive Phase Alignment (APA) technique. APA, with sufficiently large load step currents, can turn on all phases together. With both APP and APA control, ISL6326 can achieve excellent transient performance and reduce the demand on the output capacitors. Under steady state conditions the operation of the ISL6326 PWM modulator appears to be that of a conventional trailing edge modulator. Conventional analysis and design methods can therefore be used for steady state and small signal operation.
CHANNEL 1 INPUT CURRENT 10A/DIV CHANNEL 2 INPUT CURRENT 10A/DIV CHANNEL 3 INPUT CURRENT 10A/DIV 1s/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUTCAPACITOR RMS CURRENT FOR 3-PHASE CONVERTER
The output capacitors conduct the ripple component of the inductor current. In the case of multiphase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. Compare Equation 1 to the expression for the peak-to-peak current after the summation of N symmetrically phase-shifted inductor currents in Equation 2. Peak-to-peak ripple current decreases by an amount proportional to the number of channels. Output voltage ripple is a function of capacitance, capacitor equivalent series resistance (ESR), and inductor ripple current. Reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors.
( V IN - N V OUT ) V OUT I C, PP = ----------------------------------------------------------L fS V
IN
PWM Operation
The timing of each channel is set by the number of active channels. The default channel setting for the ISL6326 is four. The switching cycle is defined as the time between PWM pulse termination signals of each channel. The cycle time of the pulse signal is the inverse of the switching frequency set by the resistor between the FS pin and ground. The PWM signals command the MOSFET driver to turn on/off the channel MOSFETs. For 4-channel operation, the channel firing order is 4-3-2-1: PWM3 pulse happens 1/4 of a cycle after PWM4, PWM2 output follows another 1/4 of a cycle after PWM3, and PWM1 delays another 1/4 of a cycle after PWM2. For 3-channel operation, the channel firing order is 3-2-1. Connecting PWM4 to VCC selects three channel operation and the pulse times are spaced in 1/3 cycle increments. If PWM3 is connected to VCC, two channel operation is selected and the PWM2 pulse happens 1/2 of a cycle after PWM pulse.
(EQ. 2)
Another benefit of interleaving is to reduce input ripple current. Input capacitance is determined in part by the maximum input ripple current. Multiphase topologies can improve overall system cost and size by lowering input ripple current and allowing the designer to reduce the cost of input capacitance. The example in Figure 2 illustrates input currents from a three-phase converter combining to reduce the total input ripple current. The converter depicted in Figure 2 delivers 36A to a 1.5V load from a 12V input. The RMS input capacitor current is 5.9A. Compare this to a single-phase converter also stepping down 12V to 1.5V at 36A. The single-phase converter has 11.9A 11
Switching Frequency
Switching frequency is determined by the selection of the frequency-setting resistor, RT, which is connected from FS pin to GND (see the figures labelled Typical Applications on
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ISL6326
pages 4 and 5). Equation 3 is provided to assist in selecting the correct resistor value.
2.5X10 R T = ------------------------F SW
10 ISL6605
VIN
I (s) L
L
DCR
VOUT COUT
(EQ. 3)
INDUCTOR
C VL + R +
where FSW is the switching frequency of each phase.
VC(s)
Current Sensing
ISL6326 senses the current continuously for fast response. ISL6326 supports inductor DCR sensing, or resistive sensing techniques. The associated channel current sense amplifier uses the ISEN inputs to reproduce a signal proportional to the inductor current, IL. The sense current, ISEN, is proportional to the inductor current. The sensed current is used for current balance, load-line regulation, and overcurrent protection. The internal circuitry, shown in Figures 3, and 4, represents one channel of an N-channel converter. This circuitry is repeated for each channel in the converter, but may not be active depending on the status of the PWM3 and PWM4 pins, as described in the PWM Operation section. INDUCTOR DCR SENSING An inductor's winding is characteristic of a distributed resistance as measured by the DCR (Direct Current Resistance) parameter. Consider the inductor DCR as a separate lumped quantity, as shown in Figure 3. The channel current IL, flowing through the inductor, will also pass through the DCR. Equation 4 shows the s-domain equivalent voltage across the inductor VL.
V L = I L ( s L + DCR ) (EQ. 4)
PWM(n) ISL6326 INTERNAL CIRCUIT
In CURRENT SENSE
+ -
RISEN(n) (PTC)
ISEN-(n)
ISEN+(n)
CT
DCR I SEN = I ----------------LR ISEN FIGURE 3. DCR SENSING CONFIGURATION
With the internal low-offset current amplifier, the capacitor voltage VC is replicated across the sense resistor RISEN. Therefore, the current out of ISEN+ pin, ISEN, is proportional to the inductor current. Because of the internal filter at ISEN- pin, one capacitor, CT, is needed to match the time delay between the ISEN- and ISEN+ signals. Select the proper CT to keep the time constant of RISEN and CT (RISEN x CT ) close to 27ns. Equation 6 shows that the ratio of the channel current to the sensed current, ISEN, is driven by the value of the sense resistor and the DCR of the inductor.
DCR I SEN = I L ----------------R (EQ. 6)
A simple R-C network across the inductor extracts the DCR voltage, as shown in Figure 3. The voltage on the capacitor VC, can be shown to be proportional to the channel current IL, see Equation 5.
L s ------------- + 1 ( DCR I ) L DCR V C = -------------------------------------------------------------------( s RC + 1 ) (EQ. 5)
ISEN
If the R-C network components are selected such that the RC time constant (= R*C) matches the inductor time constant (= L/DCR), the voltage across the capacitor VC is equal to the voltage drop across the DCR, i.e., proportional to the channel current.
RESISTIVE SENSING For accurate current sense, a dedicated current-sense resistor RSENSE in series with each output inductor can serve as the current sense element (see Figure 4). This technique is more accurate, but reduces overall converter efficiency due to the additional power loss on the current sense element RSENSE. The same capacitor CT is needed to match the time delay between ISEN- and ISEN+ signals. Select the proper CT to keep the time constant of RISEN and CT (RISEN x CT ) close to 27ns.
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Equation 7 shows the ratio of the channel current to the sensed current ISEN.
R SENSE I SEN = I L ----------------------R
ISEN I
(EQ. 7)
The output of the error amplifier, VCOMP, is compared to sawtooth waveforms to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. The internal and external circuitry which control voltage regulation is illustrated in Figure 5.
EXTERNAL CIRCUIT R C CC COMP DAC ISL6326 INTERNAL CIRCUIT
L
L RSENSE VOUT COUT
ISL6326 INTERNAL CIRCUIT RISEN(n) RREF CREF ISEN-(n)
+ -
In CURRENT SENSE
REF + FB IAVG VCOMP
ISEN+(n) I R SENSE SEN = I L ------------------------R ISEN
CT
RFB
IDROOP + VDROOP VDIFF
ERROR AMPLIFIER
FIGURE 4. SENSE RESISTOR IN SERIES WITH INDUCTORS
VOUT+ VOUT-
VSEN + RGND DIFFERENTIAL REMOTE-SENSE AMPLIFIER
The inductor DCR value will increase as the temperature increases. Therefore the sensed current will increase as the temperature of the current sense element increases. In order to compensate the temperature effect on the sensed current signal, a Positive Temperature Coefficient (PTC) resistor can be selected for the sense resistor RISEN, or the integrated temperature compensation function of ISL6326 should be utilized. The integrated temperature compensation function is described in the Temperature Compensation section.
FIGURE 5. OUTPUT VOLTAGE AND LOAD-LINE REGULATION WITH OFFSET ADJUSTMENT
Channel-Current Balance
The sensed current In from each active channel are summed together and divided by the number of active channels. The resulting average current IAVG provides a measure of the total load current. Channel current balance is achieved by comparing the sensed current of each channel to the average current to make an appropriate adjustment to the PWM duty cycle of each channel with Intersil's patented current-balance method. Channel current balance is essential in achieving the thermal advantage of multiphase operation. With good current balance, the power loss is equally dissipated over multiple devices and a greater area.
The ISL6326 incorporates an internal differential remotesense amplifier in the feedback path. The amplifier removes the voltage error encountered when measuring the output voltage relative to the local controller ground reference point resulting in a more accurate means of sensing output voltage. Connect the microprocessor sense pins to the non-inverting input, VSEN, and inverting input, RGND, of the remote-sense amplifier. The remote-sense output, VDIFF, is connected to the inverting input of the error amplifier through an external resistor. A digital-to-analog converter (DAC) generates a reference voltage based on the state of logic signals at pins VID7 through VID0. The DAC decodes the eight 6-bit logic signal (VID) into one of the discrete voltages shown in Table 1. Each VID input offers a 45A pull-up to an internal 2.5V source for use with open-drain outputs. The pull-up current diminishes to zero above the logic threshold to protect voltage-sensitive output devices. External pull-up resistors can augment the pull-up current sources if case leakage into the driving device is greater than 45A.
Voltage Regulation
The compensation network shown in Figure 5 assures that the steady-state error in the output voltage is limited only to the error in the reference voltage (output of the DAC) and offset errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6326 to include the combined tolerances of each of these elements.
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TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION) VID4 VID3 VID2 VID1 VID0 VID5 VID6 VOLTAGE 400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV (V) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1.6 1.59375 1.5875 1.58125 1.575 1.56875 1.5625 1.55625 1.55 1.54375 1.5375 1.53125 1.525 1.51875 1.5125 1.50625 1.5 1.49375 1.4875 1.48125 1.475 1.46875 1.4625 1.45625 1.45 1.44375 1.4375 1.43125 1.425 1.41875 1.4125 1.40625 1.4 1.39375 1.3875 1.38125 1.375 1.36875 TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION) (Continued) VID4 VID3 VID2 VID1 VID0 VID5 VID6 VOLTAGE 400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV (V) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.3625 1.35625 1.35 1.34375 1.3375 1.33125 1.325 1.31875 1.3125 1.30625 1.3 1.29375 1.2875 1.28125 1.275 1.26875 1.2625 1.25625 1.25 1.24375 1.2375 1.23125 1.225 1.21875 1.2125 1.20625 1.2 1.19375 1.1875 1.18125 1.175 1.16875 1.1625 1.15625 1.15 1.14375 1.1375 1.13125 1.125
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TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION) (Continued) VID4 VID3 VID2 VID1 VID0 VID5 VID6 VOLTAGE 400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV (V) 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1.11875 1.1125 1.10625 1.1 1.09375 OFF OFF OFF OFF 1.0875 1.08125 1.075 1.06875 1.0625 1.05625 1.05 1.04375 1.0375 1.03125 1.025 1.01875 1.0125 1.00625 1 0.99375 0.9875 0.98125 0.975 0.96875 0.9625 0.95625 0.95 0.94375 0.9375 0.93125 0.925 0.91875 0.9125 0.90625 TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION) (Continued) VID4 VID3 VID2 VID1 VID0 VID5 VID6 VOLTAGE 400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV (V) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0.9 0.89375 0.8875 0.88125 0.875 0.86875 0.8625 0.85625 0.85 0.84375 0.8375 0.83125
TABLE 2. VR11 VID 8 BIT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OFF OFF 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875
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TABLE 2. VR11 VID 8 BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 TABLE 2. VR11 VID 8 BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875
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TABLE 2. VR11 VID 8 BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 0.82500 0.81875 0.81250 0.80625 0.80000 0.79375 0.78750 0.78125 0.77500 0.76875 0.76250 0.75625 0.75000 0.74375 0.73750 0.73125 0.72500 0.71875 TABLE 2. VR11 VID 8 BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0.71250 0.70625 0.70000 0.69375 0.68750 0.68125 0.67500 0.66875 0.66250 0.65625 0.65000 0.64375 0.63750 0.63125 0.62500 0.61875 0.61250 0.60625 0.60000 0.59375 0.58750 0.58125 0.57500 0.56875 0.56250 0.55625 0.55000 0.54375 0.53750 0.53125 0.52500 0.51875 0.51250 0.50625 0.50000 OFF OFF
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Load-Line Regulation
Some microprocessor manufacturers require a preciselycontrolled output resistance. This dependence of output voltage on load current is often termed "droop" or "load line" regulation. By adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction which works to achieve the load-line regulation required by these manufacturers. In other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. Droop can help to reduce the output voltage spike that results from fast load-current demand changes. The magnitude of the spike is dictated by the ESR and ESL of the output capacitors selected. By positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. By adding a well controlled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit. As shown in Figure 5, a current proportional to the average current of all active channels, IAVG, flows from FB through a load-line regulation resistor RFB. The resulting voltage drop across RFB is proportional to the output current, effectively creating an output voltage droop with a steady-state value defined as
V DROOP = I AVG R FB (EQ. 8)
E/A
Output Voltage Offset Programming
The ISL6326 allows the designer to accurately adjust the offset voltage. When a resistor, ROFS, is connected between OFS to VCC, the voltage across it is regulated to 1.6V. This causes a proportional current (IOFS) to flow into OFS. If ROFS is connected to ground, the voltage across it is regulated to 0.4V, and IOFS flows out of OFS. A resistor between DAC and REF, RREF, is selected so that the product (IOFS x ROFS) is equal to the desired offset voltage. These functions are shown in Figure 6. Once the desired output offset voltage has been determined, use the following formulas to set ROFS: For Positive Offset (connect ROFS to VCC):
1.6 x R REF R OFS = ----------------------------V OFFSET (EQ. 11)
For Negative Offset (connect ROFS to GND):
0.4 x R REF R OFS = ----------------------------V OFFSET (EQ. 12)
FB
DYNAMIC VID D/A
DAC
RREF REF CREF
The regulated output voltage is reduced by the droop voltage VDROOP. The output voltage as a function of load current is derived by combining Equation 8 with the appropriate sample current expression defined by the current sense method employed.
I OUT R X V OUT = V REF - V OFS - ------------ ----------------- R FB N R ISEN (EQ. 9)
VCC OR GND 1.6V + 0.4V + GND OFS ISL6326B
Where VREF is the reference voltage, VOFS is the programmed offset voltage, IOUT is the total output current of the converter, RISEN is the sense resistor connected to the ISEN+ pin, and RFB is the feedback resistor, N is the active channel number, and RX is the DCR, or RSENSE depending on the sensing method. Therefore the equivalent loadline impedance, i.e. Droop impedance, is equal to:
R FB R X R LL = ------------ ----------------N R ISEN (EQ. 10)
ROFS
VCC
FIGURE 6. OUTPUT VOLTAGE OFFSET PROGRAMMING
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Dynamic VID
Modern microprocessors need to make changes to their core voltage as part of normal operation. They direct the core voltage regulator to do this by making changes to the VID inputs during regulator operation. The power management solution is required to monitor the DAC inputs and respond to on-the-fly VID changes in a controlled manner. Supervising the safe output voltage transition within the DAC range of the processor without discontinuity or disruption is a necessary function of the core voltage regulator. In order to ensure the smooth transition of output voltage during VID change, a VID step change smoothing network, composed of RREF and CREF as shown in Figure 6, can be used. The selection of RREF is based on the desired offset voltage as detailed above in Output Voltage Offset Programming. The selection of CREF is based on the time duration for 1 bit VID change and the allowable delay time. Assuming the microprocessor controls the VID change at 1 bit every TVID, the relationship between the time constant of RREF and CREF network and TVID is given by the following equation.
C REF R REF = T VID (EQ. 13)
SOFT-START AND FAULT LOGIC
family of Intersil MOSFET drivers, which require 12V bias. 3. The voltage on EN_VTT must be higher than 0.875V to enable the controller. This pin is typically connected to the output of VTT VR.
ISL6326 INTERNAL CIRCUIT EXTERNAL CIRCUIT VCC +12V
POR CIRCUIT
ENABLE COMPARATOR + -
10k EN_PWR
910 0.875V
+ -
EN_VTT
0.875V
Operation Initialization
Prior to converter initialization, proper conditions must exist on the enable inputs and VCC. When the conditions are met, the controller begins soft-start. Once the output voltage is within the proper window of operation, VR_RDY asserts logic high.
FIGURE 7. POWER SEQUENCING USING THRESHOLDSENSITIVE ENABLE (EN) FUNCTION
Enable and Disable
While in shutdown mode, the PWM outputs are held in a high-impedance state to assure the drivers remain off. The following input conditions must be met before the ISL6326 is released from shutdown mode. 1. The bias voltage applied at VCC must reach the internal power-on reset (POR) rising threshold. Once this threshold is reached, proper operation of all aspects of the ISL6326 is guaranteed. Hysteresis between the rising and falling thresholds assure that once enabled, the ISL6326 will not inadvertently turn off unless the bias voltage drops substantially (see Electrical Specifications). 2. The ISL6326 features an enable input (EN_PWR) for power sequencing between the controller bias voltage and another voltage rail. The enable comparator holds the ISL6326 in shutdown until the voltage at EN_PWR rises above 0.875V. The enable comparator has about 130mV of hysteresis to prevent bounce. It is important that the driver ICs reach their POR level before the ISL6326 becomes enabled. The schematic in Figure 7 demonstrates sequencing the ISL6326 with the ISL66xx
When all conditions above are satisfied, ISL6326 begins the soft-start and ramps the output voltage to 1.1V first. After remaining at 1.1V for some time, ISL6326 reads the VID code at VID input pins. If the VID code is valid, ISL6326 will regulate the output to the final VID setting. If the VID code is OFF code, ISL6326 will shut down, and cycling VCC, EN_PWR or EN_VTT is needed to restart.
Soft-Start
ISL6326 based VR has 4 periods during soft-start as shown in Figure 8. After VCC, EN_VTT and EN_PWR reach their POR/enable thresholds, The controller will have fixed delay period TD1. After this delay period, the VR will begin first soft-start ramp until the output voltage reaches 1.1V Vboot voltage. Then, the controller will regulate the VR voltage at 1.1V for another fixed period TD3. At the end of TD3 period, ISL6326 reads the VID signals. If the VID code is valid, ISL6326 will initiate the second soft-start ramp until the voltage reaches the VID voltage minus offset voltage. The soft-start time is the sum of the 4 periods as shown in the following equation.
T SS = TD1 + TD2 + TD3 + TD4 (EQ. 14)
TD1 is a fixed delay with the typical value as 1.36ms. TD3 is determined by the fixed 85s plus the time to obtain valid
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VID voltage. If the VID is valid before the output reaches the 1.1V, the minimum time to validate the VID input is 500ns. Therefore the minimum TD3 is about 86s. During TD2 and TD4, ISL6326 digitally controls the DAC voltage change at 6.25mV per step. The time for each step is determined by the frequency of the soft-start oscillator which is defined by the resistor Rss from SS pin to GND. The second soft-start ramp time TD2 and TD4 can be calculated based on the following equations:
1.1xR SS TD2 = ----------------------- ( s ) 6.25x25 ( V VID - 1.1 )xR SS TD4 = ------------------------------------------------ ( s ) 6.25x25 (EQ. 15)
when an undervoltage or overvoltage condition is detected, or the controller is disabled by a reset from EN_PWR, EN_VTT, POR, or VID OFF-code.
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID code. When the output voltage at VSEN is below the undervoltage threshold, VR_RDY is pulled low.
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6326 overvoltage protection (OVP) circuit will be active after its POR. The OVP thresholds are different under different operation conditions. When VR is not enabled and during the soft-start intervals TD1, TD2 and TD3, the OVP threshold is 1.275V. Once the controller detects valid VID input, the OVP trip point will be changed to DAC plus 175mV. Two actions are taken by the ISL6326 to protect the microprocessor load when an overvoltage condition occurs. At the inception of an overvoltage event, all PWM outputs are commanded low instantly (less than 20ns). This causes the Intersil drivers to turn on the lower MOSFETs and pull the output voltage below a level to avoid damaging the load. When the VDIFF voltage falls below the DAC plus 75mV, PWM signals enter a high-impedance state. The Intersil drivers respond to the high-impedance input by turning off both upper and lower MOSFETs. If the overvoltage condition reoccurs, the ISL6326 will again command the lower MOSFETs to turn on. The ISL6326 will continue to protect the load in this fashion as long as the overvoltage condition occurs. Once an overvoltage condition is detected, normal PWM operation ceases until the ISL6326 is reset. Cycling the voltage on EN_PWR, EN_VTT or VCC below the POR-falling threshold will reset the controller. Cycling the VID codes will not reset the controller.
(EQ. 16)
For example, when VID is set to 1.5V and the Rss is set at 100k, the first soft-start ramp time TD2 will be 704s and the second soft-start ramp time TD4 will be 256s. After the DAC voltage reaches the final VID setting, VR_RDY will be set to high with the fixed delay TD5. The typical value for TD5 is 85s.
VOUT, 500mV/DIV
TD1
TD2 EN_VTT
TD3 TD4
TD5
VR_RDY 500s/DIV
FIGURE 8. SOFT-START WAVEFORMS
Fault Monitoring and Protection
The ISL6326 actively monitors output voltage and current to detect fault conditions. Fault monitors trigger protective measures to prevent damage to a microprocessor load. One common power good indicator is provided for linking to external system monitors. The schematic in Figure 9 outlines the interaction between the fault monitors and the VR_RDY signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate that the soft-start period has completed and the output voltage is within the regulated range. VR_RDY is pulled low during shutdown and releases high after a successful soft-start and a fixed delay TD5. VR_RDY will be pulled low
20
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ISL6326
VR_RDY OUTPUT CURRENT UV
+
-
50%
0A
DAC
SOFT-START, FAULT AND CONTROL LOGIC
OC
85A OUTPUT VOLTAGE IAVG
+
VDIFF
+
OV
0V
2ms/DIV
VID + 0.175V
FIGURE 10. OVERCURRENT BEHAVIOR IN HICCUP MODE. FSW = 500kHz
FIGURE 9. VR_RDY AND PROTECTION CIRCUITRY
Overcurrent Protection
ISL6326 has two levels of overcurrent protection. Each phase is protected from a sustained overcurrent condition by limiting its peak current, while the combined phase currents are protected on an instantaneous basis. In instantaneous protection mode, the ISL6326 utilizes the sensed average current IAVG to detect an overcurrent condition. See the Channel-Current Balance section for more detail on how the average current is measured. The average current is continually compared with a constant 85A reference current, as shown in Figure 9. Once the average current exceeds the reference current, a comparator triggers the converter to shutdown. At the beginning of overcurrent shutdown, the controller places all PWM signals in a high-impedance state within 20ns, commanding the Intersil MOSFET driver ICs to turn off both upper and lower MOSFETs. The system remains in this state a period of 4096 switching cycles. If the controller is still enabled at the end of this wait period, it will attempt a softstart. If the fault remains, the trip-retry cycles will continue indefinitely (as shown in Figure 10) until either controller is disabled or the fault is cleared. Note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard during this kind of operation.
For the individual channel overcurrent protection, the ISL6326 continuously compares the sensed current signal of each channel with the 120A reference current. If one channel current exceeds the reference current, ISL6326 will pull PWM signal of this channel to low for the rest of the switching cycle. This PWM signal can be turned on next cycle if the sensed channel current is less than the 120A reference current. The peak current limit of individual channel will not trigger the converter to shutdown.
Thermal Monitoring (VR_HOT/VR_FAN)
There are two thermal signals to indicate the temperature status of the voltage regulator: VR_HOT and VR_FAN. Both VR_FAN and VR_HOT pins are open-drain outputs, and external pull-up resistors are required. Those signals are valid only after the controller is enabled. The VR_FAN signal indicates that the temperature of the voltage regulator is high and more cooling airflow is needed. The VR_HOT signal can be used to inform the system that the temperature of the voltage regulator is too high and the CPU should reduce its power consumption. The VR_HOT signal may be tied to the CPU's PROC_HOT signal. The diagram of thermal monitoring function block is shown in Figure 11. One NTC resistor should be placed close to the power stage of the voltage regulator to sense the operational temperature, and one pull-up resistor is needed to form the voltage divider for the TM pin. As the temperature of the power stage increases, the resistance of the NTC will reduce, resulting in the reduced voltage at the TM pin. Figure 12 shows the TM voltage over the temperature for a typical design with a recommended 6.8k NTC (P/N: NTHS0805N02N6801 from Vishay) and 1k resistor RTM1. We recommend using those resistors for the accurate temperature compensation. There are two comparators with hysteresis to compare the TM pin voltage to the fixed thresholds for VR_FAN and
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VR_HOT signals respectively. The VR_FAN signal is set to high when the TM voltage is lower than 33% of VCC voltage, and is pulled to GND when the TM voltage increases to above 39% of VCC voltage. The VR_FAN signal is set to high when the TM voltage goes below 28% of VCC voltage, and is pulled to GND when the TM voltage goes back to above 33% of VCC voltage. Figure 13 shows the operation of those signals.
TM
0.39*Vcc 0.33*Vcc 0.28*Vcc
VR_FAN
VR_HOT
Temperature
T1 T2 T3
VCC VR_FAN
FIGURE 13. VR_HOT AND VR_FAN SIGNAL vs TM VOLTAGE
RTM1 TM
oc
0.33VCC
VR_HOT
Based on the NTC temperature characteristics and the desired threshold of the VR_HOT signal, the pull-up resistor RTM1 of TM pin is given by:
R TM1 = 2.75xR NTC ( T3 ) (EQ. 17)
RNTC
0.28VCC
RNTC(T3) is the NTC resistance at the VR_HOT threshold temperature T3. The NTC resistance at the set point T2 and release point T1 of VR_FAN signal can be calculated as:
R NTC ( T2 ) = 1.267xR NTC ( T3 ) (EQ. 18)
FIGURE 11. BLOCK DIAGRAM OF THERMAL MONITORING FUNCTION
V TM / V CC vs. Tem perature 100% 90% 80% V TM / V CC 70% 60% 50% 40% 30% 20% 0 20 40 60 80 100 Tem perature ( oC) 120 140
R NTC ( T1 ) = 1.644xR NTC ( T3 )
(EQ. 19)
With the NTC resistance value obtained from Equations 17 and 18, the temperature value T2 and T1 can be found from the NTC datasheet.
Temperature Compensation
ISL6326 supports inductor DCR sensing, or resistive sensing techniques. The inductor DCR has a positive temperature coefficient, which is about +0.38%/C. Since the voltage across inductor is sensed for the output current information, the sensed current has the same positive temperature coefficient as the inductor DCR. In order to obtain the correct current information, there should be a way to correct the temperature impact on the current sense component. ISL6326 provides two methods: integrated temperature compensation and external temperature compensation.
FIGURE 12. THE RATIO OF TM VOLTAGE TO NTC TEMPERATURE WITH RECOMMENDED PARTS
Integrated Temperature Compensation
When the TCOMP voltage is equal or greater than VCC/15, ISL6326 will utilize the voltage at TM and TCOMP pins to compensate the temperature impact on the sensed current. The block diagram of this function is shown in Figure 14.
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ISL6326 multiplexes the TCOMP factor N with the TM digital signal to obtain the adjustment gain to compensate the temperature impact on the sensed channel current. The compensated channel current signal is used for droop and overcurrent protection functions.
VCC RTM1
TM
Channel current sense Non-linear A/D I4 I3 I2 I1
Isen4 Isen3 Isen2 Isen1
Design Procedure
1. Properly choose the voltage divider for the TM pin to match the TM voltage vs temperature curve with the recommended curve in Figure 12. 2. Run the actual board under the full load and the desired cooling condition. 3. After the board reaches the thermal steady state, record the temperature (TCSC) of the current sense component (inductor or MOSFET) and the voltage at TM and VCC pins. 4. Use the following equation to calculate the resistance of the TM NTC, and find out the corresponding NTC temperature TNTC from the NTC datasheet.
R NTC ( T V TM xR TM1 ) = ------------------------------V CC - V NTC TM (EQ. 20)
oc
RNTC D/A ki
VCC RTC1
TCOMP
4-bit A/D
Droop & Over current protection
RTC2
FIGURE 14. BLOCK DIAGRAM OF INTEGRATED TEMPERATURE COMPENSATION
When the TM NTC is placed close to the current sense component (inductor), the temperature of the NTC will track the temperature of the current sense component. Therefore the TM voltage can be utilized to obtain the temperature of the current sense component. Based on VCC voltage, ISL6326 converts the TM pin voltage to a 6-bit TM digital signal for temperature compensation. With the non-linear A/D converter of ISL6326, the TM digital signal is linearly proportional to the NTC temperature. For accurate temperature compensation, the ratio of the TM voltage to the NTC temperature of the practical design should be similar to that in Figure 12. Depending on the location of the NTC and the airflow, the NTC may be cooler or hotter than the current sense component. The TCOMP pin voltage can be utilized to correct the temperature difference between NTC and the current sense component. When a different NTC type or different voltage divider is used for the TM function, the TCOMP voltage can also be used to compensate for the difference between the recommended TM voltage curve in Figure 13 and that of the actual design. According to the VCC voltage, ISL6326 converts the TCOMP pin voltage to a 4-bit TCOMP digital signal as TCOMP factor N. The TCOMP factor N is an integer between 0 and 15. The integrated temperature compensation function is disabled for N = 0. For N = 4, the NTC temperature is equal to the temperature of the current sense component. For N < 4, the NTC is hotter than the current sense component. The NTC is cooler than the current sense component for N > 4. When N > 4, the larger TCOMP factor N, the larger the difference between the NTC temperature and the temperature of the current sense component.
5. Use the following equation to calculate the TCOMP factor N:
) 209x ( T CSC - T NTC N = ------------------------------------------------------- + 4 3xTNTC + 400 (EQ. 21)
6. Choose an integral number close to the above result for the TCOMP factor. If this factor is higher than 15, use N = 15. If it is less than 1, use N = 1. 7. Choose the pull-up resistor RTC1 (typical 10k). 8. If N = 15, do not need the pull-down resistor RTC2, otherwise obtain RTC2 by the following equation:
NxR TC1 R TC2 = ---------------------15 - N (EQ. 22)
9. Run the actual board under full load again with the proper resistors connected to the TCOMP pin. 10. Record the output voltage as V1 immediately after the output voltage is stable with the full load. Record the output voltage as V2 after the VR reaches the thermal steady state. 11. If the output voltage increases over 2mV as the temperature increases, i.e. V2-V1 > 2mV, reduce N and redesign RTC2; if the output voltage decreases over 2mV as the temperature increases, i.e. V1-V2 > 2mV, increase N and redesign RTC2.
External Temperature Compensation
By pulling the TCOMP pin to GND, the integrated temperature compensation function is disabled. And one external temperature compensation network, shown in Figure 15, can be used to cancel the temperature impact on the droop (i.e. load line).
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ISL6326 General Design Guide
COMP ISL6326 Internal circuit
IDROOP
o
C FB
This design guide is intended to provide a high-level explanation of the steps necessary to create a multiphase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications.
VDIFF
Power Stages
The first step in designing a multiphase converter is to determine the number of phases. This determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board; whether through-hole components are permitted; and the total board space available for power-supply circuitry. Generally speaking, the most economical solutions are those in which each phase handles between 15 and 20A. All surface-mount designs will tend toward the lower end of this current range. If through-hole MOSFETs and inductors can be used, higher per-phase currents are possible. In cases where board space is the limiting constraint, current can be pushed as high as 40A per phase, but these designs require heat sinks and forced air to cool the MOSFETs, inductors and heat-dissipating surfaces. MOSFETs The choice of MOSFETs depends on the current each MOSFET will be required to conduct; the switching frequency; the capability of the MOSFETs to dissipate heat; and the availability and nature of heat sinking and air flow. LOWER MOSFET POWER CALCULATION The calculation for heat dissipated in the lower MOSFET is simple, since virtually all of the heat loss in the lower MOSFET is due to current conducted through the channel resistance (RDS(ON)). In Equation 24, IM is the maximum continuous output current; IPP is the peak-to-peak inductor current (see Equation 1); d is the duty cycle (VOUT/VIN); and L is the per-channel inductance.
I L, 2 ( 1 - d ) I M 2 PP P LOW, 1 = r DS ( ON ) ----- ( 1 - d ) + -------------------------------12 N (EQ. 24)
FIGURE 15. EXTERNAL TEMPERATURE COMPENSATION
The sensed current will flow out of the IDROOP pin and develop a droop voltage across the resistor equivalent (RFB) between the FB and VDIFF pins. If RFB resistance reduces as the temperature increases, the temperature impact on the droop can be compensated. An NTC resistor can be placed close to the power stage and used to form RFB. Due to the non-linear temperature characteristics of the NTC, a resistor network is needed to make the equivalent resistance between the FB and VDIFF pins reverse proportional to the temperature. The external temperature compensation network can only compensate the temperature impact on the droop, while it has no impact to the sensed current inside ISL6326. Therefore, this network cannot compensate for the temperature impact on the overcurrent protection function.
Current Sense Output
The current from the IDROOP pin is the sensed average current inside the ISL6326. In typical application, the IDROOP pin is connected to the FB pin for the application where load line is required. When load line function is not needed, the IDROOP pin can be used to obtain the load current information: with one resistor from the IDROOP pin to GND, the voltage at the IDROOP pin will be proportional to the load current:
R IDROOP R X V IDROOP = --------------------------- ----------------- I LOAD N R ISEN (EQ. 23)
where VIDROOP is the voltage at the IDROOP pin, RIDROOP is the resistor between the IDROOP pin and GND, ILOAD is the total output current of the converter, RISEN is the sense resistor connected to the ISEN+ pin, N is the active channel number, and RX is the resistance of the current sense element, either the DCR of the inductor or RSENSE depending on the sensing method. The resistor from the IDROOP pin to GND should be chosen to ensure that the voltage at the IDROOP pin is less than 2V under the maximum load current. If the IDROOP pin is not use, tie it to GND.
An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-MOSFET body diode. This term is dependent on the diode forward voltage at IM, VD(ON); the switching frequency, fS; and the length of dead times, td1 and td2, at the beginning and the end of the lower-MOSFET conduction interval respectively.
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I IM M I PP t P LOW, 2 = V D ( ON ) f S ----- + I PP t N- -------- d1 + ----- - -------- d2 2 2 N
(EQ. 25)
solutions to the loss equations for different MOSFETs and different switching frequencies.
2 2 I PP I M P UP,4 r DS ( ON ) ----- d + --------- d 12 N
Thus the total maximum power dissipated in each lower MOSFET is approximated by the summation of PLOW,1 and PLOW,2. Upper MOSFET Power Calculation In addition to RDS(ON) losses, a large portion of the upperMOSFET losses are due to currents conducted across the input voltage (VIN) during switching. Since a substantially higher portion of the upper-MOSFET losses are dependent on switching frequency, the power calculation is more complex. Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times; the lower-MOSFET body-diode reverserecovery charge, Qrr; and the upper MOSFET RDS(ON) conduction loss. When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 26, the required time for this commutation is t1 and the approximated associated power loss is PUP,1.
I M I PP t 1 P UP,1 V IN ----- + -------- ---- f S N2 2 (EQ. 26)
(EQ. 29)
Current Sensing Resistor
The resistors connected to the Isen+ pins determine the gains in the load-line regulation loop and the channel-current balance loop as well as setting the overcurrent trip point. Select values for these resistors by the following equation:
RX I R ISEN = ---------------------- ------------- OCP -6 N 85 x10 (EQ. 30)
where RISEN is the sense resistor connected to the ISEN+ pin, N is the active channel number, RX is the resistance of the current sense element, either the DCR of the inductor or RSENSE depending on the sensing method, and IOCP is the desired overcurrent trip point. Typically, IOCP can be chosen to be 1.3 times the maximum load current of the specific application. With integrated temperature compensation, the sensed current signal is independent on the operational temperature of the power stage, i.e. the temperature effect on the current sense element RX is cancelled by the integrated temperature compensation function. RX in Equation 30 should be the resistance of the current sense element at the room temperature. When the integrated temperature compensation function is disabled by pulling the TCOMP pin to GND, the sensed current will be dependent on the operational temperature of the power stage, since the DC resistance of the current sense element may be changed according to the operational temperature. RX in Equation 30 should be the maximum DC resistance of the current sense element at the all operational temperature. In certain circumstances, it may be necessary to adjust the value of one or more ISEN resistors. When the components of one or more channels are inhibited from effectively dissipating their heat so that the affected channels run hotter than desired, choose new, smaller values of RISEN for the affected phases (see the section entitled Channel-Current Balance). Choose RISEN,2 in proportion to the desired decrease in temperature rise in order to cause proportionally less current to flow in the hotter phase:
T 2 R ISEN ,2 = R ISEN ---------T 1 (EQ. 31)
At turn on, the upper MOSFET begins to conduct and this transition occurs over a time t2. In Equation 27, the approximate power loss is PUP,2.
I M I PP t 2 P UP, 2 V IN ----- - -------- ---- f S 2 2 N (EQ. 27)
A third component involves the lower MOSFET's reverserecovery charge, Qrr. Since the inductor current has fully commutated to the upper MOSFET before the lowerMOSFET's body diode can draw all of Qrr, it is conducted through the upper MOSFET across VIN. The power dissipated as a result is PUP,3 and is approximately
P UP,3 = V IN Q rr f S (EQ. 28)
Finally, the resistive part of the upper MOSFET's is given in Equation 29 as PUP,4. The total power dissipated by the upper MOSFET at full load can now be approximated as the summation of the results from Equations 26, 27, and 28. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process involving repetitive
In Equation 31, make sure that T2 is the desired temperature rise above the ambient temperature, and T1 is the measured temperature rise above the ambient temperature. While a single adjustment according to Equation 31 is usually sufficient, it may occasionally be necessary to adjust RISEN
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two or more times to achieve optimal thermal balance between all channels. Fortunately, there is a simple approximation that comes very close to an optimal solution. Treating the system as though it were a voltage-mode regulator by compensating the L-C poles and the ESR zero of the voltage-mode approximation, yields a solution that is always stable with very close to ideal transient performance.
C2 (OPTIONAL)
Load-Line Regulation Resistor
The load-line regulation resistor is labelled RFB in Figure 5. Its value depends on the desired loadline requirement of the application. The desired loadline can be calculated by the following equation:
V DROOP R LL = -----------------------I FL (EQ. 32)
RC
CC
COMP
+ RFB VDROOP -
IDROOP
Based on the desired loadline RLL, the loadline regulation resistor can be calculated by the following equation:
NR R ISEN LL R FB = --------------------------------RX (EQ. 33)
VDIFF
where N is the active channel number, RISEN is the sense resistor connected to the ISEN+ pin, and RX is the resistance of the current sense element, either the DCR of the inductor or RSENSE depending on the sensing method. If one or more of the current sense resistors are adjusted for thermal balance, as in Equation 31, the load-line regulation resistor should be selected based on the average value of the current sensing resistors, as given in the following equation:
R LL R FB = ---------RX
FIGURE 16. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6326 CIRCUIT
RISEN ( n )
n
(EQ. 34)
The feedback resistor, RFB, has already been chosen as outlined in Load-Line Regulation Resistor. Select a target bandwidth for the compensated system, f0. The target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the perHchannel switching frequency. The values of the compensation components depend on the relationships of f0 to the L-C pole frequency and the ESR zero frequency. For each of the three cases which follow, there is a separate set of equations for the compensation components.
where RISEN(n) is the current sensing resistor connected to the nth ISEN+ pin.
Compensation
The two opposing goals of compensating the voltage regulator are stability and speed. Depending on whether the regulator employs the optional load-line regulation as described in Load-Line Regulation, there are two distinct methods for achieving these goals. COMPENSATING LOAD-LINE REGULATED CONVERTER The load-line regulated converter behaves in a similar manner to a peak-current mode controller because the two poles at the output-filter L-C resonant frequency split with the introduction of current information into the control loop. The final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, RC and CC. Since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equation becomes fairly complicated.
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ISL6326
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where IFL is the full load current of the specific application, and VRDROOP is the desired voltage droop under the full load condition.
FB
ISL6326
Case 1:
1 ------------------- > f 0 2 LC 2f 0 V pp LC R C = R FB ----------------------------------0.75V
IN RC C2
CC
COMP
0.75V IN C C = ----------------------------------2V PP R FB f 0
C1
FB
Case 2:
1 1 ------------------- f 0 < ----------------------------2C ( ESR ) 2 LC V PP ( 2 ) 2 f 02 LC R C = R FB -------------------------------------------0.75 V
IN
R1
RFB
IDROOP
VDIFF
(EQ. 35) FIGURE 17. COMPENSATION CIRCUIT FOR ISL6326 BASED CONVERTER WITHOUT LOAD-LINE REGULATION
0.75V IN C C = -----------------------------------------------------------2 f 2V ( 2 ) 0 PP R FB LC
Case 3:
1 f 0 > ----------------------------2C ( ESR ) 2 f 0 V pp L R C = R FB ----------------------------------------0.75 V IN ( ESR ) 0.75V IN ( ESR ) C C C = -----------------------------------------------2V PP R FB f 0 L
In Equation 35, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and VPP is the sawtooth amplitude described in Electrical Specifications. The optional capacitor C2, is sometimes needed to bypass noise away from the PWM comparator (see Figure 16). Keep a position available for C2, and be prepared to install a highHfrequency capacitor of between 22pF and 150pF in case any leading-edge jitter problem is noted. Once selected, the compensation values in Equation 35 assure a stable converter with reasonable transient performance. In most cases, transient performance can be improved by making adjustments to RC. Slowly increase the value of RC while observing the transient performance on an oscilloscope until no further improvement is noted. Normally, CC will not need adjustment. Keep the value of CC from Equation 35 unless some performance issue is noted. COMPENSATION WITHOUT LOAD-LINE REGULATION The non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the L-C resonant frequency and a zero at the ESR frequency. A type III controller, as shown in Figure 17, provides the necessary compensation.
The first step is to choose the desired bandwidth, f0, of the compensated system. Choose a frequency high enough to assure adequate transient performance but not higher than 1/3 of the switching frequency. The type-III compensator has an extra high-frequency pole, fHF. This pole can be used for added noise rejection or to assure adequate attenuation at the error-amplifier high-order pole and zero frequencies. A good general rule is to choose fHF = 10f0, but it can be higher if desired. Choosing fHF to be lower than 10f0 can cause problems with too much phase shift below the system bandwidth. In the solutions to the compensation equations, there is a single degree of freedom. For the solutions presented in Equation 36, RFB is selected arbitrarily. The remaining compensation components are then selected according to Equation 36.
C ( ESR ) R 1 = R FB ---------------------------------------LC - C ( ESR ) LC - C ( ESR ) C 1 = ---------------------------------------R FB 0.75V IN C 2 = -----------------------------------------------------------------( 2 ) 2 f 0 f HF LCR FB V PP V PP 2 f 0 f HF LCR FB R C = -------------------------------------------------------------------2f 0.75 V HF LC - 1
IN 2
ISL6326 (EQ. 36)
FN9262.0 April 21, 2006
0.75V IN 2f HF LC - 1 C C = -----------------------------------------------------------------( 2 ) 2 f 0 f HF LCR FB V PP
In Equation 36, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and VPP is the sawtooth signal amplitude as described in Electrical Specifications. 27
ISL6326
Output Filter Design
The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter necessarily limits the system transient response. The output capacitor must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, I; the load-current slew rate, di/dt; and the maximum allowable output voltage deviation under transient loading, VMAX. Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total output voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount:
di V ( ESL ) ---- + ( ESR ) I dt (EQ. 37)
Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than VMAX. This places an upper limit on inductance. Equation 39 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater output voltage deviation than the leading edge. Equation 40 addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the per-channel inductance, C is the total output capacitance, and N is the number of active channels.
2NCVO L -------------------- V MAX - I ( ESR ) ( I ) 2 ( 1.25 ) NC L ------------------------- V MAX - I ( ESR ) V IN - V O ( I ) 2 (EQ. 39)
(EQ. 40)
Input Supply Voltage Selection
The VCC input of the ISL6326 can be connected either directly to a +5V supply or through a current limiting resistor to a +12V supply. An integrated 5.8V shunt regulator maintains the voltage on the VCC pin when a +12V supply is used. A 300 resistor is suggested for limiting the current into the VCC pin to a worst-case maximum of approximately 25mA.
Switching Frequency Selection
There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper-MOSFET loss calculation. These effects are outlined in MOSFETs, and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response and small output voltage ripple as outlined in Output Filter Design. Choose the lowest switching frequency that allows the regulator to meet the transient-response requirements.
The filter capacitor must have sufficiently low ESL and ESR so that V < VMAX. Most capacitor solutions rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. The ESR of the bulk capacitors also creates the majority of the output voltage ripple. As the bulk capacitors sink and source the inductor AC ripple current (see Interleaving and Equation 2), a voltage develops across the bulk-capacitor ESR equal to IC,PP (ESR). Thus, once the output capacitors are selected, the maximum allowable ripple voltage, VPP(MAX), determines the lower limit on the inductance.
V - N V OUT V OUT IN L ( ESR ) ----------------------------------------------------------f S V IN V PP( MAX ) (EQ. 38)
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. Their RMS current capacity must be sufficient to handle the AC component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases.
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0.3 INPUT-CAPACITOR CURRENT (IRMS/IO)
and off. Select low ESL ceramic capacitors and place one as close as possible to each upper MOSFET drain to minimize board parasitic impedances and maximize suppression.
0.3 INPUT-CAPACITOR CURRENT (IRMS/IO) IL,PP = 0 IL,PP = 0.25 IO IL,PP = 0.5 IO IL,PP = 0.75 IO
0.2
0.2
0.1 IL,PP = 0 IL,PP = 0.5 IO IL,PP = 0.75 IO 0 0 0.2 0.4 0.6 0.8 1.0
0.1
DUTY CYCLE (VO/VIN)
FIGURE 18. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR 2-PHASE CONVERTER
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VO/VIN) 0.3 INPUT-CAPACITOR CURRENT (IRMS/IO) IL,PP = 0 IL,PP = 0.25 IO IL,PP = 0.5 IO IL,PP = 0.75 IO
FIGURE 20. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR 4-PHASE CONVERTER
MULTIPHASE RMS IMPROVEMENT
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VO/VIN)
FIGURE 19. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR 3-PHASE CONVERTER
Figure 21 is provided as a reference to demonstrate the dramatic reductions in input-capacitor RMS current upon the implementation of the multiphase topology. For example, compare the input RMS current requirements of a two-phase converter versus that of a single phase. Assume both converters have a duty cycle of 0.25, maximum sustained output current of 40A, and a ratio of IL,PP to IO of 0.5. The single phase converter would require 17.3Arms current capacity while the two-phase converter would only require 10.9Arms. The advantages become even more pronounced when output current is increased and additional phases are added to keep the component cost down relative to the single phase approach.
0.6 INPUT-CAPACITOR CURRENT (IRMS/IO)
For a two phase design, use Figure 18 to determine the input-capacitor RMS current requirement given the duty cycle, maximum sustained output current (IO), and the ratio of the per-phase peak-to-peak inductor current (IL,PP) to IO. Select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the RMS current calculated. The voltage rating of the capacitors should also be at least 1.25 times greater than the maximum input voltage. Figures 19 and 20 provide the same input RMS current information for three and four phase designs respectively. Use the same approach to selecting the bulk capacitor type and number as described above. Low capacitance, high-frequency ceramic capacitors are needed in addition to the bulk capacitors to suppress leading and falling edge voltage spikes. The result from the high current slew rates produced by the upper MOSFETs turn on 29
0.4
0.2 IL,PP = 0 IL,PP = 0.5 IO IL,PP = 0.75 IO 0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VO/VIN)
FIGURE 21. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR SINGLE-PHASE CONVERTER
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ISL6326 Layout Considerations
The following layout strategies are intended to minimize the impact of board parasitic impedances on converter performance and to optimize the heat-dissipating capabilities of the printed-circuit board. These sections highlight some important practices which should not be overlooked during the layout process.
Component Placement
Within the allotted implementation area, orient the switching components first. The switching components are the most critical because they carry large amounts of energy and tend to generate high levels of noise. Switching component placement should take into account power dissipation. Align the output inductors and MOSFETs such that space between the components is minimized while creating the PHASE plane. Place the Intersil MOSFET driver IC as close as possible to the MOSFETs they control to reduce the parasitic impedances due to trace length between critical driver input and output signals. If possible, duplicate the same placement of these components for each phase. Next, place the input and output capacitors. Position one high-frequency ceramic input capacitor next to each upper MOSFET drain. Place the bulk input capacitors as close to the upper MOSFET drains as dictated by the component size and dimensions. Long distances between input capacitors and MOSFET drains result in too much trace inductance and a reduction in capacitor performance. Locate the output capacitors between the inductors and the load, while keeping them in close proximity to the microprocessor socket.
30
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ISL6326 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
2X A 9 D1 D1/2 6 INDEX AREA N 1 2 3 E1/2 E1 9 2X 0.15 C B 2X 0.15 C A 0 4X C 0.08 C SEATING PLANE SIDE VIEW NX b 4X P D2 (DATUM B) 4X P 1 (DATUM A) 6 INDEX AREA NX L Ne 8 (Nd-1)Xe REF. BOTTOM VIEW NX b 5 2 3 E2 7 E2/2 8 (Ne-1)Xe REF. D2 2N 5 0.10 M C A B 7 8 NX k A3 A1 9 TOP VIEW A2 A / / 0.10 C B E/2 E 2X 0.15 C B D D/2 0.15 C A
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VJJD-2 ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.30 3.95 3.95 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.23 6.00 BSC 5.75 BSC 4.10 6.00 BSC 5.75 BSC 4.10 0.50 BSC 0.40 40 10 10 0.60 12 0.50 0.15 4.25 4.25 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.
9 CORNER OPTION 4X A1
C L
SECTION "C-C" C L
8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
10 L
L1 e CC
10
L L1 e
9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 31
FN9262.0 April 21, 2006

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