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HT48RU80/HT48CU80 I/O Type 8-Bit MCU
Technical Document
* Tools Information * FAQs * Application Note -
HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM HA0004E HT48 & HT46 MCU UART Software Implementation Method HA0013E HT48 & HT46 LCM Interface Design HA0021E Using the I/O Ports on the HT48 MCU Series
Features
* Operating voltage: * 5768 data memory RAM * Universal Asynchronous Receiver/Transmitter
fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V
* Low voltage reset function * 56 bidirectional I/O lines (max.) * Two interrupt input * 16-bit2 programmable timer/event counter and
(UART)
* HALT function and wake-up feature reduce power
consumption
* 16-level subroutine nesting * Up to 0.5ms instruction cycle with 8MHz system clock
overflow interrupts with PFD outputs
* 8-bit1 programmable timer/event counter * On-chip RC oscillator, external crystal and RC oscil-
at VDD=5V
* Bit manipulation instruction * 16-bit table read instruction * 63 powerful instructions * All instructions in one or two machine cycles * 48-pin SSOP, 64-pin QFP package
lator
* 32768Hz crystal oscillator for timing purposes only * Watchdog Timer * 16K16 program memory ROM
General Description
The HT48RU80/HT48CU80 are 8-bit high performance, RISC architecture microcontroller devices specifically designed for multiple I/O control product applications. The mask version HT48CU80 is fully pin and functionally compatible with the OTP version HT48RU80 device. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, HALT and wake-up functions, watchdog timer, buzzer driver, as well as low cost, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer products, subsystem controllers, etc. The HT48CU80 is under development and will be available soon.
Rev. 1.00
1
April 12, 2006
HT48RU80/HT48CU80
Block Diagram
M U X RTC fS
YS
IN T 0
TM R2C TM R2
M U
P r e s c a le r X M TM R2 U X TM R1 M U X TM R0 E N /D IS WDT M U X RTC fS
YS
OSC
In te rru p t C ir c u it S ta c k 1 6 L e v e ls
RTC OSC fS
YS
TM R1C TM R1
M U
/4
X
P ro g ra m ROM
P ro g ra m C o u n te r
IN T C TM R0C TM R0 M U X
OSC /4
In s tr u c tio n R e g is te r
BP
MP
M U
X
D a ta M e m o ry
W DTS W DT P r e s c a le r PA
RTC OSC fS Y S /4 W DTOSC
In s tr u c tio n D ecoder ALU T im in g G e n e ra to r
MUX
PAC STATUS PB PBC PC PCC O p tio n R O M O T P O n ly
PA0~PA7 E X T (B Z , B Z ) P B 0 /B Z , P B 1 /B Z P B 2 /IN T 1 , P B 3 /T M R 2 PB4~PB7 P C 0 /T X , P C 1 /R X PC 2~PC 7
S h ifte r
OSC2
OS R V V
C1 ES DD SS
ACC In te rn a l RC OSC TX RX
PD PDC PE PEC PF PFC PG PGC
PD 0~PD 7
UART
PE0~PE7
PF0~PF7
PG 0~PG 7
Rev. 1.00
2
April 12, 2006
HT48RU80/HT48CU80
Pin Assignment
PB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PB4 PA3 PA2 PA1 PA0 P B 3 /T M R 2 P B 2 /IN T 1 P B 1 /B Z P B 0 /B Z PE3 PE2 PE1 PE0 PD7 PD6 PD5 PD4 VSS IN T 0 TM R0 P C 0 /T X P C 1 /R X PC2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PB6 PB7 PA4 PA5 PA6 PA7 PF0 PF1 PF2 PF3 OSC2 OSC1 VDD RES TM R1 PD3 PD2 PD1 PD0 PC7 PC6 PC5 PC4 PC3 PA1 PA0 PE7 PE6 PE5 PE4 P B 3 /T M R 2 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 IN T 0 TM R0 PG0 PG1 PG2 25 26 27 28 29 30 31 32 PG3 P C 0 /T X P C 1 /R X PC2 PC3 PC4 PC5 P B 2 /IN T 1 P B 1 /B Z P B 0 /B Z PE3 PE2 PE1 PE0 PD7 PD6 PD5 PD4 VSS 6 5 4 3 2 1 PG4 PG5 PG6 PG7 PA2 PA3 PB4 PB5 PB6 PB7 PA4 PA5 PA6
64 63 62 61 60
59 58 57 56 55 54 53 52
51 50 49 48 47 46 45 44
PA7 PF0 PF1 PF2 PF3 OSC2 OSC1 PF4 PF5 PF6 PF7 VDD RES TM R1 PD3 PD2 PD1 PD0 PC7
H T 4 8 R U 8 0 /H T 4 8 C U 8 0 6 4 Q F P -A
43 42 41 40 39 38 37 36 35 34 33
PC6
H T 4 8 R U 8 0 /H T 4 8 C U 8 0 4 8 S S O P -A
Rev. 1.00
3
April 12, 2006
HT48RU80/HT48CU80
Pin Description
Pin Name I/O Options Pull-high Wake-up Schmitt Trigger Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by configuration option. Software instructions determine if the pin is a CMOS output or input. Configuration options determine if all pins on this port have pull-high resistors and if the inputs are Schmitt trigger or non Schmitt trigger.
PA0~PA7
I/O
PB0/BZ PB1/BZ PB2/INT1 PB3/TMR2 PB4~PB7 PC0/TX PC1/RX PC2~PC7 PD0~PD7 PE0~PE7 PF0~PF7 PG0~PG7 INT0 TMR0 TMR1
I/O
Pull-high I/O or BZ/BZ
Bidirectional 8-bit input/output ports. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A configuration option for each port determines if all pins on the relevant port have pull-high resistors. Pins PB0, PB1, PB2 and PB3 are pin-shared with BZ, BZ, INT1 and TMR2, respectively. Pins PC0 and PC1 are pin-shared with the UART pins TX and RX.
I I I
3/4 3/4 3/4
External interrupt Schmitt trigger input. Edge triggered on high to low transition. Schmitt trigger input for Timer/Event Counter 0 Schmitt trigger input for Timer/Event Counter 1 OSC1, OSC2 are connected to an external RC network or external Crystal (determined by configuration option) for the internal system clock. For external RC system clock operation, OSC2 is an output pin for 1/4 system clock. These two pins also can be optioned as an RTC oscillator (32768Hz). In this case, the system clock comes from an internal RC oscillator whose nominal frequency at 5V has 4 options, 3.2MHz, 1.6MHz, 800kHz, 400kHz. Schmitt trigger reset input. Active low. Positive power supply Negative power supply, ground.
OSC1 OSC2
I O
Crystal or RC or Int. RC+RTC
RES VDD VSS
I 3/4 3/4
3/4 3/4 3/4
Note: Each pin on PAcan be programmed through a configuration option to have a wake-up function. Individual pins cannot be selected to have pull-high resistors. If the pull-high configuration is chosen for a particular port, then all input pins on this port will be connected to pull-high resistors. Pins PE4~PE7 and pins PF4~PF7 only exist on the 64-pin package. Port G only exists on the 64-pin package.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
4
April 12, 2006
HT48RU80/HT48CU80
D.C. Characteristics
Symbol Parameter Test Conditions VDD Conditions Min. 2.2 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 2.7 4 10 -2 -5 20 10 Typ. 3/4 3/4 0.6 2 0.8 2.5 4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3.0 8 20 -4 -10 60 30 Max. 5.5 5.5 1.5 4 1.5 4 8 5 10 1 2 5 10 0.3VDD VDD 0.4VDD VDD 3.3 3/4 3/4 3/4 3/4 100 50 Ta=25C Unit V V mA mA mA mA mA mA mA mA mA mA mA V V V V V mA mA mA mA kW kW
VDD
Operating Voltage
3/4 fSYS=4MHz 3/4 fSYS=8MHz 3V No load, fSYS=4MHz
IDD1
Operating Current (Crystal OSC) 5V 3V Operating Current (RC OSC) 5V Operating Current (Crystal OSC, RC OSC) Standby Current (WDTOSC On, RTC Off) 5V 3V Standby Current (WDTOSC Off, RTC Off) 5V 3V Standby Current (WDTOSC Off, RTC On) 5V Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset I/O Port Sink Current 3/4 3/4 3/4 3/4
IDD2
No load, fSYS=4MHz
IDD3
5V No load, fSYS=8MHz 3V No load, system HALT
ISTB1
ISTB2
No load, system HALT
ISTB3 VIL1 VIH1 VIL2 VIH2 VLVR IOL
No load, system HALT 3/4 3/4 3/4 3/4
3/4 LVR enabled 3V VOL=0.1VDD 5V VOL=0.1VDD
IOH
I/O Port Source Current
3V VOH=0.9VDD 5V VOH=0.9VDD 3V
RPH
Pull-high Resistance 5V
3/4
Rev. 1.00
5
April 12, 2006
HT48RU80/HT48CU80
A.C. Characteristics
Symbol Parameter Test Conditions VDD 3/4 3/4 3/4 3/4 Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V 3.2MHz fSYS3 1.6MHz System Clock (Internal RC OSC) 5V 800kHz 400kHz fTIMER Timer I/P Frequency (TMR) 3/4 3/4 3V 5V tWDT1 tWDT2 tWDT3 tRES tSST tINT 3V Watchdog Time-out Period (WDT OSC) 5V Watchdog Time-out Period (System Clock) Watchdog Time-out Period (RTC OSC) External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width 3/4 3/4 3/4 3/4 3/4 Without WDT prescaler Without WDT prescaler 3/4 Wake-up from HALT 3/4 Without WDT prescaler 8 3/4 3/4 1 3/4 1 17 1024 7.812 3/4 1024 3/4 33 3/4 3/4 3/4 3/4 3/4 ms tSYS ms ms tSYS ms 2.2V~5.5V 3.3V~5.5V 3/4 3/4 450 225 0 0 45 32 11 Min. 400 400 400 400 1800 900 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 90 65 23 Ta=25C Max. 4000 8000 4000 8000 5400 2700 1350 675 4000 8000 180 130 46 Unit kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz ms ms ms
fSYS1
System Clock (Crystal OSC)
fSYS2
System Clock (RC OSC)
tWDTOSC Watchdog Oscillator Period
Rev. 1.00
6
April 12, 2006
HT48RU80/HT48CU80
Functional Description
Execution Flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to be effectively executed in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code.
S y s te m C lo c k T1 T2 T3 T4 T1 T2
When executing a jump instruction, conditional skip execution, loading register, subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupts, the PC manages the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within the current program ROM page. When a control transfer takes place, an additional dummy cycle is required. Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into
T3 T4 T1 T2 T3 T4
O S C 2 ( R C o n ly ) PC PC PC+1 PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Mode Initial Reset External Interrupt 0 Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Timer/Event Counter 2 Overflow External Interrupt 1 UART Interrupt Skip Loading PCL Jump, Call Branch Return (RET, RETI) *13 *12 *11 *10 *9 #9 S9 BP.5 #12 #11 #10 S13 S12 S11 S10 Program Counter *13 0 0 0 0 0 0 0 *12 0 0 0 0 0 0 0 *11 0 0 0 0 0 0 0 *10 0 0 0 0 0 0 0 *9 0 0 0 0 0 0 0 *8 0 0 0 0 0 0 0 *8 #8 S8 *7 0 0 0 0 0 0 0 @7 #7 S7 *6 0 0 0 0 0 0 0 @6 #6 S6 *5 0 0 0 0 0 0 0 @5 #5 S5 *4 0 0 0 0 1 1 1 @4 #4 S4 *3 0 0 1 1 1 0 0 @3 #3 S3 *2 0 1 0 1 0 0 1 @2 #2 S2 *1 0 0 0 0 0 0 0 @1 #1 S1 *0 0 0 0 0 0 0 0 @0 #0 S0
Program Counter+2
Program Counter Note: *13~*0: Program counter bits #13~#0: Instruction code bits Rev. 1.00 7 S13~S0: Stack register bits @7~@0: PCL bits April 12, 2006
HT48RU80/HT48CU80
819216 bits2 banks, addressed by the Program Counter and table pointer. The BP register bit5 is used to select the ROM bank. When the BPs bit5=0, the ROM bank 0 ranges from 0000H to 1FFFH. When the BPs bit5=1, the ROM bank1 ranges from 2000H to 3FFFH. The CALL and JMP instruction provide only 13 bits of address to allow branching within any 8K program memory bank. When doing a CALL or JMP instruction, the upper 1 bit of the address is provided by BP5. When doing a CALL or JMP instruction, user must ensure that the bank select bit is programmed so that the desired program memory bank is addressed. If a return from CALL instruction (or interrupt) is executed, the entire 14-bit Program Counter is popped off the stack. Certain locations in the program memory are reserved for special usage:
000H 004H 008H 00CH 010H 014H 018H n00H D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t 0 S u b r o u tin e T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e E x te r n a l In te r r u p t 1 S u b r o u tin e U A R T In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 2 In te r r u p t S u b r o u tin e P ro g ra m M e m o ry
* Location 000H
This area is reserved for program initialization. After a chip reset, the program always begins execution at location 000H.
* Location 004H
This area is reserved for the external interrupt 0 service program. If the INT0 interrupt pin is activated, the interrupt enabled and the stack is not full, the program begins execution at location 004H.
* Location 008H
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
* Location 00CH
This location is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Location 010H
This area is reserved for the external interrupt 1 service program. If the INT1 interrupt pin is activated, the interrupt enabled and the stack is not full, the program begins execution at location 010H.
* Location 014H
This area is reserved for the UART interrupt service program. If a UART interrupt results from a UART TX or RX, and the interrupt is enabled and the stack is not full, the program begins execution at location 014H.
* Location 018H
nFFH
L o o k - u p T a b le ( 2 5 6 w o r d s )
1F00H 1FFFH 2000H
L o o k - u p T a b le ( 2 5 6 w o r d s )
This location is reserved for the Timer/Event Counter 2 interrupt service program. If a timer interrupt results from a Timer/Event Counter 2 overflow, and the interrupt is enabled and the stack is not full, the program begins execution at location 018H.
* Table location
3FFFH 1 6 b its N o te : n ra n g e s fro m 0 to 3 F
Program Memory Instruction TABRDC [m] TABRDL [m]
Any location in the program memory can be used as look-up tables. The instructions TABRDC [m] (the current page, one page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). The Table Table Location
*13 P13 1
*12 P12 1
*11 P11 1
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table Location Note: *13~*0: Table location bits @7~@0: Table pointer bits Rev. 1.00 8 April 12, 2006 P13~P8: Current program counter bits
HT48RU80/HT48CU80
Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in the TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 16 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 16 return addresses are stored). Data Memory - RAM The data memory (RAM) is designed with 6178 bits, and is divided into two functional groups, namely, special function registers and general purpose data memory (1928bits3banks), most of which are readable/ writeable, although some are read only. [BP REG] Bit1~Bit0 00 01 10 RAM Bank 0 1 2 The special function registers consist of an Indirect addressing register 0 (IAR0;00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (IAR1;02H), a Memory pointer register 1 (MP1;03H), a Bank pointer (BP;04H), an Accumulator (ACC;05H), a Program counter lower-order byte register (PCL;06H), a lower-order byte table pointer (TBLP;07H), a Table higher-order byte register (TBLH;08H), a Watchdog Timer option setting register (WDTS;09H), a Status register (STATUS;0AH), an Interrupt control register 0 (INTC0;0BH), a Timer/Event Counter 0 higher order byte register (TMR0H;0CH), a Timer/Event Counter 0 lower order byte register (TMR0L;0DH), a Timer/Event Counter 0 control register (TMR0C;0EH), a Timer/Event Counter 1 higher order byte register (TMR1H;0FH), a Timer/Event Counter 1 lower order byte register (TMR1L;10H), a Timer/Event Counter 1 control register (TMR1C;11H), I/O registers (PA;12H, PB;14H, PC;16H, PD;18H, PE;1AH, PF;1CH, PG;25H) and I/O control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H, PEC;1BH, PFC;1DH, PGC;26H), a Timer/Event Counter 2 (TMR2;21H), a Timer/Event Counter 2 control register (TMR2C;22H), a higher-order byte table pointer ( T B H P ; 1 F H ) , a n I n t e r r u p t co n t r o l r e g i st e r 1 (INTC1;1EH), a UART Status register (USR;28H), a UART Control register 1 (UCR1;29H), a UART Control register 2 (UCR2;2AH), a UART TX/RX Buffer register (TXR/RXR;2BH), and a UART Baud Rate generator prescaler register (BRG;2CH). On the other hand, the general purpose data memory, addressed from 40H to FFH (bank0~2), is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer registers (MP0 or MP1). Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] ([02H]) will access data memory pointed to by MP0 (MP1). Reading location 00H (02H) itself indirectly will return the result 00H. Writing indirectly results in no operation. The memory pointer registers (MP0 and MP1) are 8-bit registers. Accumulator - ACC The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator.
Rev. 1.00
9
April 12, 2006
HT48RU80/HT48CU80
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH In d ir e c t A d d r M In d ir e c t A d d r M e s s in g R e g is te r 0 P0 e s s in g R e g is te r 1 P1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C 0 TM R 0H TM R 0L TM R 0C TM R 1H TM R 1L TM R 1C PA PAC PB PBC PC PCC PD PDC PE PEC PF PFC IN T C 1 TBHP TM R2 TM R 2C : U n u s e d , R e a d a s "0 0 "
PG PGC USR UCR1 UCR2 T X R /R X R BRG S p e c ia l F u n c tio n R e g is te r s 40H
Bank 2 Bank 1 Bank 0 (1 9 2 x 3 b y te s )
FFH G e n e ra l P u rp o s e D a ta M e m o ry
RAM Mapping Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ)
Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may
The ALU not only saves the results of a data operation but also changes the status register.
Rev. 1.00
10
April 12, 2006
HT48RU80/HT48CU80
Bit No. 0 Label C Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction, otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0. Status (0AH) Register give different results from those intended. The TO flag can be affected only by a system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The device provides two external interrupts, three internal timer/event counter interrupts, and a UART TX/ RX interrupt. The Interrupt Control Register 0 (INTC0; 0BH) and Interrupt Control Register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 or INTC1 may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the proRev. 1.00 11 gram memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a high to low transition of the INT0 or INT1 and the related interrupt request flag (EIF0; bit 4 of the INTC0; EIF1; bit 4 of the INTC1) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H or 10H will occur. The interrupt request flag (EIF0 or EIF1) and EMI bits will be cleared to disable other interrupts. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 5 of the INTC0), caused by a timer 0 overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The internal Timer/Event Counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (T1F; bit 6 of the INTC0), caused by a T 1 overflow. When the interrupt is enabled, the stack is not full and the T1F is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts. The UART interrupt is initialized by setting the interrupt request flag (URF; bit 5 of the INTC1), that is caused by a regular UART receive signal, caused by a UART transmit signal. After the interrupt is enabled, the stack is not full, and the URF bit is set, a subroutine call to location 14H occurs. The related interrupt request flag (URF) is reset and the EMI bit is cleared to disable further other interrupts.
1 2 3 4 5 6~7
AC Z OV PDF TO 3/4
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HT48RU80/HT48CU80
Bit No. 0 1 2 3 4 5 6 7 Label EMI EEI0 ET0I ET1I EIF0 T0F T1F 3/4 Function Controls the master (global) interrupt (1= enable; 0= disable) Controls the external interrupt 0 (1= enable; 0= disable) Controls the Timer/Event Counter 0 interrupt (1= enable; 0= disable) Controls the Timer/Event Counter 1 interrupt (1= enable; 0= disable) External interrupt 0 request flag (1= active; 0= inactive) Internal Timer/Event Counter 0 request flag (1= active; 0= inactive) Internal Timer/Event Counter 1 request flag (1= active; 0= inactive) Unused bit, read as 0 INTC0 (0BH) Register Bit No. 0 1 2 3, 7 4 5 6 Label EEI1 EURI ET2I 3/4 EIF1 URF T2F Function Controls the external interrupt 1 (1= enable; 0= disable) Controls the UART TX or RX interrupt (1= enable; 0= disable) Controls the Timer/Event Counter 2 overflow interrupt (1= enable; 0= disable) Unused bit, read as 0 External interrupt 1 request flag (1= active; 0= inactive) UART TX or RX interrupt request flag (1= active; 0= inactive) Timer/Event Counter 2 overflow request flag (1= active; 0= inactive) INTC1 (1EH) Register The internal Timer/Event Counter 2 interrupt is initialized by setting the Timer/Event Counter 2 interrupt request flag (T2F; bit 6 of the INTC1), caused by a T 2 overflow. When the interrupt is enabled, the stack is not full and the T2F is set, a subroutine call to location 18H will occur. The related interrupt request flag (T2F) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. No. a b c d e f Interrupt Source External Interrupt 0 Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow External Interrupt 1 UART Interrupt Timer/Event Counter 2 Overflow Interrupt Priority Vector 1 2 3 4 5 6 04H 08H 0CH 010H 014H 018H
The Timer/Event Counter 0/1 interrupt request flag (T0F/T1F), external interrupt 0 request flag (EIF0), enable Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), enable external interrupt 0 bit (EEI0) and enable master interrupt bit (EMI) constitute an interrupt control register (INTC0) which is located at 0BH in the data memory. EMI, EEI0, ET0I and ET1I are used to control the enabling or disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (T0F, T1F, EIF0) are set, they will remain in the INTC0 register until the interrupts are serviced or cleared by a software instruction.
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HT48RU80/HT48CU80
The External Interrupt 1 request flag (EIF1), UART interrupt request flag (URF), Timer/Event Counter 2 interrupt request flag (T2F), External Interrupt 1 bit (EEI1), and enable UART interrupt bit (EURI), enable Timer/Event Counter 2 interrupt bit (ET2I), constitute the Interrupt Control register 1 (INTC1) which is located at 1EH in the data memory. EEI1, EURI and ET2I are used to control the enabling or disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (EIF1, URF, T2F) are set, they will remain in the INTC1 register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. Oscillator Configuration There are three oscillator circuits in the microcontroller.
V
DD
cost effective solution. However, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. In stead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. If the internal RC oscillator is used, the OSC1 and OSC2 can be selected as 32768Hz crystal oscillator (RTC OSC). Also, the frequencies of the internal RC oscillator can be 3.2MHz, 1.6MHz, 800kHz and 400kHz, depending on the options. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works within a period of approximately 65ms at 5V. The WDT oscillator can be disabled by options to conserve power. Watchdog Timer - WDT
OSC1
470pF fS Y S /4 N M O S O p e n D r a in
OSC1
OSC2 C r y s ta l O s c illa to r ( In c lu d e 3 2 7 6 8 H z )
OSC2 RC O s c illa to r
System Oscillator All of them are designed for system clocks, namely, the external RC oscillator, the external Crystal oscillator and the internal RC oscillator, which are determined by options. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power. If an RC oscillator is used, an external resistor between OSC1 and VDD is required and the resistance must range from 24kW to 1MW. The system clock, divided by 4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the most
fS
YS
The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator), RTC clock or instruction clock (system clock divided by 4), determines the options. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by options. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. The RTC clock is enabled only in the internal RC+RTC mode. Once the internal WDT oscillator (RC oscillator with a period of 65ms at 5V normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of 17ms at 5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the WDTS) can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.1 seconds at 5V. If the WDT oscillator is disabled, the WDT
W D T P r e s c a le r
/4 ROM Code O p tio n 8 - b it C o u n te r 7 - b it C o u n te r
fR
TC
W DTOSC
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
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clock may still come from the instruction clock and operates in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. The high nibbles and bit 3 of the WDTS are reserved for users defined flags, which can be used to indicate some specified status. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) or 32kHz crystal oscillator (RTC OSC) is strongly recommended, since the HALT will stop the system clock. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 WDTS Register The WDT overflow under normal operation will initialize a chip reset and set the status bit TO. But in the HALT mode, the overflow will initialize a warm reset and only the Program Counter and SP are reset to zero. To clear the WDT contents (including the WDT prescaler), three methods are adopted; external reset (a low level to RES), software instruction and a HALT instruction. The software instruction include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the option - CLR WDT times selection option. If the CLR WDT is selected (i.e. CLRWDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT, otherwise, the WDT may reset the chip as a result of time-out. Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following:
* The system oscillator will be turned off but the WDT * All of the I/O ports maintain their original status. * The PDF flag is set and the TO flag is cleared.
Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the cause for a chip reset can be determined. The PDF flag is cleared by a system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the Program Counter and SP; the others remain in their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in Port A can be independently selected to wake-up the device by options. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. The RTC oscillator still runs in the HALT mode (if the RTC oscillator is enabled). Reset There are three ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
oscillator remains running (if the WDT oscillator is selected). * The contents of the on chip RAM and registers remain unchanged.
* The WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT oscillator).
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the Program Counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets.
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TO PDF 0 u 0 1 1 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
10kW 0 .1 m F * 100kW RES
V
DD
0 .0 1 m F *
Note: u stands for unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the system resets (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay. An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset). The functional unit chip reset status are shown below. Program Counter Interrupt Prescaler WDT Timer/Event Counter Input/Output Ports Stack Pointer 000H Disable Clear Clear. After master reset, WDT begins counting Off Input mode Points to the top of the stack
OSC1
RES
Reset Circuit Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference.
VDD RES S S T T im e - o u t C h ip R eset tS
ST
Reset Timing Chart
HALT W DT
W a rm
R eset
SST 1 0 - b it R ip p le C o u n te r S y s te m R eset
C o ld R eset
Reset Configuration
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HT48RU80/HT48CU80
The states of the registers are summarized in the following table. Register TMR0H TMR0L TMR0C TMR1H TMR1L TMR1C TMR2 TMR2C Program Counter MP0 MP1 BP ACC TBLP TBLH TBHP STATUS INTC0 INTC1 WDTS PA PAC PB PBC PC PCC PD PDC PE PEC PF PFC PG PGC USR UCR1 UCR2 TXR/RXR BRG Reset (Power On) xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx 00-0 1000 000H xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --00 xxxx -000 0000 -000 -000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 1011 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx WDT Time-out RES Reset (Normal Operation) (Normal Operation) xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx 00-0 1000 000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --1u uuuu -000 0000 -000 -000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 1011 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx 00-0 1000 000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu -000 0000 -000 -000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 1011 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx RES Reset (HALT) xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx 00-0 1000 000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --01 uuuu -000 0000 -000 -000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 1011 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx WDT Time-out (HALT)* uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uu-u uuuu 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu -uuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Note: * stands for warm reset u stands for unchanged x stands for unknown
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Timer/Event Counter Three timer/event counters (TMR0, TMR1, TMR2) are implemented in this microcontroller. The Timer/Event Counter 0 contains a 16-bit programmable count-up counter and the clock may come from an external source or from the system clock divided by 4 or RTC. The Timer/Event Counter 1 contains a 16-bit programmable count-up counter and the clock may come from an external source or from the system clock divided by 4 or RTC. The Timer/Event Counter 2 contains an 8-bit programmable count-up counter and the clock may come from an external source or from the system clock or RTC. Using the internal clock sources, there are two reference time-bases for the Timer/Event Counter 0. The internal clock source can be selected as coming from fSYS/4 (can always be optioned) or RTC (enabled only by a system oscillator in the Int. RC+RTC mode) by options. Using the internal clock sources, there are two reference time-bases for the Timer/Event Counter 1. The internal clock source can be selected as coming from fSYS/4 (can always be optioned) or RTC (enabled only by a system oscillator in the Int. RC+RTC mode) by options. Using external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. While using the internal clock allows the user to generate an accurate time base. There are three registers related to the Timer/Event Counter 0, namely, TMR0H ([0CH]), TMR0L ([0DH]), and TMR0C ([0EH]). Writing to the TMR0L will only put the written data to an internal lower-order byte buffer (8 bits) and writing to the TMR0H will transfer the specified data and the contents of the lower-order byte buffer to TMR0H and TMR0L preload registers, respectively. The Timer/Event Counter 0 preload register is changed by each writing operations to theTMR0H. Reading from the TMR0H will latch the contents of the TMR0H and TMR0L counters to the destination and the lower-order byte buffer, respectively. Reading the TMR0L will read the contents of the lower-order byte buffer. The TMR0C is the Timer/Event Counter 0 control register, which defines the operating mode, counting enable or disable and active edge. There are three registers related to the Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing to the TMR1L will only put the written data to an internal lower-order byte buffer (8 bits) and writing to the TMR1H will transfer the specified data and the contents of the lower-order byte buffer to TMR1H and TMR1L preload registers, respectively. The Timer/Event Counter 1 preload register is changed by each writing operaRev. 1.00 17 tions to the TMR1H. Reading from the TMR1H will latch the contents of TMR1H and TMR1L counters to the destination and the lower-order byte buffer, respectively. Reading the TMR1L will read the contents of the lower-order byte buffer. The TMR1C is the Timer/Event Counter 1 control register, which defines the operating mode, counting enable or disable and active edge. There are two registers related to timer/event counter, namely, TMR2 (21H) and TMR2C (22H). In the timer/event counter counting mode (T2ON=1), writing TMR2 will only put the written data to the preload register (8 bits). The timer/event counter preload register is changed by each writing operations to the TMR2. Reading from the TMR2 will also latch the TMR2 to the destination. The TMR2C is the timer/event counter control register, which defines the operating mode, counting enable or disable and active edge. The T0M0, T0M1 (TMR0C), T1M0, T1M1 (TMR1C), T2M0, T2M1 (TMR2C) bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external pin (TMR0/TMR1/TMR2). The timer mode functions as a normal timer with the clock source coming from the instruction clock or RTC clock (Timer0/Timer1/Timer2). The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0/TMR1/TMR2). The counting is based on the instruction clock or RTC clock (Timer0/Timer1/Timer2). In the event count or timer mode, once the Timer/Event Counter 0/1 starts counting, it will count from the current contents in the Timer/Event Counter 0/1 to FFFFH. Once overflow occurs, the counter is reloaded from the Timer/Event Counter 0/1 preload register and at the same time generates the interrupt request flag (T0F/T1F; bit 5/6 of the INTC0). In the event count or timer mode, once the Timer/Event Counter 2 starts counting, it will count from the current contents in the timer/event counter to FFH. Once overflow occurs, the counter is reloaded from the Timer/Event Counter 2 preload register and at the same time generates the corresponding interrupt request flag (T2F; bit 6 of the INTC1). In the pulse width measurement mode with the T0ON/ T1ON/T2ON and T0E/T1E/T2E bits equal to one, once the TMR0/TMR1/TMR2 has received a transient from low to high (or high to low if the T0E/T1E/T2E bits are 0) it will start counting until the TMR0/TMR1/ TMR2 returns to the original level and resets the T0ON/T1ON/ T2ON. The measured result will remain in the Timer/Event Counter 0/1/2 even if the activated transient occurs again. In other words, only one cycle measurement can be done. Until setting the T0ON/T1ON/ T2ON, the cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the Timer/Event Counter 0/1/2 starts counting not according to the logic level but ac-
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HT48RU80/HT48CU80
Bit No. 0~2, 5 3 4 Label 3/4 T0E T0ON Unused bit, read as 0 Defines the TMR0 active edge of the Timer/Event Counter 0 (0=active on low to high; 1=active on high to low) Enables or disables the Timer 0 counting (0=disable; 1=enable) Defines the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C (0EH) Register Function
6 7
T0M0 T0M1
Bit No. 0~2, 5 3 4
Label 3/4 T1E T1ON Unused bit, read as 0
Function
Defines the TMR1 active edge of the Timer/Event Counter 1 (0=active on low to high; 1=active on high to low) Enables or disables the Timer 1 counting (0=disable; 1=enable) Defines the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR1C (11H) Register
6 7
T1M0 T1M1
Bit No.
Label Defines the prescaler stages 000: fINT=fS/2 001: fINT=fS/4 010: fINT=fS/8 T2PSC0~ 011: fINT=fS/16 T2PSC2 100: fINT=fS/32 101: fINT=fS/64 110: fINT=fS/128 111: fINT=fS/256 T2E T2ON 3/4
Function
0~2
3 4 5
Defines the active edge of the TMR2 pin input signal (0=active on low to high; 1=active on high to low) Enables or disables the timer counting (0=disable; 1=enable) Unused bit, read as 0 Defines the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR2C (22H) Register
6 7
T2M0 T2M1
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cording to the transient edges. In the case of counter overflows, the Counter 0/1/2 is reloaded from the Timer/Event Counter 0/1/2 preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (T0ON: bit 4 of the TMR0C; T1ON: bit 4 of the TMR1C; T2ON: bit 4 of the TMR2C) should be set to 1. In the pulse width measurement mode, the T0ON/ T1ON/T2ON will be cleared automatically after the measurement cycle is completed. But in the other two modes the T0ON/T1ON/T2ON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1/ 2 is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I/ET1I/ET2I can disfS
Y S /4
able the corresponding interrupt services. In the case of Timer/Event Counter 0/1/2 OFF condition, writing data to the Timer/Event Counter 0/1/2 preload register will also reload that data to the Timer/Event Counter 0/1/2. But if the Timer/Event Counter 0/1/2 is turned on, data written to it will only be kept in the Timer/Event Counter 0/1/2 preload register. The Timer/Event Counter 0/1/2 will still operate until overflow occurs (a Timer/Event Counter 0/1/2 reloading will occur at the same time). When the Timer/Event Counter 0/1/2 (reading TMR0/TMR1/TMR2) is read, the clock will be blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into consideration by the programmer.
D a ta B u s
M U
fR
TC
X TM R0 T0E T0M 1 T0M 0 T0O N
T0M 1 T0M 0
O p tio n
1 6 B its T im e r /E v e n t C o u n te r P r e lo a d R e g is te r
L o w B y te B u ffe r R e lo a d
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
1 6 B its T im e r /E v e n t C o u n te r (T M R 0 ) 2
O v e r flo w to In te rru p t BZ BZ
Timer/Event Counter 0
fS
Y S /4
M U
D a ta B u s X TM R1 T1E T1M 1 T1M 0 T1O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l 1 6 B its T im e r /E v e n t C o u n te r (T M R 1 ) 2 T1M 1 T1M 0 1 6 B its T im e r /E v e n t C o u n te r P r e lo a d R e g is te r
fR
TC
O p tio n
L o w B y te B u ffe r R e lo a d
O v e r flo w to In te rru p t BZ BZ
Timer/Event Counter 1
fR fS
TC YS
M U
fS X
(1 /2 ~ 1 /2 5 6 ) 8 - s ta g e P r e s c a le r 8 -1 M U X T2PSC 2~T2PSC 0 TM R2 f IN
T
D a ta B u s T2M 1 T2M 0 8 B its T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d
T2E
T2M 1 T2M 0 T2O N
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
8 B its T im e r /E v e n t C o u n te r (T M R 2 )
O v e r flo w to In te rru p t
Timer/Event Counter 2
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HT48RU80/HT48CU80
Input/Output Ports There are 56 bidirectional input/output lines in the microcontroller, labeled from PA to PG, which are mapped to the data memory of [12H], [14H], [16H], [18H], [1AH], [1CH] and [25H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H, 18H, 1AH, 1CH or 25H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PDC, PEC, PFC, PGC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H, 19H, 1BH, 1DH and 26H. After a chip reset, these input/output lines remain at high levels or floating state (depending on the pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H, 16H, 18H, 1AH, 1CH or 25H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of Port A has the capability of waking-up the device. There is a pull-high option available for all I/O lines (port option). Once the pull-high option of an I/O line is selected, the I/O line has a pull-high resistor. Otherwise, the pull-high resistor is absent. It should be noted that a non-pull-high I/O line operating in input mode will cause a floating state.
V
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
DD
C o n tr o l B it P u ll- h ig h Q D
CK S Q
D a ta B it Q D
CK S Q
PA0 PB0 PC2 PD0 PE0 PF0 PG0
~PA ~PB ~PC ~PD ~PE ~PF ~PG 7
7 7 7 7 7
7
W r ite D a ta R e g is te r PB0 ( P B 0 , P B 1 O n ly ) B Z
M U M U X
X
B u z z e r O p tio n ( P B 0 , P B 1 O n ly )
R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly )
W a k e - u p O p tio n
E X T = B Z fo r P B 0 o n ly , E X T = B Z fo r P B 1 o n ly , c o n tr o l= P B 0 d a ta r e g is te r
PA, PB, PC2~PC7, PD, PE, PF, PG Input/Output Ports
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HT48RU80/HT48CU80
V C o n tr o l B it Q D CK S Q P u ll- h ig h
DD
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
P C 0 /T X D a ta B it Q D CK S Q M U X & TXEN
W r ite D a ta R e g is te r
F ro m
UART TX M
R e a d D a ta R e g is te r
U X
UARTEN
PC0/TX Input/Output Ports
V D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r C o n tr o l B it P u ll- h ig h Q D CK S Q
DD
P C 1 /R X D a ta B it Q D CK S Q M U X
W r ite D a ta R e g is te r
R e a d D a ta R e g is te r To UART RX
PC1/RX Input/Output Ports
Low Voltage Reset - LVR The microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
* The low voltage (0.9V~VLVR) has to remain in its origi-
The relationship between VDD and VLVR is shown below.
VDD 5 .5 V V
OPR
5 .5 V
V 3 .0 V 2 .2 V
LVR
nal state for longer than 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function.
* The LVR uses an OR function with the external RES
0 .9 V
signal to perform a chip reset.
Note: VOPR is the voltage range for proper chip operation at 4MHz system clock.
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HT48RU80/HT48CU80
V 5 .5 V
DD
V
LVR
L V R D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since the low voltage has to maintain its original state for longer than 1ms, therefore a 1ms delay enters the reset mode. UART Bus Serial Interface The HT48RU80/HT48CU80 devices contain an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates.
* UART features * UART external pin interfacing
The integrated UART function contains the following features:

Full-duplex, asynchronous communication 8 or 9 bits character length Even, odd or no parity options One or two stop bits Baud rate generator with 8-bit prescaler Parity, framing, noise and overrun error detection Support for interrupt on address detect (last character bit=1) Separately enabled transmitter and receiver 2-byte Deep Fifo Receive Data Buffer Transmit and receive interrupts Interrupts can be initialized by the following conditions:
-
To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX pin is the UART transmitter pin, which can be used as a general purpose I/O pin if the pin is not configured as a UART transmitter, which occurs when the TXEN bit in the UCR2 control register is equal to zero. Similarly, the RX pin is the UART receiver pin, which can also be used as a general purpose I/O pin, if the pin is not configured as a receiver, which occurs if the RXEN bit in the UCR2 register is equal to zero. Along with the UARTEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the RX pin.
* UART data transfer scheme
Transmitter Empty Transmitter Idle Receiver Full Receiver Overrun Address Mode Detect
The block diagram shows the overall data transfer structure arrangement for the UART. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buffered and can be manipulated by the application program. 22 April 12, 2006
Rev. 1.00
HT48RU80/HT48CU80
T r a n s m itte r S h ift R e g is te r MSB LSB CLK TXR R e g is te r B a u d R a te G e n e ra to r T X P in R X P in CLK RXR R e g is te r B u ffe r MSB R e c e iv e r S h ift R e g is te r LSB
MCU
D a ta B u s
UART Data Transfer Scheme
Only the RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory. This shared register known as the TXR/RXR register is used for both data transmission and data reception.
* UART status and control registers
ter with TIDLE set and then writing to the TXR register. The flag is not generated when a data character, or a break is queued and ready to be sent.
RXIF The RXIF flag is the receive register status flag. When this read only flag is 0 it indicates that the RXR read data register is empty. When the flag is 1 it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available.
There are five control registers associated with the UART function. The USR, UCR1 and UCR2 registers control the overall function of the UART, while the BRG register controls the Baud rate. The actual data to be transmitted and received on the serial interface is managed through the TXR/RXR data registers.
* USR register
RIDLE The RIDLE flag is the receiver status flag. When this read only flag is 0 it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is 1 it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is 1 indicating that the UART is idle.
The USR register is the status register for the UART, which can be read by the program to determine the present status of the UART. All flags within the USR register are read only. Further explanation on each of the flags is given below:
TXIF The TXIF flag is the transmit data register empty flag. When this read only flag is 0 it indicates that the character is not transferred to the transmit shift registers. When the flag is 1 it indicates that the transmit shift register has received a character from the TXR data register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and then writing to the TXR data register. Note that when the TXEN bit is set, the TXIF flag bit will also be set since the transmit buffer is not yet full.
OERR The OERR flag is the overrun error flag, which indicates when the receiver buffer has overflowed. When this read only flag is 0 there is no overrun error. When the flag is 1 an overrun error occurs which will inhibit further transfers to the RXR receive data register. The flag is cleared by a software sequence, which is a read to the status register USR followed by an access to the RXR data register.
FERR The FERR flag is the framing error flag. When this read only flag is 0 it indicates no framing error. When the flag is 1 it indicates that a framing error has been detected for the current character. The flag can also be cleared by a software sequence which will involve a read to the USR status register followed by an access to the RXR data register.
TIDLE The TIDLE flag is known as the transmission complete flag. When this read only flag is 0 it indicates that a transmission is in progress. This flag will be set to 1 when the TXIF flag is 1 and when there is no transmit data, or break character being transmitted. When TIDLE is 1 the TX pin becomes idle. The TIDLE flag is cleared by reading the USR regis-
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HT48RU80/HT48CU80
b7 PERR NF FERR OERR R ID L E R X IF T ID L E
b0
T X IF
USR
R e g is te r
T r a n s m it d a ta r e g is te r e m p ty 1 : c h a r a c te r tr a n s fe r r e d to tr a n s m it s h ift r e g is te r 0 : c h a r a c te r n o t tr a n s fe r r e d to tr a n s m it s h ift r e g is te r T r a n s m is s io n id le 1 : n o tr a n s m is s io n in p r o g r e s s 0 : tr a n s m is s io n in p r o g r e s s R e c e iv e R X R r e g is te r s ta tu s 1 : R X R r e g is te r h a s a v a ila b le d a ta 0 : R X R r e g is te r is e m p ty R e c e iv e r s ta tu s 1 : r e c e iv e r is id le 0 : d a ta b e in g r e c e iv e d O v e rru n e rro r 1 : o v e rru n e rro r d e te c te d 0 : n o o v e rru n e rro r d e te c te d F r a m in g e r r o r fla g 1 : fr a m in g e r r o r d e te c te d 0 : n o fr a m in g e r r o r N o is e fla g 1 : n o is e d e te c te d 0 : n o n o is e d e te c te d P a r ity e r r o r fla g 1 : p a r ity e r r o r d e te c te d 0 : n o p a r ity e r r o r d e te c te d
NF The NF flag is the noise flag. When this read only flag is 0 it indicates a no noise condition. When the flag is 1 it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of an overrun. The NF flag can be cleared by a software sequence which will involve a read to the USR status register, followed by an access to the RXR data register.
* UCR1 register
The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UART function, such as overall on/off control, parity control, data transfer bit length etc. Further explanation on each of the bits is given below:
TX8 This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data, known as TX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format.
PERR The PERR flag is the parity error flag. When this read only flag is 0 it indicates that a parity error has not been detected. When the flag is 1 it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the USR status register, followed by an access to the RXR data register.
b7 UARTEN BNO PREN PRT STOPS TXBRK RX8
b0
RX8 This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data, known as RX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format.
TX8
U C R 1 R e g is te r T r a n s m it d a ta b it 8 ( w r ite o n ly ) R e c e iv e d a ta b it 8 ( r e a d o n ly ) T r a n s m it b r e a k c h a r a c te r 1 : tr a n s m it b r e a k c h a r a c te r s 0 : n o b re a k c h a ra c te rs D e fin e s th e n u m b e r o f s to p b its 1 : tw o s to p b its 0 : o n e s to p b it P a r ity ty p e b it 1 : o d d p a r ity fo r p a r ity g e n e r a to r 0 : e v e n p a r ity fo r p a r ity g e n e r a to r P a r ity e n a b le b it 1 : p a r ity fu n c tio n e n a b le d 0 : p a r ity fu n c tio n d is a b le d N u m b e r o f d a ta tr a n s fe r b its 1 : 9 - b it d a ta tr a n s fe r 0 : 8 - b it d a ta tr a n s fe r U A R T e n a b le b it 1 : e n a b le U A R T , T X & R X p in s a s U A R T p in s 0 : d is a b le U A R T , T X & R X p in s a s I/O p o r t p in s
Rev. 1.00
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HT48RU80/HT48CU80
TXBRK The TXBRK bit is the Transmit Break Character bit. When this bit is 0 there are no break characters and the TX pin operates normally. When the bit is 1 there are transmit break characters and the transmitter will send logic zeros. When equal to 1 after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset.
STOPS This bit determines if one or two stop bits are to be used. When this bit is equal to 1 two stop bits are used, if the bit is equal to 0 then only one stop bit is used.
disabled it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the baud rate counter value will be reset. When the UART is disabled, all error and status flags will be reset. The TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR, and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2, and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled it will restart in the same configuration.
* UCR2 register
PRT This is the parity type selection bit. When this bit is equal to 1 odd parity will be selected, if the bit is equal to 0 then even parity will be selected.
PREN This is parity enable bit. When this bit is equal to 1 the parity function will be enabled, if the bit is equal to 0 then the parity function will be disabled.
The UCR2 register is the second of the two UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation of the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. Further explanation on each of the bits is given below:
BNO This bit is used to select the data length format, which can have a choice of either 8-bits or 9-bits. If this bit is equal to 1 then a 9-bit data length will be selected, if the bit is equal to 0 then an 8-bit data length will be selected. If 9-bit data length is selected then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively.
TEIE This bit enables or disables the transmitter empty interrupt. If this bit is equal to 1 when the transmitter empty TXIF flag is set, due to a transmitter empty condition, the UART interrupt request flag will be set. If this bit is equal to 0 the UART interrupt request flag will not be influenced by the condition of the TXIF flag.
TIIE This bit enables or disables the transmitter idle interrupt. If this bit is equal to 1 when the transmitter idle TIDLE flag is set, the UART interrupt request flag will be set. If this bit is equal to 0 the UART interrupt request flag will not be influenced by the condition of the TIDLE flag.
UARTEN The UARTEN bit is the UART enable bit. When the bit is 0 the UART will be disabled and the RX and TX pins will function as General Purpose I/O pins. When the bit is 1 the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN control bits. When the UART is
b7 TXEN RXEN BRGH ADDEN W AKE R IE T IIE
b0
T E IE
U C R 2 R e g is te r T r a n s m itte r e m p ty in te r r u p t e n a b le 1 : T X IF in te r r u p t r e q u e s t e n a b le 0 : T X IF in te r r u p t r e q u e s t d is a b le T r a n s m itte r id le in te r r u p t e n a b le 1 : T ID L E in te r r u p t r e q u e s t e n a b le 0 : T ID L E in te r r u p t r e q u e s t d is a b le R e c e iv e r in te r r u p t e n a b le 1 : R X IF in te r r u p t r e q u e s t e n a b le 0 : R X IF in te r r u p t r e q u e s t d is a b le D e fin e s th e R X w a k e u p e n a b le 1 : R X w a k e u p e n a b le ( fa llin g e d g e ) 0 : R X w a k e u p d is a b le A d d re s s d e te c t m o d e 1 : e n a b le 0 : d is a b le H ig h b a u d r a te s e le c t b it 1 : h ig h s p e e d 0 : lo w s p e e d R e c e iv e r e n a b le b it 1 : r e c e iv e r e n a b le 0 : r e c e iv e r d is a b le T r a n s m itte r e n a b le b it 1 : tr a n s m itte r e n a b le 0 : tr a n s m itte r d is a b le
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HT48RU80/HT48CU80
RIE This bit enables or disables the receiver interrupt. If this bit is equal to 1 when the receiver overrun OERR flag or receive data available RXIF flag is set, the UART interrupt request flag will be set. If this bit is equal to 0 the UART interrupt will not be influenced by the condition of the OERR or RXIF flags.
TX pin will be controlled by the UART. Clearing the TXEN bit during a transmission will cause the transmission to be aborted and will reset the transmitter. If this occurs, the TX pin can be used as a general purpose I/O pin.
* Baud rate generator
WAKE This bit enables or disables the receiver wake-up function. If this bit is equal to 1 and if the MCU is in the Power Down Mode, a low going edge on the RX input pin will wake-up the device. If this bit is equal to 0 and if the MCU is in the Power Down Mode, any edge transitions on the RX pin will not wake-up the device.
ADDEN The ADDEN bit is the address detect mode bit. When this bit is 1 the address detect mode is enabled. When this occurs, if the 8th bit, which corresponds to RX7 if BNO=0, or the 9th bit, which corresponds to RX8 if BNO=1, has a value of 1 then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8 or 9 bit depending on the value of BNO. If the address bit is 0 an interrupt will not be generated, and the received data will be discarded.
To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the BRG register and the second is the value of the BRGH bit within the UCR2 control register. The BRGH bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value in the BRG register determines the division factor, N, which is used in the following baud rate calculation formula. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit Baud Rate 0 fSYS [64 (N + 1)] 1 fSYS [16 (N + 1)]
BRGH The BRGH bit selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the BRG register, controls the Baud Rate of the UART. If this bit is equal to 1 the high speed mode is selected. If the bit is equal to 0 the low speed mode is selected.
By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. Calculating the register and error values For a clock frequency of 8MHz, and with BRGH set to 0 determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 9600. From the above table the desired baud rate BR fSYS = [64 (N + 1)] fSYS Re-arranging this equation gives N = -1 (BRx64) 8000000 - 1 = 12.0208 Giving a value for N = (9600x 64) To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives an actual or calculated baud rate value of 8000000 BR = = 9615 [64(12 + 1)] Therefore the error is equal to
RXEN The RXEN bit is the Receiver Enable Bit. When this bit is equal to 0 the receiver will be disabled with any pending data receptions being aborted. In addition the buffer will be reset. In this situation the RX pin can be used as a general purpose I/O pin. If the RXEN bit is equal to 1 the receiver will be enabled and if the UARTEN bit is equal to 1 the RX pin will be controlled by the UART. Clearing the RXEN bit during a transmission will cause the data reception to be aborted and will reset the receiver. If this occurs, the RX pin can be used as a general purpose I/O pin.
TXEN The TXEN bit is the Transmitter Enable Bit. When this bit is equal to 0 the transmitter will be disabled with any pending transmissions being aborted. In addition the buffer will be reset. In this situation the TX pin can be used as a general purpose I/O pin. If the TXEN bit is equal to 1 the transmitter will be enabled and if the UARTEN bit is equal to 1 the
9615 9600 = 0.16% 9600
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HT48RU80/HT48CU80
The following tables show actual values of baud rate and error values for the two values of BRGH. Baud Rate K/BPS 0.3 1.2 2.4 4.8 9.6 19.2 38.4 57.6 115.2 Baud Rates for BRGH=0 fSYS=8MHz BRG 3/4 103 51 25 12 6 2 1 0 Kbaud 3/4 1.202 2.404 4.807 9.615 17.857 41.667 62.5 125 Error 3/4 0.16 0.16 0.16 0.16 -6.99 8.51 8.51 8.51 fSYS=7.159MHz BRG 3/4 92 46 22 11 5 2 1 0 Kbaud 3/4 1.203 2.38 4.863 9.322 18.64 37.29 55.93 111.86 Error 3/4 0.23 -0.83 1.32 -2.9 -2.9 -2.9 -2.9 -2.9 BRG 207 51 25 12 6 2 1 0 3/4 fSYS=4MHz Kbaud 0.300 1.202 2.404 4.808 8.929 20.83 3/4 62.5 3/4 Error 0.00 0.16 0.16 0.16 -6.99 8.51 3/4 8.51 3/4 fSYS=3.579545MHz BRG 185 46 22 11 5 2 1 0 3/4 Kbaud 0.300 1.19 2.432 4.661 9.321 18.643 3/4 55.93 3/4 Error 0.00 -0.83 1.32 -2.9 -2.9 -2.9 3/4 -2.9 3/4
Baud Rates and Error Values for BRGH = 0 Baud Rates for BRGH=1 fSYS=8MHz BRG 3/4 3/4 207 103 51 25 12 8 3 1 Kbaud 3/4 3/4 2.404 4.808 9.615 19.231 38.462 55.556 125 250 Error 3/4 3/4 0.16 0.16 0.16 0.16 0.16 -3.55 8.51 0 fSYS=7.159MHz BRG 3/4 3/4 185 92 46 22 11 7 3 3/4 Kbaud 3/4 3/4 2.405 4.811 9.520 19.454 37.287 55.93 111.86 3/4 Error 3/4 3/4 0.23 0.23 -0.832 1.32 -2.9 -2.9 -2.9 3/4 BRG 3/4 207 103 51 25 12 6 3 1 0 fSYS=4MHz Kbaud 3/4 1.202 2.404 4.808 9.615 19.231 35.714 62.5 125 250 Error 3/4 0.16 0.16 0.16 0.16 0.16 -6.99 8.51 8.51 0 fSYS=3.579545MHz BRG 3/4 185 92 46 22 11 5 3 1 3/4 Kbaud 3/4 1.203 2.406 4.76 9.727 18.643 37.286 55.930 111.86 3/4 Error 3/4 0.23 0.23 -0.83 1.32 -2.9 -2.9 -2.9 -2.9 3/4
Baud Rate K/BPS 0.3 1.2 2.4 4.8 9.6 19.2 38.4 57.6 115.2 250
Baud Rates and Error Values for BRGH = 1
* Setting up and controlling the UART
Introduction For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits, and one or two stop bits. Parity is supported by the UART hardware, and can be setup to be even, odd or no parity. For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding BNO, PRT, PREN, and STOPS bits in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received
LSB first. Although the UARTs transmitter and receiver are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission.
Enabling/disabling the UART The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. As the UART transmit and receive pins, TX and RX respectively, are pin-shared with normal I/O pins, one of the basic functions of the UARTEN control bit is to control the UART function of these two pins. If the UARTEN, TXEN and RXEN bits are set, then these two I/O pins will be setup as a TX output pin and an RX input pin respectively, in effect disabling the normal I/O pin function. If no data is being transmitted on the TX pin then it will default to a logic high value.
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Clearing the UARTEN bit will disable the TX and RX pins and allow these two pins to be used as normal I/O pins. When the UART function is disabled the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the same configuration.
* UART transmitter
Data, parity and stop bit selection The format of the data to be transferred, is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9, the PRT bit controls the choice of odd or even parity, the PREN bit controls the parity on/off function and the STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length. Start Bit Data Bits Address Bits Parity Bits Stop Bit
Example of 8-bit Data Formats 1 1 1 8 7 7 0 0 1
1
Data word lengths of either 8 or 9 bits, can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the transmit data register, which is known as the TXR register. The data to be transmitted is loaded into this TXR register by the application program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR register, if it is available. It should be noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR register has been loaded with data and the baud rate generator has defined a shift clock source. However, the transmission can also be initiated by first loading data into the TXR register, after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empty, in which case a transfer to the TXR register will result in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The TX output pin will then return to having a normal general purpose I/O pin function.
0 1 0
1 1 1
Transmitting data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows:
-
Example of 9-bit Data Formats 1 1 1 9 8 8 0 0 1
1
0 1 0
1 1 1
Transmitter Receiver Data Format The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats.
-
Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. Setup the BRG register to select the desired baud rate.
P a r ity B it N ext S ta rt B it
S ta r t B it
B it 0
B it 1
B it 2
B it 3
B it 4
B it 5
B it 6
B it 7
S to p B it
8 -B it D a ta F o r m a t P a r ity B it S ta r t B it B it 0 B it 1 B it 2 B it 3 B it 4 B it 5 B it 6 B it 7 B it 8 S to p B it N ext S ta rt B it
9 -B it D a ta F o r m a t
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-
Set the TXEN bit to ensure that the TX pin is used as a UART transmitter pin and not as an I/O pin. Access the USR register and write the data that is to be transmitted into the TXR register. Note that this step will clear the TXIF bit. This sequence of events can now be repeated to send additional data.
-
It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the following software sequence: 1. A USR register access 2. A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: 1. A USR register access 2. A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence.
the Receive Serial Shift Register, commonly known as the RSR. The data which is received on the RX external input pin, is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations.
Receiving data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin, LSB first. In the read mode, the RXR register forms a buffer between the internal bus and the receiver shift register. The RXR register is a two byte deep FIFO data buffer, where two bytes can be held in the FIFO while a third byte can continue to be received. Note that the application program must ensure that the data is read from RXR before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows:
-
Make the correct selection of BNO, PRT, PREN and STOPS bits to define the word length, parity type and number of stop bits. Setup the BRG register to select the desired baud rate. Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin and not as an I/O pin.
-
Transmit break If the TXBRK bit is set then break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13 N 0 bits and stop bits, where N=1, 2, etc. If a break character is to be transmitted then the TXBRK bit must be first set by the application program, then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized.
At this point the receiver will be enabled which will begin to look for a start bit. When a character is received the following sequence of events will occur:
-
The RXIF bit in the USR register will be set when RXR register has data available, at least one more character can be read. When the contents of the shift register have been transferred to the RXR register, then if the RIE bit is set, an interrupt will be generated. If during reception, a frame error, noise error, parity error, or an overrun error has been detected, then the error flags can be set.
-
-
The RXIF bit can be cleared using the following software sequence: 1. A USR register access 2. An RXR register read execution
* UART receiver
Introduction The UART is capable of receiving word lengths of either 8 or 9 bits. If the BNO bit is set, the word length will be set to 9 bits with the MSB being stored in the RX8 bit of the UCR1 register. At the receiver core lies
Receive break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and
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STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following:
The OERR flag can be cleared by an access to the USR register followed by a read to the RXR register.
Noise Error - NF Flag Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is detected within a frame the following will occur:
-
The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. Data will be transferred from the Shift register to the RXR register. No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt.
Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation.
Framing Error - FERR Flag The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high, otherwise the FERR flag will be set. The FERR flag is buffered along with the received data and is cleared on any reset.
The framing error flag, FERR, will be set. The receive data register, RXR, will be cleared. The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set.
Idle status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition.
Parity Error - PERR Flag The read only parity error flag, PERR, in the USR register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity is enabled, PREN = 1, and if the parity type, odd or even is selected. The read only PERR flag is buffered along with the received data bytes. It is cleared on any reset. It should be noted that the FERR and PERR flags are buffered along with the corresponding word and should be read before reading the data word.
Receiver interrupt The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1.
* UART interrupt scheme
* Managing receiver errors
Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART.
Overrun Error - OERR flag The RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in the FIFO register, while a third byte can continue to be received. Before this third byte has been entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen:
-
The OERR flag in the USR register will be set. The RXR contents will not be lost. The shift register will be overwritten. An interrupt will be generated if the RIE bit is set. 30
The UART internal function possesses its own internal interrupt and independent interrupt vector. Several individual UART conditions can generate an internal UART interrupt. These conditions are, a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if the UART interrupt is enabled and the stack is not full, the program will jump to the UART interrupt vector where it can be serviced before returning to the main program. Four of these conditions, have a corresponding USR register flag, which will generate a UART interrupt if its associated interrupt enable flag in the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable bits, while the two receiver interrupt conditions have a shared enable bit. These enable bits can be used to mask out individual UART interrupt sources. The address detect condition, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register. An RX pin April 12, 2006
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U S R R e g is te r T r a n s m itte r E m p ty F la g T X IF U C R 2 R e g is te r T E IE 1 0 IN T C 1 R e g is te r 0 1 R IE 1 0 U A R T In te rru p t R e q u e s t F la g URF EURI IN T C 0 R e g is te r EMI
T r a n s m itte r Id le F la g T ID L E
T IIE
R e c e iv e r O v e r r u n F la g O E R R
OR
R e c e iv e r D a ta A v a ila b le R X IF
ADDEN
1
0 0 1
R X P in W a k e -u p
W AKE 1
0
R X 7 if B N O = 0 R X 8 if B N O = 1
U C R 2 R e g is te r
UART Interrupt Scheme wake-up, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the microcontroller is woken up by a low going edge on the RX pin, if the WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a delay of 1024 system clock cycles before the system resumes normal operation. Note that the USR register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. The flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART register section. The overall UART interrupt can be disabled or enabled by the EURI bit in the INTC1 interrupt control register to prevent a UART interrupt from occurring.
* Address detect mode
flag is set, irrespective of the data last bit status. The address detect mode and parity enable are mutually exclusive functions. Therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit to zero. ADDEN 0 1 0 1 1 ADDEN Bit Function
* UART operation in power down mode
Bit 9 if BNO=1, UART Interrupt Bit 8 if BNO=0 Generated 0 O O X O
Setting the Address Detect Mode bit, ADDEN, in the UCR2 register, enables this special mode. If this bit is enabled then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the EURI and EMI interrupt enable bits must also be enabled for correct interrupt generation. This highest address bit is the 9th bit if BNO=1 or the 8th bit if BNO=0. If this bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is not enabled, then a Receiver Data Available interrupt will be generated each time the RXIF Rev. 1.00 31
When the MCU is in the Power Down Mode the UART will cease to function. When the device enters the Power Down Mode, all clock sources to the module are shutdown. If the MCU enters the Power Down Mode while a transmission is still in progress, then the transmission will be terminated and the external TX transmit pin will be forced to a logic high level. In a similar way, if the MCU enters the Power Down Mode while receiving data, then the reception of data will likewise be terminated. When the MCU enters the Power Down Mode, note that the USR, UCR1, UCR2, transmit and receive registers, as well as the BRG register will not be affected. The UART function contains a receiver RX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the Power Down Mode,
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then a falling edge on the RX pin will wake-up the MCU from the Power Down Mode. Note that as it takes 1024 system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the RX pin will be ignored. For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, and the UART interrupt enable bit, EURI must also be set. If these two bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes 1024 system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed. Buzzer The Buzzer function provides a means of producing a variable frequency output, suitable for applications such as Piezo-buzzer driving or other external circuits that require a precise frequency generator. The BZ and BZ pins form a complimentary pair, and are pin-shared with I/O pins, PB0 and PB1. A configuration option is used to select from one of three buzzer options. The first option is for both pins PB0 and PB1 to be used as normal I/Os, the second option is for both pins to be configured as BZ and BZ buzzer pins, the third option selects only the PB0 pin to be used as a BZ buzzer pin with the PB1 pin retaining its normal I/O pin function. Note that the BZ pin is the inverse of the BZ pin which together generate a differential output which can supply more power to connected interfaces such as buzzers. PBC Register PBC0 0 0 0 0 1 1 1 PBC Register PBC1 0 0 1 1 0 0 1 The clock source of the BZ/BZ, can originate from the timer/event counter 0/1 overflow signal selected by configuration options. For using the BZ/BZ functions, the timer/event counter 0/1 should be set properly to generate the buzzer signal. If the configuration options have selected both pins PB0 and PB1 to function as a BZ and BZ complementary pair of buzzer outputs, then for correct buzzer operation it is essential that both pins must be setup as outputs by setting bits PBC0 and PBC1 of the PBC port control register to zero. The PB0 data bit in the PB data register must also be set high to enable the buzzer outputs, if set low, both pins PB0 and PB1 will remain low. In this way the single bit PB0 of the PB register can be used as an on/off control for both the BZ and BZ buzzer pin outputs. Note that the PB1 data bit in the PB register has no control over the BZ buzzer pin PB1. If configuration options have selected that only the PB0 pin is to function as a BZ buzzer pin, then the PB1 pin can be used as a normal I/O pin. For the PB0 pin to function as a BZ buzzer pin, PB0 must be setup as an output by setting bit PBC0 of the PBC port control register to zero. The PB0 data bit in the PB data register must also be set high to enable the buzzer output, if set low pin PB0 will remain low. In this way the PB0 bit can be used as an on/off control for the BZ buzzer pin PB0. If the PBC0 bit of the PBC port control register is set high, then pin PB0 can still be used as an input even though the configuration option has configured it as a BZ buzzer output.
PB Data Register PB0 0 1 0 1 1 0 X
PB Data Register PB1 X X X X X X X
Output Function PB0=0 PB1=0 PB0=BZ PB1=BZ PB0=0 PB1=input line PB0=BZ PB1=input line PB0=input line PB1=BZ PB0=input line PB1=0 PB0=input line PB1=input line
PB0/PB1 Pin Function Control Note: X stand for dont care
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Options The following table shows all kinds of options in this microcontroller. All of the options must be defined to ensure having proper functioning system. No. 1 2 3 4 5 6 7 8 9 10 11 12 Options WDT clock source: WDT oscillator or fSYS/4 or RTC oscillator or disable CLRWDT instructions: 1 or 2 instructions Timer/Event Counter 0 clock sources: fSYS/4 or RTCOSC Timer/Event Counter 1 clock sources: fSYS/4 or RTCOSC PA bit wake-up enable or disable PA CMOS or Schmitt input PA, PB, PC, PD, PE, PF, PG pull-high enable or disable (by port) System oscillator Ext. RC, Ext. crystal, Int. RC+RTC Buzzer output enable: enabled or disabled Buzzer clock selection: TMR0 or TMR1 Int. RC frequency selection: 3.2MHz, 1.6MHz, 800kHz or 400kHz LVR enable or disable
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Application Circuits
V
DD
0 .0 1 m F * 100kW 0 .1 m F
PA0~PA7 VDD RES PB0~PB7 PC0~PC7 PD0~PD7 PE0~PE7 PF0~PF7 VSS PG 0~PG 7 TM R0
V
DD
R
OSC
470pF C1
OSC1
R C S y s te m O s c illa to r 24kW OSC2 N M O S o p e n d r a in OSC1 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r
10kW
0 .1 m F *
C2 R1
OSC2
OSC C ir c u it S e e R ig h t S id e
OSC1 OSC2
TM R1 TM R2 10pF
OSC1 32768H z OSC2 OSC C ir c u it In te r n a l R C w ith R T C O s c illa to r
IN T 0 IN T 1
TX RX
H T 4 8 R U 8 0 /H T 4 8 C U 8 0
Note: The resistance and capacitance for reset circuit should be designed to ensure that the VDD is stable and remains in a valid range of the operating voltage before bringing RES high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only) Crystal or Resonator 4MHz Crystal 4MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal & Resonator 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator C1, C2 0pF 10pF 0pF 25pF 25pF 35pF 300pF 300pF 300pF R1 10kW 12kW 10kW 10kW 10kW 27kW 9.1kW 10kW 10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
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Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
Note: x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
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HT48RU80/HT48CU80
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr
Operation Affected flag(s)
TO 3/4 CLR [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation Affected flag(s) TO 0 CLR WDT1 Description PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CLR WDT2 Description
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CPL [m] Description Operation Affected flag(s) TO 3/4
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m]
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
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CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m]
Operation Affected flag(s)
TO 3/4 DAA [m] Description
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) TO 3/4 DEC [m] Description Operation Affected flag(s) TO 3/4 DECA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
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HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0
Operation
Affected flag(s) TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation Affected flag(s) TO 3/4 RETI Description Operation Affected flag(s) TO 3/4 RL [m] Description Operation Affected flag(s) TO 3/4 RLA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7
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RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7
Affected flag(s) TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7
Operation
Affected flag(s) TO 3/4 RR [m] Description Operation Affected flag(s) TO 3/4 RRA [m] Description Operation Affected flag(s) TO 3/4 RRC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0
Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
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HT48RU80/HT48CU80
RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0
Operation
Affected flag(s) TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1)
Operation Affected flag(s)
TO 3/4 SDZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1)
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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HT48RU80/HT48CU80
SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1)
Operation Affected flag(s)
TO 3/4 SIZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1)
Operation Affected flag(s)
TO 3/4 SNZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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HT48RU80/HT48CU80
SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
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HT48RU80/HT48CU80
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation Affected flag(s) TO 3/4 TABRDL [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.00
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April 12, 2006
HT48RU80/HT48CU80
XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
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HT48RU80/HT48CU80
Package Information
48-pin SSOP (300mil) Outline Dimensions
48 A
25 B
1 C C'
24
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 395 291 8 613 85 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 637 99 3/4 10 35 12 8
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HT48RU80/HT48CU80
64-pin QFP (1420) Outline Dimensions
C D 51 33 G H
I 52 32 F A B E
64
20 K a J 1 19
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 18.80 13.90 24.80 19.90 3/4 3/4 2.50 3/4 3/4 1.15 0.10 0 Nom. 3/4 3/4 3/4 3/4 1 0.40 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.45 0.20 7
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Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SSOP 48W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 1000.1 13.0+0.5 -0.2 2.00.5 32.2+0.3 -0.2 38.20.2
Rev. 1.00
52
April 12, 2006
HT48RU80/HT48CU80
Carrier Tape Dimensions
D
E F W C B0
P0
P1
t
D1
P K2 A0
K1
SSOP 48W Symbol W P E F D D1 P0 P1 A0 B0 K1 K2 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 32.00.3 16.00.1 1.750.1 14.20.1 2.0 Min. 1.5+0.25 4.00.1 2.00.1 12.00.1 16.200.1 2.40.1 3.20.1 0.350.05 25.5
Rev. 1.00
53
April 12, 2006
HT48RU80/HT48CU80
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
54
April 12, 2006

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