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| IS61LV12824 128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES * High-speed access time: 8, 9, 10, 12 ns * CMOS low power operation -- 720 mW (typical) operating @ 9 ns -- 36 mW (typical) standby @ 9 ns * TTL compatible interface levels * Single 3.3V power supply * Fully static operation: no clock or refresh required * Three state outputs * Available in 119-pin 14x22mm PBGA DESCRIPTION The ICSI IS61LV12824 is a high-speed, static RAM organized as 131,072 words by 24 bits. It is fabricated using ICSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns with low power consumption. When CE1, CE2 are HIGH and CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE1, CE2, CE2 and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV12824 is packaged in the JEDEC standard 119-pin 14*22mm PBGA. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 24 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O23 COLUMN I/O CE2 CE1 CE2 OE WE CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. SR021-0B 1 IS61LV12824 PIN CONFIGURATION 119-pin 14x22mm PBGA 1 A B C D E F G H J K L M N P R T U NC NC I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 VCCQ I/O22 I/O23 I/O12 I/O13 I/O14 I/O15 NC NC 2 A11 A12 NC VCCQ GND VCCQ GND VCCQ GND VCCQ GND VCCQ GND VCCQ NC A10 A9 3 A14 A13 CE2 GND VCC GND VCC GND VCC GND VCC GND VCC GND NC A8 A7 4 A15 CE1 NC GND GND GND GND GND GND GND GND GND GND GND NC WE OE 5 A16 A5 CE2 GND VCC GND VCC GND VCC GND VCC GND VCC GND NC A0 A6 6 A4 A3 NC VCCQ GND VCCQ GND VCCQ GND VCCQ GND VCCQ GND VCCQ NC A1 A2 7 NC NC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 VCCQ I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 NC NC PIN DESCRIPTIONS A0-A16 Address Inputs I/O0-I/O23 Data Inputs/Outputs CE1, CE2 Chip Enable Input LOW CE2 OE WE NC Vcc VCCQ GND Chip Enable Input HIGH Output Enable Input Write Enable Input No Connection Power I/O Power Ground 2 Integrated Circuit Solution Inc. SR021-0B IS61LV12824 TRUTH TABLE Mode Not Selected Output Disabled Read Write WE X H X H H L L CE1 H L L L L L L CE2 X H H H H H H CE2 X L L L L L L OE X H X L H X H I/O0-I/O23 High-Z High-Z High-Z DOUT High-Z DIN HIHG-Z Vcc Current ISB1, ISB2 ICC 1CC ICC 1 2 3 ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC VTERM TSTG TBIAS PT IOUT Parameter Power Supply Voltage Relative to GND Terminal Voltage with Respect to GND Storage Temperature Temperature Under Bias: Com. Ind. Power Dissipation DC Output Current Value -0.5 to 5.0 -0.5 to Vcc + 0.5 -65 to + 150 -10 to + 85 -45 to + 90 2.0 20 Unit V V C C C W mA 4 5 6 7 8 9 Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC (8, 9, 10 ns) 3.3V + 10%, - 5% 3.3V + 10%, - 5% VCC (12 ns) 3.3V 10% 3.3V 10% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) GND VIN VCC GND VOUT VCC, Outputs Disabled Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 -- 2.2 -0.3 -1 -1 Max. -- 0.4 VCC + 0.3 0.8 1 1 Unit V V V V A A 10 11 12 Input Leakage Output Leakage Note: 1. VIL (min.) = -0.3V DC; VIL (min.) = -2.0V AC (pulse width 2.0 ns). VIH (max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width 2.0 ns). Integrated Circuit Solution Inc. SR021-0B 3 IS61LV12824 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 ns Symbol Parameter ICC ISB1 Test Conditions Com. Ind. Min. Max. -9 ns Min. Max. -10 ns Min. Max. -12 ns Min. Max. Unit mA mA Vcc Dynamic Operating VCC = Max., Supply Current IOUT = 0 mA, f = fMAX TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) -- -- -- -- -- -- 210 -- 70 70 10 -- -- -- -- -- -- -- 200 220 60 70 10 20 -- -- -- -- -- -- 180 210 50 55 10 20 -- -- -- -- -- -- 190 190 50 55 10 20 VCC = Max., Com. VIN = VIH or VIL, f = 0 Ind. CE1, CE2, VIH, CE2 VIL VCC = Max., Com. CE1, CE2 VCC - 0.2V, Ind. CE2 0.2V, VIN VCC - 0.2V, or VIN 0.2V, f = 0 ISB2 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 2 ns 1.5V See Figures 1 and 2 AC TEST LOADS ZO = 50 OUTPUT 50 OUTPUT 5 pF Including jig and scope 353 319 3.3V 1.5V Figure 1 Figure 2 4 Integrated Circuit Solution Inc. SR021-0B IS61LV12824 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE1, CE2 Access Time CE2 Access Time OE Access Time (2) -8 Min. Max. 9 -- 3 -- -- 0 0 0 3 -- 9 -- 8 4 5 -- 5 -- -9 Min. Max. 10 -- 3 -- -- 0 0 0 3 -- 10 -- 9 4 5 -- 5 -- -10 Min. 12 -- 3 -- -- 0 0 0 3 Max. -- 12 -- 10 4 6 -- 6 -- -12 Min. Max. 15 -- 3 -- -- 0 0 0 3 -- 15 -- 12 4 7 -- 7 -- Unit ns ns ns ns ns ns ns ns ns 1 2 3 4 5 6 7 8 9 10 11 12 tRC tAA tOHA tACE tACE2 tDOE tHZOE OE to High-Z Output tLZOE(2) OE to Low-Z Output tHZCE(2) CE1, CE2 to High-Z Output tHZCE2(2) CE2 to High-Z Output tLZCE(2) CE, CE2 to Low-Z Output tLZCE2(2) CE2 to Low-Z Output Notes: 1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested. Integrated Circuit Solution Inc. SR021-0B 5 IS61LV12824 AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE1 = CE2 = OE = VIL; CE2 = VIH) t RC ADDRESS t AA t OHA DOUT PREVIOUS DATA VALID t OHA DATA VALID READ CYCLE NO. 2(1,3) t RC ADDRESS t AA OE t OHA t DOE CE1, CE2 t HZOE t LZOE CE2 t LZCE1 t LZCE2 DOUT HIGH-Z t ACE1 t ACE2 DATA VALID t HZCE1 t HZCE2 Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1, CE2 = VIL. CE2 = VIH. 3. Address is valid prior to or coincident with CE1, CE2 LOW and CE2 HIGH transition. 6 Integrated Circuit Solution Inc. SR021-0B IS61LV12824 WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter -8 Min. Max. 8 7 7 7 0 0 -- -- -- -- -- -- -- -- -- -- 3.5 -- -9 Min. Max. 9 8 8 8 0 0 8 9 5 0 -- 3 -- -- -- -- -- -- -- -- -- -- 3.5 -- -10 Min. 10 8 8 8 0 0 8 9 5 0 -- 3 Max. -- -- -- -- -- -- -- -- -- -- 3.5 -- -12 Min. Max. 12 9 9 9 0 0 9 10 5 0 -- 3 -- -- -- -- -- -- -- -- -- -- 3.5 -- Unit ns ns ns ns ns ns ns ns ns ns ns tWC tSCE tSCE2 tAW tHA tSA tPWE1 tPWE2 tSD tHD Write Cycle Time CE1, CE2 to Write End CE2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End 1 2 3 4 5 6 7 WE Pulse Width (OE = HIGH) 6 6 4.5 0 -- 3 tHZWE(2) WE LOW to High-Z Output tLZWE(2) WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1, CE2 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. WRITE CYCLE NO. 1 (WE Controlled) t WC ADDRESS VALID ADDRESS 8 t HA t SA CE1, CE2 t SCE1 t SCE2 9 10 CE2 WE t AW t PWE1 t PWE2 t HZWE t LZWE HIGH-Z 11 12 DOUT DATA UNDEFINED t SD DIN t HD DATAIN VALID Integrated Circuit Solution Inc. SR021-0B 7 IS61LV12824 WRITE CYCLE NO. 2(1) (CE Controlled: OE = HIGH or LOW: CE1, CE2 or CE2 Terminates Write) t WC ADDRESS VALID ADDRESS t HA OE CE1, CE2 CE2 WE LOW HIGH t AW t PWE1 t SA t HZWE DATA UNDEFINED HIGH-Z t LZWE DOUT t SD DIN t HD DATAIN VALID WRITE CYCLE NO. 2(1) (WE Controlled: OE = LOW, CE1, CE2 = LOW; CE2 = HIGH: WE TEMINATES WRITE) t WC ADDRESS VALID ADDRESS OE CE1, CE2 LOW LOW HIGH t HA CE2 t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE HIGH-Z t LZWE t SD DIN t HD DATAIN VALID Note: 1. The internal Write time is defined by the overlap of CE1 and CE2 = LOW, CE2 = HIGH and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that terminates the Write. 8 Integrated Circuit Solution Inc. SR021-0B IS61LV12824 ORDERING INFORMATION Commercial Range: 0C to +70C Speed (ns) Order Part No. 8 9 10 12 IS61LV12824-8B IS61LV12824-9B IS61LV12824-10B IS61LV12824-12B Package 14*22mm PBGA 14*22mm PBGA 14*22mm PBGA 14*22mm PBGA 1 2 3 4 5 6 7 8 9 Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. SR021-0B 10 11 12 9 IS61LV12824 10 Integrated Circuit Solution Inc. SR021-0B |
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