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HDD64M72D18RPW
DDR SDRAM Module 512Mbyte (64Mx72bit), based on 32Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register Part No. HDD64M72D18RPW
GENERAL DESCRIPTION
The HDD64M72D18RPW is a 64M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module. The module consists of eighteen CMOS 32M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 184-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HDD64M72D18RPW is a DIMM( Dual in line Memory Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. All module components may be powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
* Part Identification
HDD64M72D18RPW - 10A : 100MHz (CL=2)
HDD64M72D18RPW - 13A : 133MHz (CL=2) HDD64M72D18RPW - 13B : 133MHz (CL=2.5)
* 512MB(64Mx72) Registered DDR DIMM based on 32Mx8 DDR SDRAM * 2.5V 0.2V VDD and VDDQ power supply * Auto & self refresh capability (8K Cycles / 64ms) * All input and output are compatible with SSTL_2 interface * Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock * All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock * MRS cycle with address key programs - Latency (Access from column address) : 2, 2.5 - Burst length : 2, 4, 8 - Data scramble : Sequential & Interleave * Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock * All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock * The used device is 8M x 8bit x 4Banks DDR SDRAM
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PIN ASSIGNMENT
PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
HDD64M72D18RPW
Front
VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ * CK1 * /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19
PIN
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Back
A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 KEY
PIN
62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
Frontl
VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD * /CS2 DQ48 DQ49 VSS * CK2 * /CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL
PIN
93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
Back
VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC *A13 VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ * BA2 DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23
PIN
124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Front
VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 /CK0 VSS DM8 A10 CB6 VDDQ CB7 KEY
PIN
154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184
Back
/RAS DQ45 VDDQ /CS0 /CS1 DM5 VSS DQ46 DQ47 * /CS3 VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
53 54 55 56 57 58 59 60 61
DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40
145 146 147 148 149 150 151 152 153
VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44
*These pins should be NC in the system which does not support SPD
PIN A0~A12 BA0~BA1 DQ0~DQ63 CB0~CB7 DQS0~DQS8 DM0~DM8 CK0~/CK0 CKE0~CKE1 /CS0~/CS1 /RAS /CAS
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PIN DESCRIPTION Address input Bank Select Address Data input/output Check Bit Data Strobe input/output Data-in Mask Clock input Clock enable input Chip Select input Row Address strobe Column Address strobe
2
PIN VDD VDDQ VREF VDDSPD VSS SA0~SA2 SDA SCL VDDID NC
PIN DESCRIPTION Power supply(2.5V) Power supply for DQs(2.5V) Power supply for reference Serial EEPROM Power supply(3.3) Ground Address in EEPROM Serial data I/O Serial clock VDD identification flag No connection
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FUNCTIONAL BLOCK DIAGRAM
/RCS1 /RCS0
HDD64M72D18RPW
/RCS0 /RCS1
Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ/DQS resistors should be 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD VDDQ. 5. RS0 and RS1 alternate between the back and front sides of the DIMM. 6.Address and control resistors should be 22 Ohms.
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PIN FUNCTION DESCRIPTION
Pin CK, /CK Clock Name
HDD64M72D18RPW
Input Function CK and CK are differential clock inputs. All address and control input signals are sam-pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions
CKE
Clock Enable
except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognizean LVCMOS LOW level prior to VREF being stable on power-up. CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Row/column addresses are multiplexed on the same pins.
/CS
Chip Select
A0 ~ A12
Address
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9 BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE
BA0 ~ BA1
Bank select address
command is being applied. Latches row addresses on the positive going edge of the CLK with /RAS low.
/RAS
Row address strobe
Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with /CAS low.
/CAS
Column address strobe
Enables column access. Enables write operation and row precharge.
/WE
Write enable
Latches data in starting from /CAS, /WE active. Output with read data, input with write data. Edge-aligned with read data, cen-
DQS0~8
Data Strobe
tered in write data. Used to capture write data. DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
DM0~8
Input Data Mask
on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-ing.
DQ0 ~ 63 CB0~CB7 VDDQ VDD VSS VREF VDDSPD VDDID
Data input/output Check Bit Supply Supply Supply Supply Supply
Data inputs/outputs are multiplexed on the same pins. Check Bit Input/Output pins DQ Power Supply : +2.5V 0.2V. Power Supply : +2.5V 0.2V (device specific). DQ Ground. SSTL_2 reference voltage. Serial EEPROM Power Supply : 3.3v VDD identification Flag
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDDQ supply relative to Vss Storage temperature Power dissipation SYMBOL VIN, VOUT VDD VDDQ TSTG PD
HDD64M72D18RPW
RATING -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 18
UNTE V V V C W mA
Short circuit current IOS 50 Notes: Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70C) )
PARAMETER Supply Voltage I/O Supply Voltage I/O Reference Voltage SYMBOL VDD VDDQ VREF MIN 2.3 2.3 VDDQ/2 - 50mA MAX 2.7 2.7 VDDQ/2 + 50mA I/O Termination Voltage(system) Input High Voltage Input Low Voltage Input Voltage Level, CK and /CK inputs Input Differential Voltage, CK and /CK inputs Input crossing point Voltage, CK and /CK inputs Input leakage current Output leakage current Output High current (VOUT = 1.95V) Output Low current (VOUT = 0.35V) Notes : 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled to VREF , both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. 6. These charactericteristics obey the SSTL-2 class II standards. I LI I OZ I OH I OL -2 -5 -16.8 16.8 2 5 uA uA mA mA VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) VIX (DC) VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.3 1.15 VREF + 0.04 VREF + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 1.35 V V V V V V 3 5 2 4 4 UNIT V V V 1 NOTE
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HDD64M72D18RPW
CAPACITANCE
(VDD = min to max, VDDQ = 2.5V to 2.7V, TA = 25C, f = 100MHz)
DESCRIPTION SYMBOL CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 MIN MAX 12 12 11 12 16 16 UNITS pF pF pF pF pF pF
Input capacitance(A0~A12, BA0~BA1, /RAS, /CAS,/WE) Input capacitance(CKE0,CKE1) Input capacitance(/CS0,/CS1) Input capacitance(CK0~/CK1) Input capacitance(DM0~DM8) Data & DQS input/output capacitance (DQ0 ~ DQ63, DQS0~DQS8) Data input/output capacitance (CB0~CB7))
COUT2
-
16
pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, VDD = 2.5V, T =25C)
Symbo pARAMETER l Operating current (One bank active-Precharge) Condition tRC tRC(min), tCK=100MHz for DDR200,133MHz for DDR266A & DDR266B DQ,DM and DQS inputs changing twice per clock cycle Address and control inputs changing once per clock cycle One bank open, BL=4,Reads-Refer to the following page for detailed test condition All banks idle, power-down mode CKE VIL(max), tCK=100MHz for DDR200,133MHz for DDR266A & DDR266B VIN = VREF for DQ,DQS and DM /CS VIH(min), All banks idle CKE VIH(min), tCK=100MHz for DDR200,133MHz for DDR266A & DDR266B Address and control inputs changing once per clock cycle VIN = VREF for DQ,DQS and DM /CS VIH(min), All banks idle CKE VIH(min), tCK=100MHz for DDR200,133MHz for TEST -10A version -13A -13B Unit
IDD0
1515
1695
1695
mA
Operating current (One bankOperation) Precharge powerdown standby current
IDD1
1605
1875
1875
mA
IDD2P
885
1020
1020
mA
Precharge Floating standby current
IDD2F
1020
1155
1155
mA
Precharge Quiet Standby current
IDD2Q
DDR266A & DDR266B Address and other control inputs stable with keeping VIH(min) or VIL(max)
VIN = VREF for DQ,DQS and DM One bank active; power-down mode; CKE VIL(max), tCK=100MHz for DDR200,133MHz for DDR266A & DDR266B VIN = VREF for DQ,DQS and DM. CS# >= VIH(min), CKE>=VIH(min) one bank active, active - precharge, tRC=tRASmax tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B, DQ, DQS and DM inputs changing twice per clock cycle Address and other control inputs changing once per clock cycle
6
975
1110
1110
Active power-down Mode standby current
IDD3P
1020
1155
1155
mA
Active standby IDD3N current
1110
1290
1290
mA
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Operating current (burst read) IDD4R BL = 2, reads, continuous burst One bank open, Address and control inputs changing once per clock cycle, IOUT = 0mA BL = 2, write, continuous burst One bank open, Address and control inputs changing once per clock cycle tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz, distributed refresh CKE =< 0.2V, External clock should be on tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B
HDD64M72D18RPW
2055 2415 2415
mA
Operating current (Bust write)
IDD4W
2415
2955
2955
mA mA
Auto refresh current
IDD5
2055
2415
2415
Self refresh current
Normal IDD6 Low Power IDD7A
354 327
354 327 3945
354 327 3945
mA
Operating current (Four bank operation)
Four bank interleaving with BL=4 -Refer to the following page for detailed test 3315 condition Notes: Operation at above absolute maximum rating can adversely affect device reliability
mA
AC OPERATING CONDITIONS
PARAMETER
Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs
STMBOL
VIH (AC) VIL (AC) VID (AC) VIX (AC)
MIN
VREF + 0.31
MAX
UNIT
NOTE
3
VREF - 0.31
V V V
3 1 2
0.7 0.5*VDDQ-0.2
VDDQ+0.6 0.5*VDDQ+0.2
Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
AC OPERATING TEST CONDITIONS
PARAMETER Input reference voltage for Clock Input signal maximum peak swing Input signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition VALUE 0.5 * VDDQ 1.5 1.0 VREF+0.35/VREF VREF VTT See Load Circuit UNIT V V V V V V V NOTE
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HDD64M72D18RPW
AC CHARACTERISTICS (These AC charicteristics were tested on the Component)
DDR200 PARAMETER SYMBOL -10A MIN Row cycle time Refresh row cycle time Row active time /RAS to /CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay CL=2.0 Clock cycle time CL=2.5 Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST 0.45 0.45 -0.8 -0.8 0.9 0.4 tCK 12 0.55 0.55 +0.8 +0.8 +0.6 1.1 0.6 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 12 0.55 0.55 +0.75 +0.75 +0.5 1.1 0.6 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 12 0.55 0.55 +0.75 +0.75 +0.5 1.1 0.6 ns tCK tCK ns ns ns tCK tCK tRC tRFC tRAS tRCD tRP tRRD tWR tCDLR tCCD 70 80 48 20 20 15 2 1 1 10 12 120K MAX MIN 65 75 45 20 20 15 2 1 1 7.5 12 120K DDR266A -13A MAX MIN 65 75 45 20 20 15 2 1 1 10 12 120K DDR266B -13B MAX ns ns ns ns ns ns tCK tCK tCK ns 1 1,2 1,2 3 3 3 3 2 UNIT NOTE
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Data out high impedence time from tHZQ CK-/CK CK to valid DQS-in DQS-in setup time DQS-in hold time DQS-in falling edge to CK rising-setup tDSS time DQS-in falling edge to CK rising hold tDSH time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time Address and Control Input hold time Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width Power down exit time Exit self refresh to write command Exit self refresh to bank active tXSA command Exit self refresh to read command Refresh interval time Output DQS valid window DQS write postamble time Notes : 1. 2. 3. Maximum burst refresh of 8. tXSR TREF TQH TWPST 200 7.8 0.35 0.25 200 7.8 0.35 0.25 80 tDQSH tDQSL tDSC tIS tIH tMRD tDS tDH tDIPW tPDEX tXSW 0.35 0.35 0.9 1.1 1.1 16 0.6 0.6 2 10 116 1.1 0.35 0.35 0.9 0.9 0.9 15 0.5 0.5 1.75 10 95 75 1.1 0.2 0.2 0.2 0.2 tDQSS tWPRES tWPREH 0.75 0 0.25 1.25 0.75 0 0.25 1.25 -0.8 +0.8 -0.75 +0.75
HDD64M72D18RPW
-0.75 0.75 0 0.25 0.2 +0.75 1.25 ns tCK ns tCK tCK 3 2
0.2 0.35 0.35 0.9 0.9 0.9 15 0.5 0.5 1.75 10 1.1
tCK tCK tCK tCK ns ns ns ns ns ns ns ns
75 ns 200 7.8 0.35 0.25 Cycle us tCK tCK 4 1
tHZQ transitions occurs in the same assess time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving. The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS.
4.
The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly.
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HDD64M72D18RPW
SIMPLIFIED TRUTH TABLE
COMMAND Register Register Extended MRS Mode register set Auto refresh Refresh Self refresh Entry Exit CK E n-1 H H H L H precharge H X L H L H X V CK E n X X H L H X /CS L L L L H L /R A S L L L H X L /C A S L L L H X H /WE L L H H X H DM X X X X X V BA 0,1 A10/ AP OP code OP code X X Row address L H H H X L H L L H Bank selection All banks Entry Exit Entry Exit H H L H L H H X H L X X L H L H L L H L X H L H L H L X V X X H X V X X H X H X H H H X V X X H X V L L X V X X H X V X X X X X X X V X X X 8 V X L H X X V H X X L Column Address (A0 ~A9) Column Address (A0 ~ A9) 4,6 7 5 4 4 4 A11,A12 A9~A0 NOTE 1,2 1,2 3 3 3 3
Bank active & row addr. Read & column address Write & column address Burst Stop Precharg e Auto disable Auto precharge eable Auto precharge disable Auto precharge enable
Clock suspend or active power down
Precharge power down mode DM
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0)
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PACKAGING INFORMATION
Unit : mm
HDD64M72D18RPW

133.35 0.20
U11 U1 U2 U3 U4 U12 U5 U6 U7 U8 U9
30.48 0.20
A
B
< Rear - Side >
133.35 0.20
U13 U22 U21 U20 U19 U1 0 U18 U17 U16 U15 U14
30.48 0.20
***
PCB
: 1.27 0.08 mm
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ORDERING INFORMATION
HDD64M72D18RPW
Part Number
Density
Org.
Package Low Profile
Ref.
Vcc
MODE
MAX.frq
HDD64M72D18RWP-10A
512MByte
64M x 72
184PIN DIMM Low Profile
8K
2.5V
Registered DDR Registered DDR Registered DDR
100MHz/CL2
HDD64M72D18RW-13A
512MByte
64M x 72
184PIN DIMM Low Profile
8K
2.5V
133MHz/CL2
HDD64M72D18RW-13B
512MByte
64M x 72
184PIN DIMM
8K
2.5V
133MHz/CL2 .5
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