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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853058
8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
FEATURES
* High speed 8:1 differential multiplexer * 1 differential 3.3V or 2.5V LVPECL output * 8 selectable differential PCLK, nPCLK inputs * PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Maximum output frequency: 2.5GHz * Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input * Part-to-part skew: TBD * Propagation delay: 620ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.465V to -2.375V * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS853058 is an 8:1 Differential-to-3.3V or 2.5V LVPECL / ECL Clock Multiplexer which can HiPerClockSTM operate up to 2.5GHz and is a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS853058 has 8 differential selectable clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors. The SEL2 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 000 selects PCLK0, nPCLK0).
ICS
BLOCK DIAGRAM
PCLK0 nPCLK0 PCLK1 nPCLK1 PCLK2 nPCLK2 PCLK3 nPCLK3
PCLK4 nPCLK4 PCLK5 nPCLK5 PCLK6 nPCLK6 PCLK7 nPCLK7
PIN ASSIGNMENT
PCLK0 nPCLK0 PCLK1 nPCLK1 VCC SEL0 SEL1 SEL2 PCLK2 nPCLK2 PCLK3 nPCLK3
Q0 nQ0
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
000
001
010
011
PCLK7 nPCLK7 PLCK6 nPCLK6 VCC Q0 nQ0 VEE PCLK5 nPCLK5 PCLK4 nPCLK4
100
ICS853058
24-Lead, 173-MIL TSSOP 4.4mm x 7.8mm x 0.92mm body package G Package Top View
101
110
111
SEL2 SEL1 SEL0
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 853058AG www.icst.com/products/hiperclocks.html REV. A APRIL 13, 2004
1
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853058
8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
Type Input Input Input Input Power Input Input Input Input Input Input Input Input Input Power Output Input Input Input Input Pullup/Pulldown Pulldown Pullup/Pulldown Pulldown Pulldown Pulldown Pulldown Description Non-inver ting differential LVPECL clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5, 20 6, 7, 8 9 10 11 12 13 14 15 16 17 18, 19 21 22 23 24 Name PCLK0 nPCLK0 PCLK1 nPCLK1 VCC SEL0, SEL1, SEL2 PCLK2 nPCLK2 PCLK3 nPCLK3 nPCLK4 PCLK4 nPCLK5 PCLK5 VEE nQ0, Q0 nPCLK6 PCLK6 nPCLK7 PCLK7
Inver ting differential LVPECL clock input. Pullup/Pulldown VCC/2 default when left floating. Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Pullup/Pulldown VCC/2 default when left floating. Positive supply pins. Clock select input pins. LVCMOS/LVTTL interface levels. Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input. Pullup/Pulldown VCC/2 default when left floating. Pulldown Pullup/Pulldown Pullup/Pulldown Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input. Pullup/Pulldown VCC/2 default when left floating. Pulldown Non-inver ting differential LVPECL clock input. Negative supply pin. Differential output pair. LVPECL interface levels. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Non-inver ting differential LVPECL clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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REV. A APRIL 13, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853058
8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
Test Conditions Minimum Typical 75 50 Maximum Units K K
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN RVDD/2 Parameter Input Pulldown Resistor Pullup/Pulldown Resistosr
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs SEL2 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 Q0 PCLK0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5 PCLK6 PCLK7 Outputs nQ0 nPCLK0 nPCLK1 nPCLK2 nPCLK3 nPCLK4 nPCLK5 nPCLK6 nPCLK7
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REV. A APRIL 13, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853058
8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) to the device. These ratings are stress specifi-0.5V to V + 0.5V
CC
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
0.5V to VEE - 0.5V 50mA 100mA -65C to 150C 70C/W (0 mps)
cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Operating Temperature Range, TA -40C to +85C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol VCC ICC Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 38 Maximum 3.465 Units V mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol VIH VIL IIH IIL Parameter Input High Voltage SEL0:SEL2 VCC = VIN = 3.465V, VCC = VIN = 2.625V VCC = 3.465V, VIN = 0V, VCC = 2.625V, VIN = 0V Input Low Voltage SEL0:SEL2 Input High Current Input Low Current SEL0:SEL2 SEL0:SEL2 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 -150 Units V V A A
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol Parameter IIH IIL V PP VCMR VOH VOL Input High Current Input Low Current PCLK0:PCLK7 nPCLK0:nPCLK7 PCLK0:PCLK7 nPCLK0:nPCLK7 Test Conditions VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -10 -150 0.15 1.2 VCC - 1.005 VCC - 1.78 3.3 Minimum Typical Maximum 150 Units A A A V V V V V
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage Voltage; NOTE 3 Output Low Voltage; NOTE 3
Peak-to-Peak Output Voltage Swing 0.8 VSWING NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V. NOTE 3: Outputs terminated with 50 to VCC - 2V.
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REV. A APRIL 13, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853058
8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
Test Conditions Minimum Typical -1.005 -1.78 -1.225 -1.87 800 VEE + 1.2 0 150 -10 -150 -0.94 -1.535 Maximum Units V V V V mV V A A A
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.465V TO -2.375V
Symbol VOH VOL VIH VIL V PP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLK0:PCLK7 High Current nPCLK0:nPCLK7 PCLK0:PCLK7 Input Low Current nPCLK0:nPCLK7
NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.465V TO -2.375V OR VCC = 2.375 TO 3.465V; VEE = 0V
Symbol Parameter fMAX t PD Output Frequency Propagation Delay; NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 620 TBD Test Conditions Minimum Typical Maximum 2.5 Units GHz ps ps ps
tsk(pp)
Output Rise/Fall Time 20% to 80% 150 tR / tF All parameters measured up to 1.3GHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined according with JEDEC Standard 65.
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REV. A APRIL 13, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853058
8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
SCOPE
V CC
nPCLK0:7
LVPECL
nQx
V
PP
Cross Points
V
CMR
PCLK0:7
VEE
VEE
-1.465V to -0.375V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nPCLK0:7 PCLK0:7 nQ0 Q0
tPD
nQx PART 1 Qx nQy PART 2 Qy
tsk(pp)
PROPAGATION DELAY
PART-TO-PART SKEW
80% Clock Outputs
80% VOD
20% tR tF
20%
OUTPUT RISE/FALL TIME
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REV. A APRIL 13, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853058
8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION
FOR
3.3V LVPECL OUTPUTS
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
Zo = 50 84 84
1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o
FIGURE 2A. LVPECL OUTPUT TERMINATION
853058AG
FIGURE 2B. LVPECL OUTPUT TERMINATION
REV. A APRIL 13, 2004
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853058
8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
VCC=2.5V
R1 250
R3 250
+
Zo = 50 Ohm
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL Driv er
R2 62.5
2,5V LVPECL Driv er
R1 50
R2 50
R4 62.5
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL Driv er
R1 50
R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. A APRIL 13, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853058
8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
gested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces sug-
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK
Zo = 60 Ohm
2.5V
3.3V
2.5V
R3 120
SSTL
R2 50
R4 120
PCLK
Zo = 60 Ohm
Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
nPCLK
HiPerClockS PCLK/nPCLK
R1 120
R2 120
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL IN DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3 125
R4 125
PCLK
3.3V
Zo = 50 Ohm
LVDS
R5 100
Zo = 50 Ohm
C1
R3 1K
R4 1K
PCLK
C2
Zo = 50 Ohm
nPCLK
LVPECL
R1 84
R2 84
HiPerClockS Input
Zo = 50 Ohm
nPCLK
HiPerClockS PCL K/n PC LK
R1 1K
R2 1K
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
3.3V LVPECL
Zo = 50 Ohm
C1
R3 84
R4 84
PCLK
Zo = 50 Ohm
C2
nPCLK
HiPerClockS PCLK/nPCLK
R5 100 - 200
R6 100 - 200
R1 125
R2 125
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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REV. A APRIL 13, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853058
8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
nation approaches are available in the LVPECL Termination Application Note. It is recommended at least one decoupling capacitor per power pin. The decoupling capacitor should be low ESR and located as close as possible to the power pin.
SCHEMATIC EXAMPLE
An application schematic example of ICS853058 is shown in Figure 5. The inputs can accept various types of differential signals. In this example, the inputs are driven by 3.3V LVPECL drivers. The ICS853058 output is an LVPECL driver. An example of LVPECL terminations is shown this schematic. Other termi-
Zo = 50
Logic Control Input Examples
Zo = 50
3.3V
LVPECL
Set Logic Input to '1'
RU1 1K
3.3V
Set Logic Input to '0'
RU2 Not Install
R1 50
R2 50
R3 50
To Logic Input pins
RD1 Not Install
To Logic Input pins
RD2 1K
Zo = 50
U1
Zo = 50
3.3V
LVPECL
R4 50
R5 50
R6 50
1 2 3 4 5 6 7 8 9 10 11 12
C1 0.1u
PCLK0 nPCLK0 PCLK1 nPCLK1 VCC SEL0 SEL1 SEL2 PCLK2 nPCLK2 PCLK3 nPCLK3
PCLK7 nPCLK7 PCLK6 nPCLK6 VCC Q0 nQ0 GND PCLK5 nPCLK5 PCLK4 nPCLK4
24 23 22 21 20 19 18 17 16 15 14 13
Zo = 50
3.3V
+
Zo = 50
-
LVPECL
C2 0.1u
R7 50
R8 50
ICS853058
R9 50
FIGURE 5. ICS853058 SCHEMATIC EXAMPLE
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REV. A APRIL 13, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853058
8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853058. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS853058 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 38mA = 131.67mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 1 * 30.94mW = 30.94mW
Total Power_MAX (3.465V, with all outputs switching) = 131.67mW + 30.94mW = 162.61mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.163W * 65C/W = 95.6C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
24-PIN TSSOP FORCED CONVECTION
JA by Velocity (Meters per Second)
0 70C/W 1 65C/W 2.5 62C/W
Multi-Layer PCB, JEDEC Standard Test Boards
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REV. A APRIL 13, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
ICS853058
8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 0.935V
-V
OH_MAX
) = 0.935V =V - 1.67V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.67V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.935V)/50] * 0.935V = 19.92mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50] * 1.67V = 11.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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REV. A APRIL 13, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853058
8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER RELIABILITY INFORMATION
TABLE 7.
JAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0 70C/W
1 65C/W
2.5 62C/W
TRANSISTOR COUNT
The transistor count for ICS853058 is: 326
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REV. A APRIL 13, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853058
8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
24 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MS-153
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REV. A APRIL 13, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853058
8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
Marking ICS853058AG ICS853058AG Package 24 Lead TSSOP 24 Lead TSSOP on Tape and Reel Count 60 per tube 2500 Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS853058AG ICS853058AGT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853058AG
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REV. A APRIL 13, 2004

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