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| MC74LVXT8053 Analog Multiplexer / Demultiplexer High-Performance Silicon-Gate CMOS The MC74LVXT8053 utilizes silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. This analog multiplexer/demultiplexer controls analog voltages that may vary across the complete power supply range (from VCC to GND). The LVXT8053 is similar in pinout to the high-speed HC4053A, and the metal-gate MC14053B. The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected by means of an analog switch to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel-Select and Enable inputs are compatible with TTL-type input thresholds. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic-level translator from 3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic while operating at the higher-voltage power supply. The MC74LVXT8053 input structure provides protection when voltages up to 7V are applied, regardless of the supply voltage. This allows the MC74LVXT8053 to be used to interface 5V circuits to 3V circuits. This device has been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal-gate CMOS analog switches. http://onsemi.com 16-LEAD SOIC D SUFFIX CASE 751B 16-LEAD TSSOP DT SUFFIX CASE 948F PIN CONNECTION AND MARKING DIAGRAM (Top View) VCC 16 Y 15 X 14 X1 13 X0 12 A 11 B 10 C 9 1 Y1 2 Y0 3 Z1 4 Z 5 Z0 6 Enable 7 NC 8 GND * * * * * * * * Fast Switching and Propagation Speeds Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range (VCC - GND) = 2.0 to 6.0 V Digital (Control) Power Supply Range (VCC - GND) = 2.0 to 6.0 V Improved Linearity and Lower ON Resistance Than Metal-Gate Counterparts Low Noise In Compliance With the Requirements of JEDEC Standard No. 7A LOGIC DIAGRAM Triple Single-Pole, Double-Position Plus Common Off X0 13 X1 12 For detailed package marking information, see the Marking Diagram section on page 11 of this data sheet. FUNCTION TABLE - MC74LVXT8053 Control Inputs Enable L L L L L L L L H X = Don't Care C L L L L H H H H X Select B A L L H H L L H H X L H L H L H L H X ON Channels Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 NONE X0 X1 X0 X1 X0 X1 X0 X1 X SWITCH 14 X ANALOG INPUTS/OUTPUTS Y0 1 Y1 Z0 3 Z1 5 2 Y SWITCH 15 Y COMMON OUTPUTS/INPUTS ORDERING INFORMATION Z SWITCH 4 Z Device MC74LVXT8053D MC74LVXT8053DR2 MC74LVXT8053DT MC74LVXT8053DTR2 Package SOIC SOIC TSSOP TSSOP Shipping 48 Units/Rail 2500 Units/Reel 96 Units/Rail 2500 Units/Reel CHANNEL-SELECT INPUTS PIN 16 = VCC PIN 8 = GND ENABLE NOTE: This device allows independent control of each switch. Channel-Select Input A controls the X-Switch, Input B controls the Y-Switch and Input C controls the Z-Switch 11 A 10 B 9 C 6 (c) Semiconductor Components Industries, LLC, 1999 1 March, 2000 - Rev. 2 Publication Order Number: MC74LVXT8053/D MC74LVXT8053 IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII II I III I I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIII III I II I IIIIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* SymbolIIIIIIIIIIIIII Parameter VCC VIS Vin I Positive DC Supply Voltage Analog Input Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0III V V V - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 -20 500 450 Digital Input Voltage (Referenced to GND) DC Current, Into or Out of Any Pin Power Dissipation in Still Air, Storage Temperature Range mA PD SOIC Package TSSOP Package mW Tstg TL - 65 to + 150 260 _C _C Lead Temperature, 1 mm from Case for 10 Seconds *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. v v RECOMMENDED OPERATING CONDITIONS IIII I I I I IIIIIIIIIIIIIIIIIIIII I IIII I II I II IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I IIII I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I I Symbol VCC VIS Vin Parameter Min 2.0 0.0 Max 6.0 Unit V V V V Positive DC Supply Voltage Analog Input Voltage (Referenced to GND) VCC VCC 1.2 Digital Input Voltage (Referenced to GND) Static or Dynamic Voltage Across Switch GND VIO* TA Operating Temperature Range, All Package Types - 55 + 85 _C tr, tf Input Rise/Fall Time (Channel Select or Enable Inputs) VCC = 3.3 V 0.3 V VCC = 5.0 V 0.5 V ns/V 0 0 100 20 *For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. http://onsemi.com 2 MC74LVXT8053 DC CHARACTERISTICS -- Digital Section (Voltages Referenced to GND) VCC V 3.0 4.5 5.5 3.0 4.5 5.5 5.5 5.5 Guaranteed Limit -55 to 25C 1.2 2.0 2.0 0.53 0.8 0.8 0.1 4 85C 1.2 2.0 2.0 0.53 0.8 0.8 1.0 40 125C 1.2 2.0 2.0 0.53 0.8 0.8 1.0 160 Unit V Symbol VIH Parameter Minimum High-Level Input Voltage, Channel-Select or Enable Inputs Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs Maximum Input Leakage Current, Channel-Select or Enable Inputs Maximum Quiescent Supply Current (per Package) Condition Ron = Per Spec VIL Ron = Per Spec V Iin ICC Vin = VCC or GND, Channel Select, Enable and VIS = VCC or GND; VIO = 0 V A A II II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I Guaranteed Limit Symbol Ron Parameter Test Conditions VCC V 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 5.5 - 55 to 25_C 40 30 25 30 25 20 DC ELECTRICAL CHARACTERISTICS Analog Section v 85_C v 125_C 45 32 28 35 28 25 20 12 12 50 37 30 40 35 30 25 15 15 Unit Maximum "ON" Resistance Vin = VIL or VIH VIS = VCC to GND |IS| 10.0 mA (Figures 1, 2) v v Ron Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Vin = VIL or VIH VIS = VCC or GND (Endpoints) |IS| 10.0 mA (Figures 1, 2) Vin = VIL or VIH VIS = 1/2 (VCC - GND) |IS| 10.0 mA v 15 8.0 8.0 Ioff Maximum Off-Channel Leakage Current, Any One Channel Maximum Off-Channel Leakage Current, Common Channel Vin = VIL or VIH; VIO = VCC or GND; Switch Off (Figure 3) Vin = VIL or VIH; VIO = VCC or GND; Switch Off (Figure 4) 0.1 0.5 1.0 A 5.5 0.1 1.0 2.0 Ion Maximum On-Channel Leakage Current, Channel-to-Channel Vin = VIL or VIH; Switch-to-Switch = VCC or GND; (Figure 5) 5.5 0.1 1.0 2.0 A http://onsemi.com 3 MC74LVXT8053 AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 3 ns) Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Channel-Select to Analog Output (Figure 9) VCC V 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 Guaranteed Limit -55 to 25C 30 20 15 15 4.0 3.0 1.0 1.0 30 20 15 15 20 12 8.0 8.0 10 35 50 1.0 85C 35 25 18 18 6.0 5.0 2.0 2.0 35 25 18 18 25 14 10 10 10 35 50 1.0 125C 40 30 22 20 8.0 6.0 2.0 2.0 40 30 22 20 30 15 12 12 10 35 50 1.0 pF Unit ns tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figure 10) ns tPLZ, tPHZ Maximum Propagation Delay, Enable to Analog Output (Figure 11) ns tPZL, tPZH Maximum Propagation Delay, Enable to Analog Output (Figure 11) ns Cin CI/O Maximum Input Capacitance, Channel-Select or Enable Inputs Maximum Capacitance (All Switches Off) Analog I/O Common O/I Feedthrough pF pF CPD Power Dissipation Capacitance (Figure 13)* Typical @ 25C, VCC = 5.0 V 45 * Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . http://onsemi.com 4 MC74LVXT8053 ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) VCC V Limit* 25C Unit MHz 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 120 120 120 -50 -50 -50 -37 -37 -37 25 105 135 35 145 190 -50 -50 -50 -60 -60 -60 % 3.0 4.5 5.5 0.10 0.08 0.05 dB mVPP dB Symbol BW Parameter Maximum On-Channel Bandwidth or Mi i Minimum Frequency Response F R (Figure 6) Condition fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain 0dBm t 0dB at VOS; I Increase fin Frequency Until dB F U til Meter Reads -3dB; RL = 50, CL = 10pF fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600, CL = 50pF -- Off-Channel Feedthrough Isolation (Figure 7) fin = 1.0MHz, RL = 50, CL = 10pF -- Feedthrough Noise. Channel-Select Input to Common I/O (Figure 8) Vin 1MHz Square Wave (tr = tf = 3ns); Adjust RL at Setup so that IS = 0A; Enable = GND RL = 600, CL = 50pF RL = 10k, CL = 10pF -- Crosstalk Between Any Two Switches (Figure 12) fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600, CL = 50pF fin = 1.0MHz, RL = 50, CL = 10pF THD Total Harmonic Distortion (Figure 14) fin = 1kHz, RL = 10k, CL = 50pF THD = THDmeasured - THDsource VIS = 2.0VPP sine wave VIS = 4.0VPP sine wave VIS = 5.0VPP sine wave *Limits not tested. Determined by design and verified by qualification. 45 40 Ron , ON RESISTANCE (OHMS) 35 30 25 20 15 10 5 00 1.0 2.0 VIN, INPUT VOLTAGE (VOLTS) 3.0 4.0 125C 85C 25C - 55C Figure 1a. Typical On Resistance, VCC = 3.0 V http://onsemi.com 5 MC74LVXT8053 35 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 30 25 20 15 10 5 0 0 1.0 2.0 3.0 4.0 5.0 125C 85C 25C - 55C 30 25 20 15 10 5 0 125C 85C 25C - 55C 0 1.0 2.0 3.0 4.0 5.0 6.0 VIN, INPUT VOLTAGE (VOLTS) VIN, INPUT VOLTAGE (VOLTS) Figure 1b. Typical On Resistance, VCC = 4.5 V Figure 1c. Typical On Resistance, VCC = 5.5 V PLOTTER PROGRAMMABLE POWER SUPPLY - + MINI COMPUTER DC ANALYZER VCC DEVICE UNDER TEST ANALOG IN COMMON OUT GND GND Figure 1. On Resistance Test Set-Up http://onsemi.com 6 MC74LVXT8053 VCC VCC GND OFF VCC A NC OFF 16 VCC GND VCC 16 ANALOG I/O OFF OFF VCC COMMON O/I COMMON O/I VIH 6 8 VIH 6 8 Figure 2. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up Figure 3. Maximum Off Channel Leakage Current, Common Channel, Test Set-Up VCC A ON GND VCC ANALOG I/O VIL 6 8 OFF 16 VCC fin COMMON O/I N/C 0.1F ON VCC 16 VOS dB METER CL* RL 6 8 *Includes all probe and jig capacitance Figure 4. Maximum On Channel Leakage Current, Channel to Channel, Test Set-Up Figure 5. Maximum On Channel Bandwidth, Test Set-Up VIS 0.1F fin RL OFF VCC 16 VOS dB METER CL* RL RL ON/OFF ANALOG I/O OFF/ON RL VCC 16 COMMON O/I RL CL* TEST POINT 6 8 VIL or VIH CHANNEL SELECT *Includes all probe and jig capacitance VIH VIL Vin 1 MHz tr = tf = 3 ns 6 8 11 VCC CHANNEL SELECT *Includes all probe and jig capacitance Figure 6. Off Channel Feedthrough Isolation, Test Set-Up Figure 7. Feedthrough Noise, Channel Select to Common Out, Test Set-Up http://onsemi.com 7 MC74LVXT8053 VCC VCC CHANNEL SELECT tPLH ANALOG OUT 50% GND tPHL 6 50% 8 CHANNEL SELECT *Includes all probe and jig capacitance ON/OFF ANALOG I/O OFF/ON CL* VCC 16 COMMON O/I TEST POINT Figure 9a. Propagation Delays, Channel Select to Analog Out Figure 9b. Propagation Delay, Test Set-Up Channel Select to Analog Out VCC 16 VCC 50% GND tPLH ANALOG OUT 50% tPHL 6 8 ANALOG I/O ON CL* COMMON O/I TEST POINT ANALOG IN *Includes all probe and jig capacitance Figure 10a. Propagation Delays, Analog In to Analog Out Figure 10b. Propagation Delay, Test Set-Up Analog In to Analog Out tf ENABLE tPZL ANALOG OUT 50% tr 90% 50% 10% tPLZ VCC GND HIGH IMPEDANCE 10% tPZH tPHZ VOL VOH HIGH IMPEDANCE VIH VIL VCC 1 2 1 2 POSITION 1 WHEN TESTING tPHZ AND tPZH POSITION 2 WHEN TESTING tPLZ AND tPZL VCC 16 ANALOG I/O ON/OFF CL* ENABLE 1k TEST POINT ANALOG OUT 90% 50% 6 8 Figure 11a. Propagation Delays, Enable to Analog Out Figure 11b. Propagation Delay, Test Set-Up Enable to Analog Out http://onsemi.com 8 MC74LVXT8053 VCC VIS VCC RL fin 0.1F OFF RL 6 8 *Includes all probe and jig capacitance RL CL* RL CL* 6 8 11 VCC ON 16 VOS ANALOG I/O OFF/ON ON/OFF 16 COMMON O/I NC A CHANNEL SELECT Figure 12. Crosstalk Between Any Two Switches, Test Set-Up 0 VCC 16 ON RL CL* VOS TO DISTORTION METER dB - 10 - 20 - 30 - 40 - 50 - 60 6 8 *Includes all probe and jig capacitance - 70 - 80 - 90 - 100 Figure 13. Power Dissipation Capacitance, Test Set-Up VIS 0.1F fin FUNDAMENTAL FREQUENCY DEVICE SOURCE 1.0 2.0 FREQUENCY (kHz) 3.125 Figure 14a. Total Harmonic Distortion, Test Set-Up Figure 14b. Plot, Harmonic Distortion APPLICATIONS INFORMATION The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: VCC = +5V = logic high GND = 0V = logic low The maximum analog voltage swing is determined by the supply voltages VCC. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below GND. In this example, the difference between VCC and GND is five volts. Therefore, using the configuration of Figure 15, a maximum analog signal of five volts peak-to-peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VCC - GND = 2 to 6 volts When voltage transients above VCC and/or below GND are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 16. These diodes should be able to absorb the maximum anticipated current surges during clipping. http://onsemi.com 9 MC74LVXT8053 +5V +5V 0V 16 ANALOG SIGNAL ON ANALOG SIGNAL +5V 0V VCC Dx Dx GND 6 8 11 10 9 TO EXTERNAL LSTTL COMPATIBLE CIRCUITRY 0 to VIH DIGITAL SIGNALS VCC 16 ON/OFF Dx GND VCC Dx 8 Figure 15. Application Example Figure 16. External Germanium or Schottky Clipping Diodes +5V +3V GND +5V GND 16 ANALOG SIGNAL ON/OFF ANALOG SIGNAL +5V GND 1.8 - 2.5V +3V +3V GND 16 ANALOG SIGNAL ON/OFF ANALOG SIGNAL 6 8 11 10 9 1.8 - 2.5V CIRCUITRY 6 8 11 10 9 1.8 - 2.5V CIRCUITRY MC74VHC1GT50 BUFFERS VCC = 3.0V a. Low Voltage Logic Level Shifting Control b. 2-Stage Logic Level Shifting Control Figure 17. Interfacing Low Voltage CMOS Inputs A 11 LEVEL SHIFTER 13 X1 12 14 B 10 LEVEL SHIFTER 1 X0 X Y1 2 15 C 9 LEVEL SHIFTER 3 Y0 Y Z1 5 4 ENABLE 6 LEVEL SHIFTER Z0 Z Figure 18. Function Diagram, LVXT8053 http://onsemi.com 10 MC74LVXT8053 MARKING DIAGRAMS (Top View) 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 LVXT8051 AWLYWW* 1 2 3 4 5 6 7 8 1 2 3 LVXT 8051 ALYW* 4 5 6 7 8 16-LEAD SOIC D SUFFIX CASE 751B 16-LEAD TSSOP DT SUFFIX CASE 948F *See Applications Note #AND8004/D for date code and traceability information. PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A - 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7 0 0.229 0.244 0.010 0.019 -B - 1 8 P 8 PL 0.25 (0.010) M B M G F K C -T SEATING - PLANE R X 45 M D 16 PL 0.25 (0.010) M J TB S A S http://onsemi.com 11 MC74LVXT8053 PACKAGE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K 16 2X L/2 9 J1 B -U- L PIN 1 IDENT. 1 8 SECTION N-N J N 0.25 (0.010) 0.15 (0.006) T U S A -V- N F DETAIL E C 0.10 (0.004) -T- SEATING PLANE H D G DETAIL E ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 1:00pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 1:00pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, England, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5740-2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 12 CCC EE CCC EE CCC M K1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ -W- DIM A B C D F G H J J1 K K1 L M MC74LVXT8053/D |
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