, 32.8kHz<sub>)
Operating Voltage Range
*
1.8 V to 5.5 V at 1MHz/32.8kHz
Key Interrupt input(Quasi-interrupt)
* *
Power Consumption(The LVD circuit needs 100uA or more current on all the below mode)
* *
Falling edge detection(KS0, KS1) Stand by mode(idle, stop) release
Main: Operation - 0.5mA at 1MHz, 3V Sub: Operation - 12A at LCD off, 3V Idle - 5A at LCD off idle, 3V Stop - 1A at 5.5V
Power on RESET (Program ROM MASK option)
* *
Initial power on RESET Reset operation under 2.0V Operating Temperature
*
- 40 C to 85 C
LCD Display
* * *
16 segments and 4 common pins 2, 3, and 4 common selectable Internal resistor for LCD bias(170 K)
Package Type
*
32-SOP-450A Package
1-2
S3C7281
PRODUCT OVERVIEW
BLOCK DIAGRAM
RESET
XTIN
XTOUT
P0.3 P0.2/BUZ P0.1/BUZ P0.0/CLO
I/O Port 0
Interrupt Control Block
Sub Clock Main Clock (Internal RC OSC) Instruction Register
Basic Timer
Watchdog Timer
P1.1/KS1 I/O Port 1 P1.0/KS0
Internal Interrupts Instruction Decoder Arithmetic and Logic Unit
Output Port 2
Program Counter
Watch Timer COM0-COM1
Program Status Word
LCD Driver/ Controller
COM2-COM3/ SEG0-SEG1 SEG2-SEG9 SEG10-SEG17/ P2.7-P2.0
P2.4-P2.7/ SEG13-SEG10 P2.0-P2.3/ SEG17-SEG14
Stack Pointer Power on
RESET
* AGP Option 64 x 4-Bit Data Memory 1024-Byte Program Memory
Figure 1-1. S3C7281 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C7281
PIN ASSIGNMENTS
VSS XTIN XTOUT TEST P1.0/KS0 P1.1/KS1
RESET
COM0 COM1 COM2/SEG0 COM3/SEG1 SEG2 SEG3 SEG4 SEG5 SEG6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 SCLK (note) 31 SDAT (note) 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD P0.0/CLO P0.1/BUZ P0.2/BUZ P0.3 P2.0/SEG17 P2.1/SEG16 P2.2/SEG15 P2.3/SEG14 P2.4/SEG13 P2.5/SEG12 P2.6/SEG11 P2.7/SEG10 SEG9 SEG8 SEG7
NOTE: Reserved pins for the OTP version in the future
Figure 1-2. S3C7281 32-SOP Pin Assignment Diagram
(32-SOP-450A)
S3C7281
1-4
S3C7281
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7281 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. 1-bit unit pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. Individual pins can be allocated as input or output(1-bit unit). The n-channel open-drain or pushpull output can be selected by software(1-bit unit). 4-bit I/O port. 1-bit or 4-bit write and test is possible. 4-bit unit pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. The pins can be allocated as input or output(4-bit unit). The n-channel open-drain or push-pull output can be selected by software(4-bit unit). 8-bit output port. 1-bit, 4-bit, 8-bit read/write and test is possible. The n-channel open-drain or push-pull output can be selected by software(4-bit unit). Clock output. Buzzer signal output. Inverted buzzer signal output. External interrupt with falling edge detection. LCD segment signal output. LCD segment signal output. LCD segment signal output. LCD common signal output. LCD common signal output. Crystal oscillator pins for subsystem clock. Main power supply. Ground. Chip reset signal input. Chip test signal input (must be connected to VSS). Number 31 30 29 28 Share Pin CLO BUZ
BUZ
P1.0 P1.1
I/O
5 6
KS0 KS1
P2.0 - P2.7
O
27 - 20
SEG17SEG10
CLO BUZ
BUZ
I/O I/O I/O I/O O O O O O - - - I I
31 30 29 5 6 10 11 12 - 19 20 - 27 8 9 10 11 2 3 32 1 7 4
P0.0 P0.1 P0.2 P1.0 P1.1 COM0 COM1 - P2.7 - P2.0 - SEG0 SEG1 - - - - -
KS0 KS1 SEG0 SEG1 SEG2-SEG9 SEG10-SEG17 COM0 COM1 COM2 COM3 XTIN XTOUT VDD VSS
RESET
TEST
1-5
PRODUCT OVERVIEW
S3C7281
Table 1-1. S3C7281 Pin Descriptions (Continued) Pin Name P0.0 - P0.2 P0.3 P1.0 - P1.1 P2.0 - P2.7 COM0, COM1 COM2, COM3 SEG2 - SEG9 SEG10 - SEG17 VDD VSS
RESET
Pin Type I/O I/O O O O O O - - I - I
Share Pin CLO, BUZ, BUZ KS0, KS1 SEG17 - SEG10 - SEG0, SEG1 - P2.7 - P2.1 - - - - -
Circuit Type E-2 E-2 H-28 H-4 H-6 H-5 H-28 - - B - -
RESET Value
Input Input Low output Low output Low output Low output Low output - - - - -
XTIN, XTOUT TEST
1-6
S3C7281
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VLC0 VDD VLC1 Pull-Up Resistor COM In VLC2 Schmitt Trigger VSS Out
Figure 1-3. Pin Circuit Type B
Figure 1-5. Pin Circuit Type H-4
VDD VLC0 PNE VDD Pull-up Resistor VLC1 P-CH Data N-CH Output Disable VLC2 Pull-up Resistor Enable I/O
SEG
Out
VSS Schmitt Trigger
Figure 1-4. Pin Circuit Type E-2
Figure 1-6. Pin Circuit Type H-5
1-7
PRODUCT OVERVIEW
S3C7281
VLC0
VLC1
SEG/COM
Out
VLC2
VSS
Figure 1-7. Pin Circuit Type H-6
PNE
VDD
P-CH Data Output Disable N-CH
VLC0 Output VLC1
SEG
VLC2
VSS
Figure 1-8. Pin Circuit Type H-28
1-8
S3C7281
ELECTRICAL DATA
13
OVERVIEW
ELECTRICAL DATA
In this section, information on S3C7281 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- Power-On Reset Circuit characteristics -- Subsystem clock oscillator characteristics -- I/O capacitance -- A.C. electrical characteristics -- Operating voltage range Miscellaneous Timing Waveforms -- A.C timing measurement point -- Power-On Reset timing -- Clock timing measurement at XTIN -- TCL timing -- Input timing for RESET -- Input timing for external interrupts -- Serial data transfer timing Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request
13-1
ELECTRICAL DATA
S3C7281
Table 13-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD
VI VO
Conditions - Ports 0, 1 - One I/O pin active All I/O pins active
Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 30 + 30 (Peak value) + 15(note)
Units V V V mA
IOH IOL
Output Current Low
One I/O pin active
mA
Total for pins 0, 1, 2 Operating Temperature Storage Temperature TA TSTG - -
+ 100 (Peak value) + 60(note) - 40 to + 85 - 65 to + 150
Duty .
C C
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value x
Table 13-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 Input Low Voltage VIL1 VIL2 Output High Voltage Output Low Voltage VOH Conditions Ports 0, 1, and RESET XTIN Ports 0, 1, and RESET XTIN VDD = 4.5 V to 5.5 V IOH = - 1 mA Ports 0, 1, 2 VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 0, 1, 2 VDD = 1.8 V to 5.5 V IOL = 1.6 mA VDD - 1.0 - Min 0.8VDD VDD - 0.1 - - Typ - Max VDD VDD 0.2VDD 0.1 - V V Units V
VOL
-
-
2.0
V
0.4
13-2
S3C7281
ELECTRICAL DATA
Table 13-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Leakage Current Symbol ILIH1 Conditions VI = VDD All input pins except those specified below for ILIH2 VI = VDD XTIN VI = 0 V All input pins except RESET and XTIN VI = 0 V XTIN VO = VDD All output pins VO = 0 V All output pins VI = 0 V; VDD = 5V Ports 0, 1 VDD = 3V RL2 VI = 0 V; VDD = 5V; RESET VDD = 3V LCD Voltage Dividing Resistor VLC0-COMi Voltage Drop (i = 0-3) VLC0-SEGx Voltage Drop (x = 0-17) Middle Output Voltage (note) RLCD VDC VDS VLC0 VLC1 VLC2
NOTE: It is middle output voltage when 1/4 duty and 1/3 bias.
Min -
Typ -
Max 3
Units A
ILIH2 Input Low Leakage Current ILIL1
20 - - -3
ILIL2 Output High Leakage Current Output Low Leakage Current Pull-Up Resistor ILOH ILOL RL1
- 20 - - 25 - - 50 3 -3 75 k
50 100 250 120 - - VDD-0.2 2VDD/3-0.2 VDD/3-0.2
100 200 500 170 - - VDD 2VDD/3 VDD/3
150 300 750 220 120 120 VDD+0.2 2VDD/3+0.2 VDD/3+0.2 V mV
TA = + 25 C - 15 uA per common pin - 15 uA per common pin VDD = 1.8V to 5.5V, 1/3 bias LCD clock = 0Hz
13-3
ELECTRICAL DATA
S3C7281
Table 13-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Disable LVR (5) IDD2 (2) Symbol IDD1 (2) Conditions VDD = 5 V 10% Internal RC oscillator VDD = 3 V 10% Idle mode VDD = 5 V 10% Internal RC oscillator VDD = 3 V 10% IDD3 (3) IDD4 (3) IDD5 VDD = 3 V 10% 32 kHz crystal oscillator Idle mode; VDD = 3 V 10% 32 kHz crystal oscillator Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% VDD = 5 V 10% VDD = 3 V 10% SCMOD = 0000B XTIN = 0V SCMOD = 0000B 1.15 MHz 1 MHz 1.15 MHz Min - Typ 1.0 0.5 0.5 Max 2.5 1.2 1.0 Units mA
1 MHz -
0.15 12.0 5.0 2.5 0.5 0.2 0.1
0.4 24 15 5 3 3 2 A
NOTES: 1. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, output port drive currents. 2. Data includes power consumption for subsystem clock oscillation. 3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. 4. Every values in this table is measured when the power control register (PCON) is set to "0011B". 5. Current in the LVR circuit is not included.
13-4
S3C7281
ELECTRICAL DATA
Table 13-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 2.2 V to 5.5 V) Parameter Supply Current (1) Enable LVR (5) IDD2 (2) Symbol IDD1 (2) Conditions VDD = 5 V 10% Internal RC oscillator VDD = 3 V 10% Idle mode VDD = 5 V 10% Internal RC oscillator VDD = 3 V 10% IDD3 (3) IDD4 (3) IDD5 VDD = 3 V 10% 32 kHz crystal oscillator Idle mode; VDD = 3 V 10% 32 kHz crystal oscillator Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% VDD = 5 V 10% VDD = 3 V 10% SCMOD = 0000B XTIN = 0V SCMOD = 0000B 1.15 MHz 1 MHz 1.15 MHz Min - Typ 1.12 0.6 0.62 Max 2.7 1.35 1.2 Units mA
1 MHz -
0.25 112.0 105.0 122.5 100.5 120.2 100.1
0.55 174 165 205 153 203 152 A
NOTES: 1. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, output port drive currents. 2. Data includes power consumption for subsystem clock oscillation. 3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. 4. Every values in this table is measured when the power control register (PCON) is set to "0011B". 5. When LVR is enabled, the LVR circuit needs 100A or more current on the all below mode.
13-5
ELECTRICAL DATA
S3C7281
Table 13-3. Power-On Reset Circuit Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Power-On Reset Voltage High Power-On Reset Voltage Low Power Supply Voltage Rise Time Power Supply Voltage Off Time Power-On Reset Circuit Consumption Current (2) Symbol VDDH VDDL tR tOFF IDDPR Conditions - - - - VDD = 5 V 10% VDD = 3 V 10% Min 2.2 0 10 0.5 - - Typ - 1.8 - - 120 100 Max 5.5 2.0
(1)
Units V V S S A
- 200 150
NOTE: 1. 2**5/fx(= 8.19ms at fx = 1MHz) 2. Current consumed when power-on reset circuit is provided internally.
Table 13-4. Sub System Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator
XTIN XTOUT
Clock Configuration
Parameter Oscillation frequency(1) Stabilization time (2)
Test Condition - VDD = 2.7 V to 5.5 V
Min 32 -
Typ 32.768 1.0
Max 35 2
Units kHz s
C1
C2
VDD = 1.8 V to 5.5 V External Clock
XTIN XTOUT
- 32 5
- - -
10 100 15 kHz S
XTIN input frequency (1) XTIN input high and low level width (tXTL, tXTH)
- -
NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
13-6
S3C7281
ELECTRICAL DATA
Table 13-5. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF
Table 13-6. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time
(note)
Symbol tCY f INTH, f INTL tRSL
Conditions VDD = 1.8 V to 5.5 V With subsystem clock (fxt) KS0, KS1 Input
Min 4 114 10 10
Typ - 122 - -
Max 80 125 - -
Units S
Interrupt Input High, Low Width
RESET Input Low Width
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
13-7
ELECTRICAL DATA
S3C7281
CPU Clock 250 kHz
Main OSC Frequency (Internal RC) (Divided by 4) 1.0 MHz
15.6 kHz 12.5 kHz 1 2 1.8 V 3 4 5 5.5 V 6 7 50 kHz
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 13-1. Standard Operating Voltage Range
Table 13-7. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 1.8 V - Released by RESET Released by interrupt Min 1.8 - 0 - - Typ - 0.1 - 217 / fx
(2)
Max 5.5 10 - - -
Unit V A S ms
NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
13-8
S3C7281
ELECTRICAL DATA
TIMING WAVEFORMS
Internal RESET Operation Stop Mode Data Retention Mode Idle Mode Operating Mode
~ ~ ~ ~
VDD
VDDDR Execution of STOP Instruction
RESET
tWAIT tSREL
Figure 13-2. Stop Mode Release Timing When Initiated by RESET
Idle Mode
~ ~ ~ ~
Stop Mode Data Retention Mode
Normal Operating Mode
VDD
VDDDR Execution of STOP Instruction
tSREL
tWAIT Power-down Mode Terminating Signal (Interrupt Request)
Figure 13-3. Stop Mode Release Timing When Initiated by Interrupt Request
0.8 VDD Measurement Points 0.2 VDD
0.8 VDD
0.2 VDD
Figure 13-4. A.C. Timing Measurement Points (Except for XTIN)
13-9
ELECTRICAL DATA
S3C7281
1/fxt tXTL tXTH
XTIN
VDD - 0.1 V 0.1 V
Figure 13-5. Clock Timing Measurement at XTIN
tRSL
RESET
0.2 VDD
Figure 13-6. Input Timing for RESET Signal
13-10
S3C7281
ELECTRICAL DATA
tINTL
tINTH
KS0, KS1
0.8 VDD 0.2 VDD
Figure 13-7. Input Timing for External Quais-Interrupts
tOFF
tOFF
VDD
VDDH VDD
Figure 13-8. Power-On Reset timing
13-11
S3C7281
MECHANICAL DATA
14
OVERVIEW
-- Pad diagram
MECHANICAL DATA
This section contains the following information about the device package: -- Package dimensions in millimeters
14-1
MECHANICAL DATA
S3C7281
0-8 #32 #17
12.00 0.30
0.20
32-SOP-450A
8.34
0.25
0.10
20.30 MAX 19.90 0.20
2.20 MAX
2.00
0.10 MAX
(0.43)
0.40 0.10
1.27
NOTE:
Dimensions are in millimeters.
Figure 14-1. 32-SOP Package Dimensions
14-2
0.05 MIN
0.90
0.20
#1
#16
+ 0.10 - 0.05
11.43</sub>