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| APPROVED PRODUCT C9531 PCIX I/O System Clock Generator With EMI Control Features Product Features * * * * * * * * * * * * Dedicated clock buffer power pins for reduced noise, crosstalk and jitter Buffer XIN Reference clock output Input clock frequency 33.3 MHz Output frequencies of 33.3, 66.6, 100 and 133.3 MHz selectable (PCIX requirements) One output bank of 5 clocks. SMBus clock control interface for individual clock disabling and SSCG control Output clock duty cycle is 50% ( 5%) <250 pS skew between output clocks within a bank Output jitter <175 pSec. Spread Spectrum feature for reduced EMI OE pins for entire output bank enable control and testability 28 Pin SSOP and TSSOP package Test Mode Logic Table INPUT PINS OE HIGH HIGH HIGH HIGH LOW S1 LOW LOW HIGH HIGH X S0 LOW HIGH LOW HIGH X OUTPUT PINS CLK(0:4) XIN 2 * XIN 3 * XIN 4 * XIN Tri-State REF XIN XIN XIN XIN Tri-State Note: XIN is the frequency of the clock on the device's XIN pin. Block Diagram Pin Configuration SSCG# SSCG Logic /N 1 0 CLK0 CLK1 CLK2 CLK3 CLK4 OE GOOD# REF REF VDD XIN XOUT VSS S0 S1 GOOD# VSS IA0 IA1 IA2 1 2 3 4 5 7 8 9 10 11 12 13 14 6 28 27 26 25 24 SDATA SCLK VSS VDDP CLK0 CLK1 CLK2 VSS VDDP CLK3 CLK4 AVDD VSS SSCG# C9531 XIN XOUT 23 22 21 20 19 18 17 16 15 SDATA SCLK IA(0:2) S(0,1) I 2C Control Logic AVDD OE Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07034 Rev. ** 05/02/2001 Page 1 of 14 APPROVED PRODUCT C9531 PCIX I/O System Clock Generator With EMI Control Features Pin Description Pin No. 3 4 1 14* 24, 23, 22, 19, 18 8 Pin Name XIN XOUT REF OE CLK(0:4) GOOD# PWR VDDA VDDA VDD VDD VDDP VDD I/O I O O I O O Description Crystal Buffer input pin. Connects to a crystal, or an external clock source. Serves as input clock TCLK, in Test mode. Crystal Buffer output pin. Connects to a crystal only. When a Can Oscillator is used or in Test mode, this pin is kept unconnected. Buffered inverted outputs of the signal applied at Xin, typically 33.33 MHz Output Enable for clock bank. Causes the CLK (0:4) output clocks to be in a Tri-state condition when driven to a logic low level. A bank of Five 33.3, 66.6, 100.0 or 133.3 MHz output clocks (1x, 2x, 3x or 4x Xin clock). When his output signal is a logic low level, it indicates that the output clocks of the bank are locked to the input reference clock. This output is latched. Clock Bank selection bits. These control the clock frequency that will be present on the outputs of the bank of buffers. See table on page one for frequency codes and selection values. 3.3V common power supply pin for all PCI clocks CLK (0:4). SMBus address selection input pins. See SMBus Address table, pg. 4. Enables Spread Spectrum clock modulation when at a logic low level, see pg. 3. Data for the internal SMBus circuitry, see pg. 4. Clock for the internal SMBus circuitry, see pg. 4. Power for internal analog circuitry. This supply should have a separately decoupled current source from VDD. Power supply for internal Core logic Ground pins for the device 6*, 7* S(0,1) VDD I 20, 25 10*, 11*, 12* 15* 28 27 13, 17 2 5, 9, 16, 21, 26 VDDP IA(0:2) SSCG# SDATA SCLK AVDD VDD VSS VDD VDD VDD VDD - PWR I I I/O I I PWR PWR Note: Pin numbers ending with a * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is connected to them. A bypass capacitor (0.1 F) should be placed as close as possible to each VDD pin. If these bypass capacitors are not close to the pins, their high frequency filtering characteristic will be cancelled by the lead inductance of the trace. PWR = Power connection, I = Input, O = Output and I/O = both input and output functionality of the pin(s). Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07034 Rev. ** 05/02/2001 Page 2 of 14 APPROVED PRODUCT C9531 PCIX I/O System Clock Generator With EMI Control Features Spectrum Spread Clocking Down Spread Description Spread Spectrum is a modulation technique for distributing clock period over a certain bandwidth (called Spread Bandwidth). This technique allows the distribution of the undesirable electromagnetic energy (EMI) over a wide range of frequencies therefore reducing the average radiated energy present at any frequency over a given time period. As the spread is specified as a percentage of the resting (non-spread) frequency value, it is effective at the fundamental and, to a greater extent, at all of its harmonics. In this device Spread Spectrum is enabled externally through pin 15 (SSCG#) or internally via SMBus Byte 0 Bit 0 and 6. Spread spectrum is enabled externally when the SSCG# pin is low. This pin has an internal device pull up resistor, which causes its state to default to a HIGH (spread spectrum modulation disabled) unless externally forced to a low. It may also be enabled by programming SMBus Byte 0 Bit 0 LOW (to enable SMBus control of the function) and then programming SMBus byte 0 bit 6 low to set the feature active. Spread off Spread on Center Frequency, Spread on Center Frequency, Spread off Spectrum Spreading Selection Table Output clock Frequency 33.3 MHz (XIN) 66.6 MHz (XIN*2) 100.0 MHz (XIN*3) % OF FREQUENCY SPREADING SMBus Byte 0 Bit 5 =0 1.0% (-1.0% + 0%) 1.0% (-1.0% + 0%) 1.0% (-1.0% + 0%) SMBus Byte 0 Bit 5 =1 0.5% (-0.5% + 0%) 0.5% (-0.5% + 0%) 0.5% (-0.5% + 0%) MODE Down Spread Down Spread Down Spread 133.3 MHz (XIN*4) 1.0% (-1.0% + 0%) 0.5% (-0.5% + 0%) Down Spread When SSCG is enabled, the device will down spread the clock over a range that is 1% of its resting frequency. This means that for a 100 MHz output clock the frequency will sweep through a spectral range from 99 to 100 MHz. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07034 Rev. ** 05/02/2001 Page 3 of 14 APPROVED PRODUCT C9531 PCIX I/O System Clock Generator With EMI Control Features 2-Wire SMBus Control Interface The 2-wire control interface implements a write slave only interface according to SMBus specification. The device can be read back. Sub addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported. Through the use of the IA0, IA1, and IA2 pins the SMBus address of the device may be changed so that multiple devices may reside on a single SMBus control signaling bus and not interfere with each other. SMBus Address Selection Table SMBus address of the device DE DC DA D8 D6 D4 D0 D2 IA0 BIT (Pin 10) 0 1 0 1 0 1 0 1 IA1 BIT (Pin 11) 0 0 1 1 0 0 1 1 IA2 BIT (Pin 12) 0 0 0 0 1 1 1 1 During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer cycle is a 7-bit address with a Read/Write bit (R/W#) as the LSB. R/W# = 1 in read mode. The device will respond to writes to 10 bytes (max) of data to its selected address by generating the acknowledge (low) signal on the SDATA wire following reception of each byte. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07034 Rev. ** 05/02/2001 Page 4 of 14 APPROVED PRODUCT C9531 ACK ACK BYTE 0 (Valid) BYTE N (Valid) ACK PCIX I/O System Clock Generator With EMI Control Features Transmit Receive SDATA MSB LSB ACK ACK BYTE COUNT (Don't Care) 1 1 0 1 0 0 1 0 COMMAND BYTE (Don't Care) SCLK START CONDITION 8 8 8 8 STOP CONDITION Fig.5a (WRITE) Transmit ACK BYTE COUNT ACK (Valid) (Valid) BYTE 0 ACK (Valid) BYTE1 ACK BYTE N ACK (Valid) Receiv SDATA 1 1 0 1 0 0 1 1 MSB LSB SCLK START CONDITION 8 8 8 8 STOP CONDITION Fig.5b (READ) Fig.5 Serial Control Registers NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true power up. Bytes are set to the values shown only after true power up event occurs. Following the acknowledge of the Address Byte (D2), two additional bytes must be sent: 1) "Command Code " byte, and 2) "Byte Count" byte. Although the data (bits) in these two bytes are considered "don't care"; they must be sent and will be acknowledged. Byte 0: Function Select Register Bit 7 6 5 4 3 2 1 0 @Pup 1 0 1 0 0 0 0 1 Pin# 15 7 6 Description Test Mode Enable. 1=normal operation, 0 = Test mode Spread Spectrum modulation control bit (effective only when Bit 0 of this register is set to a 0) 0=OFF, 1=ON SSCG Spread width select. 1 = 0.5%, 0 = 1.0% See Table below for clarification S1 Bank A MSB frequency control bit (effective only when Bit 0 of this register is set to a 0) S0 Bank A LSB frequency control bit (effective only when Bit 0 of this register is set to a 0) Not used Not used Hardware/SMBus frequency control. 1=Hardware (pins 6, 7, and 15), 0=SMBus Byte 0 bits 3, 4, and 6 Clarification Table for Byte0, bit5 Byte 0, bit6 0 0 1 1 Byte0, bit5 0 1 0 1 Description Frequency generated from second PLL Frequency generated from XIN Spread @ -1.0% Spread @ -0.5% Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07034 Rev. ** 05/02/2001 Page 5 of 14 APPROVED PRODUCT C9531 PCIX I/O System Clock Generator With EMI Control Features Test Table These output frequencies will be present when SMBus byte 0 bit 7 has been set to a logic 0 state. Test Function Clock Frequency Outputs CLK(0:4) XIN/4 REF XIN Table 3 Note: 1. XIN is the frequency of the clock that is present on the XIN input during test mode. Byte 1: CPU Register (1 = Enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 1 Description Reserved Reserved REF Enable/Stopped Reserved Reserved Reserved Reserved Reserved Byte 2: PCI Register (1 = Enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 18 19 22 23 24 Description Reserved Reserved Reserved CLK4 Enable/Disable CLK3 Enable/Disable CLK2 Enable/Disable CLK1 Enable/Disable CLK0 Enable/Disable Note: Stopping a clock indicated that the clock output is fixed in a logic low state. This effect will occur within 2 clock cycles from the time the bit is set and does so in a manner so as not to cause any short or runt clock cycles. When the stop is bit is changed from a stopped state to a running state the same (maximum 2 click latency) delay occurs with the first cycle being full in period (for the frequency that is selected). Internal Crystal Oscillator This device will operate in two input reference clock configurations. In its simplest mode a 33.33 MHz fundamental cut parallel resonant crystal is attached to the XIN and XOUT pins. In the second mode a 33.33MHz input reference clock is driven in on the XIN clock from an external source. In this application the XOUT pin is left disconnected. Output Clock Tri-state Control All of the clocks in the Bank may be placed in a tri-state condition by bringing their relevant OE pins to a logic low state. This transition to and from a tristate and active condition is a totally asynchronous event and clock glitching may occur during the transitioning states. This function is intended as a board level testing feature. When output clocks are being enabled and disabled in active environments the SMBus control register bits are the preferred mechanism to control these signals in an orderly and predictable manner. Both output enable pins contain internal pull-up resistors that will insure that a logic 1 (high) is maintained and sensed by the device if no external circuitry is connected to these pins. Output Clock Frequency Control All of the output clocks have their frequency selected by the logic state of the S0 and S1 control bits. The source of these control signals is determined by the SMBus register Byte 0 Bit 0. At initial power up this bit is set of a logic 1 state and Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07034 Rev. ** 05/02/2001 Page 6 of 14 APPROVED PRODUCT C9531 PCIX I/O System Clock Generator With EMI Control Features Output Clock Frequency Control (Cont.) thus the frequency selections are controlled by the logic levels present on the device's S(0,1) pins. If the application does not use an SMBus interface then hardware frequency selection S(0,1) must be used. If it is desired to control the output clocks using an SMBus interface, then this bit (Byte 0 Bit 0) must first be set to a low state. After this is done the device will use the contents of the internal SMBus register Bytes 0 Bits 3 and 4 to control the output clock's frequency. Absolute Maximum Ratings Maximum Power Supply: Storage Temperature: Operating Temperature: Maximum ESD protection 5.5 -65C to + 150C 0C to +70C 2000V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout) Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07034 Rev. ** 05/02/2001 Page 7 of 14 APPROVED PRODUCT C9531 Conditions note 1 note 2 For internal Pull up resistors, note 1 and note 3 PCIX I/O System Clock Generator With EMI Control Features DC Parameters Characteristic Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Current (@VIL = VSS) Input High Current (@VIL = VDD) Tri-State leakage Current Dynamic Supply Current Unloaded Supply Current Input pin capacitance Pin inductance Crystal pin capacitance Crystal DC Bias Voltage Crystal Startup time Note1: Note2: Note3: Note4: Note5: Symbol VIL1 VIH1 VIL2 VIH2 IIL IIH Ioz Idd3.3V Isdd Cin Lpin Cxtal VBIAS Txs 32 0.3Vdd 34 Vdd/2 Min 2.0 2.2 -66 Typ Max 1.0 1.0 -5 5 10 160 30 5 7 38 0.7Vdd 40 Units Vdc Vdc Vdc Vdc A A A mA mA pF nH pF V S From Stable 3.3V power supply. from XIN and XOUT Pins to Ground. note 5 note 4 Device running, OE at a logic low level (outputs disabled). VDD = AVDD = VDDP = 3.3V 5%, TA = 0C to +70C Applicable to input signals: S0, S1, OE and SSCG# Applicable to Sdata, and Sclk. Although internal pull-up resistors have a typical value of 250K, this value may vary between 200K and 500K. All outputs load in accordance with table 1. Although the device will reliably interface with crystals of a 17pF - 20pF CL range, it is optimized to interface with a typical CL = 18pF crystal specifications. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07034 Rev. ** 05/02/2001 Page 8 of 14 APPROVED PRODUCT C9531 PCIX I/O System Clock Generator With EMI Control Features AC Parameters Output Frequency Symbol Parameter 133 MHz Min 7.0 3 3 0.50 1.0 Max 8.0 1.33 250 175 4.0 100 MHz Min 9.5 4 4 0.50 1.0 Max 10.5 1.33 250 175 4.0 750 10.0 10.0 3 10.0 10.0 3 10.0 10.0 3 10.0 10.0 3 66 MHz Min 14.5 6 6 0.50 1.0 Max 15.5 1.33 250 175 4.0 33 MHz Min 29.5 11 11 0.50 1.0 Max 30.5 1.33 250 175 4.0 Units Notes Tcyc THIGH TLOW Tr / Tf TSKEW TCCJ Tr / Tf TCCJ tpZL, tpZH tpLZ, tpHZ tstable Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: CLK(0:4) period CLK(0:4) period CLK(0:4) low time CLK(0:4) rise and fall times (Any CLK ) to (Any CLK) Skew time CLK(0:4) Cycle to Cycle Jitter REFOUT rise and fall times REFOUT Cycle to Cycle Jitter OE to clock enable delay (all outputs) OE to clock disable delay (all outputs) All clock Stabilization from power-up ns ns ns ns ps ps ns pS ns ns ms 1, 2, 4 2,6 2, 7 2, 3 2, 4, 5.9 2, 4, 5 2, 3 2, 4 8 This parameter is measured as an average over 1uS duration, with an input frequency of 33.333 MHz All outputs loaded as per table 1 below. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V (see Fig.6A and Fig.6B) Probes are placed on the pins, and measurements are acquired at 1.5V. (See Figs.6A & 6B) This measurement is applicable with Spread ON or OFF. Probes are placed on the pins, and measurements are acquired at 2.4Vs, (see Figs. 6A & 6B) Probes are placed on the pins, and measurements are acquired at 0.4V. The time specified is measured from when all VDD's reach their respective supply rail (3.3V) till the frequency output is stable and operating within the specifications Applicable only to clocks within the same bank Output Name CLK(0:4) REF Table 1 Max Load (in pF) 30 20 Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07034 Rev. ** 05/02/2001 Page 9 of 14 APPROVED PRODUCT C9531 3 . 3 V S ig n a ls tD C PCIX I/O System Clock Generator With EMI Control Features Test and Measurement Setup - Output under Test Probe 2 .4 V 3 .3 V Load Cap 1 .5 V 0 .4 V 0V Tr Tf Fig. 6A Fig. 6B Output Buffer Characteristics Buffer Characteristics for CLK(0:4), and REF Characteristic Symbol Min Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current IOH1 IOH2 IOL1 IOL2 -33 -11 9.4 22 Typ Max Units mA mA mA mA Conditions VDD-0.5 1.2V 0.4V 1.2V VDD = AVDD = VDDP = 3.3V 5%, TA = 0C to +70C Suggested Oscillator Crystal Parameters Characteristic Frequency Tolerance Symbol Fo TC TS TA Operating Mode Load Capacitance CXTAL Min 33.00 Typ 33.33 20 Max 33.5 +/-100 +/- 100 5 pF Units MHz PPM PPM PPM Note 1 Stability (TA -10 to +60C) Note 1 Aging (first year @ 25C) Note 1 Parallel Resonant, Note 1 The crystal's rated load. Note 1 Conditions Effective Series RESR 40 Ohms Note 2 Resistance (ESR) Note1: For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meets or exceeds these specifications Note 2: Larger values may cause this device to exhibit oscillator startup problems To obtain the maximum accuracy, the total circuit loading capacitance should be equal to CXTAL. This loading capacitance is the effective capacitance across the crystal pins and includes the clock generating device pin capacitance (CFTG), any circuit traces (CPCB), and any onboard discrete load capacitors (CDISC). Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07034 Rev. ** 05/02/2001 Page 10 of 14 APPROVED PRODUCT C9531 PCIX I/O System Clock Generator With EMI Control Features Suggested Oscillator Crystal Parameters (Cont.) The following formula and schematic may be used to understand and calculate either the loading specification of a crystal for a design or the additional discrete load capacitance that must be used to provide the correct load to a known load rated crystal. CL = (CXINPCB + CXINFTG + CXINDISC) X (CXOUTPCB + CXOUTFTG + CXOUTDISC) (CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB + CXOUTFTG + COUTDISC) Where: CXTAL CXOUTFTG CXOUTFTG CXINPCB CXOUTPCB CXINDISC CXOUTDISC = = = = = = = the load rating of the crystal the clock generators XIN pin effective device internal capacitance to ground the clock generators XOUT pin effective device internal capacitance to ground the effective capacitance to ground of the crystal to device PCB trace the effective capacitance to ground of the crystal to device PCB trace any discrete capacitance that is placed between the XIN pin and ground any discrete capacitance that is placed between the XOUT pin and ground XIN CXINFTG CXOUTFTG CXINPCB CXOUTPCB CXINDISC CXOUTDISC XOUT Clock Generator As an example, and using this formula for this datasheet's device, a design that has no discrete loading capacitors (CDISC) and each of the crystal to device PCB traces has a capacitance (CPCB) to ground of 4pF (typical value) would calculate as: CL = (4pF + 36pF + 0pF) X (4pF + 36pF + 0pF) (4pF + 36pF + 0pF) + (4pF + 36pF + 0pF) = 40 X 40 40 + 40 = 1600 80 = 20pF Therefore to obtain output frequencies that are as close to this data sheets specified values as possible, in this design example, you should specify a parallel cut crystal that is designed to work into a load of 20pF. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07034 Rev. ** 05/02/2001 Page 11 of 14 APPROVED PRODUCT C9531 PCIX I/O System Clock Generator With EMI Control Features Package Drawing and Dimensions 28 Pin TSSOP Outline Dimensions INCHES SYMBOL A A1 A2 B C D C L E H E e H L a 0.244 0.018 0 MIN 0.002 0.031 0.007 0.004 0.378 0.169 NOM 0.039 0.382 0.173 0.026 BSC 0.252 0.024 0.260 0.030 8 6.20 0.45 0 MAX 0.047 0.006 0.041 0.012 0.008 0.386 0.177 MIN 0.05 0.80 0.19 0.09 9.60 4.30 MILLIMETERS NOM 1.00 9.70 4.40 0.65 BSC 6.40 0.60 6.60 0.75 8 MAX 1.20 0.15 1.05 0.30 0.20 9.80 4.50 D A2 A1 B e A a 28 Pin SSOP Outline Dimensions INCHES SYMBOL A A1 A2 B C D E e H L a 0.291 0.022 0 MIN 0.002 0.065 0.009 0.004 0.390 0.197 NOM 0.069 0.402 0.209 0.026 BSC 0.307 0.030 0.323 0.037 8 7.40 0.55 0 MAX 0.079 0.006 0.073 0.015 0.010 0.413 0.220 MIN 0.05 1.65 0.22 0.09 9.90 5.00 MILLIMETERS NOM 1.75 10.20 5.30 0.65 BSC 7.80 0.75 8.20 0.95 8 MAX 2.0 0.15 1.85 0.38 0.25 10.50 5.60 Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07034 Rev. ** 05/02/2001 Page 12 of 14 APPROVED PRODUCT C9531 PCIX I/O System Clock Generator With EMI Control Features Ordering Information Part Number C9531CY C9531CT Package Type 28 Pin SSOP 28 Pin TSSOP Production Flow Commercial, 0C to +70C Commercial, 0C to +70C Note: The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Cypress C9531 Date Code, Lot # Marking: Example: C9531CT Package Y = SSOP T = TSSOP Revision Device Number Notice Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design, performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. Products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of its products in the life supporting and medical applications. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07034 Rev. ** 05/02/2001 Page 13 of 14 APPROVED PRODUCT C9531 PCIX I/O System Clock Generator With EMI Control Features Document Title: C9531 PCIX I/O System Clock Generator with EMI Control Features Document Number: 38-07034 Rev. ECN No. ** 106962 Issue Date 06/12/01 Orig. of Change IKA Description of Change Convert from IMI to Cypress Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07034 Rev. ** 05/02/2001 Page 14 of 14 |
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