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| CY25701 Programmable High-Frequency Crystal Oscillator with Spread Spectrum (SSXO) Features * Crystal Oscillator with Spread Spectrum Clock (SSC) * Wide operating output (SSCLK) frequency range * 10-166 MHz * Programmable spread spectrum with nominal 31.5 kHz modulation frequency * Center spread: 0.25% to 2.0% * Down spread: -0.5% to -4.0% * Integrated phase-locked loop (PLL) * Low cycle-to-cycle Jitter * 3.3V operation * Output Enable function * Package available in 4-Lead Plastic JE SMD Benefits * Provides wide range of spread percentages for maximum electromagnetic interference (EMI) reduction, to meet regulatory agency electromagnetic compliance (EMC) requirements. Reduces development and manufacturing costs and time-to-market. * Eliminates the need for external crystal oscillator. * Internal PLL to generate up to 166 MHz output. * Suitable for most PC, consumer, and networking applications. * Application compatibility in standard and low-power systems. * In-house programming of samples and prototype quantities is available using the CY3672 programming kit and CY3613 socket adapter. Production quantities are available through Cypress's value-added distribution partners or by using third-party programmers from BP Microsystems, HiLo Systems, and others. Logic Block Diagram Pin Configuration CY25701 4-pin Plastic SMD PLL with MODULATION CONTROL RFB 1 2 OE VSS VDD 4 SSCLK 3 CXIN PROGRAMMABLE CONFIGURATION CXOUT OUTPUT DIVIDERS and MUX 3 SSCLK 1 OE 4 VDD 2 VSS Cypress Semiconductor Corporation Document #: 38-07684 Rev. *B * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised October 15, 2004 CY25701 Pin Definition Pin 1 2 3 4 OE VSS SSCLK VDD Name Power supply ground. Spread spectrum clock output. 3.3V power supply. The CY25701 uses a programmable configuration memory array to synthesize output frequency and spread%. The spread% is programmed to either center spread or down spread with various spread percentages. The range for center spread is from 0.25% to 2.00%. The range for down spread is from -0.5% to -4.0%. Contact the factory for smaller or larger spread% amounts if required. Refer to Table 2 for spread selection values. The frequency modulated SSCLK output can be programmed from 10-166 MHz. The CY25701 is available in a 4-pin plastic SMD package with operating temperature range of -20 to 70C. Description Output Enable pin: Active HIGH. If OE = 1, SSCLK is enabled. Functional Description The CY25701 is a Spread Spectrum Crystal Oscillator (SSXO) IC used for the purpose of reducing EMI found in today's high-speed digital electronic systems. The device uses a Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the embedded input crystal. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies are greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency (EMC) requirements and improve time-to-market without degrading system performance. Table 1. Programming Data Requirement Pin Function Pin Name Pin# Units Program Value Output Frequency SSCLK 3 MHz ENTER DATA Spread Percent Code SSCLK 3 % ENTER DATA Frequency Modulation SSCLK 3 kHz 31.5 Table 2. Spread Percent Selection Center Spread Down Spread Code Percentage Code Percentage A 0.25% G -0.5% B 0.5% H -1.0% C 0.75% J -1.5% D 1.0% K -2.0% E 1.5% L -3.0% F 2.0% M -4.0% Programming Description Field/Factory-Programmable CY25701 Field/Factory programming is available for samples and manufacturing by Cypress and its distributors. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. Once the request has been processed, you will receive a new part number, samples, and data sheet with the programmed values. This part number will be used for additional sample requests and production orders. Additional information on the CY25701 can be obtained from the Cypress web site at www.cypress.com. Output Frequency, SSCLK Output (SSCLK, pin 3) The modulated frequency at the SSCLK output is produced by synthesizing the embedded crystal oscillator frequency input. The range of synthesized clock is from 10-166 MHz. Spread Percentage (SSCLK, pin 3) The SSCLK spread can be programmed to various spread percentage values from 0.25% to 2.0% for Center Spread and from -0.5% to -4.0% for Down Spread. Refer to Table 2 for available spread options Frequency Modulation (SSCLK, pin 3) The frequency modulation is programmed at 31.5 kHz for all SSCLK frequencies from 10 to 166 MHz. Contact the factory if a higher-modulation frequency is required. Document #: 38-07684 Rev. *B Page 2 of 7 CY25701 Absolute Maximum Rating Supply Voltage (VDD) .................................... -0.5V to +7.0V DC Input Voltage....................................-0.5V to VDD + 0.5V Storage Temperature (Non-condensing) .... -55C to +100C Junction Temperature ................................ -40C to +125C Data Retention @ Tj = 125C................................> 10 years Package Power Dissipation...................................... 350 mW Min. 3.00 -20 - 10 30.0 0.05 Typ. 3.30 - - - 31.5 - Max. 3.60 70 15 166 33.0 500 Unit V C pF MHz kHz ms Operating Conditions Parameter VDD TA CLOAD FSSCLK FMOD TPU Supply Voltage Ambient Temperature Max. Load Capacitance @ pin 3 SSCLK output frequency, CLOAD = 15 pF Spread Spectrum Modulation Frequency Power-up time for VDD to reach minimum specified voltage (power ramp must be monotonic) Description DC Electrical Characteristics Parameter IOH IOL VIH VIL IIH IIL IOZ CIN [1] Description Output High Current (pin 3) Output Low Current (pin 3) Input High Voltage (pin 1) Input Low Voltage (pin 1) Input High Current (pin 1) Input Low Current (pin 1) Input Capacitance (pin 1) Supply Current Condition VOH = VDD - 0.5, VDD = 3.3V (source) VOL = 0.5, VDD= 3.3V (sink) CMOS levels, 70% of VDD CMOS levels, 30% of VDD Vin = VDD Vin = VSS Pin 1, or OE VDD = 3.3V, SSCLK = 10 to 166 MHz, CLOAD = 0, OE = VDD Min. 10 10 0.7VDD - - - -10 - - Typ. 12 12 - - - - - 5 - Max. - - VDD 0.3VDD 10 10 10 7 30 Unit mA mA V V A A A pF mA Output Leakage Current (pin 3) Three-state output, OE = 0 IVDD AC Electrical Characteristics[1] Parameter DC tR tF TCCJ1[2] Description Output Duty Cycle Output Rise Time Output Fall Time Cycle-to-Cycle Jitter SSCLK (Pin 3) Output Disable Time (pin1 = OE) Output Enable Time (pin1 = OE) PLL Lock Time Aging in Frequency Condition SSCLK, Measured at VDD/2 20%-80% of VDD, CL = 15pF 20%-80% of VDD, CL = 15pF SSCLK 133 MHz, Measured at VDD/2 25 MHz SSCLK <133 MHz, Measured at VDD/2 SSCLK < 25 MHz, Measured at VDD/2 TOE1 TOE2 TLOCK f Time from falling edge on OE to stopped outputs (Asynchronous) Time from rising edge on OE to outputs at a valid frequency (Asynchronous) Time for SSCLK to reach valid frequency TA = 25C, First year Min. 45 - - - - - - - - -5 Typ. 50 - - - - - 150 150 - - Max. 55 2.7 2.7 200 400 1% of 1/SSCK 350 350 10 5 Unit % ns ns ps ps s ns ns ms ppm Notes: 1. Guaranteed by characterization, not 100% tested. 2. Jitter is configuration dependent. Actual jitter is dependent on output frequencies, spread percentage, temperature, and output load. For more information, refer to the application note, "Jitter in PLL Based Systems: Causes, Effects, and Solutions" available at http://www.cypress.com/clock/appnotes.html, or contact your local Cypress Field Application Engineer. Document #: 38-07684 Rev. *B Page 3 of 7 CY25701 Application Circuit Power VDD 1 OE VDD 4 0.1uF CY25701 2 VSS SSCLK 3 Switching Waveforms Duty Cycle Timing (DC = t1A/t1B) SSCLK t1A t1B Output Rise/Fall Time SSCLK Tr Tf Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3) Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4) Refer to AC Electrical Characteristics table for SR (Slew Rate) values. VDD 0V Output Enable/Disable Timing OUTPUT ENABLE VDD 0V VIL VIH TOE2 (Asynchronous) SSCLK TOE1 High Impedance Document #: 38-07684 Rev. *B Page 4 of 7 CY25701 Informational Graphs [3] 172.5 171.5 170.5 169.5 168.5 167.5 166.5 165.5 164.5 163.5 162.5 161.5 160.5 159.5 0 20 40 60 80 100 120 Time (us) 140 160 180 200 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= -4% Fnominal 169.5 169 168.5 168 167.5 167 166.5 166 165.5 165 164.5 164 163.5 163 162.5 0 20 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= +/-1% Fnominal 40 60 80 100 120 Time (us) 140 160 180 200 68.5 68 67.5 67 66.5 66 65.5 65 64.5 64 63.5 0 20 Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= -4% 67.5 67 66.5 Fnominal Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= +/-1% 66 65.5 65 64.5 Fnominal 40 60 80 100 120 Time (us) 140 160 180 200 0 20 40 60 80 100 120 Time (us) 140 160 180 200 Ordering Information Part Number[4,5] CY25701JXCZZZZ CY25701JXCZZZZT CY25701FJXC CY25701FJXCT Package description 4-Lead Plastic JE SMD - Lead-free 4-Lead Plastic JE SMD, Tape and Reel - Lead-free 4-Lead Plastic JE SMD - Lead-free 4-Lead Plastic JE SMD, Tape and Reel - Lead-free Product Flow Commercial, -20 to 70C Commercial, -20 to 70C Commercial, -20 to 70C Commercial, -20 to 70C Notes: 3. The "Informational Graphs" are meant to convey the typical performance levels. No performance specifications is implied or guaranteed. Refer to the tables on pages 4 and 5 for device specifications. 4. "ZZZZ" denotes the assigned product dash number. This number will be assigned by factory after the output frequency and spread percent programming data is received from the customer. 5. "FJXC" suffix is used for products programmed in field by Cypress distributors. Document #: 38-07684 Rev. *B Page 5 of 7 CY25701 Package Drawing and Dimension 4-Lead JE04A 10.20.3 (10.5 MAX) 4 1.00.2 (1.0) 5.0 5.60.2 (5.8 MAX) 3.6 1.00.2 (1.0) 1 1.3 2.1 2.4 2.5 (2.7 MAX) +0.2 -0.1 4.6 0.1 0.51 0.150.1 (0.05 MIN) 5.080.1 DIMENSIONS IN MILLIMETERS REFERENCE JEDEC: N/A PKG. WEIGHT: 0.24 gms 5.08 RECOMMENDED SOLDERING PATTERN 51-85204-** All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07684 Rev. *B Page 6 of 7 (c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY25701 Document History Page Document Title: CY25701 Programmable High-Frequency Crystal Oscillator with Spread Spectrum (SSXO) Document Number: 38-07684 REV. ** *A *B ECN NO. 224108 258974 279379 Issue Date See ECN See ECN See ECN Orig. of Change RGL RGL RGL New data sheet Corrected the product suffix (lead-free) in the ordering information table Added note 4 Added ordering part numbers Description of Change Document #: 38-07684 Rev. *B Page 7 of 7 |
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