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ILX508A
7926-pixel CCD Linear Image Sensor (B/W)
Description The ILX508A is a reduction type CCD linear sensor developed for high resolution copiers. This sensor reads A3-size documents at a density of 600 DPI (Dot Per Inch). A built-in timing generator and clock-drivers ensure direct drive at 5V logic for easy use. In addition reset pulse can switch between internal generation and external input. Features * Number of effective pixels: 7926 pixels * Pixel size: 7m x 7m (7m pitch) * Built-in timing generator and clock-drivers * Ultra high sensitivity * Ultra low lag/low dark voltage * Output method * Maximum operating frequency: 12.5MHz Absolute Maximum Ratings * Supply voltage VDD1 VDD2 * Operation temperature * Storage temperature Pin Configuration (Top View) 24 pin DIP (Ceramic)
11 6 -10 to +60 -30 to +80
VGG GND VDD1 VOUT GND ROG VDD2 VDD2 RSSW 1 2 3 4 5 6 7 8 9
V V C C
1 24 CLK 23 VDD1 22 RS/SH 21 VDD1 20 VDD1 19 GND 18 VDD2 17 GND 16 T4 15 T3 7926 14 T2 13 NC
T1 10 GND 11 NC 12
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E96X33-PS
Block Diagram
VDD1 23 21 20 17 16 15 14 19 18 13
VDD1
VDD1
GND
VDD2
GND
T4
T3
T2
NC
Clock-drivers
CCD analog shift register Read out gate
S1 S2
D18
D115 D99
S7925
* Output amplifier * Sample-and-hold circuit * Feed through suppression circuit
S7926
D116
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Read out gate CCD analog shift register Clock-drivers Clock-pulse generator Sample-and-hold pulse generator 5 7 VDD2 VDD2 8 GND 24 CLK 9 RSSW 22 RS/SH
4
D17
D98
VOUT
12
NC
VGG
1
Mode selector
Read out gate pulse generator
2
3
10 T1
11 GND
6 ROG
GND
VDD1
ILX508A
ILX508A
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol VGG GND VDD1 VOUT GND ROG VDD2 VDD2 RSSW T1 GND NC NC T2 T3 T4 GND VDD2 GND VDD1 VDD1 RS/SH VDD1 CLK Description Output circuit gate bias GND 9V power supply Signal output GND Clock pulse 5V power supply 5V power supply RS pulse external, internal selection (External RS VDD1, Internal RS GND) Test pin (5V) GND NC NC Test pin (GND) Test pin (5V) Test pin (GND) GND 5V power supply GND 9V power supply 9V power supply Clock pulse or S/H switch 9V power supply Clock pulse
Output mode is changeable as follows. 22pin 9pin GND VDD1 GND Internal RS without S/H -- VDD1 Internal RS with S/H -- RS -- External RS without S/H
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ILX508A
Recommended Voltage Item VDD1 VDD2 Min. 8.5 4.75 Typ. 9.0 5.0 Max. 9.5 5.25 Unit V V
Note) Rules for raising and lowering power supply voltage. To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V). To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).
Clock Characteristics Item Input capacity of CLK Input capacity of ROG Input capacity of RS/SH CLK frequency RS frequency Symbol CCLK CROG C RS/SH fCLK fRS Min. -- -- -- -- -- Typ. 10 10 10 1 1 Max. -- -- -- 12.5 12.5 Unit pF pF pF MHz MHz
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ILX508A
Electrooptical Characteristics1 (Ta = 25C, VDD1 = 9V, VDD2 = 5V, Light source = 3200K, CLK = 1MHz, Internal RS mode without S/H, IR cut filter, CM-500S (t = 1.0mm)) Item Sensitivity1 Sensitivity2 Sensitivity nonuniformity Saturation output voltage Saturation exposure Even and odd black level DC difference Dark voltage average Dark signal nonuniformity Image lag 9V supply current 5V supply current Total transfer efficiency Output impedance Offset level Dynamic range Symbol R1 R2 PRNU VSAT SE V VDRK DSNU IL IVDD1 IVDD2 TTE ZO VOS DR Min. 7.5 -- -- 1.0 0.072 -- -- -- -- -- -- 90 -- -- 500 Typ. 10.8 24.6 5 1.5 0.139 1.0 0.3 0.6 0.02 16 5 97 600 3.0 5000 Max. 13.9 -- 12.5 -- -- 10.0 2 5 -- 32 16 -- -- -- -- Unit V/(lx * s) V/(lx * s) % V lx * s mV mV mV % mA mA % V -- Remarks 2 3 4 5 6 7 8 9 10 -- -- -- -- 11 12
1 In accorcance with the given electrooptical characteristics, the even black level is defined as the mean value of D8, D10, D12, D14, and D16. 2 For the sensitivity test light is applied with a uniform intensity of illumination. 3 W lamp (2854K). 4 PRNU is defined as indicated below. Ray incidence conditions are the same as for 2. PRNU = (VMAX - VMIN)/2 x 100 [%] VAVE
Where the 7926 pixels are divided into blocks of 102, even and odd pixels, respectively (Even and odd last blocks are 87.) The maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE. 5 Use below the minimum value of the saturation output voltage. 6 Saturation exposure is defined as follows. SE = VSAT R1
7 Indicates the DC difference in value between odd black level and even black level. 8 optical signal accumulated time int stands at 10ms. 9 The difference between the maximum and mean values of the dark output voltage is calculated for even and odd respectively. The larger value is defined as the dark signal nonuniformity. Optical signal accumulated time int stands at 10ms. 10 VOUT = 500mV (Typ.)
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ILX508A
11 VOS is defined as indicated below.
Vout
VOS GND
12 Dynamic range is defined as follows. DR = VSAT VDRK
When the optical signal accumulated time is shorter, the dynamic range gets wider because the optical signal accumulated time is in proportion to the dark voltage.
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Application Circuit (External RS)
CLK
RS
9V
5V 23 22 20 21 16 17 15 14 19 18 13
24
CLK
T4 (D)
VDD1 (D)
VDD1 (A)
VDD1 (A)
GND (D)
VDD2 (D)
VGG (A)
RS/SH (D)
GND (D)
T3 (D)
T2 (D)
VDD1 (A)
ROG
GND (A)
VDD2 (D)
GND (A)
PSSW (D)
VOUT (A)
1 2 3 7 4 8 10
5
6 9
VDD2 (D)
T1 (D)
GND (A)
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11 1k ROG 2SA1175
12
NC
NC
0.01
10/10V
0.01
0.01
10/16V
10/16V
Output signal
When noise influence into output signal is large, connect pins indicated by (A) to the analog power supply and pins indicated by (D) to the digital power supply, and also use a decoupling capacitor of large capacitance.
ILX508A
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Clock Timing Diagram (External RS)
5
ROG
0
1
1
5
CLK
0
5
RS
0
2 3 4
D1
D2 D3 D4 D5 D6
D16 D17 D18 D19 D20
D96 D97 D98 S1 S2 S3 S4
VOUT Optical black (80 pixels) Effective picture elements signal (7926 pixels)
Dummy signal (98 pixels)
1 line output period (8042 pixels)
D7923 D7924 D7925 D7926 D99 D100 D106 D107 D108 D109 D116
Dummy signal (18 pixels)
8042
2
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ILX508A
ILX508A
Clock pulse Waveform Conditions CLK, ROG pulse related
t8 t9
ROG
t2
CLK
t1
t3
Internal RS mode
t8 t9
CLK
t4
t5
Vout t10 t11 t10
External RS mode
CLK
t4
t5
t9
t8
RS
t7
t6
t13 t10 t12
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ILX508A
Item ROG, CLK pulse timing ROG, CLK pulse timing ROG pulse high level period CLK pulse high level period CLK pulse low level period RS pulse low level period CLK, RS pulse timing Input clock pulse rise/fall time Input clock pulse voltage High level Low level Internal RS Signal output delay time External RS 1 The frequency of CLK is 1MHz. t1 t3 t2 t4 t5 t6 t7 t8, t9
Symbol
Min. 200 1200 1200 40 40 25 60 -- 4.5 0 -- -- -- --
Typ. 300 1500 1500 5001 5001 1001 5501 5 5.0 -- 95 70 45 60
Max. -- -- -- -- -- -- 10 + t4 + t5 10 5.5 0.5 -- -- -- --
Unit ns ns ns ns ns ns ns ns V V ns ns ns ns
VCLK, VROG VRS t10 t11 t12 t13
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ILX508A
Example of Representative Characteristics (VDD1 = 9V, VDD2 = 5V, Ta = 25C)
Spectral sensitivity characteristics (Standard characteristics)
1.0
0.8
Relative sensitivity
0.6
0.4
0.2
0 400
500
600
700 Wavelength [nm]
800
900
1000
MTF of main scanning direction (Standard characteristics)
Spatial frequency [cycle/mm] 0 1.0 14.3 28.6 42.9 57.1 71.4
0.8
0.6
MTF
0.4 0.2 0 0 0.2 0.4 0.6 0.8 1.0 Normalized spatial frequency
Dark signal output temperature characteristics (Typical characteristics)
Integration time output voltage characteristics (Typical characteristics)
10 5
Output voltage rate
Output voltage rate
1
1 0.5
0.5
0.1 0 10 20 30 40 50 60 Ta - Ambient temperature [C]
0.1 1 5 int - integration time [ms] 10
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ILX508A
Operational frequency characteristics of the VDD1 supply current (Typical characteristics)
Operational frequency characteristics of the VDD2 supply current (Typical characteristics)
60
IVDD1 - VDD1 supply current [mA]
15
IVDD2 - VDD2 supply current [mA]
0 2 4 6 8 10 12.5
50
40
10
30
20
5
10
0 fCLK - CLK clock frequency [MHz]
0 0 2 4 6 8 10 12.5 fCLK - CLK clock frequency [MHz]
Offset level vs. VDD1 characteristics (Typical characteristics)
6 Ta = 25C 5 5 6
Offset level vs. VDD2 characteristics (Typical characteristics)
Ta = 25C
VOS - Offset level [V]
4
VOS - Offset level [V]
4
3
3
2
VOS VDD1
2
~ 0.35 -
1
1
VOS VDD2
~ -0.14 -
0 8.5 VDD1 [V] 9 9.5
0 4.75 VDD2 [V] 5 5.25
Offset level vs. Temperature characteristics (Typical characteristics)
6
5
VOS - Offset level [V]
4
VOS Ta
3
2
~ - 0.8mV/C -
1
0 0 10 20 30 40 50 60 Ta - Ambient temperature [C]
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ILX508A
Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates use boxes treated for the prevention of static charges. 2) Regulation for raising and lowering the power supply voltage. When raising the supply voltage, first raise VDD1 (9V) and then VDD2 (5V). Similarly, lower VDD2 (5V) first and then VDD1 (9V). 3) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficienty. c) To dismount an imaging device do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface blow it off with an air blow. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
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Package Outline
Unit: mm
24Pin DIP (400mil)
71.0 0.9
24 13
V 12 68.0 0.15
9.0 0.15
5.0 0.5
0.8 0.1
4.0 0.5
0.3 M 1. The height from the bottom to the sensor surface is 1.42 0.3mm. 2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5.
PACKAGE STRUCTURE
PACKAGE MATERIAL
Ceramic
LEAD TREATMENT
GOLD PLATING
LEAD MATERIAL
42ALLOY
PACKAGE WEIGHT
5.8g
ILX508A
0.97 0.3
3.1 0.5
2.54 0.25 0.46 0.15
2.29
+0.1 0.25 -0.0 5
1st. pin Index 1.27
(AT STAND OFF) 10.16 0.3
1
10.0 0.5
H
No.1 Pixel
0 to 9
9.21 0.8
55.482 (7m x 7926Pixels)
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