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LMX2315/LMX2320/LMX2325 PLLatinum Frequency Synthesizer for RF Personal Communications LMX2325 2.5 GHz LMX2320 2.0 GHz LMX2315 1.2 GHz
February 2002
LMX2315/LMX2320/LMX2325 PLLatinumTM Frequency Synthesizer for RF Personal Communications LMX2325 2.5 GHz LMX2320 2.0 GHz LMX2315 1.2 GHz
General Description
The LMX2315/2320/2325's are high performance frequency synthesizers with integrated prescalers designed for RF operation up to 2.5 GHz. They are fabricated using National's ABiC IV BiCMOS process. A 64/65 or a 128/129 divide ratio can be selected for the LMX2315 and LMX2320 RF synthesizer at input frequencies of up to 1.2 GHz and 2.0 GHz, while 32/33 and 64/65 divide ratios are available in the 2.5 GHz LMX2325. Using a proprietary digital phase locked loop technique, the LMX2315/ 2320/2325's linear phase detector characteristics can generate very stable, low noise signals for controlling a local oscillator. Serial data is transferred into the LMX2320 and the LMX2325 via a three line MICROWIRETM interface (Data, Enable, Clock). Supply voltage can range from 2.7V to 5.5V. The LMX2315, LMX2320 and the LMX2325 feature very low current consumption, typically 6 mA, 10 mA and 11 mA respectively. The LMX2315, LMX2320 and the LMX2325 are available in a TSSOP 20-pin surface mount plastic package.
Features
RF operation up to 2.5 GHz 2.7V to 5.5V operation Low current consumption Dual modulus prescaler: LMX2325: 32/33 or 64/65 LMX2320/LMX2315: 64/65 or 128/129 n Internal balanced, low leakage charge pump n Power down feature for sleep mode: ICC = 30 A (typ) at VCC = 3V n Small-outline, plastic, surface mount TSSOP, 0.173" wide n n n n
Applications
n Cellular telephone systems (GSM, IS-54, IS-95, (RCR-27) n Portable wireless communications (DECT, PHS) n CATV n Other wireless communication systems
Block Diagram
DS012339-1
TRI-STATE (R) is a registered trademark of National Semiconductor Corporation. MICROWIRETM and PLLatinumTM are trademarks of National Semiconductor Corporation.
(c) 2002 National Semiconductor Corporation
DS012339
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LMX2315/LMX2320/LMX2325
Connection Diagram
LMX2315/LMX2320/LMX2325
DS012339-2
20-Lead (0.173" Wide) Thin Shrink Small Outline Package (TM) Order Number LMX2315TM, LMX2315TMX, LMX2325TM, LMX2325TMX, LMX2320TM or LMX2320TMX See NS Package Number MTC20
Pin Descriptions
Pin No. 1 Pin Name OSCIN I/O I Description Oscillator input. A CMOS inverting gate input intended for connection to a crystal resonator for operation as an oscillator. The input has a VCC/2 input threshold and can be driven from an external CMOS or TTL logic gate. May also be used as a buffer for an externally provided reference oscillator. Oscillator output. Power supply for charge pump. Must be VCC. Power supply voltage input. Input may range from 2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. O O I I I I Internal charge pump output. For connection to a loop filter for driving the input of an external VCO. Ground. Lock detect. Output provided to indicate when the VCO frequency is in "lock". When the loop is locked, the pin's output is HIGH with narrow low pulses. Prescaler input. Small signal input from the VCO. High impedance CMOS Clock input. Data is clocked in on the rising edge, into the various counters and registers. Binary serial data input. Data entered MSB first. LSB is control bit. High impedance CMOS input. Load enable input (with internal pull-up resistor). When LE transitions HIGH, data stored in the shift registers is loaded into the appropriate latch (control bit dependent). Clock must be low when LE toggles high or low. See Serial Data Input Timing Diagram. Phase control select (with internal pull-up resistor). When FC is LOW, the polarity of the phase comparator and charge pump combination is reversed. Analog switch output. When LE is HIGH, the analog switch is ON, routing the internal charge pump output through BISW (as well as through Do). Monitor pin of phase comparator input. CMOS output. Output for external charge pump. p is an open drain N-channel transistor and requires a pull-up resistor. Power Down (with internal pull-up resistor). PWDN = HIGH for normal operation. PWDN = LOW for power saving. Power down function is gated by the return of the charge pump to a TRI-STATE (R) condition. 20 2,9,12 r NC O Output for external charge pump. r is a CMOS logic output. No connect.
3 4 5 6 7 8 10 11 13 14
OSCOUT VP VCC Do GND LD fIN CLOCK DATA LE
O
15 16 17 18 19
FC BISW fOUT p PWDN
I O O O I
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LMX2315/LMX2320/LMX2325
Functional Block Diagram
DS012339-3
Note 1: The prescalar for the LMX2315 and LMX2320 is either 64/65 or 128/129, while the prescalar for the LMX2325 is 32/33 or 64/65. Note 2: The power down function is gated by the charge pump to prevent unwanted frequency jumps. Once the power down pin is brought low the part will go into power down mode when the charge pump reaches a TRI-STATE condition.
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LMX2315/LMX2320/LMX2325
Absolute Maximum Ratings (Notes 4, 3)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Power Supply Voltage VCC VP Voltage on Any Pin with GND = 0V (VI) Storage Temperature Range (TS) Lead Temperature (TL) (solder, 4 sec.) -0.3V to +6.5V -0.3V to +6.5V -0.3V to +6.5V -65C to +150C +260C
Recommended Operating Conditions
Power Supply Voltage VCC VP Operating Temperature (TA) 2.7V to 5.5V VCC to +5.5V -40C to +85C
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Note 4: This device is a high performance RF integrated circuit with an ESD rating < 2 kV and is ESD sensitive. Handling and assembly of this device should be done at ESD workstations.
Electrical Characteristics
LMX2325 and LMX2320 VCC = VP = 3.0V; LMX2315 VCC = VP = 5.0V; -40C < TA < 85C, except as specified Symbol ICC Power Supply Current Parameter LMX2315 LMX2320 LMX2325 ICC-PWDN fIN Power Down Current Maximum Operating Frequency LMX2315 LMX2320 LMX2325 fOSC f PfIN VOSC VIH VIL IIH IIL IIH IIL IIH IIL IDo-source IDo-sink IDo-source IDo-sink IDo-Tri IDo vs VDo Charge Pump TRI-STATE Current Charge Pump Output Current Magnitude Variation vs Voltage (Note 7) Charge Pump Output Current High-Level Input Current (LE, FC) Low-Level Input Current (LE, FC) Charge Pump Output Current Oscillator Frequency No Load on OSCout Phase Detector Frequency Input Sensitivity Oscillator Sensitivity High-Level Input Voltage Low-Level Input Voltage High-Level Input Current (Clock, Data) Low-Level Input Current (Clock, Data) Oscillator Input Current VCC = 2.7V to 3.3V VCC = 3.3V to 5.5V OSCIN (Note 5) (Note 5) VIH = VCC = 5.5V VIL = 0V, VCC = 5.5V VIH = VCC = 5.5V VIL = 0V, VCC = 5.5V VIH = VCC = 5.5V VIL = 0V, VCC = 5.5V VCC = VP = 3.0V, VDo = VP/2 VCC = VP = 3.0V, VDo = VP/2 VCC = VP = 5.0V, VDo = VP/2 VCC = VP = 5.0V, VDo = VP/2 0.5V VDo VP - 0.5V T = 85C 0.5V VDo VP - 0.5V T = 25C 15 % -2.5 -100 -1.0 -100 -2.5 2.5 -5.0 5.0 2.5 1.0 1.0 -1.0 -1.0 1.2 5 5 10 -15 -10 0.5 0.7 VCC 0.3 VCC 1.0 1.0 100 +6 +6 VPP V V A A A A A A mA mA mA mA nA Conditions VCC = 3.0V VCC = 5.0V VCC = 3.0V VCC = 3.0V VCC = 3.0V VCC = 5.0V Min Typ 6.0 6.5 10 11 30 60 Max 8.0 8.5 13.5 15 180 350 1.2 2.0 2.5 20 40 MHz MHz MHz dBm GHz Units mA mA mA mA A A
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LMX2315/LMX2320/LMX2325
Electrical Characteristics
Symbol IDo-sink vs IDo-source IDovs T
(Continued)
LMX2325 and LMX2320 VCC = VP = 3.0V; LMX2315 VCC = VP = 5.0V; -40C < TA < 85C, except as specified Parameter Charge Pump Output Current Sink vs Source Mismatch (Note 7) Charge Pump Output Current Magnitude Variation vs Temperature (Note 7) VOH VOL VOH VOL IOL IOH RON tCS tCH tCWH tCWL tES tEW High-Level Output Voltage Low-Level Output Voltage High-Level Output Voltage (OSCOUT) Low-Level Output Voltage (OSCOUT) Open Drain Output Current (p) Open Drain Output Current (p) Analog Switch ON Resistance (2315) Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width High Clock Pulse Width Low Clock to Enable Set Up Time Enable Pulse Width See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing 50 10 50 50 50 50 IOH = -1.0 mA (Note 6) IOL = 1.0 mA (Note 6) IOH = -200 A IOL = 200 A VCC = 5.0V, VOL = 0.4V VOH = 5.5V 100 1.0 100 VCC - 0.8 0.4 VCC - 0.8 0.4 V V V V mA A ns ns ns ns ns ns -40C < T < 85C VDo = VP/2 10 % T = 25C Conditions VDo = VP/2 10 % Min Typ Max Units
Note 5: Except fIN and OSCIN Note 6: Except OSCOUT Note 7: See related equations in Charge Pump Current Specification Definitions
Typical Performance Characteristics
ICC vs VCC LMX2320/25 ICC vs VCC LMX2315
DS012339-4 DS012339-51
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LMX2315/LMX2320/LMX2325
Typical Performance Characteristics
Charge Pump Current vs Do Voltage
(Continued) Charge Pump Current vs Do Voltage
DS012339-40
DS012339-7
Charge Pump Current Variation
Sink vs Source Mismatch vs Do Voltage
DS012339-8
DS012339-9
IDo TRI-STATE vs Do Voltage
Oscillator Input Sensitivity
DS012339-14 DS012339-5
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LMX2315/LMX2320/LMX2325
Typical Performance Characteristics
LMX2320/25 Input Sensitivity vs Frequency
(Continued) LMX2320/25 Input Sensitivity vs Frequency
DS012339-10
DS012339-11
LMX2315 Input Sensitivity vs Frequency
LMX2315 Input Sensitivity vs Frequency
DS012339-41
DS012339-42
LMX2320/25 Input Sensitivity at Temperature Variation, VCC = 3V
LMX2320/25 Input Sensitivity at Temperature Variation, VCC = 5V
DS012339-12
DS012339-13
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LMX2315/LMX2320/LMX2325
Typical Performance Characteristics
LMX2315 Input Sensitivity at Temperature Variation, VCC = 5V
(Continued)
LMX2315 Input Sensitivity at Temperature Variation, VCC = 3V
DS012339-43
DS012339-44
LMX2315 Input Impedance vs Frequency VCC = 2.7V to 5.5V, fIN = 100 MHz to 1,600 MHz
LMX2320/25 Input Impedance vs Frequency VCC = 2.7V to 5.5V, fIN = 500 MHz to 3000 MHz
DS012339-45
DS012339-15
Marker Marker Marker Marker
1 2 3 4
= = = =
500 MHz, Real = 69, Imag. = -330 900 MHz, Real = 36, Imag. = -193 1 GHz, Real = 35, Imag. = -172 1,500 MHz, Real = 30, Imag. = -106
1 2 3 4
= = = =
1.5 1.8 2.0 2.5
GHz, GHz, GHz, GHz,
Real Real Real Real
= = = =
48, 44, 42, 36,
Im Im Im Im
= = = =
-128 -102 -90 -72
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LMX2315/LMX2320/LMX2325
Charge Pump Current Specification Definitions
DS012339-16
I1 = CP sink current at VDo = VP - V I2 = CP sink current at VDo = VP/2 I3 = CP sink current at VDo = V I4 = CP source current at VDo = VP - V I5 = CP source current at VDo = VP/2 I6 = CP source current at VDo = V V = Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to VCC and ground. Typical values are between 0.5V and 1.0V. 1. IDo vs VDo = Charge Pump Output Current magnitude variation vs Voltage = [12 * |I1| - |I3|]/[12 * {|I1| + |I3|}] * 100% and [12 * |I4| - |I6|]/[12 * {|I4| + |I6|}] * 100% 2. IDo-sink vs IDo-source = Charge Pump Output Current Sink vs Source Mismatch = [|I2| - |I5|]/[12 * {|I2| + |I5|}] * 100% 3. IDo vs TA = Charge Pump Output Current magnitude variation vs Temperature = [|I2 @ temp| - |I2 @ 25C|]/|I2 @ 25C| * 100% and [|I5 @ temp| - |I5 @ 25C|]/|I5 @ 25C| * 100% 4. K = Phase detector/charge pump gain constant = 12 * {|I2| + |I5|}
RF Sensitivity Test Block Diagram
DS012339-17
Note 8: N = 10,000
R = 50
P = 64
Note 9: Sensitivity limit is reached when the error of the divided RF output, fOUT, is greater than or equal to 1 Hz.
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LMX2315/LMX2320/LMX2325
Functional Description
The simplified block diagram below shows the 19-bit data register, the 14-bit R Counter and the S Latch, and the 18-bit N Counter (intermediate latches are not shown). The data stream is clocked (on the rising edge) into the DATA input, MSB first. If the Control Bit (last bit input) is HIGH, the DATA is transferred into the R Counter (programmable reference divider) and the S Latch (prescaler select: LMX2315 and LMX2320: 64/65 or 128/129; LMX2325 32/33 or 64/65). If the Control Bit (LSB) is LOW, the DATA is transferred into the N Counter (programmable divider).
DS012339-18
PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) AND PRESCALER SELECT (S LATCH) If the Control Bit (last bit shifted into the Data Register) is HIGH, data is transferred from the 19-bit shift register into a 14-bit latch (which sets the 14-bit R Counter) and the 1-bit S Latch (S15, which sets the prescaler: 64/65 or 128/129 for the LMX2315/20 or 32/33 or 64/65 for the LMX2325). Serial data format is shown below.
DS012339-6
14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO Divide R 3 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 011 100 S S S S SSSSSSSSSS Ratio 14 13 12 11 10 9 8 7 6 5 4 3 2 1
* 16383
* 1
* 1
* 1
* 1
* 1
********* 111111111
Notes: Divide ratios less than 3 are prohibited. Divide ratio: 3 to 16383 S1 to S14: These bits select the divide ratio of the programmable reference divider. C: Control bit (set to HIGH level to load R counter and S Latch) Data is shifted in MSB first.
Prescaler Select LMX2315/20 128/129 64/65 LMX2325 64/65 32/33
S 15 0 1
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LMX2315/LMX2320/LMX2325
Functional Description
(Continued)
PROGRAMMABLE DIVIDER (N COUNTER) The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control Bit (last bit shifted into the Data Register) is LOW, data is transferred from the 19-bit shift register into a 7-bit latch (which sets the 7-bit Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter). Serial data format is shown below.
DS012339-20
Note: S8 to S18: Programmable counter divide ratio control bits (3 to 2047)
7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER) Divide Ratio A 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 S 7 S 6 S 5 S 4 S 3 S 2 S 1
* 127
* 1
* 1
* 1
* 1
* 1
* 1
* 1
Note: Divide ratio: 0 to 127 BA
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER) Divide Ratio B 3 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 SSSSSSSSS 18 17 16 15 14 13 12 11 10 S 9 S 8
* 2047
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
* 1
Note: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited) BA
PULSE SWALLOW FUNCTION fVCO = [(P x B) + A] x fOSC/R fVCO: Output frequency of external voltage controlled oscillator (VCO) B: Preset divide ratio of binary 11-bit programmable counter (3 to 2047) A: Preset divide ratio of binary 7-bit swallow counter (0 A 127, A B) fOSC: Output frequency of the external reference frequency oscillator R: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16383) P: Preset modulus of dual moduIus prescaler (64 or 128 for 2315/20 or 32 or 64 for 2325)
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LMX2315/LMX2320/LMX2325
Functional Description
SERIAL DATA INPUT TIMING
(Continued)
DS012339-21
Notes: Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first. Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6 V/ns with amplitudes of 2.2V @ VCC = 2.7V and 2.6V @ VCC = 5.5V.
Phase Characteristics
In normal operation, the FC pin is used to reverse the polarity of the phase detector. Both the internal and any external charge pump are affected. Depending upon VCO characteristics, FC pin should be set accordingly: When VCO characteristics are like (1), FC should be set HIGH or OPEN CIRCUIT; When VCO characteristics are like (2), FC should be set LOW. When FC is set HIGH or OPEN CIRCUIT, the monitor pin of the phase comparator input, fout, is set to the reference divider output, fr. When FC is set LOW, fout is set to the programmable divider output, fp. PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS VCO Characteristics
DS012339-22
DS012339-23
Notes: Phase difference detection range: -2 to +2 The minimum width pump up and pump down current pulses occur at the Do pin when the loop is locked. FC = HIGH
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LMX2315/LMX2320/LMX2325
Analog Switch
The analog switch is useful for radio systems that utilize a frequency scanning mode and a narrow band mode. The purpose of the analog switch is to decrease the loop filter time constant, allowing the VCO to adjust to its new frequency in a shorter amount of time. This is achieved by adding another filter stage in parallel. The output of the charge pump is normally through the Do pin, but when LE is set HIGH, the charge pump output also becomes available at BISW. A typical circuit is shown below. The second filter stage (LPF-2) is effective only when the switch is closed (in the scanning mode).
DS012339-24
Typical Crystal Oscillator Circuit
A typical circuit which can be used to implement a crystal oscillator is shown below.
Typical Lock Detect Circuit
A lock detect circuit is needed in order to provide a steady LOW signal when the PLL is in the locked state. A typical circuit is shown below.
DS012339-52 DS012339-26
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LMX2315/LMX2320/LMX2325
Typical Application Example
DS012339-27
Operational Notes: * VCO is assumed AC coupled. ** RIN increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10 to 200 depending on the VCO power level. fIN RF impedance ranges from 40 to 100. *** 50 termination is often used on test boards to allow use of external reference oscillator. For most typical products a CMOS clock is used and no terminating resistor is required. OSCIN may be AC or DC coupled. AC coupling is recommended because the input circuit provides its own bias. (See Figure below)
DS012339-28
Layout Hints: Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful board layout. This is a static sensitive device. It should be handled only at static free work stations.
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LMX2315/LMX2320/LMX2325
Application Information
LOOP FILTER DESIGN A block diagram of the basic phase locked loop is shown.
DS012339-29
FIGURE 1. Basic Charge Pump Phase Locked Loop An example of a passive loop filter configuration, including the transfer function of the loop filter, is shown in Figure 2. Open Loop Gain = i/e = H(s) G(s) = K Z(s) KVCO/Ns Closed Loop Gain = o/i = G(s)/[1 + H(s) G(s)]
DS012339-30
FIGURE 2. 2nd Order Passive Filter
Define the time constants which determine the pole and zero frequencies of the filter transfer function by letting T2 = R2 * C2 and (1)
DS012339-31
FIGURE 3. Open Loop Transfer Function Thus we can calculate the 3rd order PLL Open Loop Gain in terms of frequency
(2) The PLL linear model control circuit is shown along with the open loop transfer function in Figure 3. Using the phase detector and VCO gain constants [K and KVCO] and the loop filter transfer function [Z(s)], the open loop Bode plot can be calculated. The loop bandwidth is shown on the Bode plot (p) as the point of unity gain. The phase margin is shown to be the difference between the phase at the unity gain point and -180.
(3) From equation 3 we can see that the phase term will be dependent on the single pole and zero such that () = tan-1 ( * T2) - tan-1 ( * T1) + 180 (4) By setting
(5) we find the frequency point corresponding to the phase inflection point in terms of the filter time constants T1 and T2. This relationship is given in equation 6. (6)
DS012339-32
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LMX2315/LMX2320/LMX2325
Application Information
(Continued)
For the loop to be stable the unity gain point must occur before the phase reaches -180 degrees. We therefore want the phase margin to be at a maximum when the magnitude of the open loop gain equals 1. Equation 3 then gives
N RFopt (MHz) fref (kHz)
Main divider ratio. Equal to RFopt/fref Radio Frequency output of the VCO at which the loop filter is optimized. Frequency of the phase detector inputs. Usually equivalent to the RF channel spacing.
(7) Therefore, if we specify the loop bandwidth, p, and the phase margin, p, Equations 1 through 7 allow us to calculate the two time constants, T1 and T2, as shown in equations 8 and 9. A common rule of thumb is to begin your design with a 45 phase margin.
In choosing the loop filter components a trade off must be made between lock time, noise, stability, and reference spurs. The greater the loop bandwidth the faster the lock time will be, but a large loop bandwidth could result in higher reference spurs. Wider loop bandwidths generally improve close in phase noise but may increase integrated phase noise depending on the reference input, VCO and division ratios used. The reference spurs can be reduced by reducing the loop bandwidth or by adding more low pass filter stages but the lock time will increase and stability will decrease as a result. THIRD ORDER FILTER A low pass filter section may be needed for some applications that require additional rejection of the reference sidebands, or spurs. This configuration is given in Figure 4. In order to compensate for the added low pass section, the component values are recalculated using the new open loop unity gain frequency. The degradation of phase margin caused by the added low pass is then mitigated by slightly increasing C1 and C2 while slightly decreasing R2. The added attenuation from the low pass filter is: ATTEN = 20 log[(2fref * R3 * C3)2 + 1] (13) (14) Then in terms of the attenuation of the reference spurs added by the low pass pole we have Defining the additional time constant as T3 = R3 * C3
(8)
(9) From the time constants T1, and T2, and the loop bandwidth, p, the values for C1, R2, and C2 are obtained in equations 10 to 12.
(10)
(11)
(12) KVCO (MHz/V) Voltage Controlled Oscillator (VCO) Tuning Voltage constant. The frequency vs voltage tuning ratio. Phase detector/charge pump gain constant. The ratio of the current output to the input phase differential. (15) We then use the calculated value for loop bandwidth c in equation 12, to determine the loop filter component values in equations 16-18. c is slightly less than p, therefore the frequency jump lock time will increase.
K (mA)
(16)
(17)
(18)
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LMX2315/LMX2320/LMX2325
Application Information
(Continued)
Consider the following application examples: Example #1 KVCO = 20 MHz/V K = 5 mA (*) RFopt = 900 MHz Fref = 200 kHz N = RFopt/fref = 4500 p = 2 * 20 kHz = 1.256e5 p = 45 ATTEN = 20 dB
Converting to standard component values gives the following filter values, which are shown in Figure 4. C1 R2 C2 R3 C3 = = = = = 1000 pF 3.3 k 10 nF 22 k 100 pF
DS012339-46
Note: *See related equation for K in Charge Pump Current Specification Definitions. For this example VP = 5.0V. The value of K can then be approximated using the curves in the Typical Peformance Characteristics for Charge Pump Current vs. Do Voltage. The units for K are in mA. You may also use K = (5 mA/2 rad), but in this case you must convert KVCO to (rad/V) multiplying by 2.
FIGURE 4. 20 kHz Loop Filter
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LMX2315/LMX2320/LMX2325
Application Information
(Continued)
MEASUREMENT RESULTS (Example #1)
DS012339-48
FIGURE 7. PLL Phase Noise @ 1 kHz Offset
DS012339-47
The phase noise level at 1 kHz offset is -79.5 dBc/Hz.
FIGURE 5. PLL Reference Spurs The reference spurious level is < -74 dBc, due to the loop filter attenuation and the low spurious noise level of the LMX2315.
DS012339-50
FIGURE 8. Frequency Jump Lock Time Of concern in any PLL loop filter design is the time it takes to lock in to a new frequency when switching channels. Figure 8 shows the switching waveforms for a frequency jump of 865 MHz to 915 MHz. By narrowing the frequency span of the HP53310A Modulation Domain Analyzer enables evaluation of the frequency lock time to within 500 Hz. The lock time is seen to be less than 500 s for a frequency jump of 50 MHz. Example #2 KVCO = 34 MHz/V K = 2.8 mA (*) RFopt = 1665 MHz Fref = 300 kHz N = RFopt/fref = 5550 p = 2 * 20 kHz = 1.256e5 p = 43 ATTEN = 12 dB
DS012339-49
FIGURE 6. PLL Phase Noise 10 kHz Offset The phase noise level at 10 kHz offset is -80 dBc/Hz.
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LMX2315/LMX2320/LMX2325
Application Information
(Continued)
Converting to standard component values gives the following filter values, which are shown in Figure 4. C1 R2 C2 R3 C3 = = = = = 560 pF 6.8 k 2700 pF 27 k 56 pF
MEASUREMENT RESULTS (Example #2)
Note: *See related equation for K in Charge Pump Current Specification Definitions. For this example VP = 3.3V. The value for K can then be approximated using the curves in the Typical Performance Characteristics for Charge Pump Current vs. Do Voltage. The units for K are in mA. You may also use K = (2.8 mA/2 rad), but in this case you must convert KVCO to (rad/V) multiplying by 2.
DS012339-34 DS012339-33
FIGURE 10. PLL Reference Spurs The reference spurious level is < -65 dBc, due to the loop filter attenuation and the low spurious noise level of the LMX2320.
FIGURE 9. 20 kHz Loop Filter
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LMX2315/LMX2320/LMX2325
Application Information
(Continued)
DS012339-37
FIGURE 13. Frequency Jump Lock Time
DS012339-35
FIGURE 11. PLL Phase Noise @ 150 Hz Offset The phase noise level at 150 Hz offset is -81.1 dBc/Hz. The spurs at 60 and 180 Hz offset are due to 60 Hz line noise from the power supply.
Of concern in any PLL loop filter design is the time it takes to lock in to a new frequency when switching channels. Figure 13 shows the switching waveforms for a frequency jump of 1650.9 MHz to 1683.9 MHz. By narrowing the frequency span of the HP53310A Modulation Domain Analyzer enables evaluation of the frequency lock time to within 1 kHz. The lock time is seen to be less than 500 s for a frequency jump of 33 MHz. EXTERNAL CHARGE PUMP The LMX PLLatinum series of frequency synthesizers are equipped with an internal balanced charge pump as well as outputs for driving an external charge pump. Although the superior performance of NSC's on board charge pump eliminates the need for an external charge pump in most applications, certain system requirements are more stringent. In these cases, using an external charge pump allows the designer to take direct control of such parameters as charge pump voltage swing, current magnitude, TRI-STATE leakage, and temperature compensation. One possible architecture for an external charge pump current source is shown in Figure 14. The signals p and r in the diagram, correspond to the phase detector outputs of the 2315/20/25 frequency synthesizers. These logic signals are converted into current pulses, using the circuitry shown in Figure 14, to enable either charging or discharging of the loop filter components to control the output frequency of the PLL. Referring to Figure 14, the design goal is to generate a 5 mA current which is relatively constant to within 5V of the power supply rail. To accomplish this, it is important to establish as large of a voltage drop across R5, R8 as possible without saturating Q2, Q4. A voltage of approximately 300 mV provides a good compromise. This allows the current source reference being generated to be relatively repeatable in the absence of good Q1, Q2/Q3, Q4 matching. (Matched transistor pairs is recommended.) The p and r outputs are rated for a maximum output load current of 1 mA while 5 mA current sources are desired. The voltages developed across R4, 9 will consequently be approximately 258 mV, or 42 mV less than R8, 5, due to the current density differences {0.026*1n (5 mA/1 mA)} through the Q1, Q2/Q3, Q4 pairs. In order to calculate the value of R7 it is necessary to first estimate the forward base to emitter voltage drop (Vfn,p) of
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FIGURE 12. PLL Phase Noise 20 kHz Offset The phase noise level at 20 kHz offset is -80 dBc/Hz.
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LMX2315/LMX2320/LMX2325
Application Information
(Continued)
Design Parameters
the transistors used, the VOL drop of p, and the VOH drop of r's under 1 mA loads. (p's VOL < 0.1V and (r,s VOH < 0.1V). Knowing these parameters along with the desired current allow us to design a simple external charge pump. Separating the pump up and pump down circuits facilitates the nodal analysis and give the following equations.
ISINK = ISOURCE = 5.0 mA; Vfn = Vfp = 0.8V Irmax = Ipmax = 1 mA VR8 = VR5 = 0.3V VOLp = VOHp = 100 mV
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FIGURE 14. Therefore select EXAMPLE Typical Device Parameters n =100, p = 50 Typical System Parameters VP = 5.0V; Vcntl = 0.5V-4.5V; Vp = 0.0V, Vr = 5.0V
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LMX2315/LMX2320/LMX2325 PLLatinum Frequency Synthesizer for RF Personal Communications LMX2325 2.5 GHz LMX2320 2.0 GHz LMX2315 1.2 GHz
Physical Dimensions
inches (millimeters) unless otherwise noted
NS Package Number MTC20 20-Lead (0.173" Wide) Thin Shrink Small Outline Package (TM) Order Number LMX2315TM, LMX2320TM or LMX2325TM For Tape and Reel Order Number LMX2315TMX, LMX2320TMX or LMX2325TMX (2500 Units per Reel)
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