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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12513-3E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89820 Series
MB89821/823/P825/PV820
s DESCRIPTION
MB89820 series is a line of single-chip microcontrollers using the F2MC-8L* CPU core which can operate at low voltage but at high speed. In addition to an LCD controller/driver allowing 200-pixel display the microcontrollers contain a variety of peripheral functions such as timers, a UART, a serial interface, and an external interrupt. The configuration of the MB89820 series is therefore best suited to control of LCD display panels. *: F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
* Minimum execution time: 0.8 s/5 MHz (VCC = +5.0 V) * F2MC-8L family CPU core Multiplication and division instructions 16-bit arithmetic operations Instruction set optimized for controllers Test and branch instructions Bit manipulation instructions, etc. * LCD controller/driver Max. 50 segments x 4 commons Divided resistor for LCD power supply
(Continued)
s PACKAGES
80-pin Plastic QFP
80-pin Ceramic MQFP
(FPT-80P-M11)
(MQP-80C-P01)
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MB89820 Series
(Continued) * Three types of timers 8-bit PWM timer (also usable as a reload timer) 8-bit pulse width count timer (also usable as a reload timer) 20-bit time-base timer
* Two serial interfaces 8-bit synchronous serial interface (Switchable transfer direction allows communication with various equipment.) UART (5-, 7-, 8-bit transfer capable) * External interrupt: 2 channels Capable of wake-up from low-power consumption modes (with an edge detection function) * Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)
s PRODUCT LINEUP
Part number Parameter
MB89821
MB89823
MB89P825 One-time PROM product
MB89PV820 Piggyback/evaluation product for evaluation and development 32 K x 8 bits (external ROM)
Classification
Mass production product (mask ROM products)
ROM size
4 K x 8 bits 8 K x 8 bits 16 K x 8 bits (internal mask ROM) (internal mask ROM) (internal PROM, programming with general-purpose EPROM programmer) 128 x 8 bits Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: I/O ports (N-ch open-drain): I/O ports (N-ch open-drain): I/O ports (CMOS): Input ports: Total: 256 x 8 bits 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.8 s/5 MHz (VCC = 5.0 V) 7.2 s/5 MHz (VCC = 5.0 V)
RAM size CPU functions
1024 x 8 bits
Ports
16 (All also serve as segment pins.)*1 6 6 (5 ports also serve as peripheral I/O.) 4 (1 port also serves as an external interrupt input.) 32 (max.)
8-bit PWM timer
8-bit reload timer operation (toggled output capable) 8-bit resolution PWM operation Operating clock (pulse width count timer output: 0.8 s, 12.8 s, 51.2 s/5 MHz) 8-bit reload timer operation 8-bit pulse width count operation (continuous measurement capable "H" width, "L" width, or single-cycle measurement capable) Operating clock (0.8 s, 3.2 s, 25.6 s/5 MHz) 8 bits One clock selectable from four transfer clocks (one external shift clock, three internal shift clock, three internal shift clocks: 1.6 s, 6.4 s, 25.6 s/5 MHz) LSB first/MSB first selectability
8-bit pulse width count timer
8-bit serial I/O
(Continued)
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MB89820 Series
(Continued)
Part number
MB89821
Parameter
MB89823
MB89P825
MB89PV820
UART LCD controller/ driver
5-, 7-, 8-bit transfer capable Internal baud-rate generator (max. 78125 bps/5 MHz) Common output: 4 Segment output: 50 (max.) Operating mode: 1/2 bias, 1/2 duty; 1/3 bias, 1/3 duty; 1/3 bias, 1/4 duty LCD display RAM size: 50 x 4 bits Dividing resistor for LCD driving: Built-in (An external resistor selectable) 2 channels (edge selectable) (1 channel also serves as a pulse width count timer input) Sleep mode, stop mode CMOS 2.2 V*3 to 6.0 V 2.7 V to 6.0 V MBM27C256A-20TV (LCC package)
External interrupt Standby mode Process Operating voltage*2 EPROM for use
*1: The function is selected by the mask option. *2: Varies with conditions such as the operating frequency. (See section "s Electrical Characteristics.") *3: The operation at less than 2.2 V is assured separately. Please contact FUJITSU LIMITED.
s PACKAGE AND CORRESPONDING PRODUCTS
Package FPT-80P-M11 MQP-80C-P01 : Available x x : Not available MB89821 MB89823 MB89P825 MB89PV820 x
Note: For more information about each package, see section "s Package Dimensions."
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MB89820 Series
s DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: * On the MB89821, the register bank address upper than 0140H cannot be used. On the MB89823 and MB89P825, each register bank addresses upper than 0180H can be used. * On the MB89P825, addresses BFF0H to BFF6H comprise the option setting area, option settings can be read by reading these addresses. * The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
* In the case of the MB89PV820, add the current consumed by the EPROM which is connected to the top socket. * However, the current consumption in sleep/stop modes is the same. (For more information, see section " s Electrical Characteristics."
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product. Before using options check section "s Mask Options." Take particular care on the following point: * Options are fixed on the MB89PV820.
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MB89820 Series
s PIN ASSIGNMENT
(Top view)
VSS X1 X0 RST MOD1 MOD0 P45/SCK P44/SO P43/SI P42/PWC/INT1 P41/PWM P40 P33 P32 P31 P30/INT0 P25 P24 P23 P22
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
V1 V2 V3 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32
P21 P20 VCC P17/SEG49 P16/SEG48 P15/SEG47 P14/SEG46 P13/SEG45 P12/SEG44 P11/SEG43 A10/SEG42 P07/SEG41 P06/SEG40 P05/SEG39 P04/SEG38 P03/SEG37 P02/SEG36 P01/SEG35 P00/SEG34 SEG33 (FPT-80P-M11)
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MB89820 Series
(Top view) SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 V3 V2 V1 X1 X0 VSS RST MOD1 MOD0 P45/SCK P44/SO P43/SI P42/PWC/INT1 P41/PWM P40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
101 102 103 104 105 106 107 108 109
93 92 91 90 89 88 87 86 85
Each pin inside the dashed line is for the MB89PV820 only.
SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 VCC SEG30 SEG31 SEG32 SEG33 P00/SEG34 P01/SEG35 P02/SEG36 P03/SEG37 P04/SEG38 P05/SEG39 P06/SEG40 P07/SEG41 P10/SEG42 P11/SEG43
*
Pin assignment on package top (MB89PV820 only) Pin no. 81 82 83 84 85 86 87 88 Pin name N.C. VPP A12 A7 A6 A5 A4 A3 Pin no. 89 90 91 92 93 94 95 96 Pin name A2 A1 A0 N.C. O1 O2 O3 VSS Pin no. 97 98 99 100 101 102 103 104 Pin name N.C. O4 O5 O6 O7 O8 CE A10 Pin no. 105 106 107 108 109 110 111 112 Pin name OE N.C. A11 A9 A8 A13 A14 VCC
N.C.: Internally connected. Do not use. 6
P33 P32 P31 P30/INT0 P25 P24 P23 P22 P21 P20 P17/SEG49 P16/SEG48 P15/SEG47 P14/SEG46 P13/SEG45 P12/SEG44 (MQP-80C-P01)
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
110 111 112 81 82 83 84
100 99 98 97 96 95 94
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MB89820 Series
s PIN DESCRIPTION
Pin no. QFP 3 2 6 5 4
*1
MQFP 14 13 18 17 16
*2
Pin name X0 X1 MOD0 MOD1 RST
Circuit type A B C
Function Clock crystal oscillator pins Operating mode selection pins Connect directly to VSS. Reset I/O pin This pin is an N-ch open-drain type with a pull-up resistor, and a hysteresis input type. "L" is output from this pin by an internal reset source (optional function). The internal circuit is initialized by the input of "L". General-purpose N-ch open-drain I/O ports Also serve as an LCD controller/driver segment output. The port and segment output are switched by mask option in 8-bit unit. General-purpose N-ch open-drain I/O ports Also serve as an LCD controller/driver segment output. The port and segment output are switched by mask option in 4 to 1-bit unit. General-purpose N-ch open-drain I/O ports A pull-up resistor option is provided. General-purpose input port The input is hysteresis input. Also serves as an external interrupt input (INT0). A pull-up resistor option is provided. General-purpose input ports These pins are a hysteresis input type. A pull-up resistor option is provided. General-purpose I/O port A pull-up resistor option is provided. General-purpose I/O port A pull-up resistor option is provided. Also serves as an 8-bit PWM timer toggle output (PWM). General-purpose I/O port A pull-up resistor option is provided. Also serves as an 8-bit pulse width count timer input (PWC) and an external interrupt input (INT1). The PWC and INT1 input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as an 8-bit serial I/O and a UART data input (SI). The SI input is hysteresis input.
39 to 32
50 to 43 P00/SEG34 to P07/SEG41
D
31 to 24
42 to 35 P10/SEG42 to P17/SEG49
D
22 to 17 16
34 to 29 P20 to P25 28 P30/INT0
F H
15 to 13
27 to 25 P31 to P33
H
12 11
24 23
P40 P41/PWM
E E
10
22
P42/PWC/INT1
E
9
21
P43/SI
E
*1: FPT-80P-M11 *2: MQP-80C-P01
(Continued)
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MB89820 Series
(Continued)
Pin no. QFP*1 8 MQFP*2 20 Pin name P44/SO Circuit type E Function General-purpose I/O port A pull-up resistor option is provided. Also serves as a serial I/O and a UART data output (SO). General-purpose I/O port A pull-up resistor option is provided. Also serves as a serial I/O and a UART clock I/O (SCK). The SCK input is hysteresis input. LCD controller/driver segment output pins
7
19
P45/SCK
E
73 to 40
5 to 1, SEG0 to 80 to 56, SEG33 54 to 51 9 to 6 COM0 to COM3 VCC VSS
G
77 to 74 80 to 78 23 1
G -- -- --
LCD controller/driver common output pins LCD driving power supply pins Power supply pin Power supply (GND) pin
12 to 10 V1 to V3 55 15
*1: FPT-80P-M11 *2: MQP-80C-P01
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MB89820 Series
* External EPROM pins (MB89PV820 only) Pin no. 82 83 84 85 86 87 88 89 90 91 93 94 95 96 98 99 100 101 102 103 104 105 107 108 109 110 111 112 81 92 97 106 Pin name VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS O4 O5 O6 O7 O8 CE A10 OE A11 A9 A8 A13 A14 VCC N.C. I/O O O "H" level output pin Address output pins Function
I
Data input pins
O I
Power supply (GND) pin Data input pins
O O O O
ROM chip enable pin Outputs "H" during standby. Address output pin ROM output enable pin Outputs "L" at all times. Address output pins
O O O -- EPROM power supply pin Internally connected pins Be sure to leave them open.
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MB89820 Series
s I/O CIRCUIT TYPE
Type A
X1
Circuit
Remarks * Crystal oscillator circuit * At an oscillation feedback resistor of approximately 1 M/5.0 V
X0
Standby control signal
B C
R P-ch
* At an output pull-up resistor (P-ch) of approximately 50 k/5.0 V * Hysteresis input
N-ch
D
P-ch N-ch P-ch N-ch
* N-ch open-drain output * CMOS input
N-ch Port
* Segment output optional * CMOS output * CMOS input * Hysteresis input (peripheral input)
E
R P-ch P-ch
N-ch Peripheral Port
* Pull-up resistor optional
(Continued)
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MB89820 Series
(Continued)
Type F
R P-ch
Circuit
Remarks * N-ch open-drain output * CMOS input
N-ch
* Pull-up resistor optional G
P-ch N-ch P-ch N-ch
* LCD controller/driver
H
R
* Hysteresis input
* Pull-up resistor optional
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MB89820 Series
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in section "s Electrical Characteristics" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.
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MB89820 Series
s PROGRAMMING TO THE EPROM ON THE MB89P825
The MB89P825 is an OTPROM (one-time PROM) version for the MB89820 series.
1. Features
* 16-Kbyte PROM on chip * Options can be set using the EPROM programmer. * Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in EPROM mode is diagrammed below.
Address 0000H I/O 0080H RAM 0180H Single chip EPROM mode (Corresponding addresses on EPROM programmer)
Not available
8000H Not available BFF0H Option area BFF6H Not available C000H PROM 16 KB FFFFH
0000H Vacancy (Read value FFH) 3FF0H Option area 3FF6H Vacancy (Read value FFH) 4000H EPROM 16 KB 7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P825 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. * Programming procedure
(1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to FFFFH while operating as a single chip assign to 4000H to 7FFFH in EPROM mode). Load option data into addresses 3FF0H to 3FF5H of the EPROM programmer. (For information about each corresponding option, see "7. OTPROM Option Bit Map." (3) Program with the EPROM programmer. 13
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MB89820 Series
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product for a product with a blanked OTPROM microcomputer program.
Program, verify
Aging +150C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Package FPT-80P-M11 Compatible socket adapter ROM-80QF2-28DP-8L3
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
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MB89820 Series
7. OTPROM Option Bit Map
Bit 7 Vacancy 3FF0H Readable Vacancy 3FF1H Readable Vacancy 3FF2H Readable Vacancy 3FF3H Readable Vacancy 3FF4H Readable Vacancy 3FF5H Readable Bit 6 Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Bit 5 Vacancy Readable Vacancy Readable Vacancy Readable P25 Pull-up 1: No 0: Yes P45 Pull-up 1: No 0: Yes Vacancy Readable Bit 4 Vacancy Readable Vacancy Readable Vacancy Readable P24 Pull-up 1: No 0: Yes P44 Pull-up 1: No 0: Yes Vacancy Readable Bit 3 Vacancy Readable Vacancy Readable Vacancy Readable P23 Pull-up 1: No 0: Yes P43 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes Bit 2 Reset pin output 1: Yes 0: No Vacancy Readable Vacancy Readable P22 Pull-up 1: No 0: Yes P42 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes Bit 1 Oscillation stabilization time 1: 217/FC 0: 213/FC Vacancy Readable Vacancy Readable P21 Pull-up 1: No 0: Yes P41 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes Bit 0 Power-on reset 1: Yes 0: No Vacancy Readable Vacancy Readable P20 Pull-up 1: No 0: Yes P40 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes
Notes: * Set each bit to 1 to erase. * Do not write 0 to the vacant bit. The read value of the vacant bit is 1, unless 0 is written to it.
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MB89820 Series
s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32 (Rectangle) Adapter socket part number ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in each mode, such as 32 Kbyte PROM, option area is diagrammed below.
Address 0000H
Single chip I/O
Corresponding addresses in EPROM programmer
0080H RAM 0480H Not available 8000H 0000H
PROM 32 KB
EPROM 32 KB
FFFFH
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0000H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer.
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MB89820 Series
s BLOCK DIAGRAM
X0 X1 20-bit time-base timer
Oscillator
Clock controller 8-bit PWM timer P41/PWM
8-bit pulse width timer/ counter Port 2 N-ch open-drain I/O port 8-bit serial I/O
Noise cancellation
Port 4
RST
Reset circuit (WDT)
Internal bus
External interrupt
P42/PWC/INT1
6 P20 to P25
P45/SCK P44/SO P43/SI
P30/INT0
External interrupt
UART
3 P31 to P33
Port 3
I/O port
CMOS I/O port
P40
RAM
N-ch open-drain I/O port Port 0 and port 1 8 P00/SEG34 to P07/SEG41 8 P10/SEG42 to P17/SEG49 LCD controller/driver 34 SEG0 to SEG33
16 F2MC-8L CPU
ROM
Other pins MOD0, MOD1, VCC, VSS
4 3
COM0 to COM3 V1 to V3
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MB89820 Series
s CPU CORE
1. Memory Space
The microcontrollers of the MB89820 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89820 series is structured as illustrated below. Memory Space
MB89821 MB89823 MB89P825 MB89PV820
0 00 0H I/O 0 08 0H Vacancy 00C0H 0 10 0H 0 14 0H RAM 192 B Register
0000 H 0080 H I/O
0000H 0080H I/O
0000H 0080H I/O
0100 H 0180 H
RAM 256 B Register
0100H 0180H
RAM 256 B Register
0 1 0 0H
RAM 1 KB Register
0200H
0480H Unused Unused Unused Unused
8000H
C000H E000H F0 00 H ROM 4 KB FFFFH FFFFH ROM 8 KB PROM 16 KB External ROM 32 KB
FFFFH
FFFFH
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MB89820 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS): A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code
Initial value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, IL0 = 11 Other bits are undefined.
16 bits PC A T IX EP SP PS
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) Structure of the Program Status Register
15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C
Vacancy Vacancy Vacancy
IL1, 0
RP
CCR
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MB89820 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes b1 b0
"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 Low = no interrupt High-low High
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: V-flag: Set when an arithmetic operation results in 0. Cleared otherwise. Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction.
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MB89820 Series
The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 16 banks can be used on the MB89823 (RAM 256 x 8 bits). The bank currently in use is indicated by the register bank pointer (RP). Note: The number of register banks that can be used varies with the RAM size. MB89821 MB89823 MB89P825 MB89PV820 0100H to 013FH 0100H to 017FH 0100H to 017FH 0100H to 01FFH 8 banks 16 banks 16 banks 32 banks
Register Bank Configuration
This address = 0100 H + 8 x (RP) R0 R1 R2 R3 R4 R5 R6 R7 16 banks Memory area
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MB89820 Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (R/W) (R/W) SMR SDR (R/W) (W) (R/W) (R/W) (R/W) (R/W) CNTR COMR PCR1 PCR2 RLBR NCCR (R/W) (W) PDR4 DDR4 (R) PDR3 (R/W) (R/W) (R/W) STBC WDTC TBCR (R/W) PDR2 (R/W) PDR1 Read/write (R/W) Register name PDR0 Vacancy Port 1 data register Vacancy Port 2 data register Vacancy Vacancy Vacancy Standby control register Watchdog timer control register Time-base timer control register Vacancy Port 3 data register Vacancy Port 4 data register Port 4 data direction register Vacancy Vacancy PWM timer control register PWM timer compare register PWC pulse width control register 1 PWC pulse width control register 2 PWC reload buffer register PWC noise cancellation control register Vacancy Vacancy Vacancy Vacancy Serial mode register Serial data register Vacancy Vacancy Register description Port 0 data register
(Continued)
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MB89820 Series
(Continued)
Address 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H to 5FH 60H to 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH Note: Do not use vacancies. (W) (W) (W) ILR1 ILR2 ILR3 (R/W) (R/W) (R/W) VRAM LCR1 SEGR (R/W) EIC1 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) Register name SMC1 SRC SSD SIDR/SODR SMC2 Register description UART serial mode control register 1 UART serial rate control register UART serial status/data register UART serial data register UART serial mode control register 2 Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy External interrupt 1 control register Vacancy Display data RAM LCD controller/driver control register Segment output selection register Vacancy Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Vacancy
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MB89820 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = 0.0 V) Parameter Power supply voltage LCD power supply voltage Symbol VCC V3 VI1 Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 Max. VSS + 7.0 VSS + 7.0 VCC + 0.3 Unit V V V V3 pin VI1 must not exceed VSS + 7.0 V. Except P00 to P07 and P10 to P17 for the MB89P825/PV820, and P20 to P25 without a pull-up resistor P00 to P07 and P10 to P17 (when selected as ports) for the MB89821/ 823, and P20 to P25 without a pullup resistor P00 to P07 and P10 to P17 for the MB89P825/PV820 VO1 must not exceed VSS + 7.0 V. Except P00 to P07 and P10 to P17 for the MB89P825/PV820, and P20 to P25 without a pull-up resistor P00 to P07 and P10 to P17 (when selected as ports) for the MB89821/ 823, and P20 to P25 without a pullup resistor P00 to P07 and P10 to P17 for the MB89P825/PV820 Except power supply pins Average value (operating current x operating rate) Except power supply pins Except power supply pins Average value (operating current x operating rate) Except power supply pins Remarks
Input voltage VI2 VSS - 0.3 VSS + 7.0 V
VI3
VSS - 0.3
V3 + 0.3
V
VO1
VSS - 0.3
VCC + 0.3
V
Output voltage VO2 VSS - 0.3 VSS + 7.0 V
VO3 "L" level output current "L" level average output current Total "L" level output current "H" level output current "H" level average output current Total "H" level output current Power consumption Operating temperature Storage temperature IOL IOLAV IOL IOH IOHAV IOH PD TA Tstg
VSS - 0.3 -- -- -- -- -- -- -- -40 -55
V3 + 0.3 10 4 40 -5 -2 -10 300 +85 +150
V mA mA mA mA mA mA mW C C
Precautions: Permanent device damage may occur if the above "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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MB89820 Series
2. Recommended Operating Conditions
(VSS = 0.0 V) Parameter Symbol Value Min. 2.2* Power supply voltage VCC 1.5 Max. 6.0* 6.0 Unit V V Remarks Normal operation assurance range* Retains the RAM state in stop mode V3 pin LCD power supply range. The optimum value is dependent on the element in use.
LCD power supply voltage Operating temperature
V3 TA
VSS -40
6.0 +85
V C
* : The minimum operating power supply voltage varies with the operating frequency.
6
5 Operation assurance range Operating voltage (V) 4
3
2
1
1
2
3
4
5
Clock operating frequency (MHz) 4.0 2.0 1.3 1.0 0.8
Minimum execution time (instruction cycle) (s) Note: The shaded area is assured only for the MB89821/823.
Figure 1
Operating Voltage vs. Clock Operating Frequency
Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FC.
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MB89820 Series
3. DC Characteristics
(VCC = V3 = +5.0 V, VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Min. Typ. Max.
Parameter
Symbol
Pin P00 to P07, P10 to P17, P20 to P25, P30 to P33, P40 to P45 RST, MOD0, MOD1, INT0, SCK, SI, PWC/INT1 P00 to P07, P10 to P17, P22 to P25, P30 to P33, P40 to P45 RST, MOD0, MOD1, INT0, SCK, SI, PWC/INT1
Condition
VIH "H" level input voltage VIHS
--
0.7 VCC*1
--
VCC + 0.3*1
V
--
0.8 VCC
--
VCC + 0.3
V
VIL "L" level input voltage VILS
--
VCC - 0.3
--
0.3 VCC*1
V
--
VSS - 0.3
--
0.2 VCC
V P00 to P07 and P10 to P17 (when selected as ports) for the MB89821/823, and P20 to P25 without pull-up resistor
Open-drain output pin application voltage "H" level output voltage "L" level output voltage
VD
P20 to P25, P00 to P07, P10 to P17
--
VSS - 0.3
--
VCC + 6.0
V
VOH
P40 to P45
IOH = -2 mA
2.4
--
--
V
VOL1 VOL2
ILI1 Input leakage current (Hi-z output leakage current) ILI2
P00 to P07, P10 to P17, IOL = 1.8 mA P20 to P25, P40 to P45 RST IOL = 4 mA MOD0, MOD1, P30 to P33, P40 to P45 MOD0, MOD1, 0.0 V < VI < VCC P00 to P07, P10 to P17, P30 to P33, P40 to P45 P00 to P07, P10 to P17, P20 to P25 0.0 V < VI < 6.0 V P20 to P25
-- -- --
-- -- --
0.4 0.4 5
V V A Without pull-up resistor for the MB89821/823 Without pull-up resistor for the MB89P825/PV820 Without pull-up resistor for the MB89821/823 Without pull-up resistor for the MB89P825/PV820
--
--
5
A
--
--
1 1
A A
--
--
(Continued)
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MB89820 Series
(Continued)
(VCC =V3 = +5.0 V, VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Min. Typ. Max. 25 50 100 k With pull-up resistor
Parameter Pull-up resistance
Symbol
Pin P20 to P25, P30 to P33, P40 to P45, RST
Condition
RPULL
V1 = 0.0 V
Common output RVCOM impedance Segment output RVSEG impedance LCD divided RLCD resistance LCD leakage current ILCDL
COM0 to COM3 V1 to V3 = +5.0 V SEG0 to SEG49 V1 to V3 = +5.0 V -- V1 to V3, COM0 to COM3, SEG0 to SEG49 Between V3 and VSS --
-- -- 30 --
-- -- 60 --
2.5 15 120 1
k k k A MB89821, mA MB89823, MB89PV820 mA MB89P825 MB89821, MB89823, mA MB89PV820, MB89P825 A A pF MB89821, MB89823 MB89PV820, MB89P825
ICC
FC = 5 MHz tinst*3 = 0.8 s FC = 5 MHz tinst*3 = 0.8 s Sleep mode TA = +25C Stop mode Other than VCC and VSS f = 1 MHz
-- --
3.5 4.0 1.1
5.0 6.5 1.7
Power supply current*2
ICCS
VCC
--
-- -- --
0.1 0.1 10
1 10 --
ICCH Input capacitance
CIN
*1: The input voltage to P00 to P07 and P10 to P17 for the MB89P825/PV820 must not exceed the LCD power supply voltage (V3 pin voltage). *2: The measurement condition of power supply current is as follows: the external clock, open output pins and the external LCD dividing resistor. In the case of the MB89PV820, the current consumed by the connected EPROM and ICE is not included. *3: For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics."
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MB89820 Series
4. AC Characteristics
(1) Reset Timing (VCC = +5.0 V10%, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. -- 48 tXCYL -- ns
Parameter RST "L" pulse width
Symbol t ZLZH
tZLZH
RST
0.2 VCC 0.2 VCC
(2) Power-on Reset (VSS = 0.0 V, TA = -40C to +85C) Parameter Power supply rising time Power supply cut-off time Symbol tR -- tOFF 1 -- ms Condition Value Min. -- Max. 50 Unit ms Remarks Power-on reset function only Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
2.0 V
VCC
0.2 V 0.2 V tOFF 0.2 V
tR
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MB89820 Series
(3) Clock Timing (VSS = 0.0 V, TA = -40C to +85C) Parameter Clock frequency Clock cycle time Input clock duty ratio* Input clock rising/ falling time Symbol FC tXCYL duty tCR tCF X0 X0, X1 -- Pin Condition Value Min. 1 200 30 -- Typ. -- -- -- -- Max. 5 1000 70 10 Unit MHz ns % ns Crystal or ceramic resonator External clock External clock Remarks
* : duty = PWH/tHCYL, PWL/tHCYL
X0 and X1 Timing and Conditions
tXCYL PWH tCR 0.8 VCC 0.8 VCC tCF PWL
X0
0.2 VCC 0.2 VCC 0.2 VCC
Clock Conditions
When a crystal or ceramic resonator is used
When an external clock in use
X0
X1 FC
X0
X1 Open FC
C0
C1
(4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol tinst Value (typical) 4/FC Unit s Remarks tinst = 0.8 s when operating at FC = 5 MHz
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MB89820 Series
(5) Serial I/O Timing (VCC = +5.0 V10%, VSS = 0.0 V, TA = -40C to +85C) Parameter Serial clock cycle time SCK SO time Valid SI SCK SCK valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SO time Valid SI SCK SCK valid SI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK SCK, SO Internal shift clock SI, SCK mode SCK, SI SCK External SCK, SO shift clock mode SI, SCK SCK, SI Condition Value Min. 2 tinst* -200 0.5 tinst* 0.5 tinst* 1 tinst* 1 tinst* 0 0.5 tinst* 0.5 tinst* Max. -- 200 -- -- -- -- 200 -- -- Unit s ns s s s s ns s s Remarks
* : For information on tinst, see "(4) Instruction Cycle." (6) UART Timing (VCC = +5.0 V10%, VSS = 0.0 V, TA = -40C to +85C) Parameter Serial clock cycle time SCK SO time Valid SI SCK SCK valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SO time Valid SI SCK SCK valid SI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK SCK, SO Internal shift clock SI, SCK mode SCK, SI SCK External SCK, SO shift clock mode SI, SCK SCK, SI Condition Value Min. 2 tinst* -200 0.5 tinst* 0.5 tinst* 1 tinst* 1 tinst* 0 0.5 tinst* 0.5 tinst* Max. -- 200 -- -- -- -- 200 -- -- Unit s ns s s s s ns s s Remarks
* : For information on tinst, see "(4) Instruction Cycle."
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MB89820 Series
Internal Shift Clock Mode
tSCYC
SCK
0.8 V tSLOV
2.4 V 0.8 V
SO
2.4 V 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SI
0.2 VCC
External Shift Clock Mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
SCK
0.2 VCC tSLOV
0.2 VCC
SO
2.4 V 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SI
0.2 VCC
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MB89820 Series
(7) Peripheral Input Timing (VCC = +5.0 V10%, VSS = 0.0 V, TA = -40C to +85C) Parameter Peripheral input "H" pulse width Peripheral input "L" pulse width Symbol tILIH tIHIL Pin Condition Value Min. 2 tinst* -- 2 tinst* -- s Max. -- Unit s Remarks
PWC/INT1 INT0
* : For information on tinst, see "(4) Instruction Cycle."
tILIH 0.8 VCC
tIHIL 0.8 VCC
PWC/INT1 INT0
0.2 VCC
0.2 VCC
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MB89820 Series
s EXAMPLE CHARACTERISTICS
(1) "L" Level Output Voltage (2) "H" Level Output Voltage
VOL1 (V) 0.6 TA = +25C 0.5 0.4 0.3 0.2 0.1 0
VOL vs. IOL VCC = 2.5 V VCC = 3.0 V VCC = 2.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V
VCC - VOH vs. IOH VCC = 2.5 V VCC - VOH (V) VCC = 2.0 V VCC = 3.0 V 1.0 TA = +25C 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V
0
1
2
3
4
5
6
7
8
9 10 IOL (mA)
0
0
-1
-2
-3
-4
-5 IOH (mA)
(3)
"H" Level Input Voltage/"L" Level Input Voltage (CMOS Input)
(4)
"H" level Input Voltage/"L" Level Input Voltage (CMOS Hysteresis Input)
VIN vs. VCC
VIN vs. VCC VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1 2 3 4 5 6 7 VCC (V) TA = +25C
VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1 2 3 4
TA = +25C VIHS
VILS
5
6
7 VCC (V)
VIHS: Threshold when input voltage in hysteresis characteristics is set to "H" level VILS: Threshold when input voltage in hysteresis characteristics is set to "L" level
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MB89820 Series
(5) Power Supply Current (External Clock)
ICC vs. V CC ICC(mA) 5.0 4.5 FC = 5 MHz 4.0 FC = 4.2 MHz 3.5 3.0 2.5 2.0 1.5 FC = 1 MHz 1.0 0.5 0 1 2 3 4 5 6 7 VCC (V) FC = 3 MHz TA = +25C ICCS (mA) 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 2 3 4 5 6 7 VCC (V) FC = 1 MHz FC = 4.2 MHz FC = 3 MHz ICCS vs. VCC TA = +25C FC = 5 MHz
(6) Pull-up Resistance
RPULL vs. VCC RPULL (k) 1,000 500 TA = +25C
100 50 TA = +25C
10 1 2 3 4 5 6 7 VCC (V)
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MB89820 Series
s INSTRUCTIONS
Execution instructions can be divided into the following four groups: * * * * Transfer Arithmetic operation Branch Others
Table 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Meaning
(Continued)
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MB89820 Series
(Continued)
Symbol EP PC SP PS dr CCR RP Ri x (x) (( x )) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very x is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Meaning
Columns indicate the following: Mnemonic: ~: #: Operation: TL, TH, AH: Assembler notation of an instruction Number of instructions Number of bytes Operation of an instruction A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: * "-" indicates no change. * dH is the 8 upper bits of operation description data. * AL and AH must become the contents of AL and AH immediately before the instruction is executed. * 00 becomes 00. N, Z, V, C: OP code: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F This indicates 48, 49, ... 4F.
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MB89820 Series
Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) (A) ( (IX) +off ) (A) (ext) (A) ( (EP) ) (A) (Ri) (A) (A) d8 (A) (dir) (A) ( (IX) +off) (A) (ext) (A) ( (A) ) (A) ( (EP) ) (A) (Ri) (dir) d8 ( (IX) +off ) d8 ( (EP) ) d8 (Ri) d8 (dir) (AH),(dir + 1) (AL) ( (IX) +off) (AH), ( (IX) +off + 1) (AL) (ext) (AH), (ext + 1) (AL) ( (EP) ) (AH),( (EP) + 1) (AL) (EP) (A) (A) d16 (AH) (dir), (AL) (dir + 1) (AH) ( (IX) +off), (AL) ( (IX) +off + 1) (AH) (ext), (AL) (ext + 1) (AH) ( (A) ), (AL) ( (A) ) + 1) (AH) ( (EP) ), (AL) ( (EP) + 1) (A) (EP) (EP) d16 (IX) (A) (A) (IX) (SP) (A) (A) (SP) ( (A) ) (T) ( (A) ) (TH),( (A) + 1) (TL) (IX) d16 (A) (PS) (PS) (A) (SP) d16 (AH) (AL) (dir): b 1 (dir): b 0 (AL) (TL) (A) (T) (A) (EP) (A) (IX) (A) (SP) (A) (PC) TL - - - - - AL AL AL AL AL AL AL - - - - - - - - - AL AL AL AL AL AL - - - - - - - - - - - - - - - AL AL - - - - TH - - - - - - - - - - - - - - - - - - - - - AH AH AH AH AH AH - - - - - - - - - - - - - - - - AH - - - - AH - - - - - - - - - - - - - - - - - - - - - dH dH dH dH dH dH dH - - dH - dH - - - dH - - AL - - - dH dH dH dH dH NZVC ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++++ ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0
Notes: * During byte transfer to A, T A is restricted to low bytes. * Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family)
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MB89820 Series
Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 Arithmetic Operation Instructions (62 instructions) # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Operation (A) (A) + (Ri) + C (A) (A) + d8 + C (A) (A) + (dir) + C (A) (A) + ( (IX) +off) + C (A) (A) + ( (EP) ) + C (A) (A) + (T) + C (AL) (AL) + (TL) + C (A) (A) - (Ri) - C (A) (A) - d8 - C (A) (A) - (dir) - C (A) (A) - ( (IX) +off) - C (A) (A) - ( (EP) ) - C (A) (T) - (A) - C (AL) (TL) - (AL) - C (Ri) (Ri) + 1 (EP) (EP) + 1 (IX) (IX) + 1 (A) (A) + 1 (Ri) (Ri) - 1 (EP) (EP) - 1 (IX) (IX) - 1 (A) (A) - 1 (A) (AL) x (TL) (A) (T) / (AL),MOD (T) (A) (A) (T) (A) (A) (T) (A) (A) (T) (TL) - (AL) (T) - (A) C A CA (A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) TL - - - - - - - - - - - - - - - - - - - - - - - dL - - - - - - - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - - - - - - - 00 - - - - - - - - - - - - - - - - - - - - - - - AH - - - - - dH - - - - - - dH - - - - dH - - - dH dH 00 dH dH dH - - - - - - - - - - - - - - - - - - - - NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++- ---- ---- ++-- +++- ---- ---- ++-- ---- ---- ++R- ++R- ++R- ++++ ++++ ++-+ ++-+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 toDF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65
(Continued)
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MB89820 Series
(Continued)
Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 # 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (dir) - d8 ( (EP) ) - d8 ( (IX) +off) - d8 (Ri) - d8 (SP) (SP) + 1 (SP) (SP) - 1 TL - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - - NZVC ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++++ ++++ ++++ ++++ ---- ---- OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1
Table 4 Branch Instructions (17 instructions) Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 # 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Operation If Z = 1 then PC PC + rel If Z = 0 then PC PC + rel If C = 1 then PC PC + rel If C = 0 then PC PC + rel If N = 1 then PC PC + rel If N = 0 then PC PC + rel If V N = 1 then PC PC + rel If V N = 0 then PC PC + reI If (dir: b) = 0 then PC PC + rel If (dir: b) = 1 then PC PC + rel (PC) (A) (PC) ext Vector call Subroutine call (PC) (A),(A) (PC) + 1 Return from subrountine Return form interrupt TL - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - dH - - NZVC ---- ---- ---- ---- ---- ---- ---- ---- -+-- -+-- ---- ---- ---- ---- ---- ---- Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30
Table 5 Other Instructions (9 instructions) Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI ~ 4 4 4 4 1 1 1 1 1 # 1 1 1 1 1 1 1 1 1 Operation TL - - - - - - - - - TH - - - - - - - - - AH - dH - - - - - - - NZVC ---- ---- ---- ---- ---- ---R ---S ---- ---- OP code 40 50 41 51 00 81 91 80 90
39
40
3 PUSHW A SETC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP A A,ext POPW MOV MOVW CLRI A,PS SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC 4 5 6 7 8 9 A B C D E F XCH A A XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS XCHW XORW ANDW ORW A, T A A A A, T A A A XOR AND OR MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX MOVW MOVW CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC
L
H
0
1
2
0
NOP
SWAP
RET
RETI
1
MULU
DIVU
A
A
JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A
2
ROLC
CMP
ADDC
SUBC
A
A
A
s INSTRUCTION MAP
3
RORC
CMPW
ADDCW
SUBCW
A
A
A
MB89820 Series
4
MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8
5
MOV
CMP
A,dir
A,dir
ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP
6 CMP @EP,#d8
CMP CLRB BBC MOVW MOVW MOVW XCHW MOV CMP ADDC SUBC MOV XOR AND OR MOV dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 CLRB BBC MOVW MOVW MOVW XCHW dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 R7 R6 CALLV #7 R5 CALLV #6 BLT rel R4 CALLV #5 BGE rel R3 CALLV #4 BZ rel R2 CALLV #3 BNZ rel R1 CALLV #2 BN rel R0 CALLV #1 BP rel CALLV #0 BC rel BNC rel
7
MOV CMP ADDC SUBC MOV XOR AND OR MOV A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8
8
MOV
CMP
A,R0
A,R0
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel
9
MOV
CMP
A,R1
A,R1
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel
A
MOV
CMP
A,R2
A,R2
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel
B
MOV
CMP
A,R3
A,R3
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel
C
MOV
CMP
A,R4
A,R4
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel
D
MOV
CMP
A,R5
A,R5
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel
E
MOV
CMP
A,R6
A,R6
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel
F
MOV
CMP
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A,R7
A,R7
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel
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MB89820 Series
s MASK OPTIONS
Part number No. Specifying procedure Pull-up resistors P20 to P25, P30 to P33, P40 to P45 Power-on reset With power-on reset Without power-on reset Oscillation stabilization time selection (FC = 5 MHz)*1 Approx. 217/FC (Approx. 26.2 ms) Approx. 213/FC (Approx. 1.64 ms) Reset pin output With reset output Without reset output Segment output switching 50 segments: No port selection 49 segments: Selection of P17 48 segments: Selection of P17 to P16 46 segments: Selection of P17 to P14 42 segments: Selection of P17 to P10 34 segments: Selection of P17 to P10 and P07 to P00 MB89821/823 Specify when ordering masking Selectable by pin Selectable MB89P825 Set with EPROM programmer Can be set per pin Can be set MB89PV820 Setting not possible (Fixed) Without pull-up resistor With power-on reset Oscillation stabilization time Approx. 217/FC (Approx. 26.2 ms) With reset output
1 2
3
Selectable
Can be set
4
Selectable
Can be set
5
Selectable*2
Can be set*3
Can be set*3
*1: The oscillation settling time is generated by dividing the oscillation clock frequency. Since the oscillation period is not stable immediately after oscillation has been started, therefore, the oscillation settling time in the above list should be regarded as a reference. *2: Port selection must be same setting of the segment output selection register of LCD controller. *3: Note that, when ports are set, the input voltage value for the port pins are different from those for mask ROM products. Ports are set by the register setting of the segment output selection register of LCD controller.
s ORDERING INFORMATION
Part number MB89821PFM MB89823PFM MB89P825PFM MB89PV820CF Package 80-pin Plastic QFP (FPT-80P-M11) 80-pin Ceramic MQFP (MQP-80C-P01) Remarks
41
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MB89820 Series
s PACKAGE DIMENSIONS
80-pin Plastic QFP (FPT-80P-M11)
16.000.20(.630.008)SQ
60
14.000.10(.551.004)SQ
41
1.50 -0.10 +.008 .059 -.004
+0.20
61
40
12.35 15.00 (.486) (.591) REF NOM
1 PIN INDEX
80 21
LEAD No.
1 20
"A" 0.300.10 (.012.004) 0.13(.005)
M
Details of "A" part 0.127 .005
+0.05 -0.02 +.002 -.001
0.65(.0256)TYP
0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0
10
0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F80016S-1C-2
Dimensions in mm (inches)
80-pin Ceramic MQFP (MQP-80P-P01)
18.70(.736)TYP 12.00(.472)TYP 16.300.33 (.642.013) 15.580.20 (.613.008) 1.50(.059)TYP 1.00(.040)TYP 4.50(.177) TYP 1.20 -0.20 +.016 .047 -.008
+0.40
INDEX AREA
0.800.25 (.0315.010) 0.800.25 (.0315.010)
1.270.13 (.050.005) 22.300.33 (.878.013) 24.70(.972) TYP 0.30(.012) TYP 18.120.20 12.02(.473) (.713.008) TYP 10.16(.400) 14.22(.560) TYP TYP
INDEX AREA 18.40(.724) REF
INDEX 6.00(.236) TYP 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.400.10 (.016.004) 1.50(.059) TYP 1.00(.040) TYP
1.270.13 (.050.005)
0.400.10 (.016.004)
1.20 -0.20 +.016 .047 -.008
+0.40
0.150.05 8.70(.343) (.006.002) MAX
C
1994 FUJITSU LIMITED M80001SC-4-2
Dimensions in mm (inches)
42
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MB89820 Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281 0770 Fax: (65) 281 0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9703 (c) FUJITSU LIMITED
Printed in Japan
44

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