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| NJU26150 General Description General Purpose Digital Signal Processor Package The NJU26150 is a high performance 24-bit general purpose digital signal processor. The NJU26150 has an internal program memory to download outside EEPROM program. After download, the NJU26150 starts automatically. The NJU26150 is suitable for any kind of audio products, such as AV Receiver, Car Audio. FEATURES NJU26150 Pin assignment is same as the NJU26100 Series. The common PCB is available for the NJU26150. After being ROMed (NJU26100 Series), no change is necessary for PCB and host processor program. The NJU26150 is useful for reducing time-to-market and a product with specification-change possibility. 2K words Delay Memory (word=16bits) 4K words Program Memory (word=16bits) Digital Signal Processor Specification 24bit Fixed-point Digital Signal Processing Maximum Clock Frequency : 38MHz Digital Audio Interface : 3 Input ports / 3 Output ports Power Supply : DSP Core : 2.5V, I/O interface: 2.5V ( +3.3V tolerant ) Package : QFP 32pin The detail hardware specification of the NJU26150 is described in the " NJU26100 Series Hardware Data Sheet". In respect to software commands, request NJR. Ver.2003-08-25 -1- NJU26150 Function Block Diagram AD1/SDIN AD2/ SSX NJU26150 DSP ARITHMETIC UNIT SERIAL AUDIO INTERFACE BCKO LRO SDO0 24-BIT x 24-BIT MULTIPLIER ALU SDO1 SDO2 SDI0 SDI1 SCL/SCK SDA/SDOUT SERIAL HOST INTERFACE PROGRAM CONTROL RESETX MCK XI XO TIMING GENERATOR ADDRESS GENERATION UNIT SDI2 BCKI LRI DELAY RAM DATA RAM BOOT ROM PROGRAM RAM GPIO AND CONFIGURATION INTERFACE SCL2 SDA2 Fig. 1 NJU26150 Block Diagram -2- Ver.2003-08-25 NJU26150 Pin Configuration VDDR VDDR VDDC VDDC VSSR 24 VSSR 23 VSSC VSSC 22 21 20 19 18 17 SDI0 SDI1 SDI2 LRI BCKI MCK BCKO LRO 25 SCL2 VSSC VDDC RESETX VSSO XO XI VDDO 16 26 15 27 14 28 13 NJU26150 29 30 31 32 1 12 11 10 9 2 3 4 5 6 7 8 SCL/SCK SDA/SDOUT AD1/SDIN AD2/SSX Fig. 2 NJU26150 Pin Configuration SDO2 SDO1 SDO0 SDA2 Ver.2003-08-25 -3- NJU26150 Pin Description Table 1 Pin Description No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name SDO2 SDO1 SDO0 SDA2 SCL/SCK SDA/SDOUT AD1/SDIN AD2/SSX VDDO XI XO VSSO RESETX VDDC VSSC SCL2 I/O O O O IO I IO I I P I O G I P G IO Pin Description Audio Data Output 2 Audio Data Output 1 Audio Data Output 0 I/O Data, Pull-up No. 17 18 19 20 21 22 23 24 25 26 27 28 29 Pin Name VDDC VDDC VSSC VSSC VDDR VDDR VSSR VSSR SDI0 SDI1 SDI2 LRI BCKI MCK BCKO LRO I/O P P G G P P G G I I I I I O O O Pin Description DSP Core Supply +2.5V DSP Core Supply +2.5V DSP Core Supply GND DSP Core Supply GND I/O Power +2.5V I/O Power +2.5V I/O Power GND I/O Power GND Power Power Power Power Supply Supply Supply Supply I2C clock / Serial clock I2C I/O / Serial Out I2C Address / Serial In I2C Address/Serial enable OSC Power Supply +2.5V OSC Clock Input OSC Clock Output OSC Power Supply GND Reset Audio Data Input 0 Audio Data Input 1 Audio Data Input 2 LR Clock Input Bit Clock Input A/D,D/A Clock Output Bit Clock Output LR Clock Output DSP Core Power Supply 30 +2.5V DSP Core Power Supply 31 GND Clock Output 32 * I : Input, O : Output, IO : Bi-directional, P : +Power, G : GND * Package is shown in fig. 3. -4- Ver.2003-08-25 NJU26150 Audio Data Output The NJU26150 audio interface provides industry standard serial data formats of I2S, MSB-first left-justified or MSB-first right-justified. The NJU26150 audio interface provides three data inputs, SDI0, SDI1,SDI2 and three data outputs, SDO0, SDO1, SDO2 as shown in table 2 and 3. Table 2 Symbol SDI0 SDI1 SDI2 Serial Audio Input Pin Pin No. 25 26 27 Description Audio Data Input 0 Audio Data Input 1 Audio Data Input 2 Table 3 Symbol SDO0 SDO1 SDO2 Serial Audio Output Pin Pin No. 3 2 1 Description Audio Data Output 0 Audio Data Output 1 Audio Data Output 2 I C address 2 AD1 and AD2 pins are used to configure the seven-bit SLAVE address of the serial host interface. These pins offer additional flexibility to SLAVE address. 4 addresses could be chosen by AD1 and AD2-pin. The AD1 and AD2-pin addresses are decided by the connections of AD1 and AD2-pin. The AD1 and AD2 addresses should be the same level as AD1 and AD2-pin connections. . Table 4 I2C Bus SLAVE Address bit7 bit6 bit5 bit4 Bit3 bit2 bit1 bit0 0 0 1 1 1 AD2*1 AD1*1 R/W *1 AD1 or AD2 address is 0 when AD1 or AD2-pin is "L". AD1 or AD2 address is 1 when AD1 or AD2-pin is "H". The detail I2C bus timing of the NJU26150 is described in the " NJU26100 Series Hardware Data Sheet". Ver.2003-08-25 -5- NJU26150 Application The application circuit diagram of the NJU26150 is shown in Fig.3a and Fig.3b. The NJU26150 and EEPROM realize the function of the NJU261xx shown in Fig.3a. The program exists in EEPROM. The program is downloaded into the NJU26150. The NJU26150 pin 4 (SDA2) should be connected to VDD through a 4.7K-ohm resister. The NJU261xx pin connections are shown in Fig.3b. The EEPROM is deleted. In case of selecting I2C, the NJU261xx pin 4(SEL1) should be connected to GND through a 4.7K ohm resister. *Notice: In case of selecting Serial bus, the NJU261xx pin 4 (SEL1) should be connected to VDD through a 4.7K ohm resister. 4.7K Micro Processor 6 5 8 7 SDA SCL AD2 AD1 /SDOUT /SCK /SSX /SDIN 0.1uF 1 2 3 4 A0 A1 A2 VSS VCC WP SCL SDA 8 7 6 5 4.7K 16 4 SCL2 SDA2 NJU26150 I2C Serial EEPROM 24LC64 - I/P (Microchip) Fig. 3a NJU26150 application on circuit diagram ROM Micro Processor 4.7K 6 5 8 7 8 7 6 5 4.7K 16 4 TEST2 SEL1 SDA SCL AD2 AD1 /SDOUT /SCK /SSX /SDIN 0.1uF 1 2 3 4 A0 A1 A2 VSS VCC WP SCL SDA NJU261xx Fig. 3b NJU261xx application on circuit diagram -6- Ver.2003-08-25 NJU26150 Download Procedure The procedure of the download to the NJU26150 is described as follows. 1) Micro Processor releases RESET. 2) The NJU26150 starts download procedure from EEPROM automatically. 3) Send NOP command (0xff) and read the NJU26150 in order to check download procedure. When the reply status is 0x83, the download procedure is under running. When the reply status is 0x80, the download procedure is finished. * In download procedure, the NJU26150 does not accept the command. The unacceptable command period is shown in table 5. Table 5 Unacceptable command time after RESET System Clock Fs Unacceptable command time after RESET 36.864MHz 48KHz 1sec 33.868MHz 44.1KHz 1sec 24.576MHz 32KHz 1.5sec Table 6 EEPROM List ( Reference Data ) Maker Part Number VDD ATMEL AT24C64 1.8 - 5.5V Micro Chip 24AA64 1.8 - 5.5V 24LC64 2.5 - 5.5V SAMSUNG KS24L641 2.0 - 5.5V SII S-24CV64A 1.8 - 5.5V AKM AK6012AF 1.8 - 5.5V ST-Micro M24C64-R 1.8 - 5.5V Rohm BR24C64/F 2.7 - 5.5V Hitachi HN58X2464 1.8 - 5.5V Package PDIP, SOIC, TSSOP PDIP, SOIC, TSSOP, MSOP DIP, SOP DIP, SOP, TSSOP SOP PDIP, SO, TSSOP DIP, SOP SOP, TSSOP License Information 1. Purchase of I2C components of New Japan Radio Co. ,Ltd or one of sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard specification as defined by Philips. Ver. 1.20 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2003-08-25 -7- |
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