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XCR5064: 64 Macrocell CPLD
0 14*
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Product Specification CPLD. These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. For 3V applications, Xilinx also offers the high speed PZ3064 CPLD that offers these features in a full 3V implementation. The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 7.5 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2.0 ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 9.5 ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. The XCR5064 CPLDs are supported by industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses a Xilinx developed tool, XPLA Professional (available on the Xilinx web site). The XCR5064 CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others.
Features.
* * * * * * * * * * * * * * * * * * * Industry's first TotalCMOSTM PLD - both CMOS design and process technologies Fast Zero Power (FZPTM) design technique provides ultra-low power and very high speed High speed pin-to-pin delays of 7.5 ns Ultra-low static power of less than 100 A 100% routable with 100% utilization while all pins and all macrocells are fixed Deterministic timing model that is extremely simple to use Four clocks available Programmable clock polarity at every macrocell Support for asynchronous clocking Innovative XPLATM architecture combines high speed with extreme flexibility 1000 erase/program cycles guaranteed 20 years data retention guaranteed Logic expandable to 37 product terms PCI compliant Advanced 0.5 E2CMOS process Security bit prevents unauthorized access Design entry and verification using industry standard and Xilinx CAE tools Reprogrammable using industry standard device programmers Innovative Control Term structure provides either sum terms or product terms in each logic block for: - Programmable 3-state buffer - Asynchronous macrocell register preset/reset Programmable global 3-state pin facilitates bed of nails' testing without using logic resources Available in PLCC,VQFP, and PQFP packages Available in both Commercial and Industrial grades
* * *
Description
The XCR5064 CPLD (Complex Programmable Logic Device) is the second in a family of CoolRunner(R) CPLDs from Xilinx. These devices combine high speed and zero power in a 64 macrocell CPLD. With the FZP design technique, the XCR5064 offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 A at standby without the need for ` turbo bits' or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing DS043 (v1.3) October 9, 2000
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XCR5064: 64 Macrocell CPLD
XPLA Architecture
Figure 1 shows a high level block diagram of a 64 macrocell device implementing the XPLA architecture. The XPLA architecture consists of logic blocks that are interconnected by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a 36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic block also provides 32 ZIA feedback paths from the macrocells and I/O pins. From this point of view, this architecture looks like many other CPLD architectures. What makes the CoolRunner family unique is what is inside each logic block and the design technique used to implement these logic blocks. The contents of the logic block will be described next.
figured as either SUM or PRODUCT terms, and are used to control the preset/reset and output enables of the 16 macrocells' flip-flops. The PAL array consists of a programmable AND array with a fixed OR array, while the PLA array consists of a programmable AND array with a programmable OR array. The PAL array provides a high speed path through the array, while the PLA array provides increased product term density. Each macrocell has five dedicated product terms from the PAL array. The pin-to-pin tPD of the XCR5064 device through the PAL array is 7.5 ns. If a macrocell needs more than five product terms, it simply gets the additional product terms from the PLA array. The PLA array consists of 32 product terms, which are available for use by all 16 macrocells. The additional propagation delay incurred by a macrocell using one or all 32 PLA product terms is just 2.0 ns. So the total pin-to-pin tPD for the XCR5064 using six to 37 product terms is 9.5 ns (7.5 ns for the PAL + 2.0 ns for the PLA).
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic block contains control terms, a PAL array, a PLA array, and 16 macrocells. the six control terms can individually be con-
MC1 MC2 I/O MC16 16 16 ZIA MC1 MC2 I/O MC16 16 16 16 16 LOGIC BLOCK 36 36 LOGIC BLOCK 16 16 LOGIC BLOCK 36 36 LOGIC BLOCK
MC1 MC2 I/O MC16
MC1 MC2 I/O MC16
SP00439
Figure 1: Xilinx XPLA CPLD Architecture
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XCR5064: 64 Macrocell CPLD
36 ZIA INPUTS
CONTROL 5
6
PAL ARRAY
PLA ARRAY
(32) SP00435A
Figure 2: Xilinx XPLA Logic Block Architecture
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TO 16 MACROCELLS
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XCR5064: 64 Macrocell CPLD Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in the CoolRunner family. The macrocell consists of a flip-flop that can be configured as either a D- or T-type. A D-type flip-flop is generally more useful for implementing state machines and data buffering. A T-type flip-flop is generally more useful in implementing counters. All CoolRunner family members provide both synchronous and asynchronous clocking and provide the ability to clock off either the falling or rising edges of these clocks. These devices are designed such that the skew between the rising and falling edges of a clock are minimized for clocking integrity. There are 4 clocks available on the XCR5064 device. Clock 0 (CLK0) is designated as the "synchronous" clock and must be driven by an external source. Clock 1 (CLK1), Clock 2 (CLK2), and Clock 3 (CLK3) can either be used as a synchronous clock (driven by an external source) or as an asynchronous clock (driven by a macrocell equation). The timing for asynchronous clocks is different in that the tCO time is extended by the amount of time that it takes for the signal to propagate through the array and reach the clock network, and the tSU time is reduced. Two of the control terms (CT0 and CT1) are used to control the Preset/Reset of the macrocell's flip-flop. The Preset/Reset feature for each macrocell can also be disabled. Note that the Power-on Reset leaves all macrocells in the "zero" state when power is properly applied. The other four control terms (CT2-CT5) can be used to control the Output Enable of the macrocell's output buffers. The reason there are as many control terms dedicated for the Output Enable of the macrocell is to insure that all CoolRunner devices are PCI compliant. The macrocell's output buffers can also be always enabled or disabled. All CoolRunner devices also provide a Global 3-state (GTS) pin, which, when enabled and pulled Low, will 3-state all the outputs of the device. This pin is provided to support "In-Circuit Testing" or "Bed-of-Nails Testing". There are two feedback paths to the ZIA: one from the macrocell, and one from the I/O pin. The ZIA feedback path before the output buffer is the macrocell feedback path, while the ZIA feedback path after the output buffer is the I/O pin ZIA path. When the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented in the macrocell. When the I/O pin is used as an input, the output buffer will be 3-stated and the input signal will be fed into the ZIA via the I/O feedback path, and the logic implemented in the buried macrocell can be fed back to the ZIA via the macrocell feedback path. It should be noted that unused inputs or I/Os should be properly terminated.
Terminations
The CoolRunner XCR5064 CPLDs are TotalCMOS devices. As with other CMOS devices, it is important to consider how to properly terminate unused inputs and I/O pins when fabricating a PC board. Allowing unused inputs and I/O pins to float can cause the voltage to be in the linear region of the CMOS input structures, which can increase the power consumption of the device. The XCR5064 CPLDs have programmable on-chip pull-down resistors on each I/O pin. These pull-downs are automatically activated by the fitter software for all unused I/O pins. Note that an I/O macrocell used as buried logic that does not have the I/O pin used for input is considered to be unused, and the pull-down resistors will be turned on. We recommend that any unused I/O pins on the XCR5064 device be left unconnected. There are no on-chip pull-down structures associated with the dedicated input pins. Xilinx recommends that any unused dedicated inputs be terminated with external 10k pull-up resistors. These pins can be directly connected to V CC or GND, but using the external pull-up resistors maintains maximum design flexibility should one of the unused dedicated inputs be needed due to future design changes.
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XCR5064: 64 Macrocell CPLD
TO ZIA
PAL PLA D/T INIT (P or R) CLK0 CLK0 CLK1 CLK1 CLK2 CLK2 CLK3 CLK3 CT0 CT1 GND CT2 CT3 CT4 CT5 VCC GND SP00457 Q
GTS GND
Figure 3: XCR5064 Macrocell Architecture
Simple Timing Model
Figure 4 shows the CoolRunner Timing Model. The CoolRunner timing model looks very much like a 22V10 timing model in that there are three main timing parameters, including tPD , tSU, and tCO. In other architectures, the user may be able to fit the design into the CPLD, but is not sure whether system timing requirements can be met until after the design has been fit into the device. This is because the timing models of competing architectures are very complex and include such things as timing dependencies on the number of parallel expanders borrowed, sharable expanders, varying number of X and Y routing channels used, etc. In the XPLA architecture, the user knows up front whether the design will meet system timing requirements. This is due to the simplicity of the timing model. For example, in the XCR5064 device, the user knows up front that if a given output uses 5product terms or less, the tPD = 7.5 ns, the
tSU_PAL = 4 ns, and the tCO = 5.5 ns. If an output is using six to 37 product terms, an additional 2 ns must be added to the tPD and tSU timing parameters to account for the time to propagate through the PLA array.
TotalCMOS Design Technique for Fast Zero Power
Xilinx is the first to offer a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its Sum of Products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLD which are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 5 and Table 1 showing the ICC vs. Frequency of our XCR5064 TotalCMOS CPLD.
INPUT PIN
tPD_PAL = COMBINATORIAL PAL ONLY tPD_PLA = COMBINATORIAL PAL + PLA
OUTPUT PIN
INPUT PIN
REGISTERED tSU_PAL = PAL ONLY tSU_PLA = PAL + PLA
D
Q
REGISTERED tCO
OUTPUT PIN
GLOBAL CLOCK PIN
SP00441
Figure 4: CoolRunner Timing Model
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XCR5064: 64 Macrocell CPLD
180 160 140 120 100 ICC (mA) 80 60 40 20 0 TYPICAL
0
20
40
60
80
100
120
140
FREQUENCY (MHz) SP00450A
Figure 5: VCC vs. Frequency at VCC = 5.0V, 25C
Table 1: ICC vs. Frequency (VCC = 5.0V. 25C) Frequency (MHz) Typical ICC (mA) 0 0.08 20 24 40 47 60 72 80 92 100 114 120 141 140 163
Absolute Maximum Ratings1
Symbol VCC VI VOUT IIN IOUT TJ Tstr
Notes: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. 2. The chip supply voltage must rise monotonically.
Parameter Supply voltage2 Input voltage Output voltage Input current Output current Maximum junction temperature Storage temperature
Min. -0.5 -1.2 -0.5 -30 -100 -40 -65
Max. 7.0 VCC +0.5 VCC +0.5 30 100 150 150
Unit V V V mA mA C C
Operating Range
Product Grade Commercial Industrial Temperature 0 to +70C -40 to +85C Voltage 5.0V +5% 5.0V +10%
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XCR5064: 64 Macrocell CPLD
DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0C TAMB +70C; 4.75V VCC 5.25V Symbol VIL VIH VI VOL VOH II IOZ ICCQ1 ICCD1, 2 IOS CIN CCLK CI/O
Notes: 1. See Table 1 on page 6 for typical values. 2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing. 3. Typical values, not tested.
Parameter Input voltage low Input voltage high Input clamp voltage Output voltage low Output voltage high Input leakage current 3-stated output leakage current Standby current Dynamic current Short circuit output current3 Input pin capacitance3 Clock input capacitance3 I/O pin capacitance3
Test Conditions V CC = 4.75V V CC = 5.25V V CC = 4.75V, IIN = -18 mA V CC = 4.75V, IOL = 12 mA V CC = 4.75V, IOH = -12 mA V IN = 0 to VCC V IN = 0 to VCC V CC = 5.25V, TAMB = 0C V CC = 5.25V, TAMB = 0C at 1 MHz V CC = 5.25V, TAMB = 0C at 50 MHz One pin at a time for no longer than 1 second TAMB = 25C, f = 1 MHz TAMB = 25C, f = 1 MHz TAMB = 25C, f = 1 MHz
Min. 2.0
Max. 0.8 -1.2 0.5
2.4 -10 -10
-50
10 10 80 3 65 -200 8 12 10
Unit V V V V V A A A mA mA mA pF pF pF
5
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XCR5064: 64 Macrocell CPLD
AC Electrical Characteristics1 For Commercial Grade Devices
Commercial: 0C TAMB +70C; 4.75V VCC 5.25V Symbol tPD_PAL tPD_PLA tCO tSU_PAL tSU_PLA tH tCH tCL tR tF fMAX1 fMAX2 fMAX3 tBUF tPDF_PAL tPDF_PLA tCF tINIT tER tEA tRP tRR
Notes: 1. Specifications measured with one output switching. See Figure 6 and Table 2 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output C L = 5 pF.
Min. Propagation delay time, input (or feedback node) to output through PAL 2 Propagation delay time, input (or feedback node) to output through PAL 3 & PLA Clock to out (global synchronous clock from pin) 2 Setup time (from input or feedback node) through PAL 4 Setup time (from input or feedback node) through PAL + PLA 6 Hold time Clock High time 4 Clock Low time 4 Input Rise time Input Fall time Maximum FF toggle rate2 (1/tCH + tCL) 125 Maximum internal frequency2 (1/tSUPAL + tCF ) 125 Maximum external frequency2 (1/tSUPAL + tCO) 105 Output buffer delay time Input (or feedback node) to internal feedback node delay time through PAL Input (or feedback node) to internal feedback node delay time through PAL+PLA Clock to internal feedback node delay time Delay from valid VCC to valid reset Input to output disable2, 3 Input to output valid2 Input to register preset2 Input to register reset2
Parameter
7 Max. 7.5 9.5 5.5 Min. 2 3 2 6 8.5 5 5 20 20 100 87 77 1.5 6 8 4 50 10 10 10 10
10 Max. 10 12.5 7
Unit ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns s ns ns ns ns
0
0
20 20
1.5 8.5 11 5.5 50 12 12 12.5 12.5
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XCR5064: 64 Macrocell CPLD
DC Electrical Characteristics For Industrial Grade Devices
Industrial: -40C TAMB +85C; 4.5V V CC 5.5V Symbol VIL VIH VI VOL VOH II IOZ ICCQ1 ICCD1, 2 IOS CIN CCLK CI/O
Note: 1. See Table 1 on page 6 for typical values. 2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing. 3. Typical values, not tested.
Parameter Input voltage low Input voltage high Input clamp voltage Output voltage low Output voltage high Input leakage current 3-stated output leakage current Standby current Dynamic current Short circuit output current3 Input pin capacitance3 Clock input capacitance3 I/O pin capacitance3
Test Conditions V CC = 4.5V V CC = 5.5V V CC = 4.5V, IIN = -18 mA V CC = 4.5V, IOL = 12 mA V CC = 4.5V, IOH = -12 mA V IN = 0 to VCC V IN = 0 to VCC V CC = 5.5V, Tamb = -405C V CC = 5.5V, TAMB = -40C at 1 MHz VCC = 5.5V, TAMB = -40C at 50 MHz One pin at a time for no longer than 1 second TAMB = 25C, f = 1 MHz TAMB = 25C, f = 1 MHz TAMB = 25C, f = 1 MHz
Min. 2.0
Max. 0.8 -1.2 0.5
2.4 -10 -10
-50
10 10 100 4 70 -230 8 12 10
Unit V V V V V A A A mA mA mA pF pF pF
5
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XCR5064: 64 Macrocell CPLD
AC Electrical Characteristics1 For Industrial Grade Devices
Industrial:-40C TAMB +85C; 4.5V V CC 5.5V Symbol tPD_PAL tPD_PLA tCO tSU_PAL tSU_PLA tH tCH tCL tR tF fMAX1 fMAX2 fMAX3 tBUF tPDF_PAL tPDF_PLA tCF tINIT tER tEA tRP tRR
Notes: 1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output C L = 5 pF.
Min. Propagation delay time, input (or feedback node) to output through PAL 2 Propagation delay time, input (or feedback node) to output through 3 PAL + PLA Clock to out (global synchronous clock from pin) 2 Setup time (from input or feedback node) through PAL 6 Setup time (from input or feedback node) through PAL + PLA 8.5 Hold time Clock High time 5 Clock Low time 5 Input Rise time Input Fall time Maximum FF toggle rate2 (1/tCH + tCL) 100 Maximum internal frequency2 (1/tSUPAL + tCF ) 87 Maximum external frequency2 (1/tSUPAL + tCO) 77 Output buffer delay time Input (or feedback node) to internal feedback node delay time through PAL Input (or feedback node) to internal feedback node delay time through PAL+PLA Clock to internal feedback node delay time Delay from valid VCC to valid reset Input to output disable2, 3 Input to output valid2 Input to register preset2 Input to register reset2
Parameter
10 Max. 10 12.5 7 Min. 2 3 2 7 9.5 5 5 20 20 100 74 67 1.5 8.5 11 5.5 50 12 12 12.5 12.5
12 Max. 12 14.5 8
Unit ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns s ns ns ns ns
0
0
20 20
1.5 10.5 13 6.5 50 13 13 13.5 13.5
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XCR5064: 64 Macrocell CPLD
Switching Characteristics
The test load circuit and load values for the AC Electrical Characteristics are illustrated below.
VCC
S1
COMPONENT R1 R2
R1
VALUES 470 250 35 pF
C1
VIN VOUT
MEASUREMENT
R2 C1
S1 Open Closed Closed
S2 Closed Open Closed
tPZH tPZL tP
S2
Note: For tPHZ and tPLZ C = 5 pF.
SP00458A
8.00
VDD = 5V, 25C
Voltage Waveform
7.80
+3.0V 90%
10%
7.60
0V tR 1.5ns tF 1.5ns
7.40
SP00368
tPD_PAL (ns) 7.20
MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
Input Pulses
7.00
Table 2: t PD_PAL vs. Number of Outputs Switching (VCC = 5.0V) Number Of Outputs Typical (ns) 1 6.8 2 6.9 4 7.0 8 7.5 12 7.7 16 7.9
6.80
6.60 1 2 4 8 12 16 NUMBER OF OUTPUTS SWITCHING
Figure 6: t PD_PAL vs. Outputs Switching
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XCR5064: 64 Macrocell CPLD
Pin Function and Layout
XCR5064 I/O Pins
FuncMacrotion PC44 VQ44 cell Block PC68 PC84 PQ100 Notes
FuncMacrotion PC44 VQ44 cell Block
PC68
PC84 PQ100 Notes
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14
4 5 6 7 8 9 11 12 21 20 19 18 17 16 14 13 24 25 26 27 28 29 31
42 43 44 1 2 3 5 6 15 14 13 12 11 10 8 7 18 19 20 21 22 23 25
4 5 7 8 9 10 12 13 14 15 17 18 33 32 30 29 28 27 25 24 23 22 20 19 36 37 39 40 41 42 44 45 46 47 49
4 5 6 8 9 10 11 12 14 15 16 17 18 20 21 22 41 40 39 37 36 35 34 33 31 30 29 28 27 25 24 23 44 45 46 48 49 50 51 52 54 55 56 57 58 60
94 95 96 98 99 100 3 4 6 8 10 11 12 14 15 16 39 38 37 35 34 33 32 31 27 25 23 22 21 19 18 17 42 43 44 46 47 48 49 50 54 56 58 59 60 62
3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 41 40 39 38 37 36 34 33
26 35 34 33 32 31 30 28 27
50 65 64 62 61 60 59 57 56 55 54 52 51
61 62 81 80 79 77 76 75 74 73 71 70 69 68 67 65 64 63
63 64 87 86 85 83 82 81 78 77 75 73 71 70 69 67 66 65
XCR5064 Global, Power, and No connect Pins
Pin Type PC44 VQ44 PC68 IN0 43 37 67 IN1 1 39 1 IN2 44 38 68 IN3 2 40 2 gtsn 44 38 68 CLK0 43 37 67 CLK1 24 18 36 CLK2 21 15 33 CLK3 4 42 4 Vcc 3, 15, 9, 17, 3, 11, 23, 35 29, 41 21, 31, 35, 43, 53, 63 GND 10, 22, 4, 16, 6, 16, 30, 42 24, 36 26, 34, 38, 48, 58, 66 No Connects PC84 83 1 84 2 84 83 44 41 4 3, 13, 26, 38, 43, 53, 66, 78 7, 19, 32, 42, 47, 59, 72, 82 PQ100 Notes 89 91 90 92 90 (1) 89 42 39 94 5, 20, 36, 41, 53, 68, 84, 93 13, 28, 40, 45, 61, 76, 88, 97 1, 2, 7, 9, 24, 26, 29, 30, 51, 52, 55, 57, 72, 74, 79, 80
(1) Global Tri State pin facilitates bed of nails testing without using logic resources.
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XCR5064: 64 Macrocell CPLD XCR5064 - 44-pin PLCC
6 1 40
XCR5064 - 84-pin PLCC
11 39 1 75
7
12
74
LCC
LCC
17
29
32
54
18
28 SP00452A
33
53 SP00455B
XCR5064 - 100-pin PQFP XCR5064 - 44-pin VQFP
100 44 34 1 1 33 QFP QFP 30 11 23 31 12 22 SP00453B SP00456B 50 51 80 81
XCR5064 - 68-pin PLCC
9 1 61
10
60
LCC
26
44
27
43
SP00454B
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XCR5064: 64 Macrocell CPLD
Ordering Information Example: XCR5064 -7 PC 44 C
Device Type Speed Options Temperature Range Number of Pins Package Type
Speed Options -12: 12 ns pin-to-pin delay -10: 10 ns pin-to-pin delay -7: 7.5 ns pin-to-pin delay
Temperature Range C = Commercial, TA = 0C to +70C I = Industrial, TA = -40C to +85C Packaging Options VQ44: 44-pin VQFP PC44: 44-pin PLCC PC68: 68-pin PLCC PC84: 84-pin PLCC PQ100: 100-pin PQFP
Component Availability
Pins Type Code XCR5064 44 Plastic VQFP VQ44 I C, I C Plastic PLCC PC44 I C, I C 68 Plastic PLCC PC68 I C, I C 84 Plastic PLCC PC84 I C, I C 100 Plastic PQFP PQ100 I C, I C
-12 -10 -7
Revision History
Date 9/16/99 2/10/00 8/10/00 10/09/00 Version # 1.0 1.1 1.2 1.3 Revision Initial Xilinx release. Converted to Xilinx Format and updated. Updated features and pinout tables. Added Discontinuation Notice.
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