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| PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR 1/6-INCH SOC VGA CMOS DIGITAL IMAGE SENSOR Features PART NUMBER: MT9V112I2ASTC * DigitalClarityTM CMOS Imaging Technology * System-On-a-Chip (SOC)--Completely integrated camera system * Ultra-low power, low cost, progressive scan CMOS image sensor * Superior low-light performance * On-chip image flow processor (IFP) performs sophisticated processing: Color recovery and correction, sharpening, gamma, lens shading correction, and on-the-fly defect correction * Filtered image downscaling to arbitrary size with smooth, continuous zoom and pan * Automatic Features: Auto exposure, auto white balance (AWB), auto black reference (ABR), auto flicker avoidance, auto color saturation, and auto defect identification and correction * Fully automatic Xenon and LED-type flash support, fast exposure adaptation * Multiple parameter contexts, easy/fast mode switching * Camera control sequencer automates: Snapshots, snapshots with flash, and video clips * Simple two-wire serial programming interface * ITU-R BT.656 (YCbCr), 565RGB, 555RGB, or 444RGB formats (progressive scan) * Raw and processed Bayer formats Table 1: PARAMETER Key Performance Parameters TYPICAL VALUE Optical Format Active Imager Size 1/6-inch (4:3) 2.30mm(H) x 1.73mm(V) 2.88mm Diagonal Active Pixels 640H x 480V Pixel Size 3.6m x 3.6m Color Filter Array RGB Bayer Pattern Shutter Type Electronic Rolling Shutter (ERS) Maximum Data Rate/ 12 MPS-13.5 MPS/ Master Clock 24 MHz-27 MHz Frame Rate (VGA 640H x 480V) 30 fps at 27 MHz ADC Resolution 10-bit, on-chip Responsivity 1.0 V/lux-sec (550nm) Dynamic Range 71dB 44dB SNRMAX Supply Voltage I/O Digital Core Digital Analog Power Consumption Operating Temperature Packaging 1.7V-3.6V 1.7V-1.9V or 2.5V-3.1V (1.8V or 2.8V nominal) 2.5V-3.1V (2.8V nominal) 76mW at 1.8V, 15fps -30C to +70C 36-Ball ICSP, wafer or die Applications * * * * Cellular phones PDAs Toys Other battery-powered products 09005aef8154a39d/09005aef8175e6cc MT9V112_1.fm- Rev. A 1/05 EN 1 (c)2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Register Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Typical Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Sensor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Lens Shading Correction and Black Level Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Defect Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Interpolation, Aperture, and Color Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Resize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Camera Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Camera Interface and Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Contexts, Snapshots, and Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Output Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Image Flow Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Image Flow Processor Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Sensor Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Pixel Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Sensor Core Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Contexts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Viewfinder/Preview and Full-Resolution/Snapshot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Preview Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Snapshot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Switching Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Turning Frame Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Default Blanking Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 User Blanking Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Typical Resolutions, Modes, and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Reset, Clocks, and Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Serial Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Bus Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Data Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 09005aef8154a39d/09005aef8175e6cc MT9V112TOC.fm- Rev. A 1/05 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 2 PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Two-Wire Serial Interface Sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 16-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 16-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 8-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 8-Bit READ Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Two-wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 09005aef8154a39d/09005aef8175e6cc MT9V112TOC.fm- Rev. A 1/05 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Internal Registers Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Typical Configuration (connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 36-Ball ICSP Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Sensor Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Pixel Color Pattern Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Spatial Illustration of Image Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Primary Sensor Core Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Horizontal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Typical Spectral Characteristics (preliminary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Image Center Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 WRITE Timing to R0x09:0--Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 READ Timing from R0x09:0; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 WRITE Timing to R0x09:0--Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 READ Timing from R0x09:0; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Serial Host Interface Start Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Serial Host Interface Stop Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Serial Host Interface Data Timing for Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Serial Host Interface Data Timing for Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Acknowledge Signal Timing After an 8-bit Write to the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Acknowledge Signal Timing After an 8-bit Read from the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 36-Ball ICSP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 09005aef8154a39d/09005aef8175e6cc MT9V112LOF.fm- Rev. A1/05 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ball Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Data Ordering in YCbCr Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Output Data Ordering in Processed Bayer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Output Data Ordering in RGB Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Output Data Ordering in (8 + 2) Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Colorpipe Registers - Address Page 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Camera Control Registers - Address Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Colorpipe Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Camera Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Sensor Registers - Address Page 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Sensor Core Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Register Address Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Blanking Parameter Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 User Blanking Minimum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Blanking Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 STANDBY Effect on the Output State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 I/O Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Two-Wire Interface ID Address Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 09005aef8154a39d/09005aef8175e6cc MT9V112LOT.fm - Rev. A 1/05 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR The Micron Imaging MT9V112 is a VGA-format, single-chip camera CMOS active-pixel digital image sensor. This device combines the MT9V012 image sensor core with fourth-generation digital image flow processor technology from Micron Imaging. It captures high-quality color images at VGA resolution. The VGA CMOS image sensor features DigitalClarity--Micron's breakthrough low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS. The sensor is a complete camera-on-a-chip solution designed specifically to meet the low-power, lowcost demands of battery-powered products such as cellular phones, PDAs, and toys. It incorporates sophisticated camera functions on-chip and is programmable through a simple two-wire serial interface. The MT9V112 performs sophisticated processing functions including color recovery, color correction, sharpening, programmable gamma correction, auto black reference clamping, auto exposure, automatic 50Hz/60Hz flicker avoidance, lens shading correction, auto white balance (AWB), and on-the-fly defect identification and correction. Additional features include day/night mode configurations; special camera effects such as sepia tone and solarization; and interpolation to arbitrary image size with continuous filtered zoom and pan. The device supports both Xenon and LEDtype flash light sources in several snapshot modes. The MT9V112 can be programmed to output progressive-scan images up to 30 frames per second (fps). The image data can be output in any one of six 8-bit formats: * ITU-R BT.656 (formerly CCIR656, progressive scan only) YCbCr * 565RGB * 555RGB * 444RGB * Raw Bayer * Processed Bayer The FRAME_VALID and LINE_VALID signals are output on dedicated balls, along with a pixel clock that is synchronous with valid data. General Description Functional Overview The MT9V112 is a fully-automatic, single-chip camera, requiring only a power supply, lens, and clock source for basic operation. Output video is streamed via a parallel 8-bit DOUT port, shown in Figure 1 on page 7. The output pixel clock is used to latch data, while FRAME_VALID and LINE_VALID signals indicate the active video. The MT9V112 internal registers are configured using a two-wire serial interface. The device can be put in a low-power sleep mode by asserting STANDBY and shutting down the clock. Output signals can be tri-stated. Both tri-stating output signals and entry in standby mode also can be achieved via two-wire serial interface register writes. The MT9V112 accepts input clocks up to 27 MHz, delivering up to 30 fps for VGA resolution images. Internal Architecture Internally, the MT9V112 consists of a sensor core and an image flow processor (IFP). The IFP is divided in two sections: the colorpipe (CP), and the camera controller (CC). The sensor core captures raw Bayerencoded images that are then input in the IFP The CP . section of the IFP processes the incoming stream to create interpolated, color-corrected output, and the CC section controls the sensor core to maintain the desired exposure and color balance, and to support snapshot modes. The sensor core, CP, and CC registers are grouped in three separate address spaces, shown in Figure 2. When accessing internal registers via the two-wire serial interface, select the desired address space by programming the R240 register. The MT9V112 accelerates mode-switching with hardware-assisted context switching, and supports taking snapshots, flash snapshots, and video clips using a configurable sequencer. The MT9V112 supports a range of color formats derived from four primary color representations: YCbCr, RGB, raw Bayer (unprocessed, directly from the sensor), and processed Bayer (Bayer format data regenerated from processed RGB). The device also supports a variety of output signaling/timing options: * Standard FRAME_VALID/LINE_VALID video interface with gated pixel clocks * ITU-R BT.656 marker-embedded video interface with either gated or uniform pixel clocking 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Register Notation The following register address notations are used in this document: * R Figure 1: Functional Block Diagram SCLK SDATA Sensor Core . 640H x 480V . 1/6-inch optical format . Auto black compensation . Programmable analog gain . Programmable exposure . 10-bit ADC . H/W context switch to/from preview . Bayer RGB output Pixel Data SRAM Line Buffers CLKIN STANDBY Control Bus (Two-Wire Serial Interface Transactions) + Sensor control (gains, shutter, etc.) Control Bus (Two-Wire Serial Interface Transactions) Image Flow Processor Camera Control VDDQ/DGND V DD/DGND VAA /AGND VAAPIX Auto exposure Auto white balance Flicker detect/avoid Camera control: Snapshots, flash, video, clip Control Bus Image Flow Processor Colorpipe DOUT [7:0] (Two-Wire Serial Lens shading correction Color interpolation Interface Filtered resize and zoom Transactions) Defect correction Color correction Image Data Gamma correction Color conversion + formatting PIXCLK FRAME_VALID LINE_VALID STROBE Figure 2: Internal Registers Grouping Image Flow Processor Sensor Core Registers R[255:0] Color Pipeline Registers R[255:0] Camera Control Registers R[255:0] Page 0 Page 1 Page 2 NOTE: Internal registers are grouped in three address spaces. Program R240 selects the desired address space. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Typical Connections Figure 3 shows typical MT9V112 device connections. For low-noise operation, the MT9V112 requires separate power supplies for analog and digital. Incoming digital and analog ground conductors can be tied together next to the die. Both power supply rails should be decoupled to ground using capacitors. The use of inductance filters is not recommended. The MT9V112 also supports different digital core (VDD/DGND) and I/O power (VDDQ/DGND) power domains that can be at different voltages. Figure 3: Typical Configuration (connection) VDD VDDQ VAA VAAPIX Power1 Power1 Power1 Power1 1.5k2 1.5k2 VDDQ VDD VAA VAAPIX DOUT(7:0) SADDR STANDBY from Controller or Digital GND Master Clock Two-Wire Serial Interface 1k STANDBY CLKIN SDATA SCLK TEST_ENABLE RESET# DGNDQ PIXCLK LINE_VALID FRAME_VALID To CMOS Camera Port STROBE To Xenon or LED Flash Driver 10F DGND AGND DGND VDDQ VDD AGND VAAPIX VAA 0.1F 1F 0.1F 1F 0.1F 1F 0.1F 1F DGND DGND AGND AGND NOTE: 1. A 1.5K resistor value is recommended, but may be greater for slower two-wire speed. 2. MT9V112 STANDBY can be connected to customer's ASIC controller directly or to Digital GND, depending on the controller's capability. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Figure 4: 36-Ball ICSP Assignment 1 2 3 4 5 6 A VDD DOUT3 DOUT5 DOUT7 CLKIN VDD B DOUT0 DGND DOUT4 DOUT6 VDDQ LINE _VALID C DOUT1 DOUT2 DGND DGND FRAME _VALID VDD D DOUT _LSB0 DOUT _LSB1 DGND DGND TEST _ENABLE VAA E SADDR VDDQ STROBE RESET# DGND AGND F VDD PIXCLK SCLK STAND BY SDATA VAAPIX Top View (Ball Down) Table 2: BALL ASSIGNMENT A5 E4 E1 D5 F3 F4 F5 B1, C1, C2, A2, B3, A3, B4, A4 D1 D2 C5 B6 F2 E3 E6 B2, C3, C4, D3, D4, E5 Ball Description NAME CLKIN RESET# SADDR TEST_ENABLE SCLK STANDBY SDATA DOUT(7:0) DOUT_LSB0 DOUT_LSB1 FRAME_VALID LINE_VALID PIXCLK STROBE AGND DGND TYPE Input Input Input Input Input Input Output Output Output Output Output Output Output Output Supply Supply DESCRIPTION Master clock in sensor. Active LOW: asynchronous reset. Two-Wire Serial Interface Device ID selection 1:0xBA, 0:0x90. Tie to DGND for normal operation. (Manufacturing use only.) Two-Wire Serial Interface Clock. Multifunctional signal to control device addressing, power-down, and state functions (covering output enable function). Two-Wire Serial Interface Data I/O. Pixel Data Output bit 0, DOUT(7) (most significant bit (MSB)), DOUT(0) (least significant bit (LSB)). Sensor bypass mode output 0--typically left unconnected for normal SOC operation. Sensor bypass mode output 1--typically left unconnected for normal SOC operation. Active HIGH: FRAME_VALID; indicates active frame. Active HIGH: LINE_VALID, DATA_VALID; indicates active pixel. Pixel clock output. Active HIGH: strobe (Xenon) or turn on (LED) flash. Analog ground. Core digital ground. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 2: BALL ASSIGNMENT D6 F6 A1, A6, C6, F1 B5, E2 NOTE: Ball Description (continued) NAME VAA VAAPIX VDD VDDQ TYPE Supply Supply Supply Supply DESCRIPTION Analog power: 2.5V-3.1V (2.8V nominal). Pixel array analog power supply: 2.5V-3.1V (2.8V nominal). Core digital power: 1.7V-1.9V or 2.5V-3.1V (1.8V or 2.8V nominal). I/O digital power: 1.7V-3.6V. All inputs and outputs are implemented with bidirectional buffers. Care must be taken that all inputs are driven and all outputs are driven if tri-stated. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Architecture Overview The MT9V112 consists of a sensor core, the color processing pipeline, and a measurement and control logic block (the camera controller). Below is a brief overview of the architecture. and color saturation adjustments can be made both by the user and the auto exposure unit (for dynamic saturation reduction in high or low lighting situations). Resize The IFP can resize to virtually any output resolution through digitally filtered sub-sampling. Output resolutions include, but are not limited to, VGA, QVGA, CIF, and QCIF. When the output resolution is smaller than the sensor-generated image, smooth, continuous zoom and pan become available. The user simply defines the zoom window, pan offset, and output resolution, and the resizer calculates all other parameters for the resize function. Sensor Core The sensor core is taken from the MT9V012 standalone sensor and includes a number of features specifically targeting the mobile market. Of primary interest is support for preview/viewfinding with hardwareaccelerated switching to full resolution for snapshots. This switch can be achieved without adversely affecting exposure or color balance. This enables taking single frame and Xenon flash snapshots while minimizing snapshot lag. LED snapshots are discussed below; they also benefit significantly from this feature. Camera Control The camera controller continuously accumulates image brightness and color statistics. Two units use these measurements to adjust the sensor and colorpipe settings. The auto exposure unit adjusts gain and shutter-width to maintain a user-defined luma target. The image measurement region can be modified to permit, for example, back light compensation. The user can also control the speed and sensitivity of the algorithm from highly responsive (for LED flash and viewfinding) to somewhat dampened (for video). Finally, the unit can detect 50Hz or 60Hz rolling flicker bars (due to ambient illumination) and adjusts exposure appropriately to eliminate this adverse effect on image quality. The AWB module adjusts gains and the CCM to compensate for the effects of changing scene illumination on the quality of the color rendition. The user has control over the region of the scene to be analyzed as well as the responsivity of the algorithm to illuminant changes. Lens Shading Correction and Black Level Conditioning The stream of raw data from the sensor enters the pipeline and undergoes several transformations. Image stream processing starts with conditioning the black level and applying a digital gain. The lens shading block compensates for spatially varying signal loss caused by the lens. The block is programmable and implements separate correction functions for R,G, and B independently. Defect Correction Following lens correction, the data stream is analyzed for the presence of defects. A two-dimensional digital filter calculates suitable replacement values. Edge sensitivity minimizes false detections, helping to preserve image sharpness. Interpolation, Aperture, and Color Correction The Bayer pixel pattern data is interpolated to recover missing color components for each pixel following defect correction. Configurable aperture correction sharpens the image and to avoid amplifying noise, can be programmed to be less aggressive in low light conditions. The resulting interpolated RGB data passes through the current color correction matrix (CCM), gamma, and color saturation corrections. The CCM can be manually loaded or dynamically configured by the auto white balance (AWB) unit. The gamma correction unit is fully user-programmable, Camera Interface and Test Patterns The MT9V112 outputs process video as a standard ITU-R BT.656 stream, an RGB stream, or as processed or unprocessed Bayer data. The ITU-R BT.656 stream contains YCbCr 4:2:2 data with optional embedded synchronization codes. This output is typically suitable for subsequent display by standard (progressive scan) video equipment, or JPEG/MPEG compression. RGB functionality provides support for LCD devices. The MT9V112 can be configured to output 16-bit RGB (RGB565), 15-bit RGB (RGB555), and two types of 12-bit RGB (RGB444). The user can configure internal registers to swap odd and even bytes, chrominance channels, and luminance and chrominance components to ease interfacing to application processors. Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 11 PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR To assist in integration and system debug, a variety of test patterns are provided, from simple ramps to colorbars. * The resizer (output resolutions for preview and snapshot) * Camera interface (e.g., RGB565 for LCD preview and YCbCr for snapshots) To facilitate taking snapshots and flash snapshots, the IFP includes a camera control sequencer that automates the process of stepping through a number of preset configurable programs. In addition to basic snapshots, there are programs for both Xenon and LED assisted snapshots. A flash-triggering controller provides an appropriate timing strobe for synchronizing the onset of flash illumination with the rolling shutter. Contexts, Snapshots, and Flash For a number of parameters, registers are provided for storing two "contexts": context A and context B. These contexts enable the user to setup the camera for a number of different modes, then switch between modes with a single register WRITE to the global context control register (GCCR). A typical example is to use context A for viewfinder/preview settings and context B for snapshots. Functions supporting context switching include: 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Output Data Ordering Table 3: MODE Default Swap CrCb SwapYC Swap CrCb, SwapYC Data Ordering in YCbCr Mode BYTE Cbi Cri Yi Yi Yi Yi Cbi Cri Cri Cbi Yi+1 Yi+1 Yi+1 Yi+1 Cri Cbi Table 4: MODE Default Flip Bayer Col Flip Bayer Row Flip Bayer Col, Flip Bayer Row Output Data Ordering in Processed Bayer Mode LINE First Second First Second First Second First Second BYTE Gi Bi Ri Gi Bi Gi Gi Ri Ri+1 Gi+1 Gi+1 Bi+1 Gi+1 Ri+1 Bi+1 Gi+1 Gi+2 Bi+2 Ri+2 Gi+2 Bi+2 Gi+2 Gi+2 Ri+2 Ri+3 Gi+3 Gi+3 Bi+3 Gi+3 Ri+3 Bi+3 Gi+3 Table 5: Output Data Ordering in RGB Mode BYTE First Second First Second First Second First Second D7 R7 G4 0 G5 R7 B7 0 G7 D6 R6 G3 R7 G4 R6 B6 0 G6 D5 R5 G2 R6 G3 R5 B5 0 G5 D4 R4 B7 R5 B7 R4 B4 0 G4 D3 R3 B6 R4 B6 G7 0 R7 B7 D2 G7 B5 R3 B5 G6 0 R6 B6 D1 G6 B4 G7 B4 G5 0 R5 B5 D0 G5 B3 G6 B3 G4 0 R4 B4 MODE (SWAP DISABLED) RGB565 RGB555 RGB444x RGBx444 Table 6: MODE 8 + 2 bypass Output Data Ordering in (8 + 2) Bypass Mode BYTE First Second D7 B9 0 D6 B8 0 D5 B7 0 D4 B6 0 D3 B5 0 D2 B4 0 D1 B3 B1 D0 B2 B0 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Image Flow Processor Registers Table 7: REGISTER #DEC (HEX) 5 (05) 6 (06) 8 (08) 37 (25) 52 (34) 53 (35) 58 (3A) 59 (3B) 60 (3C) 71 (47) 72 (48) 83 (53) 84 (54) 85 (55) 86 (56) 87 (57) 88 (58) 104 (68) 128 (80) 129 (81) 130 (82) 131 (83) 132 (84) 133 (85) 134 (86) 135 (87) 136 (88) 137 (89) 138 (8A) 139 (8B) 140 (8C) 141 (8D) Colorpipe Registers - Address Page 1 REGISTER NAME Aperture Correction Operating Mode Control Output Format Control Color Saturation Control Luma Offset Luma Clip Output Format Control 2A Lens Correction Parameter 1 Lens Correction Parameter 2 Reserved Test Pattern Generator Control Gamma Correction Parameter 1 Gamma Correction Parameter 2 Gamma Correction Parameter 3 Gamma Correction Parameter 4 Gamma Correction Parameter 5 Gamma Correction Parameter 6 Reserved Lens Correction Parameter 3 Lens Correction Parameter 4 Lens Correction Parameter 5 Lens Correction Parameter 6 Lens Correction Parameter 7 Lens Correction Parameter 8 Lens Correction Parameter 9 Lens Correction Parameter 10 Lens Correction Parameter 11 Lens Correction Parameter 12 Lens Correction Parameter 13 Lens Correction Parameter 14 Lens Correction Parameter 15 Lens Correction Parameter 16 DATA FORMAT 0000 0000 0000 dddd dddd dddd 0ddd dddd 0000 0ddd dddd dddd 0000 0000 00dd dddd dddd dddd dddd dddd dddd dddd dddd dddd 0ddd dddd dddd dddd -- -- -- 0000 0000 d000 0ddd -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DEFAULT VALUE DEC (HEX) MODULE 3 (0003) 28686 (700E) 128 (0080) 5 (0005) 16 (0010) 61456 (F010) 512 (0200) 1066 (042A) 1024 (0400) 24 (0018) 0 (0000) 7700 (1E14) 17966 (462E) 34666 (876A) 47008 (B7A0) 57548 (E0CC) 0 (0000) 17 (0011) 3 (0003) 0 (0000) Interp Cfg Cfg rgb2yuv Camlnt Camlnt CamInt LensCorr LensCorr -- FifoInt GmaCorr GmaCorr GmaCorr GmaCorr GmaCorr GmaCorr -- LensCorr LensCorr 0 (0000) LensCorr 0 (0000) LensCorr 0 (0000) LensCorr 0 (0000) LensCorr 0 (0000) LensCorr 0 (0000) LensCorr 0 (0000) LensCorr 0 (0000) LensCorr 0 (0000) LensCorr 0 (0000) LensCorr 0 (0000) LensCorr 0 (0000) LensCorr 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 7: REGISTER #DEC (HEX) 142 (8E) 143 (8F) 144 (90) 145 (91) 146 (92) 147 (93) 148 (94) 149 (95) 153 (99) 154 (9A) 155 (9B) 157 (9D) 159 (9F) 160 (A0) 161 (A1) 162 (A2) 163 (A3) 164 (A4) 165 (A5) 166 (A6) 167 (A7) 168 (A8) 169 (A9) 170 (AA) 171 (AB) 172 (AC) 174 (AE) 175 (AF) 180 (B4) 182 (B6) 183 (B7) 184 (B8) 185 (B9) 186 (BA) 187 (BB) 188 (BC) 189 (BD) 190 (BE) Colorpipe Registers - Address Page 1 (continued) REGISTER NAME Lens Correction Parameter 17 Lens Correction Parameter 18 Lens Correction Parameter 19 Lens Correction Parameter 20 Lens Correction Parameter 21 Lens Correction Parameter 22 Lens Correction Parameter 23 Lens Correction Parameter 24 Line Counter Frame Counter Output Format Control 2--Context B Reserved Reserved--obsolete Reserved--obsolete Reducer Horizontal Size Resize--Context B Reserved--obsolete Reserved--obsolete Reducer Vertical Size Resize--Context B Reducer Horizontal Pan Resize Reducer Horizontal Zoom Resize Reducer Horizontal Size Resize--Context A Reducer Vertical Pan Resize Reducer Vertical Zoom Resize Reducer Vertical Size Resize--Context A Reducer Current Zoom Horizontal Reducer Current Zoom Vertical Reducer Zoom Step Size Reducer Zoom Control Reserved Lens Correction Parameter 25 Lens Correction Parameter 26 Lens Correction Parameter 27 Lens Correction Parameter 28 Lens Correction Parameter 29 Lens Correction Parameter 30 Lens Correction Parameter 31 Lens Correction Parameter 32 Lens Correction Parameter 33 DATA FORMAT -- -- -- -- -- -- -- -- ???? ???? ???? ???? ???? ???? ???? ???? 0ddd dddd dddd dddd -- -- -- 0000 0ddd dddd dddd -- -- 0000 0ddd dddd dddd 0d00 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0d00 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0??? ???? ???? 0000 0??? ???? ???? dddd dddd dddd dddd 0000 00dd 0ddd dddd -- -- -- -- -- -- -- -- -- -- DEFAULT VALUE DEC (HEX) MODULE 0 (0000) LensCorr 0 (0000) LensCorr 0 (0000) LensCorr 0 (0000) LensCorr 0 (0000) LensCorr 0 (0000) LensCorr 0 (0000) LensCorr 0 (0000) LensCorr N/A N/A 512 (0200) 9390 (24AE) 0 (0000) 640 (0280) 480 (01E0) 0 (0000) 480 (01E0) 480 (01E0) 0 (0000) 640 (0280) 320 (0140) 0 (0000) 480 (01E0) 240 (00F0) 640 (0280) 480 (01E0) 3081 (0C09) 0 (0000) 32 (0020) 0 (0000) 0 (0000) 0 (0000) 0 (0000) 0 (0000) 0 (0000) 0 (0000) 0 (0000) 0 (0000) CamInt CamInt CamInt -- - - Interp - - Interp Interp Interp Interp Interp Interp Interp Interp Interp Interp Interp -- LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 7: REGISTER #DEC (HEX) 191 (BF) 192 (C0) 193 (C1) 194 (C2) 195 (C3) 196 (C4) 200 (C8) 201 (C9) 202 (CA) 203 (CB) 204 (CC) 205 (CD) 206 (CE) 207 (C) 208 (D0) 220 (DC) 221 (DD) 222 (DE) 223 (DF) 224 (E0) 225 (E1) 226 (E2) 227 (E3) Colorpipe Registers - Address Page 1 (continued) REGISTER NAME Lens Correction Parameter 34 Lens Correction Parameter 35 Lens Correction Parameter 36 Lens Correction Parameter 37 Lens Correction Parameter 38 Lens Correction Parameter 39 Global Context Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Gamma Correction Parameter 7 Gamma Correction Parameter 8 Gamma Correction Parameter 9 Gamma Correction Parameter 10 Gamma Correction Parameter 11 Gamma Correction Parameter 12 Effects Mode Effects Sepia DATA FORMAT -- -- -- -- -- -- dddd dddd dddd dddd dddd dddd dddd dddd -- -- -- -- -- -- -- -- -- -- -- -- -- dddd dddd 0000 0ddd dddd dddd dddd dddd DEFAULT VALUE DEC (HEX) MODULE 0 (0000) 0 (0000) 0 (0000) 0 (0000) 0 (0000) 0 (0000) 0 (0000) 0 (0000) N/A N/A N/A N/A N/A N/A N/A 7700 (1E14) 17966 (462E) 34666 (876A) 47008 (B7A0) 57548 (E0CC) 0 (0000) 28672 (7000) 45091 (B023) LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr CntxCtl MBist/ samobs MBist/ samobs MBist/ samobs MBist/ samobs MBist/ samobs MBist/ samobs MBist/ samobs MBist/ samobs GmaCorr GmaCorr GmaCorr GmaCorr GmaCorr GmaCorr GmaCorr GmaCorr 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 8: REGISTER # DEC (HEX) 2 (02) 3 (03) 4 (04) 9 (09) 10 (0A) 11 (0B) 12 (0C) 13 (0D) 14 (0E) 15 (0F) 16 (10) 17 (11) 18 (12) 19 (13) 20 (14) 21 (15) 22 (16) 23 (17) 24 (18) 25 (19) 26 (1A) 27 (1B) 28 (1C) 29 (1D) 30 (1E) 31 (1F) 32 (20) 33 (21) 34 (22) 35 (23) 36 (24) 38 (26) 39 (27) 40 (28) 41 (29) 42 (2A) 43 (2B) 44 (2C) 45 (2D) 46 (2E) 47 (2F) 48 (30) Camera Control Registers - Address Page 2 REGISTER NAME Color Correction Parameter 1 Color Correction Parameter 2 Color Correction Parameter 3 Color Correction Parameter 4 Color Correction Parameter 5 Color Correction Parameter 6 Color Correction Parameter 7 Color Correction Parameter 8 Color Correction Parameter 9 Color Correction Parameter 10 Color Correction Parameter 11 Color Correction Parameter 12 Color Correction Parameter 13 Color Correction Parameter 14 Color Correction Parameter 15 Color Correction Parameter 16 Color Correction Parameter 17 Color Correction Parameter 18 Color Correction Parameter 19 Color Correction Parameter 20 Color Correction Parameter 21 Color Correction Parameter 22 Color Correction Parameter 23 Color Correction Parameter 24 AWB Parameter 1 AWB Parameter 2 AWB Parameter 3 AWB Parameter 4 AWB Parameter 5 AWB Parameter 6 AWB Parameter 7 Auto Exposure Horizontal Window Boundaries Auto Exposure Vertical Window Boundaries AWB Parameter 8 AWB Parameter 9 AWB Parameter 10 Auto Exposure Horizontal Center Window Boundaries Auto Exposure Vertical Center Window Boundaries AWB Window Boundaries Auto Exposure Target and Precision Control Auto Exposure Speed and Sensitivity Control--Context A AWB Parameter 11 DATA FORMAT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- dddd dddd dddd dddd dddd dddd dddd dddd -- -- -- dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd -- DEFAULT VALUE DEC (HEX) MODULE 174 (00AE) 10531 (2923) 1188 (04A4) 182 (00B6) 208 (00D0) 144 (0090) 217 (00D9) 150 (0096) 54 (0036) 77 (0073) 93 (005D) 201 (00C9) N/A N/A N/A 73 (0049) 23 (0017) 1 (0011) 46 (002E) 52 (0034) 3 (0003) 62 (003E) 77 (004D) 90 (005A) 108 (006C) 160 (00A0) 51220 (C814) 32896 (8080) 55648 (D960) 55648 (D960) 32512 (7F00) 32768 (8000) 32776 (8008) 61218 (EF22) 36211 (8D73) 208 (00D0) 24608 (6020) 24608 (6020) 61600 (F0A0) 3146 (0C4A) 57120 (DF20) N/A ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr AWB AWB AWB AWB AWB AWB AWB AE AE AWB AWB AWB AE AE AWB AE AE AWB 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 8: REGISTER # DEC (HEX) 49 (31) 50 (32) 51 (33) 54 (36) 55 (37) 56 (38) 57 (39) 58 (3A) 59 (3B) 60 (3C) 61 (3D) 62 (3E) 63 (3F) 70 (46) 75 (4B) 76 (4C) 77 4D) 79 (4F) 87 (57) 88 (58) 89 (59) 90 (5A) 91 (5B) 92 (5C) 93 (5D) 94 (5E) 95 (5F) 96 (60) 97 (61) 98 (62) 99 (63) 100 (64) 101 (65) 103 (67) 104 (68) 106 (6A) 107 (6B) 108 (6C) 109 (6D) 110 (6E) 111 (6F) 112 (70) 113 (71) 114 (72) Camera Control Registers - Address Page 2 (continued) REGISTER NAME AWB Parameter 12 AWB Parameter 13 Auto Exposure Parameter 1 Auto Exposure Parameter 2 Auto Exposure Parameter 3 Auto Exposure Parameter 4 Auto Exposure Parameter 5 Auto Exposure Parameter 6 Auto Exposure Parameter 7 Auto Exposure Parameter 8 Auto Exposure Parameter 9 AWB Parameter 14 Auto Exposure Parameter 10 Auto Exposure Parameter 11 Reserved Auto Exposure Parameter 12 Auto Exposure Parameter 13 Reserved Auto Exposure Parameter 14 Auto Exposure Parameter 15 Auto Exposure Parameter 16 Auto Exposure Parameter 17 Flicker Control 0 Reserved Reserved Color Correction Parameter 2 Color Correction Parameter 26 Color Correction Parameter 27 Reserved Auto Exposure Digital Gains Monitor Reserved Reserved Auto Exposure Parameter 18 Auto Exposure Digital Gain Limits Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DATA FORMAT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ?000 0000 0000 0ddd -- -- -- -- -- -- ???? ???? ???? ???? -- -- -- dddd dddd dddd dddd -- -- -- -- -- -- -- -- -- -- DEFAULT VALUE DEC (HEX) MODULE N/A AWB N/A AWB 5230 (146E) AE 30736 (7810) AE 768 (0300) AE 1088 (0440) AE 1702 (06A6) AE 1702 (06A6) AE 1371 (055B) AE 1371 (055B) AE 6105 (17D9) AE 7423 (1CFF) AWB N/A AE 55552(D900) AE 0 (0000) -- N/A AE N/A AE 0 (0000) -- 470 (01D6) AE 564 (0234) AE 1970 (01D6) AE 564 (0234) AE 2 (0002) FD 4108 (100C) -- 5392 (1510) -- 26952 (6948) ColorCorr 14632 (3928) ColorCorr 2 (0002) ColorCorr 32896 (8080) -- 4112 (1010) AE N/A -- 23036(59FC) -- 0 (000) AE 16400 (4010) AE 17 (0011) -- N/A -- N/A -- N/A -- N/A -- N/A -- N/A -- N/A -- N/A -- N/A -- 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 8: REGISTER # DEC (HEX) 115 (73) 116 (74) 117 (75) 118 (76) 119 (77) 120 (78) 121 (79) 122 (7A) 123 (7B) 124 (7C) 125 (7D) 130 (82) 131 (83) 132 (84) 133 (85) 134 (86) 135 (87) 136 (88) 137 (89) 138 (8A) 139 (8B) 140 (8C) 141 (8D) 142 (8E) 143 (8F) 144 (90) 145 (91) 146 (92) 147 (93) 148 (94) 149 (95) 150 (96) 151 (97) 152 (98) 153 (99) 156 (9C) 180 (B4) 181 (B5) 198 (C6) 199 (C7) 200 (C8) 201 (C9) 202 (CA) 203 (CB) Camera Control Registers - Address Page 2 (continued) REGISTER NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Auto Exposure Parameter 19 Auto Exposure Parameter 20 Auto Exposure Parameter 21 Auto Exposure Parameter 22 Auto Exposure Parameter 23 Auto Exposure Parameter 24 Auto Exposure Parameter 25 Auto Exposure Parameter 26 Auto Exposure Parameter 27 Auto Exposure Parameter 28 Auto Exposure Parameter 29 Auto Exposure Parameter 30 Auto Exposure Parameter 31 Auto Exposure Parameter 32 Auto Exposure Parameter 33 Auto Exposure Parameter 34 Auto Exposure Parameter 35 Auto Exposure Parameter 36 Auto Exposure Parameter 37 Auto Exposure Parameter 38 Reserved Reserved Reserved Reserved Auto Exposure Speed and Sensitivity--Context B Reserved Reserved Reserved Reserved Global Context Control Context Control Parameter 2 Camera Control Sequencer Parameter Camera Control Sequencer Parameter 2 DATA FORMAT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- dddd dddd dddd dddd -- -- -- -- dddd dddd dddd dddd -- -- -- DEFAULT VALUE DEC (HEX) MODULE N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 1020 (03FC) 769 (0301) 193 (00C1) 929 (03A1) 980 (03D4) 983 (03D7) 921 (0399) 1016 (03F8) 28 (001C) 957 (03BD) 987 (03DB) 957 (03BD) 1020 (03FC) 990 (03DE) 990 (03DE) 990 (03DE) 990 (03DE) 31 (001F) 65 (0041) 867 (0363) 0 (0000) N/A 255 (00FF) 1 (0001) 57120 (DF20) 32 (0020) N/A 0 (0000) N/A 0 (0000) N/A N/A 0 (0000) -- -- -- -- -- -- -- -- -- -- -- AE AE AE AE AE AE AE AE AE AE AE AE AE AE AE AE AE AE AE AE -- -- -- -- AE -- -- -- -- CntxCtl CntxCtl CntxCtl CntxCtl 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 8: REGISTER # DEC (HEX) 204 (CC) 205 (CD) 206 (CE) 207 (CF) 208 (D0) 209 (D1) 210 (D2) 211 (D3) 212 (D4) 213 (D5) 239 (EF) 242 (F2) 243 (F3) 245 (F5) 246 (F6) 255 (FF) NOTE: Camera Control Registers - Address Page 2 (continued) REGISTER NAME Camera Control Sequencer Parameter 3 Camera Control Sequencer Parameter 4 Camera Control Sequencer Parameter 5 Camera Control Sequencer Parameter 6 Camera Control Sequencer Parameter 7 Camera Control Sequencer Parameter 8 Camera Control Sequencer Parameter 9 Camera Control Sequencer Parameter 10 Camera Control Sequencer Parameter 11 Camera Control Sequencer Parameter 12 AWB Parameter 15 AWB Parameter 16 Reserved Color Correction Parameter 29 Color Correction Parameter 30 Color Correction Parameter 39 DATA FORMAT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DEFAULT VALUE DEC (HEX) MODULE 0 (0000) CntxCtl 2190 (21A0) CntxCtl 7835 (1E9B) CntxCtl 19018(4A4A) CntxCtl 5773 (168D) CntxCtl 77 (004D) CntxCtl 0 (0000) CntxCtl 0 (0000) CntxCtl 520 (0208) CntxCtl 0 (0000) CntxCtl 8 (0008) AWB 0 (0000) AWB 0 (0000) -- 135 (0040) ColorCorr 127 (007F) ColorCorr 43136(A880) ColorCorr Data Format Key: 0 = "Don't Care" bit. The exceptions: R0:0 and R255:0, which are hardwired R/O binary values. d = R/W bit ? = R/O bit. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Image Flow Processor Register Description Configuration The vast majority of IFP registers associate to one of the IFP modules. These modules are identified in Table 7 on page 14 and in Table 8 on page 17. Detailed register descriptions follow in Table 9 and in Table 10 on page 28. A few registers create effects across a number of module functions. These include R240 page map register (R/W); R6:1 0x106 operating mode control register (R/W); R8:1 0x108 output format control register (R/W); the R62:2 0x23E gain types and CCM threshold register--the gain threshold for CCM adjustment (R/W). Table 9: REGISTER# (HEX) R5:1--0x105 Default Description Bit 3 Bits 2:0 Colorpipe Register Description DESCRIPTION - Aperture Correction 0x0003 Aperture correction scale factor used for sharpening. Enables automatic sharpness reduction control (see R51:2 0x233). Sharpening factor: "000"--No sharpening. "001"--25% sharpening. "010"--50% sharpening. "011"--75% sharpening. "100"--100% sharpening. "101"--125% sharpening. "110"--150% sharpening. "111"--200% sharpening. R6:1--0x106 - Operating Mode Control (R/W) Default 0x700E Description This register specifies the operating mode of the IFP. Bit 15 Enables manual white balance. User can set the base matrix and color channel gains. This bit must be asserted and de-asserted with a frame in between to force new color correction settings to take effect. Bit 14 Enables auto exposure. Bit 13 Enables on-the-fly defect correction. Bit 12 Reserved--obsolete. The user should write "0" to this bit. Bit 11 Not used. Bit 10 Enables lens shading correction. 1: Enables lens shading correction. Bits 9:8 Reserved. Bit 7 Enables flicker detection. 1: Enables automatic flicker detection. Bit 6 Reserved for future expansion. Bit 5 Reserved. Bit 4 Bypasses color correction matrix. 1: Outputs "raw" color bypassing color correction. 0: Normal color processing. Bits 3:2 Auto exposure back light compensation control. "00"--Auto exposure sampling window is specified by R38:2 and R39:2 ("large window"). "01"--Auto exposure sampling window is specified by R43:2 and R44:2 ("small window"). "1X"--Auto exposure sampling window is specified by the weighted sum of the large window and the small window, with the small window weighted four times more heavily. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 9: Bit 1 Colorpipe Register Description (continued) Enables auto white balance. 1: Enables auto white balance. 0: Freezes white balance at current values. Bit 0 Reserved for future expansion. R8:1--0X108 - Output Format Control (R/W) Default 0x0080 Description This register specifies the output timing and format in conjunction with R58:1 or R155:1 (depending on the context). Bits 15:11 Reserved for future expansion. Bit 10 Gate PIXCLK. 0: PIXCLK not gated. 1: PIXCLK gated with LINE_VALID. Bit 9 Flip Bayer columns in processed Bayer output mode. 0: Column order is green, red and blue, green. 1: Column order is red, green and green, blue. Bit 8 Flip Bayer row in processed Bayer output mode. 0: First row contains green and red; the second row contains blue and green. 1: First row contains blue and green; the second row contains green and red. Bit 7 Controls the values used for the protection bits in Rec. ITU-R BT.656 codes. 0: Use zeros for the protection bits. 1: Use the correct values. Bit 5 Multiplexes Y (in YCbCr mode) or green (in RGB mode) channel on all channels (monochrome). 1: Forces Y/G onto all channels. Bit 4 Disables Cb color output channel (Cb = 128) in YCbCr mode and disables the blue color output channel (B = 0) in RGB mode. 1: Forces Cab to 128 or B to 0. Bit 3 Disables Y color output channel (Y = 128) in YCbCr and disables the green color output channel (G = 0) in RGB mode. 1: Forces Y to 128 or G to 0. Bit 2 Disables Cr color output channel (Cr = 128) in YCbCr mode and disables the red color output channel (R = 0) in RGB mode. 1: Forces Cr to 128 or R to 0. Bit 1 Toggles the assumptions about Bayer vertical CFA shift. 0: Row containing red comes first. 1: Row containing blue comes first. Bit 0 Toggles the assumptions about Bayer horizontal CFA shift. 0: Green comes first. 1: Red or blue comes first. R37:1--0x125 - Color Saturation Control (R/W) Default 0x0005 Description This register specifies the color saturation control settings. Bit 5:3 Specify overall attenuation of the color saturation. "000"--Full color saturation "001"--75% of full saturation "010"--50% of full saturation "011"--37.5% of full saturation "100"--25% of full saturation "101"--150% of full saturation "110"--Black and white 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 9: Bit 2:0 Colorpipe Register Description (continued) Specify color saturation attenuation at high luminance (linearly increasing attenuation from no attenuation to monochrome at luminance of 224). "000"--No attenuation. "001"--Attenuation starts at luminance of 216. "010"--Attenuation starts at luminance of 208. "011"--Attenuation starts at luminance of 192. "100"--Attenuation starts at luminance of 160. "101"--Attenuation starts at luminance of 96. R52:1--0x134 - Luma Offset (can be used to control brightness) (R/W) Default 0x0010 Description Offset added to the luminance prior to output. Bits 15:8 Y Offset in YCbCr mode. Bits 7:0 Offset in RGB mode. R53:1--0x135 - Luma Clip (R/W) Default 0xF010 Description Clipping limits for output luminance. Bits 15:8 Highest value of output luminance. Bits 7:0 Lowest value of output luminance. R58:1--0x13A - Output Format Control 2--Context A (R/W) Default 0x0200 Description Output format control 2--context A. Bit 14 Output processed Bayer data. Bit 13 Debug flicker luma. Bit 12 Reserved. Bit 11 Enables embedding Rec. ITU-R BT.656 synchronization codes in the output data. See R155:1. Bit 10 Entire image processing is bypassed and raw bayer is output directly. In YCbCr or RGB mode: 0: Normal operation, sensor core data flows through IFP. 1: Bypass IFP and output Imager data directly (full 10 bits). The image data still passes through the camera interface FIFO and the 10 bits are formatted to two output bytes through the camera interface; i.e., 8 + 2. Data rate is effectively the same as default 16-bit /per pixel modes. Auto exposure/AWB, etc., still function and control the sensor, though they are assuming some gain/correction through the colorpipe. See R155:1. Bit 9 Inverts output pixel clock. By default, this bit it asserted and data is launched off the falling edge of PIXCLK for capture by the receiver on the rising edge. See R155:1. Bit 8 Enables RGB output. 0: Output YCbCr data. 1: Output RGB format data as defined by R58:1[7:6]. Bits 7:6 RGB output format: "00"--16-bit RGB565. "01"--15-bit RGB555. "10"--12-bit RGB444x. "11"--12-bit RGBx444. Bits 5:4 Test Ramp output: "00"--Off. "01"--By column. "10"--By row. "11"--By frame. Outputs RGB or YCbCr values are shifted 3 bits up. Use with R58:1[5:4] to test LCDs with low color depth. Averages two nearby chrominance bytes. See R155:1. Bit 3 Bit 2 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 9: Colorpipe Register Description (continued) Bit 1 In YCbCr mode swap C and Y bytes. In RGB mode, swap odd and even bytes. See R155:1. Bit 0 In YCbCr mode, swaps Cb and Cr channels. In RGB mode, swaps R and B channels. See R155:1. R72:1--0x148 - Test Pattern Generator control (R/W) Default 0x0000 Description This register enables test pattern generation at the input of the image processor. Values greater than "0" turn on the test pattern generator. The brightness of the flat-color areas depends on the value programmed (from 6-1) in this register. The value 7 produces the color bar pattern. Value 0 selects the sensor image. Bit 7 Test pattern selection. Bits 2:0 1: Forces WB digital gains to 1.0. 0: Normal operation. R153:1--0x199 - Line Counter (R/O) Default N/A Description Use line counter to determine the number of the line currently being output. Bits 15:0 Line count. R154:1--0x19A - Frame Counter (R/O) Default N/A Description Use frame counter to determine the index of the frame currently being output. Bits 15:0 Frame count. R155:1--0x19B - Output Format Control 2--Context B (R/W) Default 0x0200 Description Output format control 2--context B. Bit 14 Output processed Bayer data. Bit 13 Reserved. Bit 12 Reserved Bit 11 Enables embedding Rec. ITU-R BT.656 synchronization codes to the output data. See R58:1. Bit 10 Entire image processing is bypassed and raw bayer is output directly. In YCbCr or RGB mode: 0: Normal operation, sensor core data flows through IFP. 1: Bypass IFP and output Imager data directly (full 10 bits). The image data still passes through the camera interface FIFO and the 10 bits are formatted to two output bytes through the camera interface; i.e., 8 + 2. Data rate is effectively the same as default 16-bit /per pixel modes. auto exposure/AWB, etc. still function and control the sensor, though they are assuming some gain/correction through the colorpipe. See R58:1. Bit 9 Inverts output pixel clock. By default, this bit it asserted and data is launched off the falling edge of PIXCLK for capture by the receiver on the rising edge. See R58:1. Bit 8 Enables RGB output. 0: Output YCbCr data. 1: Output RGB format data as defined by R155:1[7:6]. See R58:1. Bits 7:6 RGB output format: "00"--16-bit RGB565. "01"--15-bit RGB555. "10"--12-bit RGB444x. "11"--12-bit RGBx444. Bits 5:4 Test Ramp output: "00"--Off. "01"--By column. "10"--By row. "11"--By frame. Bit 3 Bit 2 Output RGB or YCbCr values are shifted 3 bits up. Use with R58:1[5:4] to test LCDs with low color depth. Averages two nearby chrominance bytes. See R58:1 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 9: Colorpipe Register Description (continued) Bit 1 In YCbCr mode swap C and Y bytes. In RGB mode, swap odd and even bytes. See R58:1. Bit 0 In YCbCr mode, swaps Cb and Cr channels. In RGB mode, swaps R and B channels. See R58:1. R161:1--0x1A1 - Reducer Horizontal Output Size Resize--Context B (R/W) R164:1--0x1A4 - Reducer Vertical Output Size Resize--Context B (R/W) Default 0x0IE0 Description Controls reducer vertical output size in context B. (Sensor Window Height 179 = YZoom Window Height = Output YSize) Bits 10:0 Y Size. R165:1--0x1A5 - Reducer Horizontal Pan Resize (R/W) Default 0x0000 Description Controls reducer horizontal pan. Pan and Zoom settings are NOT context switchable. The same field of view will be active for both context A and context B. Bit 14 0: MT9V112-compatible offset from X = 0. 1: Centered origin at 320 for more convenient zoom and resize. Bits 10:0 X Pan: Unsigned offset from X = 0 (Bit 14 = 0), or two's complement from X = 320 (Bit 14 = 1). R166:1--0x1a6 - Reducer Horizontal Zoom Resize (R/W) Default 0x0280 Description Controls reducer horizontal zoom. Pan and Zoom settings are NOT context switchable. The same field of view will be active for both context A and context B. Bits 10:0 X Zoom. R167:1--0x1a7 - Reducer Horizontal Output Size Resize--Context A (R/W) Default 0x0140 Description Controls reducer horizontal output size in context A. Bits 10:0 X Size. R168:1--0x1A8 - Reducer Vertical Pan Resize (R/W) Default 0x0000 Description Controls reducer vertical pan. Pan and Zoom settings are NOT context switchable. The same field of view will be active for both context A and context B. Bit 14 0: MT9V112-compatible origin at Y = 0. 1: Centered origin at Y = 240 for more convenient zoom and resize. Bits 10:0 Y Pan: unsigned offset from y = 0 (Bit 14 = 0), or two's complement from Y = 240 (Bit 14 = 1). R169:1--0x1A9 - Reducer Vertical Zoom Resize (R/W) Default 0x0IE0 Description Controls reducer vertical zoom. Pan and Zoom settings are NOT context switchable. The same field of view will be active for both context A and context B. Bits 10:0 Y Zoom. R170:1--0x1AA - Reducer Vertical Output Size Resize--Context A (R/W) Default 0x00F0 Description Controls reducer vertical output size in context A. Bits 10:0 Y Size. R171:1--0x1AB - Reducer Current Horizontal Zoom (R/O) Default 0x0280 Description Current horizontal zoom. Bits 13:12 IR X shift. 0: No IR 1: 2x 2: 4x 3: 8x 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 9: Bits 11:0 Colorpipe Register Description (continued) Current zoom window width. After automatic zoom (R175:1), copy R171:1 to the snapshot X Zoom register R166:1 (context A) or R160:1 (context B) so the snapshot has the same field of view as preview. Also copy to snapshot X Size register R167:1 (context A) or R161 (context B) for largest snapshot. R172:1--0x1AC - Reducer Current Vertical Zoom (R/O) Default 0x0IE0 Description Current vertical zoom. Bits 13:12 IR Y Shift. 0: No IR 1: 2x 2: 4x 3: 8x Bits 11:0 Current zoom window height. After automatic zoom (R175:1), copy R172:1 to the snapshot Y Zoom register R169:1 (context A) or R163:1 (context B) so the snapshot has the same field of view as preview. Also copy to snapshot X Size register R170:1 (context A) or R164 (context B) for largest snapshot. R174:1--0x1AE - Reducer Zoom Step Size (R/W) Default 0x0C09 Description Zoom step sizes. Should be a multiple of the aspect ratio 5:4 for VGA or 4:3 VGA or 11:9 for CIF. Bits 15:8 Zoom step size in X. Bits 7:0 Zoom step size in Y. R175:1--0x1AF - Reducer Zoom Control (R/W) Default 0x0000 Description Resize Interpolation and zoom control. Bit 15:10 Reserved. Bit 9 Starts automatic "zoom out" in step sizes defined in R174:1. Bit 8 Starts automatic "zoom in" in step sizes defined in R174:1. Bit 7:0 Reserved. R200:1--0x1C8 - Global Context Control (R/W) Default 0x0000 Description Defines sensor and colorpipe context for current frame. Registers R200:0, R200:1, and R200:2 are shadows of each other. See description in R200:2. It is recommended that all updates to R200:n are handled by means of a WRITE to R200:2. Bit 15:0 See R200:2[15:0]. R226:1--0x1E2 - Effects Mode (R/W) Default 0x7000 Description This register specifies which of several special effects to apply to each pixel passing through the pixel pipe. Bits 15:8 Solarization threshold. Bits 2:0 Specification of the effects mode. "000"--No effect (pixels pass through unchanged). "001"--Monochrome (chromas set to 0). "010"--Sepia (chromas set to the value in the effects sepia register). "011"--Negative (all color channels inverted). "100"--Solarize (luma conditionally inverted). "101"--Solarize2 (luma conditionally inverted, chromas inverted when luma inverted). R227:1--0x1E3 - Effects Sepia (R/W) Default 0xB023 Description This register specifies the chroma values for the sepia effect. In sepia mode, the chroma values of each pixel are set to this value. By default, this register contains a brownish color, but it can be set to an arbitrary color. Bit 15 Sign of Cb. Bits 14:8 Magnitude of Cb in 0.7 fixed point. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 9: Bit 7 Bits 6:0 Colorpipe Register Description (continued) Sign of Cr. Magnitude of Cr in 0.7 fixed point. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 10: Camera Control Register Description R38:2--0x226 - Auto Exposure Horizontal Window Boundaries (R/W) Default 0x8000 Description This register specifies the left and right boundaries of the window used by the auto exposure measurement engine. The values programmed in the registers are the fractional percentage, where 128 (decimal) is the right-most edge of the frame, 64 (decimal) is the middle of the frame, and 0 is the left-most edge of the frame. Bits 15:8 Right window boundary. Bits 7:0 Left window boundary. R39:2--0x227 - Auto Exposure Vertical Window Boundaries (R/W) Default 0x8008 Description This register specifies the top and bottom boundaries of the window used by the auto exposure measurement engine. The values programmed in the registers are the fractional percentage, where 128 (decimal) is the bottom edge of the frame, 64 (decimal) is the middle of the frame, and 0 is the top edge of the frame. Bits 15:8 Bottom window boundary. Bits 7:0 Top window boundary. R43:2--0x22B - Auto Exposure Horizontal Center Window Boundaries (R/W) Default 0x6020 Description This register specifies the left and right boundaries of the window used by the auto exposure measurement engine in back light compensation mode. The values programmed in the registers are the fractional percentage, where 128 (decimal) is the right-most edge of the frame, 64 (decimal) is the middle of the frame, and 0 is the left-most edge of the frame. Bits 15:8 Right window boundary. Bits 7:0 Left window boundary. R44:2--0x22C - Auto Exposure Vertical Center Window Boundaries (R/W) Default 0x6020 Description This register specifies the top and bottom boundaries of the window used by the auto exposure measurement engine in back light compensation mode. The values programmed in the registers are the fractional percentage, where 128 (decimal) is the bottom edge of the frame, 64 (decimal) is the middle of the frame, and "0" is the top edge of the frame. Bits 15:8 Bottom window boundary. Bits 7:0 Top window boundary. R45:2--0x22D - AWB Window Boundaries (R/W) Default 0xF0A0 Description This register specifies the boundaries of the window used by the AWB measurement engine. Essentially, it describes the AWB measurement window in terms relative to the size of the image--horizontally, in units of 1/10ths of the width of the image; vertically, in units of 1/16 of the height of the image. So although the positioning is highly quantized, the window remains roughly in place as the resolution changes. Bits 15:12 Bottom window boundary (in units of blocks). Bits 11:8 Top window boundary (in units of blocks). Bits 7:4 Right window boundary (in units of 2 blocks). Bits 3:0 Left window boundary (in units of 2 blocks). R46:2--0x22E - Auto Exposure Target and Precision Control (R/W) Default 0x0C4A Description This register specifies the luma target of the auto exposure algorithm and the size of the window/range around the target in which no auto exposure adjustment is made. This window is centered on target, but the value programmed in the register is 1/2 of the window size. Bits 15:8 Half-size of the auto exposure stability window/range. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 10: Camera Control Register Description (continued) Bits 7:0 Luma value of the auto exposure target. R47:2--0x22F - Auto Exposure Speed and Sensitivity Control--Context A (R/W) Default 0xDF20 Description This register specifies the speed and sensitivity to changes of auto exposure in context A. Bit 15 Reserved. Bit 14 Reserved. Bits 13:12 Reserved. Bit 11 Reserved. Bit 10 Reserved. Bit 9 Reserved. Bits 8:6 Factor of reduction of the difference between current luma and target luma. In one adjustment auto exposure advances from current luma to target as follows: "000"--1/4 way going down, 1/8 going up. "001"--1/4 way in both directions. "010"--1/2 way in both directions. "011"--1/2 way going down, 1/4 going up. "100"--All the way in both directions (fast adaptation!). "101"--3/4 way in both directions. "110"--7/8 way in both directions. "111"--Reserved. Currently the same as "100" Bit 5 Bits 4:3 Bits 2:0 Reserved Auto exposure luma is updated every N frames, where N is given by this field. Hysteresis control via time-averaged smoothing of luma data. Luma measurements for auto exposure are time-averaged as follows: "000"--Auto exposure luma = current luma. "001"--Auto exposure luma = 1/2 current luma + 1/2 buffered value. "010"--Auto exposure luma = 1/4 current luma + 3/4 buffered value. "011"--Auto exposure luma = 1/8 current luma + 7/8 buffered value. "100"--Auto exposure luma = 1/16 current luma + 15/16 buffered value. "101"--Auto exposure luma = 1/32 current luma + 31/32 buffered value. "110"--Auto exposure luma = 1/64 current luma + 63/64 buffered value. "111"--Auto exposure luma = 1/128 current luma + 127/128 buffered value. R91:2--0x25B - Flicker Control (R/W) Default 0x0002 Description Primary Flicker Control Register. Bit 15 (READ only) 50Hz/60Hz detected. 0: 50Hz detected. 1: 60Hz detected. Bit 2 Reserved. Bit 1 When in "manual" flicker mode (R91:2[0] = 1), defines which flicker frequency to avoid. 0: Forces 50Hz detection. 1: Forces 60Hz detection. Bit 0 0: Auto flicker detection. 1: Manual Mode. R98:2--0x262 - Auto Exposure Digital Gains Monitor (R/W*) Default Description These digital gains are applied within the IFP; they are independent of the imager gains. Bits 15:8 Post-lens correction digital gain (writable if auto exposure is disabled). Bits 7:0 Pre-lens correction digital gain (writable if auto exposure is disabled). 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 10: Camera Control Register Description (continued) R103:2--0x267 - Auto Exposure Digital Gain Limits (R/W) Default 0x4010 Description This register specifies the upper limits of the digital gains used by the auto exposure algorithm. The values programmed to this register are 16 times the absolute gain values. The value of 16 represents the gain 1.0. Bits 15:8 Maximum limit on post-lens correction digital gain. Bits 7:0 Maximum limit on pre-lens correction digital gain. R156:2--0x29C - Auto Exposure Speed and Sensitivity Control--Context B (R/W) Default 0xDF20 Description This register specifies the speed and sensitivity to auto exposure changes in context B. Bit 15 Reserved. Bit 14 Reserved. Bits 13:12 Reserved. Bit 11 Reserved. Bit 10 Reserved. Bit 9 Reserved. Bits 8:6 Factor of reduction of the difference between current luma and target luma. In one adjustment, auto exposure advances from current luma to target as follows: "000"--1/4 way going down, 1/8 going up. "001"--1/4 way in both directions. "010"--1/2 way in both directions. "011"--1/2 way going down, 1/4 going up. "100"--All the way in both directions (fast adaptation!). "101"--3/4 way in both directions. "110"--7/8 way in both directions. "111"--Reserved. Currently the same as "100." Bit 5 Bits 4:3 Bits 2:0 Reserved. Auto exposure luma is updated every N frames, where N is given by this field. Hysteresis control via time-averaged smoothing of luma data. Luma measurements for auto exposure are time-averaged as follows: "000"--Auto exposure luma = current luma. "001"--Auto exposure luma = 1/2 current luma + 1/2 buffered value. "010"--Auto exposure luma = 1/4 current luma + 3/4 buffered value. "011"--Auto exposure luma = 1/8 current luma + 7/8 buffered value. "100"--Auto exposure luma = 1/16 current luma + 15/16 buffered value. "101"--Auto exposure luma = 1/32 current luma + 31/32 buffered value. "110"--Auto exposure luma = 1/64 current luma + 63/64 buffered value. "111"--Auto exposure luma = 1/128 current luma + 127/128 buffered value. R180:2 - Reserved R200:2--0x2C8 - Global Context Control (R/W) Default 0x0000 Description Defines sensor and colorpipe context for current frame. Context A is typically used to define preview or viewfinder mode, while context B is typically used for snapshots. The bits of this register directly control the respective functions, so care must be taken when writing to this register if a bad frame is to be avoided during the context switch. Bit 15 Controls assertion of sensor restart on update of global context control register. This helps ensure that the very next frame is generated with the new context (a problem with regard to exposure due to the rolling shutter). This bit is automatically cleared once the restart has occurred. 0: Do not restart sensor. 1: Restart sensor. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 10: Camera Control Register Description (continued) Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Reserved. Reserved. Reserved. Reserved. Resize/zoom context. Switch resize/zoom contexts: 0: Context A 1: Context B Output format control 2 Context. See R58:1 and R155:1. 0: Context A 1: Context B Gamma table context. 0: Context A 1: Context B Arm Xenon Flash. Blanking control. This is primarily for use by the internal sequencer when taking automated (e.g., flash) snapshots. Setting this bit stops frames from being sent over the BT656 external pixel interface. This is useful for ensuring that the desired frame during a snapshot sequence is the only frame captured by the host. 0: No blanking 1: Blank frames to host Reserved. Reserved. Sensor Read Mode context (skip mode, power mode (second ADC on/off), see R33:0 and R32:0. 0: Context A 1: Context B LED Flash ON: 0: Turn off LED Flash 1: Turn on LED Flash Vertical blanking context: 0: Context A 1: Context B Horizontal blanking context: 0: Context A 1: Context B Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Sensor Core Overview The sensor consists of a pixel array of 695 x 504 total, an analog readout chain, 10-bit ADC with programmable gain and black offset, and timing and control. Figure 6: Pixel Array Description (0, 0) 14 Black Rows Figure 5: Sensor Core Block Diagram VGA (640 x 480) + 4-pixel boundary for 12 Black Columns color correction + additional active column + additional active row = 649 x 489 active pixels 34 Black Columns Control Register Active Pixel Sensor (APS) Array Communication Bus to IFP Clock (694,503) Sync Signals Timing and Control 1 Black Row Analog Processing ADC 10-Bit Data to IFP Pixel Data Format Pixel Array Structure The sensor core pixel array is configured as 695 columns by 504 rows, shown in Figure 6. The first 34 columns and the first 14 rows of pixels are optically black, and can be used to monitor the black level. The last 12 columns and the last row of pixels also are optically black. The black row data is used internally for the automatic black level adjustment. However, these black rows can also be read out by setting the sensor to raw data output mode. There are 649 columns by 489 rows of opticallyactive pixels that provide a four-pixel boundary around the VGA (640 x 480) image to avoid boundary effects during color interpolation and correction. The additional active column and additional active row are used to enable horizontally and vertically mirrored readout to start on the same color pixel. The sensor core uses an RGB Bayer color pattern, shown in Figure 7. The even-numbered rows contain green and red color pixels, and odd-numbered rows contain blue and green color pixels. The even-numbered columns contain green and blue color pixels; odd-numbered columns contain red and green color pixels. Figure 7: Pixel Color Pattern Detail (top right corner) Column Readout Direction . . . Black Pixels First Clear Pixel (34, 14) G Row Readout Direction R G G B R G G B R G G B B ... G R G R G R G B G B G R G B G B G R G B G B G R G B G B 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Output Data Format The sensor core image data is read out in a progressive scan. Valid image data is surrounded by horizontal blanking and vertical blanking, shown in Figure 8. LINE_VALID is HIGH during the shaded region of the figure. FRAME_VALID timing is described in "Appendix A" on page 52. Figure 8: Spatial Illustration of Image Readout P0,0 P0,1 P0,2.....................................P0,n-1 P0,n P1,0 P1,1 P1,2.....................................P1,n-1 P1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VALID IMAGE HORIZONTAL BLANKING Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00 Pm,0 Pm,1.....................................Pm,n-1 Pm,n 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 VERTICAL BLANKING 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VERTICAL/HORIZONTAL BLANKING 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Sensor Core Registers Table 11: Sensor Registers - Address Page 0 REGISTER# DEC (HEX) 0 (0x00) 1 (0x01) 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) 7 (0x07) 8 (0x08) 9 (0x09) 10 (0x0A) 11 (0x0B) 12 (0x0C) 13 (0x0D) 32 (0x20) 33 (0x21) 34 (0x22) 35 (0x23) 36 (0x24) 43 (0x2B) 44 (0x2C) 45 (0x2D) 46 (0x2E) 47 (0x2F) 48 (0x30) 49 (0x31) 50 (0x32) 51 (0x33) 52 (0x34) 53 (0x35) 54 (0x36) 55 (0x37) 59 (0x3B) 60 (0x3C) 61 (0x3D) 62 (0x3E) 63 (0x3F) 64 (0x40) 65 (0x41) 66 (0x42) 88 (0x58) 89 (0x59) 90 (0x5A) REGISTER NAME Chip Version Row Start Column Start Row Width Column Width Horizontal Blanking--Context B Vertical Blanking--Context B Horizontal Blanking--Context A Vertical Blanking--Context A Shutter Width Row Speed Extra Delay Shutter Delay Reset Read Mode--Context B Read Mode--Context A Reserved Flash Control Reserved Green1 Gain Blue Gain Red Gain Green2 Gain Global Gain Reserved Reserved Reserved Reserved Reserved Clip Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved New Black Level Algorithm Reserved Reserved DATA FORMAT 0001 0010 0010 1001 (LSB) 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 00dd dddd dddd dddd 0ddd dddd dddd dddd 00dd dddd dddd dddd 0ddd dddd dddd dddd dddd dddd dddd dddd ddd0 000d dddd dddd 00dd dddd dddd dddd 00dd dddd dddd dddd d000 00dd 00dd dddd dd00 0ddd dddd dddd 0000 0d00 0000 dd00 -- ??dd dddd dddd dddd -- 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DEFAULT VALUE DEC (HEX) 4649 (0x1229) 18 (0x12) 38 (0x0026) 480 (0x01E0) 640 (0x280) 203 (0xCB) 11 (0x0B) 203 (0xCB) 11 (0x0B) 470 (0x1D6) 17 (0x0011) 0 (0x0000) 0 (0x0000) 8 (0x0008) 1792 (0x0700) 1024 (0x0400) 299 (0x012B) 1544 (0x0608) 16384 (0x4000) 32 (0x0020) 32 (0x0020) 32 (0x0020) 32 (0x0020) 32 (0x0020) 1066 (0x042A) 7168 (0x1C00) 42 (0x002A) 833 (0x0341) 49160 (0xC009) 8226 (0x2022) 61680 (0xF0F0) 0 (0x0000) 33 (0x0021) 6688 (0x1A20) 8222 (0x201E) 8224 (0x2020) 4128 (0x1020) 8192 (0x2000) 215 (0x00D7) 1911 (0x0777) 0 (0x000) 12 (0x000C) 57354 (0xE00A) 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 11: Sensor Registers - Address Page 0 (continued) REGISTER# DEC (HEX) 91 (0x5B) 92 (0x5C) 93 (0x5D) 94 (0x5E) 95 (0x5F) 96 (0x60) 97 (0x61) 98 (0x62) 99 (0x63) 100 (0x64) 112 (0x70) 113 (0x71) 114 (0x72) 115 (0x73) 116 (0x74) 117 (0x75) 118 (0x76) 119 (0x77) 120 (0x78) 121 (0x79) 122 (0x7A) 123 (0x7B) 124 (0x7C) 125 (0x7D) 126 (0x7E) 127 (0x7F) 128 (0x80) 129 (0x81) 130 (0x82) 131 (0x83) 132 (0x84) 133 (0x85) 134 (0x86) 135 (0x87) 200 (0xC8) 240 (0xF0) 241 (0xF1) 245 (0xF5) 246 (0xF6) 247 (0xF7) 248 (0xF8) 249 (0xF9) 250 (0xFA) 251 (0xFB) 252 (0xFC) REGISTER NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Context Control Page Map Bytewise Address Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DATA FORMAT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- d000 0000 d000 dddd 0000 0000 0000 0ddd Reserved -- -- -- -- -- -- -- -- DEFAULT VALUE DEC (HEX) N/A N/A N/A N/A 8989 (0x231D) 128 (0x0080) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 31498 (0x7B0A) 31498 (0x7B0A) 6414 (0x190E) 29967 (0x750F) 22322 (0x5732) 22068 (0x5634) 29493 (0x7335) 12306 (0x3012) 30978 (0x7902) 29958 (0x7506) 30474 (0x770A) 30729 (0x7809) 32006 (0x7D06) 12560 (0x3110) 126 (0x007E) 31745 (0x7C01) 22788 (0x5904) 22788 (0x5904) 22282 (0x570A) 22539 (0x580B) 18188 (0x470C) 18446 (0x480E) 23298 (0x5B02) 92 (0x005C) 11 (0x000B) 0 (0x0000) Reserved 1023 (0x03FF) 511 (0x01FF) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 11: Sensor Registers - Address Page 0 (continued) REGISTER# DEC (HEX) 253 (0xFD) 255 (0x00) NOTE: REGISTER NAME Reserved Chip Version DATA FORMAT -- 0001 0010 0010 1001 (LSB) DEFAULT VALUE DEC (HEX) 0 (0x0000) 4649 (0x1229) Data Format Key: 0 = "Don't Care" bit d = R/W bit ? = R/O bit. The exceptions: R0:0 and R255:0, which are hardwired R/O binary values. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 12: Sensor Core Register Descriptions BIT FIELD DESCRIPTION DEFAULT (HEX) 0x1229 0x12 Y YM SYNC'D TO FRAME START BAD READ/ FRAME WRITE R W R0:0--0x000 - Chip Version (R/O) Bits 15:0 Hardwired READ only. R1:0--0x001 - Row Start Bits 10:0 The first row to be read out (not counting dark rows that may Row Start be read). To window the image down, set this register to the starting Y value. Setting a value less than 8 is not recommended since the dark rows should be read using Reg0x022. R2:0--0x002 - Column Start Bits 10:0 The first column to be read out (not counting dark columns that Col Start may be read). To window the image down, set this register to the starting X value. Setting a value below 0x18 is not recommended since readout of dark columns should be controlled by Reg0x022. R3:0--0x003 - Row Width Bits 10:0 Number of rows in the image to be read out (not counting dark Row Width rows or border rows that may be read). R4:0--0x004 - Column Width Bits 10:0 Number of columns in image to be read out (not counting dark Col Width columns or border columns that may be read). R5:0--0x005 - Horizontal Blanking--Context B Bits 10:0 Number of blank columns in a row when context B is chosen (bit Horizontal 0, Reg0x0C8 = 1). The extra columns are added at the beginning Blanking B of a row. The minimum supported value is 132. R6:0--0x006 - Vertical Blanking--Context B Bits 14:0 Number of blank rows in a frame when context B is chosen (bit Vertical 1, Reg0x0C8 = 1). This number must be equal to or larger than Blanking B the number of dark rows read out in a frame specified by Reg0x022. R7:0--0x007 - Horizontal Blanking--Context A Bits 10:0 Number of blank columns in a row when context A is chosen (bit Horizontal 0, Reg0x0C8 = 0). The extra columns are added at the beginning Blanking A of a row. The minimum supported value is 132. R8:0--0x008 - Vertical Blanking--Context A Bits 14:0 Number of blank rows in a frame when context A is chosen (bit Vertical 1, Reg0x0C8 = 1). This number must be equal to or larger than Blanking A the number of dark rows read out in a frame specified by Reg0x022. R9:0--0x009 - Shutter Width Bits 15:0 Integration time in number of rows. In addition to this register, Shutter the shutter delay register (Reg0x0C) and the overhead time Width influences the integration time for a given row time. R10:0--0x00A - Row Speed Bit 13 Invert to cb clock. Bit 8 Invert pixel clock. When set, LINE_VALID, FRAME_VALID, and Invert Pixel DATA_OUT is set to the falling edge of PIXCLK. When clear, they Clock are set to the rising edge if there is no pixel clock delay. 0x26 Y YM W 0x1E0 Y YM W 0x284 Y YM W 0xCB Y YM W 0x0B Y N W 0xCB Y YM W 0xB Y N W 0x1D6 Y N W -- 0x0 -- N -- 0 -- W 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 12: Sensor Core Register Descriptions (continued) BIT FIELD Bits 7:4 Delay Pixel Clock DESCRIPTION DEFAULT (HEX) 0x1 SYNC'D TO FRAME START N BAD READ/ FRAME WRITE 0 W Delay PIXCLK in half-master-clock cycles. When set, the pixel clock can be delayed in increments of half-master- clock cycles compared to the synchronization of FRAME_VALID, LINE_VALID, and DATA_OUT. Bits 3:0 The pixel clock period is doubled, so the ADC clock period Pixel Clock remains the same for one programmed register value. The value Speed "0" is not allowed, and "1" is used instead. R11:0--0x00B - Extra Delay Bits 13:0 Extra blanking inserted between frames specified in pixel clocks. Extra Delay Can be used to get a more exact frame rate. For integration times less than a frame, however, it might affect the integration times for parts of the image. R12:0--0x00C - Shutter Delay Bits 10:0 The amount of time from the end of the sampling sequence to Shutter the beginning of the pixel reset sequence. This variable is Delay automatically halved in low-power mode, so the time in use remains the same. This register has an upper value defined by the fact that the reset needs to finish prior to readout of that row to prevent changes in the row time. R13:0--0x00D - Reset Bit 15 0: Normal operation, updates changes to registers that affect Synchronize image brightness at the next frame boundary (integration time, Changes integration delay, gain, horizontal blanking and vertical blanking, window size, row/column skip, or row mirror. 1: Do not update any changes to these settings until this bit is returned to "0." All registers that are frame-synchronized are affected by this bit setting. Bit 13 Setting this bit turns off all SOC clocks. Stop_soc Bit 12 By setting this bit, the CLK_IN is divided by two before going to Div 2 master clock control. Bit 10 Setting this bit converts SHIP_ID from default to the other Switch (0xBA/0xBB => 0x90/0x91). Two-wire Interface ID Bit 9 When set, a forced restart occurs when a bad frame is detected. Restart Bad This can shorten the delay when waiting for a good frame Frames because the delay when masking out a bad frame is the integration time rather than the full frame time. Bit 8 0: Only output good frames (default) Show Bad A bad frame is defined as the first frame following a change to: Frames window size or position, horizontal blanking, pixel clock speed, zoom, row or column skip, or mirroring. 1: Output all frames (including bad frames) Bit 7 Setting this bit stops STANDBY from affecting entry to or exit Inhibit from the low-power state. Standby Bit 6 By default, asserting STANDBY causes the ball interface to enter Drive High-Z. Setting this bit stops STANDBY from contributing to Signals output enable control. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 0x1 Y YM W 0x0 Y 0 W 0x0 Y N W 0x0 N 0 W 0x0 0x0 0x0 N N N 0 0 N W W W 0x0 N 0 W 0x0 N 0 W 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 12: Sensor Core Register Descriptions (continued) BIT FIELD Bit 5 Reset SOC Bit 4 Output Disable Bit 3 Chip Enable DESCRIPTION This reset signal is fed directly to the SOC part of the chip, and has no functionality in a stand alone sensor. When set, the output signals are tri-stated. DEFAULT (HEX) 0x0 0x0 SYNC'D TO FRAME START N N BAD READ/ FRAME WRITE 0 0 W W 0: Stop sensor readout. When this is returned to "1," sensor readout restarts and begins resetting the starting row in a new frame. To reduce the digital power, the master clock to the sensor can be disabled or STANDBY can be used. 1: Normal operation. Bit 2 0: Normal operation (default) Standby 1: Disable analog circuitry and internal clocks. Whenever this bit is set to "1" the chip enable bit (bit 3) should be set to "0." Bit 1 Setting this bit causes the sensor to abandon the current frame Restart and start resetting the first row. The delay before the first valid frame is read out equals the integration time. This bit always reads "0." Bit 0 Setting this bit puts the sensor in reset mode; this sets the sensor Reset to its default power-up state. Clearing this bit resumes normal operation. R32:0--0x020 - Read Mode--Context B 0: LINE_VALID determined by bit 9. Bit 15 Ineffective if Continuous LINE_VALID is set. XOR Line 1: LINE_VALID = "Continuous" Line Valid XOR Frame Valid, Valid Bit 14 0: Normal LINE_VALID (default, no line valid during vertical Continuous blanking). Line Valid 1: "Continuous" LINE_VALID (continue producing line valid during vertical blanking). Bit 10 When READ mode context B is selected (bit 3, Reg0x0C8 = 1): Low-Power 0: Full power, maximum readout speed. Mode-- 1: Low power. Maximum readout frequency is now half of the Context B master clock, and the pixel clock is automatically adjusted as described for the pixel clock speed register. Bit 9 This bit indicates whether to show the border enabled by bit 8. Show When bit 8 is 0, this bit has no meaning. When bit 8 is 1, this bit Border decides whether the border pixels should be treated as extra active pixels (1) or extra blanking pixels (0). Bit 8 When this bit is set, a 4-pixel border is output around the active Over Sized image array independent of readout mode (skip, zoom, mirror, etc.). Setting this bit therefore adds eight to the numbers of rows and columns in the frame. Bits 7:6 Reserved. Bit 5 Column Skip 4x Bit 4 Row Skip 4x 0: Normal readout. 1: READ out two columns, and then skip six columns (as with rows). 0: Normal readout. 1: READ out two rows, and then skip six rows (i.e., row 8, row 9, row 16, row 17...). 0x1 N YM W 0x0 N YM W 0x0 N YM W 0x0 N YM W 0x0 N 0 W 0x0 N 0 W 0x1 Y YM W 0x1 N 0 W 0x1 Y YM W 0x0 0x0 Y Y YM YM W W 0x0 Y YM W 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 12: Sensor Core Register Descriptions (continued) BIT FIELD Bit 3 Column Skip 2x -- Context B Bit 2 Row Skip 2x-- Context B Bit 1 Mirror Columns DESCRIPTION DEFAULT (HEX) 0x0 SYNC'D TO FRAME START Y BAD READ/ FRAME WRITE YM W When READ mode context B is selected (bit 3, Reg0x0C8 = 1): 0: Normal readout. 1: READ out two columns, and then skip two columns (as with rows). When READ mode context B is selected (bit 3, Reg0x0C8 = 1): 0: Normal readout. 1: READ out two rows, then skip two rows (i.e., row 8, row 9, row 12, row 13...). Read out columns from right to left (mirrored). When set, column readout starts from column (Col Start + Col Size) and continues down to (Col Start + 1). When clear, readout starts at Col Start and continues to (Col Start + Col Size - 1). This ensures that the starting color is maintained. Bit 0 Read out rows from bottom to top (upside down). When set, Mirror row readout starts from row (Row Start + Row Size) and Rows continues down to (Row Start + 1). When clear, readout starts at Row Start and continues to (Row Start + Row Size - 1). This ensures that the starting color is maintained. R33:0--0x021 - Read Mode--Context A Bit 10 When READ mode, context A is selected (bit 3, Reg0x0C8 = 0): Low-Power 0: Full power, maximum readout speed. Mode-- 1: Low power. Maximum readout frequency is now half of the Context A master clock, and the pixel clock is automatically adjusted as described for the pixel clock speed register. Bit 3 When READ mode context A is selected (bit 3, Reg0x0C8 = 0): Column 0: Normal readout. Skip 2x -- 1: READ out two columns, and then skip two columns (as with Context A rows). Bit 2 When READ mode context A is selected (bit 3, Reg0x0C8 = 0): Row Skip 0: Normal readout. 2x-- 1: READ out two rows, and then skip two rows (i.e., row 8, row Context A 9, row 12, row 13...). R35:0--0x023 - Flash Control Bit 15 READ only bit that indicates whether FLASH_STROBE is enabled. Flash Strobe Bit 14 Reserved. Bit 13 Enable Xenon flash. When set, the FLASH_STROBE output signal Xenon Flash is pulsed HIGH for the programmed period during vertical blanking. This is achieved by keeping the integration time equal to one frame and the pulse width less than the vertical blanking time. Bits 12:11 Delay of the flash pulse measured in frames. Frame Delay Bit 10 0: In Xenon mode, the flash should be enabled after the End of readout of a frame. Reset 1: In Xenon mode, the flash should be triggered after the resetting of a frame. 0x0 Y YM W 0x0 Y YM W 0x0 Y YM W 0x1 Y YM W 0x0 Y YM W 0x0 Y YM W 0x0 -- 0x0 0 -- Y 0 -- N R -- W 0x0 N N W 0x1 N N W 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 12: Sensor Core Register Descriptions (continued) BIT FIELD Bit 9 Every Frame Bit 8 LED Flash DESCRIPTION DEFAULT (HEX) 0x1 0x0 SYNC'D TO FRAME START N Y BAD READ/ FRAME WRITE N Y W W 0: Flash should be enabled for one frame only. 1: Flash should be enabled every frame. Enables LED flash. When set, the FLASH_STROBE goes on prior to the start of a frame reset. When disabled, the FLASH_STROBE remains HIGH until readout of the current frame completes. Bits 7:0 Length of FLASH_STROBE pulse when Xenon flash is enabled. Xenon The value specifies the length in 1,024 master clock cycle Count increments. R43:0--0x02B - Green1 Gain Bits 11:9 Total gain = (Bit 9 + 1) x (Bit 10 + 1) (Bit 11 + 1) x analog gain Digital Gain (each bit gives 2x gain). Bits 8:7 Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives Analog 2x gain). Gain Bits 6:0 Initial gain = bits (6:0) x 0.03125. Initial Gain R44:0--0x02C - Blue Gain Bits 11:9 Total gain = (Bit 9 + 1) x (Bit 10 + 1) (Bit 11 + 1) x analog gain Digital Gain (each bit gives 2x gain). Bits 8:7 Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives Analog 2x gain). Gain Bits 6:0 Initial gain = bits (6:0) x 0.03125. Initial Gain R45:0--0x02D - Red Gain Bits 11:9 Total gain = (Bit 9 + 1) x (Bit 10 + 1) x (Bit 11 + 1) x analog gain Digital Gain (each bit gives 2x gain). Bits 8:7 Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives Analog 2x gain). Gain Bits 6:0 Initial gain = bits (6:0) x 0.03125. Initial Gain R46:0--0x02E - Green2 Gain Bits 11:9 Total gain = (Bit 9 + 1) x (Bit 10 + 1) x (Bit 11 + 1) x analog gain Digital Gain (each bit gives 2x gain). Bits 8:7 Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives Analog 2x gain). Gain Bits 6:0 Initial gain = bits (6:0) x 0.03125. Initial Gain R47:0--0x02F - Global Gain Bits 11:0 This register can be used to set all four gains at once. When Global Gain read, it returns the value stored in Reg0x2B. R200:0--0x0C8 - Context Control Bit 15 Setting this bit causes the sensor to abandon the current frame Restart and start resetting the first row. Same physical register as Reg0x00D, bit 1. 0x08 N N W 0x0 0x0 Y Y N N W W 0x20 Y N W 0x0 0x0 Y Y N N W W 0x20 Y N W 0x0 0x0 Y Y N N W W 0x20 Y N W 0x0 0x0 Y Y N N W W 0x20 Y N W 0x20 Y N W 0x0 N YM W 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 12: Sensor Core Register Descriptions (continued) BIT FIELD Bit 7 Xenon Flash Enable Bit 3 Read Mode Select DESCRIPTION Enable Xenon flash. Same physical register as Reg0x023, bit 13. DEFAULT (HEX) 0x0 SYNC'D TO FRAME START Y BAD READ/ FRAME WRITE N W Bit 2 LED Flash Enable Bit 1 0: Use vertical blanking, context A, Reg0x008. 1: Use vertical blanking, context B, Reg0x006. Vertical Blanking Select Bit 0 0: Use horizontal blanking, context A, Reg0x007. Horizontal 1: Use horizontal blanking, context B, Reg0x005. Blanking Select R240:0--0x0F0 - Page Map Bits 2:0 Page mapping register. Must be kept at 0 to be able to WRITE Page Map to/READ from sensor. Used in the SOC to access other pages with registers. R241:0--0x0F1 - Byte-Wise Address Special address to perform 8-bit (instead of 16-bit) READs and Bit 0 Byte-Wise WRITEs to the sensor. For additional information, see "TwoAddress Wire Serial Interface Sample" on page 54 and "Appendix A" on page 52. R255:0--0x000 - Chip Version (R/O) Bits 15:0 Hardwired READ only. 0: Use READ mode, context A, Reg0x021. 1: Use READ mode, context B, Reg0x020. Note that bits found only in the READ mode context B register is always taken from that register. Enable LED flash. Same physical register as Reg0x023, bit 8. 0x1 Y YM W 0x0 Y Y W 0x1 Y YM W 0x1 Y YM W 0x0 N 0 W N/A 0 0 0 0x1229 R 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR NOTE: Notation used in the above table: Sync'd to frame start 0 = Not applicable, e.g., read-only register. N = The register value is updated and used immediately. Y = The register value is updated at next frame start as long as the synchronize-changes bit is 0. Note also that frame start is defined as when the first dark row is read out. By default, this is eight rows before FRAME_VALID goes HIGH. Bad frame A bad frame is a frame where all rows do not have the same integration time, or offsets to the pixel values changed during the frame. 0 = Not applicable, e.g., read-only register. N = Changing the register value does not produce a bad frame. Y = Changing the register value might produce a bad frame. YM = Yes, but the bad frame is masked out unless the show-bad-frames feature is enabled. Read / Write R = read-only register/bit. W = read / write register/bit. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Modes and Timing This section provides an overview of typical usage modes for the MT9V112. WRITE, a READ from R200:1 or R200:2 results in 0x1F0B being read. Note that the MSB is cleared automatically by the sensor. A READ from R200:0 results in 0x000B, as only the lower 4 bits and the restart MSB are implemented in the sensor core. Contexts The MT9V112 supports hardware-accelerated context switching. A number of parameters have two copies of their setup registers; this allows two "contexts" to be loaded at any given time. These are referred to as context A and context B. Context selection for any single parameter is determined by the global context control register (GCCR, see R200:2). There are copies of this register in each address page. A WRITE to any one of them has the identical effect. However, a READ from address page 0 only returns the subset bits of R200 that are specific to the sensor core. Contexts are generically named because they can be utilized for a variety of purposes. One typical usage model is to define context A as viewfinder or preview mode and context B as snapshot mode. The device defaults are configured with this in mind. This mechanism enables the user to have settings for viewfinder and snapshot modes loaded at the same time, and then switch between them with a single WRITE to a register (e.g., R200:2). Clocks The sensor core is a master in the system. The sensor core frame rate defines the overall image flow pipeline frame rate. Horizontal blanking and vertical blanking are influenced by the sensor configuration, and are also a function of certain image flow pipeline functions--particularly resize. The relationship of the primary clocks are depicted in Figure 9. The image flow pipeline typically generates up to 16-bits per pixel--for example, YCbCr or RGB565--but has only an 8-bit port through which to communicate this pixel data. There is no phase-locked loop (PLL), so the primary input clock (CLKIN) must be twice the fundamental pixel rate (defined by the sensor pixel clock). To generate VGA images at 30 fps, the sensor core requires a clock in the 24 MHz-27 MHz range. The device defaults assume a 24 MHz clock, and minimum clock frequency is 2 MHz. Viewfinder/Preview and FullResolution/Snapshot Modes No context switching is necessary in the sensor core because this is a single ADC device. Context switching occurs in the colorpipe stage. Preview Mode QVGA (320 x 240) images are generated at up to 30 fps. The reduced-size images are generated by a scaling down operation. The sensor always outputs a VGA size image to the colorpipe in both context A and context B. Snapshot Mode VGA (640 x 480) images are generated at up to 30 fps. This is typically selected by setting R200:n[10] = 1 selecting resize/zoom context B. Switching Modes Typically, switching to snapshot mode is achieved by writing R200:2 = 0x9F0B. This restarts the sensor and sets most contexts to context B. Following this Figure 9: Primary Sensor Core Clock Relationships Sensor Master Clock CLKIN Sensor Core 10 bits/pixel 1 pixel/clock Sensor Pixel Clock Colorpipe 16 bits/pixel 1 pixel/clock Output Interface 16 bits/pixel (typical) 0.5 pixel/clock 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Turning Frame Rates Actual frame rates can be tuned by adjusting various sensor parameters. The sensor registers are in address page 0, some of which are shown in Table 13. Table 13: Register Address Functions REGISTER R0x04:0 R0x03:0 R0x07:0, R0x05:0 R0x08:0, R0x06:0 FUNCTION Column width, typically 640 in the MT9V112 Row width, typically 480 in the MT9V112 Horizontal blanking, default is 203 (units of sensor pixel clocks) Vertical blanking, default is 11 (rows including black rows) Default Blanking Calculations The MT9V112 default blanking calculations are shown in Table 14. Table 14: Blanking Parameter Calculations PARAMETER PC_PERIOD Sensor Pixel Clock Period A: Active Data Time (per line): R0 x 04:0 + 8 (border) * PC_PERIOD Q: Horizontal Blanking: [R0 x 05:0 | R0 x 07:0] * PC_PERIOD Row Time = Q + A P: Frame Start / End Blanking: 6 * PC_PERIOD V: Vertical Blanking: [R0 x 06:0 | R0 x 08:0] * (Q + A) + (Q - 2 * P) F: Total Frame Time: (R0 x 03:0 + [R0 x 06:0 | R00 x 08:0]) * (Q + A) CALCULATION (2/24)s = 0.083s 648 x (2/24) = 53.784s 154 x (2/24) = 12.782s 66.566s 6 x (2/24) = 0.5s (11 x 66.566) + (12.782 - 1.0) = 744s (488 + 11) x 66.566s = 33216.434s 30 fps In the MT9V112, the sensor core adds four border pixels all the way around the image, taking the active image size to 648 x 488 in full power mode. This is achieved through the default settings: * oversize and show border bits are set by default * oversize and show border bits are not context switchable, and therefore, their location is only in read mode context B. User Blanking Calculations When calculating blanking for different clock rates, minimum values for horizontal blanking and vertical blanking must be taken into account. Table 15 shows minimum values for each register. Table 15: User Blanking Minimum Values PARAMETER MINIMUM Horizontal Blanking 132 (sensor pixel clocks) Vertical Blanking 6 + Reg0x22:0[2:0] rows 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Output Timing Figure 10: Vertical Timing E FRAME_VALID A LINE_VALID C D B F D[7:0] Line 0 Line 1 LineN-3 LineN-2 LineN-1 Line 0 NO DATA Figure 11: Horizontal Timing PIXCLK LINE_VALID D[7:0] 10 FF 00 00 80 CB0 Y0 CR1 Y1 CB3 Y3 CRn -1 Yn FF 00 00 90 Typical Resolutions, Modes, and Timing The parameters listed in Table 16 are illustrated in a waveform diagram, Figure 10. Table 21 on page 50 provides values for these parameters in some common resolutions and operating modes. Table 16: Blanking Definitions DESIGNATION (A) (B) (C) (D) (E) (F) DEFINITION FRAME_VALID (rising edge) to LINE_VALID (rising edge) delay LINE_VALID (falling edge) to FRAME_VALID (falling edge) delay LINE_VALID (HIGH/valid) time LINE_VALID (LOW/horizontal blanking) time FRAME_VALID (HIGH/valid) time FRAME_VALID (LOW/vertical blanking) time 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Reset, Clocks, and Standby Reset Power-up reset is asserted/de-asserted on RESET#. It is active LOW. In this reset state, all control registers have the default values. Soft reset is asserted/de-asserted by the two-wire serial interface program. In soft-reset mode, the twowire serial interface and register ring bus are still running. All control registers are reset using default values. See R13:0. Clocks The MT9V112 has two primary clocks; a master clock coming from the CLKIN signal, and a pixel clock via a clock-gated operation running at half frequency of the master clock. All device clocks are turned off in power-down mode. When the MT9V112 operates in sensor stand-alone mode, the image flow pipeline clocks can be shut off to conserve power. See R13:0 on page 38. When the MT9V112 is operated with the MT9M111 in a dual-camera application, the MT9V112 employs a divide-by-two clock option, allowing a 54 MHz input to the master clock. For more information about this feature, see the R13:0 register description on page 38 in Table 12. Standby STANDBY is a multifunctional signal that controls power-down, device addressing, and tri-state functions. Table 17 shows how STANDBY affects the output signal state. Hard standby is asserted/de-asserted on STANDBY. It is active HIGH. In this hard standby state, all internal clocks are turned off and the analog block is in standby mode to save power consumption. The signal state is High-Z when R13[4] = 0 and R13[6] = 0. Two-wire interface ID addressing is based on the result of SADDR XOR R13:0[10]. (The R13:0[10] default is "0".) The R13:0[10] bit is not writable when STANDBY is asserted "1." Soft standby is asserted/de-asserted by a two-wire serial interface to R13:0[2]. In soft standby, all internal clocks are turned off, the analog block is in standby mode, but the signal state is not affected. Following the assertion of either hard or soft standby, the analog circuitry completes reading the current row and then enters the standby state. It is necessary to keep clocking the sensor for an entire row time to ensure proper entry into the standby state. . Table 17: STANDBY Effect on the Output State DRIVE SIGNAL R13:0[6] 0 0 1 x OUTPUT DISABLE R13:0[4] 0 0 0 1 STANDBY 0 1 x x OUTPUT STATE Driven High-Z Driven High-Z 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Electrical Specifications Table 18: Electrical Characteristics and Operating Conditions TA = Ambient = 25C PARAMETER I/O Digital Voltage (VDDQ) Core Digital Voltage (VDD) Analog Voltage (VAA) Pixel Supply Voltage (VAAPIX) Leakage Current Operating Temperature NOTE: CONDITION N/A N/A N/A STANDBY, no clocks Measured at junction MIN 1.7 1.7 2.5 2.5 2.5 -30 TYP 1.8 2.8 2.8 2.8 MAX 3.6 1.9 3.1 3.1 3.1 10 +70 UNIT V V V V A C VDD, VAA, and VAAPIX must all be at the same potential to avoid excessive current draw. Care must be taken to avoid excessive noise injection in the analog supplies if all three supplies are tied together. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Table 19: I/O Parameters SIGNAL PARAMETER All Outputs DEFINITIONS Load capacitance Output signal slew CONDITION 2.8V, 30pF load 2.8V, 5pF load 1.8V, 30pF load 1.8V, 5pF load MIN TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2 24 TYP 0.72 1.25 0.34 0.51 MAX TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 27 UNIT pF V/ns V/ns V/ns V/ns V V mA mA mA mA V V V V pF MHz MHz VOH VOL IOH IOL IOZ VIH VIL IIN Signal CAP freq Output high voltage Output low voltage Output high current Output low current Tri-state output leakage current Input high voltage Input low voltage Input leakage current Input signal capacitance Master clock frequency VDDQ = 2.8V, VOH = 2.4V VDDQ = 1.8V, VOH = 1.4V VDDQ = 2.8V, VOL = 0.4V VDDQ = 1.8V, VOL = 0.4V VDDQ = 2.8V VDDQ = 1.8V VDDQ = 2.8V VDDQ = 1.8V All Inputs CLKIN Absolute minimum VGA at 30 fps Power Consumption Table 20: Power Consumption MODE VGA at 15 fps SENSOR/mW 54 IMAGE-FLOW PROC/mW 18 I/OS (10pF)/mW 4 TOTAL M/mW 76 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR I/O Timing By default, the MT9V112 launches pixel data, FRAME_VALID, and LINE_VALID synchronously with the falling edge of PIXCLK. The expectation is that the user captures data, FRAME_VALID, and LINE_VALID using the rising edge of PIXCLK. The timing diagram is shown in Figure 12. As an option, the polarity of the PIXCLK can be inverted from the default. This is achieved by programming R58:1[9] or R155:1[9] to "0." Figure 12: I/O Timing Tclkin_min_high Tclkinf_pixclkr Tclkin_min_low Tclkin_min_period CLKIN Tclkinr_pixclkf Tpixclk_min_high Tpixclk_min_low PIXCLK Tclkinr_dout Tdout_su Tdout_ho DATA[7:0] Tclkinr_fvlv Tfvlv_su Tfvlv_ho FRAME_VALID LINE_VALID UNDEFINED Table 21: I/O Timing SLOW SIGNAL CLKIN PARAMETER Tclkin_min_high Tclkin_min_low Tclkin_min_period Tclkinr_pixclkf Tclkinf_pixclkfr Tpixclk_min_low Tpixclk_min_high Tclkinr_dout Tdout_su Tdout_ho Tclkinr_fvlv Tfvlv_su Tfvlv_ho CONDITIONS MIN TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD MAX TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD MIN TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD FAST MAX TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns PIXCLK 50:50, 27 MHz CLKIN 50:50, 27 MHz CLKIN 50:50, 27 MHz CLKIN 50:50, 27 MHz CLKIN 50:50, 27 MHz CLKIN 50:50, 27 MHz CLKIN DATA[7:0] FRAME_VALID/ LINE_VALID 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Figure 13: Typical Spectral Characteristics (preliminary) Quantum Efficiency 40 35 B G R Quantum Efficiency (%) 30 25 20 15 10 5 0 350 450 550 650 750 850 950 1050 Wavelength (nm) Figure 14: Image Center Offset Pixel column number increasing Pixel row number increasing Pixel (0, 0) Die Image (Optical) Center Coordinates (X, Y) = (-2.46m, 186.19m) Die Center Coordinates (X, Y) = (0, 0) Y increasing X increasing NOTE: Figure not to scale. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 51 PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Appendix A Serial Bus Description Registers are written to and read from the MT9V112 through the two-wire serial interface bus. The sensor is a serial interface slave controlled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred in and out of the MT9V112 through the serial data (SDATA) line. The SDATA line is pulled up to VDDQ off-chip by a 1.5K resistor. Either the slave or the master device can pull the SDATA line down--the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. register address has been received. The master then transfers the data, 8 bits at a time, with the slave sending an acknowledge bit after each eight bits. The MT9V112 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. The master sends the write mode slave address and 8-bit register address, just as in the write request. The master then sends a start bit and the read mode slave address. The master clocks out the register data, eight bits at a time, and sends an acknowledge bit after each 8-bit transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a noacknowledge bit. Protocol The two-wire serial interface defines several different transmission codes, as follows: * a start bit * a(an) (no) acknowledge bit * an 8-bit message * a stop bit * the slave device 8-bit address SADDR and R13:0[10] are used to select between two different addresses in case of conflict with another device. If SADDR XOR R13:0[10] is LOW, the slave address is 0x90; if SADDR XOR R13:0[10] is HIGH, the slave address is 0xBA. See Table 22. Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. Table 22: Two-Wire Interface ID Address Switching SADDR 0 0 1 1 R13:0[10] 0 1 0 1 TWO-WIRE INTERFACE ADDRESS ID 0x90 0xBA 0xBA 0x90 Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH. Stop Bit The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH. Slave Address The 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1 bit of direction. A "0" in the LSB of the address indicates write mode, and a "1" indicates read mode. The write address of the sensor is 0xBA; the read address is 0xBB. This applies only when the SADDR is set HIGH. Sequence A typical read or write sequence begins with the master sending a start bit. After the start bit, the master sends the 8-bit slave device address. The last bit of the address determines if the request is a READ or a WRITE, where a "0" indicates a WRITE and a "1" indicates a READ. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master transfers the 8bit register address for where a write should take place. The slave sends an acknowledge bit to indicate that the Data Bit Transfer One data bit is transferred during each clock pulse. The serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the two-wire serial interface clock--it can only change when the serial clock is LOW. Data is transferred 8 bits at a time, followed by an acknowledge bit. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Acknowledge Bit The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver signals an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse. No-Acknowledge Bit The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Two-Wire Serial Interface Sample Write and read sequences (SADDR = 1). expects the register address to come first, followed by the 16-bit data. After each 8-bit transfer, the image sensor sends an acknowledge bit. All 16 bits must be written before the register is updated. After 16 bits are transferred, the register address is automatically incremented so that the next 16 bits are written to the next register. The master stops writing by sending a start or stop bit. 16-Bit Write Sequence A typical write sequence for writing 16 bits to a register is shown in Figure 15. A start bit sent by the master starts the sequence, followed by the write address. The image sensor sends an acknowledge bit and Figure 15: WRITE Timing to R0x09:0--Value 0x0284 SCLK SDATA 0xBA Address Start ACK Reg 0x09 ACK 0000 0010 ACK 1000 0100 Stop ACK 16-Bit Read Sequence A typical read sequence is shown in Figure 16. The master WRITEs the register address, as in a write sequence. Then a start bit and the read address specify that a read is about to occur from the register. The master then clocks out the register data, 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address should be incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a noacknowledge bit. Figure 16: READ Timing from R0x09:0; Returned Value 0x0284 SCLK SDATA 0xBA Address Start ACK ACK Reg0x09 0xBB Address Start ACK ACK NACK 0000 0010 1000 0100 Stop 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 54 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR 8-Bit Write Sequence To be able to write one byte at a time to the register, a special register address is added. The 8-bit write is started by writing the upper 8 bits to the desired register, then writing the lower 8 bits to the special register address (R0xF1:0). The register is not updated until all 16 bits have been written. It is not possible to update just half of a register. In Figure 17, a typical sequence for an 8-bit WRITE is shown. The second byte is written to the special register (R0xF1:0). Figure 17: WRITE Timing to R0x09:0--Value 0x0284 SCLK SDATA 0xBA Address Start ACK Reg0x09 ACK 0000 0010 ACK 0xBA Address Start ACK Reg0xF1 ACK 1000 0100 Stop ACK 8-Bit READ Sequence To read one byte at a time, the same special register address is used for the lower byte. The upper 8 bits are read from the desired register. By following this with a read from the special register (R0xF1:0), the lower 8 bits are accessed (Figure 18). The master sets the noacknowledge bits. Figure 18: READ Timing from R0x09:0; Returned Value 0x0284 SCLK SDATA 0xBA Address Start ACK ACK Reg0x09 0xBB Address Start ACK NACK 0000 0010 ** SCLK SDATA ** 0xBA Address Start ACK Reg0xF1 ACK 0xBB Address Start ACK 1000 0100 Stop NACK 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Two-wire Serial Bus Timing The two-wire serial interface operation requires a certain minimum of master clock cycles between transitions. These are specified below in master clock cycles. Figure 21: Serial Host Interface Data Timing for Write 4 SCLK 4 Figure 19: Serial Host Interface Start Condition Timing 5 SCLK 4 SDATA SDATA NOTE: SDATA is driven by an off-chip transmitter. Figure 20: Serial Host Interface Stop Condition Timing 5 SCLK 4 Figure 22: Serial Host Interface Data Timing for Read 5 SCLK SDATA SDATA NOTE: NOTE: All timing are in units of master clock cycle. SDATA is pulled LOW by the sensor, or allowed to be pulled HIGH by a pull-up resistor off-chip. Figure 23: Acknowledge Signal Timing After an 8-bit Write to the Sensor 6 SCLK Sensor pulls down SDATA pin 3 SDATA Figure 24: Acknowledge Signal Timing After an 8-bit Read from the Sensor 7 SCLK Sensor tri-states SDATA pin (turns off pull down) 6 SDATA NOTE: After a read, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read sequence is complete, the master must generate a no acknowledge by leaving SDATA to float HIGH. On the following cycle, a start or stop bit may be used. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 56 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Figure 25: 36-Ball ICSP Package 0.95 (FOR REFERENCE ONLY) 1.17 0.10 B SEATING PLANE 0.10 A 0.22 (FOR REFERENCE ONLY) 0.175 (FOR REFERENCE ONLY) 0.575 0.050 3.75 36X O0.35 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. THE PRE-REFLOW DIAMETER IS O0.33 0.375 0.075 BALL A1 BALL A1 ID BALL A1 CORNER 2.900 0.075 4.00 CTR 0.75 TYP BALL A6 PIXEL (0,0) 2.90 0.05 2.714 0.075 3.75 1.875 C L 5.80 0.075 1.728 CTR 4.00 CTR 0.186 (FOR REFERENCE ONLY) OPTICAL CENTER PACKAGE CENTER 0.75 TYP C L 1.875 2.90 0.05 2.304 CTR OPTICAL AREA MAXIMUM ROTATION OF OPTICAL AREA RELATIVE TO PACKAGE EDGES: 1 MAXIMUM TILT OF OPTICAL AREA RELATIVE TO B 0.3. SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn, 3% Ag, 0.5% Cu BALL PADS O 0.27 SOLDER MASK DEFINED SUBSTRATE MATERIAL: PLASTIC LAMINATE ENCAPSULANT: EPOXY MAXIMUM TILT OF OPTICAL AREA RELATIVE TO TOP OF COVER GLASS: 0.3. LID MATERIAL: BOROSILICATE GLASS 0.40 THICKNESS IMAGE SENSOR DIE 5.80 0.075 NOTE: All dimensions in millimeters. Data Sheet Designation Preliminary This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm - Rev. A 1/05 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 57 PRELIMINARY MT9V112 SOC VGA DIGITAL IMAGE SENSOR Revision History * Original Document, Rev A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11/04 09005aef8154a39d/09005aef8175e6cc MT9V112_2.fm- Rev. A 1/05 EN 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. |
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