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PCA9554/PCA9554A 8-bit I2C and SMBus I/O port with interrupt
Product data Supersedes data of 2002 May 13 2002 Jul 26
Philips Semiconductors
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt
PCA9554/PCA9554A
DESCRIPTION
The PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C/SMBus applications and were developed to enhance the Philips family of I@C I/O expanders. The improvements include higher drive capability, 5V I/O tolerance, lower supply current, individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, pushbuttons, LEDs, fans, etc..
FEATURES
* Operating power supply voltage range of 2.3 to 5.5 V * 5 V tolerant I/Os * Polarity inversion register * Active low interrupt output * Low stand-by current * Noise filter on SCL/SDA inputs * No glitch on power-up * Internal power-on reset * 8 I/O pins which default to 8 inputs * 0 to 400 kHz clock frequency * ESD protection exceeds 2000 V HBM per JESD22-A114, * Latch-up testing is done to JESDEC Standard JESD78 which * Four packages offered: SO16, SSOP16, TSSOP16, and
HVQFN16 exceeds 100 mA 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
The PCA9554/54A consist of an 8-bit Configuration register (Input or Output selection); 8-bit Input register, 8-bit Output register and an 8-bit Polarity inversion register (Active high or Active low operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion Register. All registers can be read by the system master. Although pin to pin and I2C address compatible with the PCF8574 series, software changes are required due to the enhancements and are discussed in Application Note AN469. The PCA9554/54A open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. Three hardware pins (A0, A1, A2) vary the fixed I2C address and allow up to eight devices to share the same I2C/SMBus. The PCA9554A is identical to the PCA9554 except that the fixed I2C address is different allowing up to sixteen of these devices (eight of each) on the same I2C/SMBus.
ORDERING INFORMATION
PACKAGES 16-Pin Plastic SO (wide) 16-Pin Plastic SSOP 16-Pin Plastic TSSOP 16-Pin Plastic HVQFN 16-Pin Plastic SO (wide) 16-Pin Plastic SSOP 16-Pin Plastic TSSOP TEMPERATURE RANGE -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C ORDER CODE PCA9554D PCA9554DB PCA9554PW PCA9554BS PCA9554AD PCA9554ADB PCA9554APW TOPSIDE MARK PCA9554D 9554DB 9554DH 9554 PCA9554AD 9554A 9554ADH DRAWING NUMBER SOT162-1 SOT338-1 SOT403-1 SOT629-1 SOT162-1 SOT338-1 SOT403-1 SOT629-1
16-Pin Plastic HVQFN -40 to +85 C PCA9554ABS 554A Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging. I2C is a trademark of Philips Semiconductors Corporation. SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent.
2002 Jul 26
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853-2243 28672
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt
PCA9554/PCA9554A
PIN CONFIGURATION -- SO, SSOP, TSSOP
A0 1 A1 2 16 VDD 15 SDA 14 SCL 13 INT 12 I/O7 11 I/O6 10 I/O5 9 I/O4
PIN CONFIGURATION -- HVQFN
A1 16 A0 15 VDD 14 SDA 13 12 SCL 11 INT 10 I/O7 9 5 6 7 8 I/O6 I/O5
A2 I/O0 I/O1 I/O2
1 2 3 4
A2 3 I/O0 4 I/O1 5 I/O2 6 I/O3 7 VSS 8
I/O3
VSS I/O4
su01410
Figure 1. Pin configuration -- SO, SSOP, TSSOP
TOP VIEW
su01670
Figure 2. Pin Configuration -- HVQFN
PIN DESCRIPTION
SO. SSOP, TSSOP PIN NUMBER 1 2 3 4-7 8 9 13 14 15 16 HVQFN PIN NUMBER 15 16 1 2-5 6 7-10 11 12 13 14 SYMBOL A0 A1 A2 I/O0-3 VSS I/O4-7 INT SCL SDA VDD FUNCTION Address input 0 Address input 1 Address input 2 I/O0 to I/O3 Supply ground I/O4 to I/O7 Interrupt output (open drain) Serial clock line Serial data line Supply voltage
BLOCK DIAGRAM
A0 A1 A2 SCL SDA INPUT FILTER I2C/SMBUS CONTROL 8-BIT INPUT/ OUTPUT PORTS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 VDD POWER-ON RESET VSS LP FILTER NOTE: ALL I/Os ARE SET TO INPUTS AT RESET INT VCC
WRITE pulse READ pulse
SU01411
Figure 3. Block diagram
2002 Jul 26
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt
PCA9554/PCA9554A
REGISTERS Command Byte
Command 0 1 2 3 Protocol Read byte Read/write byte Read/write byte Read/write byte Function Input port register Output port register Polarity inversion register Configuration register
Register 2 - Polarity Inversion Register
bit
default
N7 0
N6 0
N5 0
N4 0
N3 0
N2 0
N1 0
N0 0
This register allows the user to invert the polarity of the Input Port Register data. If a bit in this register is set (written with `1'), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a `0'), the Input Port data polarity is retained.
The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read.
Register 3 - Configuration Register
bit
default
C7 1
C6 1
C5 1
C4 1
C3 1
C2 1
C1 1
C0 1
Register 0 - Input Port Register
bit
default
I7 1
I6 1
I5 1
I4 1
I3 1
I2 1
I1 1
I0 1
This register is a read only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect.
This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs with a weak pull-up to VDD.
Power-on Reset
When power is applied to VDD, an internal power-on reset holds the PCA9554 in a reset state until VDD has reached VPOR. At that point, the reset condition is released and the PCA9554 registers and state machine will initialize to their default states.
Register 1 - Output Port Register
bit
default
O7 1
O6 1
O5 1
O4 1
O3 1
O2 1
O1 1
O0 1
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, NOT the actual pin value.
Interrupt Output
The open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the input port register is read. Note that changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input port register.
2002 Jul 26
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt
PCA9554/PCA9554A
SIMPLIFIED SCHEMATIC OF I/O0 TO I/O7
DATA FROM SHIFT REGISTER CONFIGURATION REGISTER DATA FROM SHIFT REGISTER D FF WRITE CONFIGURATION PULSE WRITE PULSE CK Q D FF I/O0 TO I/O7 CK Q Q2 Q Q Q1 100 k OUTPUT PORT REGISTER DATA VDD
OUTPUT PORT REGISTER INPUT PORT REGISTER D FF READ PULSE CK Q Q
VSS
INPUT PORT REGISTER DATA
TO INT
DATA FROM SHIFT REGISTER WRITE POLARITY PULSE
D FF CK
Q
POLARITY REGISTER DATA
Q
POLARITY INVERSION REGISTER
SU01472
NOTE: At Power-on Reset, all registers return to default values. Figure 4. Simplified schematic of I/O0 to I/O7
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high impedance input with a weak pull-up (100 k typ.) to VDD. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the output port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low impedance paths that exist between the pin and either VDD or VSS.
2002 Jul 26
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt
PCA9554/PCA9554A
Device address
SLAVE ADDRESS slave address
0
1
0
0
A2
A1
A0 R/W
0
1
1
1
A2
A1
A0 R/W
FIXED
HARDWARE SELECTABLE
fixed
programmable
su01669
su01418
Figure 5. PCA9554 address
Figure 6. PCA9554A address
Bus transactions
Data is transmitted to the PCA9554/PCA9554A registers using the write mode as shown in Figures 7 and 8. Data is read from the PCA9554/PCA9554A registers using the read mode as shown in Figures 9 and 10. These devices do not implement an auto-increment function so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent.
SCL
1
2
3
4
5
6
7
8
9 command byte
slave address
data to port
SDA
S
0
1
0
0
A2
A1
A0
0 R/W
A
0
0
0
0
0
0
0
1
A acknowledge from slave
DATA 1
A
P
start condition
acknowledge from slave
acknowledge from slave
WRITE TO PORT
DATA OUT FROM PORT tpv
DATA 1 VALID
su01421
Figure 7. WRITE to output port register
SCL
1
2
3
4
5
6
7
8
9
slave address
command byte
data to register
SDA
S
0
1
0
0
A2
A1
A0
0 R/W
A
0
0
0
0
0
0
1
1/0
A acknowledge from slave
DATA
A
P
start condition
acknowledge from slave
acknowledge from slave
DATA TO REGISTER
su01422
Figure 8. WRITE to configuration or polarity inversion registers
2002 Jul 26
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt
PCA9554/PCA9554A
slave address
acknowledge from slave
acknowledge from slave
slave address
acknowledge from slave
data from register
acknowledge from master
S
0
1
0
0
A2 A1 A0
0 R/W
A
COMMAND BYTE
A
S
0
1
0
0
A2 A1 A0
1 R/W
A
DATA first byte
A
at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter data from register no acknowledge from master
DATA last byte
NA
P
su01424
Figure 9. READ from register
SCL
1
2
3
4
5
6
7
8
9 data from port data from port
slave address
SDA
S
0
1
0
0
A2
A1
A0
1 R/W
A acknowledge from slave
DATA 1
A acknowledge from master
DATA 4
NA
P stop condition
start condition
no acknowledge from master
READ FROM PORT
DATA INTO PORT tph
DATA 2
DATA 3 tps
DATA 4
INT
tiv
tir
su01465
NOTES: 1. This figure assumes the command byte has previously been programmed with 00h. 2. Transfer of data can be stopped at any moment by a stop condition. Figure 10. READ input port register
2002 Jul 26
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt
PCA9554/PCA9554A
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDD II VI/O II/O IDD ISS Ptot Tstg Tamb Supply voltage DC input current DC voltage on an I/O DC output current on an I/O Supply current Supply current Total power dissipation Storage temperature range Operating ambient temperature PARAMETER CONDITIONS MIN -0.5 -- VSS - 0.5 -- -- -- -- -65 -40 MAX 6.0 20 5.5 50 85 100 200 +150 +85 UNIT V mA V mA mA mA mW C C
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt
PCA9554/PCA9554A
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under "Handling MOS devices".
DC CHARACTERISTICS
SYMBOL Supplies VDD IDD Istbl Istbh VPOR VIL VIH IOL IL CI I/Os VIL VIH Supply voltage Supply current Standby current Standby current
VDD = 2.3 to 5.5 V; VSS = 0 V; Tamb = -40 to +85 C; unless otherwise specified. PARAMETER CONDITIONS MIN 2.3 Operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs No load; VI = VDD or VSS -- -- -- -- -0.5 0.7 VDD VOL = 0.4V VI = VDD = VSS VI = VSS 3 -1 -- -0.5 2.0 VOL = 0.5 V; VDD = 2.3 V; Note 1 VOL = 0.7 V; VDD = 2.3 V; Note 1 IO OL LOW level output current VOL = 0.5 V; VDD = 4.5 V; Note 1 VOL = 0.7 V; VDD = 4.5 V; Note 1 VOL = 0.5 V; VDD = 3.0 V; Note 1 VOL = 0.7 V; VDD = 3.0 V; Note 1 IOH = -8 mA; VDD = 2.3 V; Note 2 IOH = -10 mA; VDD = 2.3 V; Note 2 VO OH HIGH level output voltage IOH = -8 mA; VDD = 3.0 V; Note 2 IOH = -10 mA; VDD = 3.0 V; Note 2 IOH = -8 mA; VDD = 4.75 V; Note 2 IOH = -10 mA; VDD = 4.75 V; Note 2 IIH IIL CI CO IOL VIL VIH ILI Input leakage current Input leakage current Input capacitance Output capacitance LOW level output current LOW level input voltage HIGH level input voltage Input leakage current VOL = 0.4 V VDD = 3.6 V; VI = VDD VDD = 5.5 V; VI = VSS 8 10 8 10 8 10 1.8 1.7 2.6 2.5 4.1 4.0 -- -- -- -- 3 -0.5 2.0 -1 TYP -- 104 550 0.25 1.5 -- -- -- -- 6 -- -- 10 13 17 24 14 19 -- -- -- -- -- -- -- -- 3.7 3.7 -- -- -- -- MAX 5.5 175 700 1 1.65 0.3 VDD 5.5 -- +1 10 0.8 5.5 -- -- -- -- -- -- -- -- -- -- -- -- 1 -100 5 5 -- 0.8 5.5 1 UNIT V A A A V V V mA A pF V V mA mA mA mA mA mA V V V V V V A A pF pF mA V V A
Power-on reset voltage LOW level input voltage HIGH level input voltage LOW level output current Leakage current Input capacitance LOW level input voltage HIGH level input voltage
input SCL; input/output SDA
Interrupt INT Select Inputs A0, A1, A2
NOTES: 1. The total current sunk by all I/Os must be limited to 100 mA. 2. The total current sourced by all I/Os must be limited to 85 mA.
2002 Jul 26
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Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt
PCA9554/PCA9554A
SDA
tF
tLOW
tR
tSU;DAT
tF
tHD;STA
tSP
tR
tBUF
SCL
S
tHD;STA
tHD;DAT tHIGH
tSU;STA
SR
tSU;STD
P
S
SU01469
Figure 11. Definition of timing
AC SPECIFICATIONS
SYMBOL fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tF tR tSP Port Timing tPV tPS tPH tIV tIR Output data valid Input data setup time Input data hold time Interrupt valid Interrupt reset -- 100 1 -- -- 200 -- -- 4 4 -- 100 1 -- -- 200 -- -- 4 4 ns ns s s s PARAMETER Operating frequency Bus free time between STOP and START conditions Hold time after (repeated) START condition Repeated START condition setup time Setup time for STOP condition Data in hold time Valid time for ACK condition2 Data out valid time3 Data setup time Clock LOW period Clock HIGH period Clock/Data fall time Clock/Data rise time Pulse width of spikes that must be suppressed by the input filters STANDARD MODE I2C BUS MIN 0 4.7 4.0 4.7 4.0 0 0.3 300 250 4.7 4.0 -- -- -- MAX 100 -- -- -- -- -- 3.45 -- -- -- -- 300 1000 50 FAST MODE I2C BUS MIN 0 1.3 0.6 0.6 0.6 0 0.1 50 100 1.3 0.6 20 + 0.1 Cb --
1
UNITS 400 -- -- -- -- -- 0.9 -- -- -- -- 300 300 50 kHz s s s s ns s ns ns s s ns ns ns
MAX
20 + 0.1 Cb1
Interrupt Timing
NOTES: 1. Cb = total capacitance of one bus line in pF. 2. tVD;ACK = time for Acknowledgement signal from SCL low to SDA (out) low. 3. tVD;DAT = minimum time for SDA data out to be valid following SCL low.
2002 Jul 26
10
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt
PCA9554/PCA9554A
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
2002 Jul 26
11
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt
PCA9554/PCA9554A
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
2002 Jul 26
12
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt
PCA9554/PCA9554A
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
2002 Jul 26
13
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt
PCA9554/PCA9554A
HVQFN16: plastic heatsink very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm
SOT629-1
2002 Jul 26
14
Philips Semiconductors
Product data
8-bit I2C and SMBus I/O port with interrupt
PCA9554/PCA9554A
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 07-02
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 10163
Philips Semiconductors
2002 Jul 26 15

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