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1CY M18 21
fax id: 2010
CYM1821
16K x 32 Static RAM Module
Features
* High-density 512-Kbit SRAM module * 32-bit standard footprint supports densities from 16K x 32 through 1M x 32 * High-speed CMOS SRAMs -- Access time of 12 ns * Low active power -- 4W (max.) * SMD technology * TTL-compatible inputs and outputs * Low profile -- Max. height of .50 in. * Small PCB footprint -- 1.0 sq. in. * JEDEC-compatible pinout constructed from eight 16K x 4 SRAM SOJ packages mounted on an epoxy laminate board with pins. Four chip selects (CS1, CS2, CS3, and CS4) are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. Writing to each byte is accomplished when the appropriate chip selects (CSN) and write enable (WE) inputs are both LOW. Data on the input/output pins (I/OX) is written into the memory location specified on the address pins (A0 through A13). Reading the device is accomplished by taking the chip selects (CSN) LOW, while write enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the data input/output pins (I/OX).The data input/output pins stay in the high-impedance state when write enable (WE) is LOW, or the appropriate chip selects are HIGH. Two pins (PD0 and PD1) are used to identify module memory density in applications where alternate versions of the JEDEC standard modules can be interchanged.
Functional Description
The CYM1821 is a high-performance 512-Kbit static RAM module organized as 16K words by 32 bits. This module is
Logic Block Diagram
PD0 - GND PD1 - OPEN
14
Pin Configuration
PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE NC CS1 CS3 NC GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND
ZIP Top View
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63
A0 - A13 OE WE
16K x 4 SRAM CS1 16K x 4 SRAM CS2 16K x 4 SRAM CS3 16K x 4 SRAM CS4
4
I/O0 - I/O3
16K x 4 SRAM
4
I/O4 - I/O7
4
I/O8 - I/O11
16K x 4 SRAM
4
I/O12 - I/O15
GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND NC CS2 CS4 NC OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31
1821-2
4
I/O16 - I/O19
16K x 4 SRAM
4
I/O20 - I/O23
4
I/O24 - I/O27
16K x 4 SRAM
4
I/O28 - I/O31
1821-1
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose * CA 95134 * 408-943-2600 November 1988 - Revised January 1995
CYM1821
Selection Guide
1821-12 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 12 960 450 1821-15 15 960 450 1821-20 20 720 160 1821-25 25 720 160 1821-35 35 720 160 1821-45 45 720 160
Maximum Ratings
(Above which the useful life may be impaired.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................... -10C to +85C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V
DC Input Voltage ............................................-0.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 5V 10%
Electrical Characteristics Over the Operating Range
1821-12 1821-15 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[1] VCC Operating Supply Current Automatic CS Power-Down Current[2] Automatic CS Power-Down Current[2] GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, CS < VIL Max. VCC, CS > VIH, Min. Duty Cycle = 100% Max. VCC, CSN > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.5 -20 -20 Min. 2.4 0.4 VCC 0.8 +20 +20 -350 960 450 160 2.2 -0.5 -20 -20 Max. 1821-20 1821-25 1821-35 1821-45 Min. 2.4 0.4 VCC 0.8 +20 +20 -350 720 160 160 Max. Unit V V V V A A mA mA mA mA
Capacitance[3]
Parameter CINA CINB COUT Description Input Capacitance (ADDR, OE, WE) Input Capacitance (CS) Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 70 35 20 Unit pF pF pF
Notes: 1. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 2. A pull-up resistor to V CC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 3. Tested on a sample basis.
2
CYM1821
AC Test Loads and Waveforms
481 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: OUTPUT 255 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE 255 GND < 5 ns
1821-3
481 3.0V
ALL INPUT PULSES 90% 10% 90% 10% < 5 ns
1821-4
(a)
(b)
THE VENIN EQUIVALENT 167 1.73V
]
Switching Characteristics Over the Operating Range[4]
1821-12 Parameter READ CYCLE tRC tAA tOHA tACS tDOE tLZOE tHZOE tLZCS tHZCS tPU tPD WRITE tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CS LOW to Low Z[5] 3 8 0 12 12 10 10 2 0 10 10 2 3 0 7 15 12 12 2 0 12 10 2 3 0 7 0 15 20 15 15 2 2 15 10 2 3 0 7 CS HIGH to High Z[5, 6] CS LOW to Power-Up CS HIGH to Power-Down CYCLE[7] Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z[6] ns ns ns ns ns ns ns ns ns ns 2 8 3 8 0 20 2 12 10 2 8 5 8 12 12 2 15 10 3 8 15 15 2 20 10 20 20 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 1821-15 Min. Max. 1821-20 Min. Max. Unit
Notes: 4. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/I OH and 30-pF load capacitance. 5. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed by design and not 100% tested. 6. tHZCS and t HZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3
CYM1821
Switching Characteristics Over the Operating Range (continued)[4]
1821-25 Parameter READ CYCLE tRC tAA tOHA tACS tDOE tLZOE tHZOE tLZCS tHZCS tPU tPD WRITE tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CS LOW to Low Z[5] CS HIGH to High Z[5, 6] 0 25 25 20 20 2 2 20 13 2 3 0 7 35 25 25 2 2 25 15 2 5 0 10 CS LOW to Power-Up CS HIGH to Power-Down CYCLE[7] Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z[6] 45 35 35 2 2 30 20 2 5 0 15 ns ns ns ns ns ns ns ns ns ns 5 10 0 35 3 15 10 15 0 45 3 25 15 3 20 10 20 25 25 3 35 25 3 20 35 35 3 45 30 45 45 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 1821-35 Min. Max. 1821-45 Min. Max. Unit
4
CYM1821
Switching Waveforms
Read Cycle No. 1
[8,9]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1821-5
Read Cycle No. 2 (WE Controlled) [8,10]
CS tACS OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZCS tPU VCC SUPPLY CURRENT 50% DATA VALID tPD ICC 50% ISB
1821-6
tRC
tHZOE tHZCS HIGH IMPEDANCE
Write Cycle No. 1 (WE Controlled) [7]
tWC ADDRESS tSCS CS tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED
1821-7
tAW tPWE
tHA
tHD
tLZWE HIGH IMPEDANCE
Notes: 8. WE is HIGH for read cycle. 9. Device is continuously selected, CS = VIL and OE= VIL. 10. Address valid prior to or coincident with CS transition LOW.
5
CYM1821
Switching Waveforms (continued)
[7,11]
Write Cycle No. 2 (CS Controlled)
tWC ADDRESS tSA CS tAW tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT HIGH IMPEDANCE DATA UNDEFINED
1821-8
tSCS
tHA
tHD
Note: 11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Truth Table
CSN H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Read Write Deselect Mode Deselect/Power-Down
Ordering Information
Speed 12 15 20 25 35 45 Ordering Code CYM1821PM-12C CYM1821PZ-12C CYM1821PM-15C CYM1821PZ-15C CYM1821PM-20C CYM1821PZ-20C CYM1821PM-25C CYM1821PZ-25C CYM1821PM-35C CYM1821PZ-35C CYM1821PM-45C CYM1821PZ-45C Document #: 38-M-00015-E Package Name PM01 PZ01 PM01 PZ01 PM01 PZ01 PM01 PZ01 PM01 PZ01 PM01 PZ01 Package Type 64-Pin Plastic SIMM Module 64-Pin Plastic ZIP Module 64-Pin Plastic SIMM Module 64-Pin Plastic ZIP Module 64-Pin Plastic SIMM Module 64-Pin Plastic ZIP Module 64-Pin Plastic SIMM Module 64-Pin Plastic ZIP Module 64-Pin Plastic SIMM Module 64-Pin Plastic ZIP Module 64-Pin Plastic SIMM Module 64-Pin Plastic ZIP Module Commercial Commercial Commercial Commercial Commercial Operating Range Commercial
6
CYM1821
a
Package Diagrams
64-Pin Plastic SIMM Module PM01
0.125 DIA. + .001 2 PLCS 3.845 3.855 3.580 3.588
0.330 MAX
0.400
0.525 MAX
0.250 0.080 0.250
PIN 1
0.050 TYP
0.62 R + .001 0.250 3.35 (64 PINS)
0.145 REF PIN 64
64-Pin Plastic ZIP Module PZ01
Bottom View
0.050
3.640 3.660
0.330 MAX
0.050 0.120 0.150
0.500 MAX
0.008 0.014 0.135 0.165 Pin 1 0.015 0.025 0.250 TYP 0.100 TYP 0.050 TYP 0.100 TYP DIMENSIONS IN INCHES MIN. MAX.
(c) Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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