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| Rev 1; 4/05 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection General Description The DS1856 dual, temperature-controlled, nonvolatile (NV) variable resistors with three monitors consists of two 256-position, linear, variable resistors; three analog monitor inputs (MON1, MON2, MON3); and a direct-todigital temperature sensor. The device provides an ideal method for setting and temperature-compensating bias voltages and currents in control applications using minimal circuitry. The variable resistor settings are stored in EEPROM memory and can be accessed over the 2-wire serial bus. Relative to other members of the family, the DS1856 is essentially a DS1859 with a DS1852-friendly memory map. In particular, the DS1856 can be configured so the 128 bytes of internal Auxiliary EEPROM memory is mapped into Main Device Table 00h and Table 01h, maintaining compatibility between both the DS1858/DS1859 and the DS1852. The DS1856 also features password protection equivalent to the DS1852, further enhancing compatibility between the two. Features SFF-8472 Compatible Five Monitored Channels (Temperature, VCC, MON1, MON2, MON3) Three External Analog Inputs (MON1, MON2, MON3) That Support Internal and External Calibration Scalable Dynamic Range for External Analog Inputs Internal Direct-to-Digital Temperature Sensor Alarm and Warning Flags for All Monitored Channels Two Linear, 256-Position, Nonvolatile TemperatureControlled Variable Resistors Resistor Settings Changeable Every 2C Three Levels of Security Access to Monitoring and ID Information Configurable with Separate Device Addresses 2-Wire Serial Interface Two Buffers with TTL/CMOS-Compatible Inputs and Open-Drain Outputs Operates from a 3.3V or 5V Supply -40C to +95C Operating Temperature Range DS1856 Applications Optical Transceivers Optical Transponders Instrumentation and Industrial Controls RF Power Amps Diagnostic Monitoring Ordering Information PART DS1856E-050 DS1856E-050/T&R DS1856B-050 RES0/RES1 RESISTANCE (k) 50/50 50/50 50/50 PIN-PACKAGE 16 TSSOP 16 TSSOP 16-Ball CSBGA Typical Operating Circuit VCC VCC = 3.3V 4.7k 2-WIRE INTERFACE Tx-FAULT 4.7k 1 2 3 4 5 LOS 6 IN2 7 8 N.C. GND MON3 MON2 MON1 SDA SCL OUT1 IN1 OUT2 VCC H1 L1 H0 16 15 14 13 12 DECOUPLING CAPACITOR Ordering Information continued at end of data sheet. +Denotes lead free. *Future product--contact factory for availability. T&R denotes tape-and-reel. All parts operate at the -40C to +95C temperature range. 0.1F Pin Configurations TOP VIEW A SDA 1 IN1 SCL VCC H1 SCL 2 OUT1 3 L1 IN1 4 16 VCC 15 H1 14 L1 TO LASER BIAS CONTROL TO LASER MODULATION CONTROL DS1856 L0 B OUT2 SDA H0 11 Rx POWER* 10 Tx POWER* 9 Tx BIAS* DIAGNOSTIC INPUTS C N.C. IN2 OUT1 MON3 DS1856 13 H0 12 L0 11 MON3 10 MON2 9 MON1 OUT2 5 IN2 6 D GND 1 L0 2 MON1 3 MON2 4 N.C. 7 GND 8 *SATISFIES SFF-8472 COMPATIBILITY CSBGA (4mm x 4mm) 1.0mm PITCH TSSOP ______________________________________________ Maxim Integrated Products 1 For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC Relative to Ground ...........-0.5V to +6.0V Voltage Range on Inputs Relative to Ground* ..............................................-0.5V to (VCC + 0.5V) Voltage Range on Resistor Inputs Relative to Ground* ..............................................-0.5V to (VCC + 0.5V) Current into Resistors............................................................5mA *Not to exceed 6.0V. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Temperature Range ...........................-40C to +95C Programming Temperature Range .........................0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature .......................................See IPC/JEDEC J-STD-020A RECOMMENDED OPERATING CONDITIONS (TA = -40C to +95C, unless otherwise noted.) PARAMETER Supply Voltage Input Logic 1 (SDA, SCL) Input Logic 0 (SDA, SCL) Resistor Inputs (L0, L1, H0, H1) Resistor Current High-Impedance Resistor Current Input Logic Levels (IN1, IN2) IRES IROFF Input logic 1 Input logic 0 1.6 0.9 SYMBOL VCC VIH VIL (Note 1) (Note 2) (Note 2) CONDITIONS MIN 2.85 0.7 x Vcc -0.3 -0.3 -3 0.001 TYP MAX 5.50 VCC + 0.3 +0.3 x VCC VCC + 0.3 +3 0.1 UNITS V V V V mA A V DC ELECTRICAL CHARACTERISTICS (VCC = 2.85V to 5.5V, TA = -40C to +95C, unless otherwise noted.) PARAMETER Supply Current Input Leakage Low-Level Output Voltage (SDA, OUT1, OUT2) Full-Scale Input (MON1, MON2, MON3) Full-Scale VCC Monitor I/O Capacitance Digital Power-On Reset Analog Power-On Reset CI/O POD POA 1.0 2.0 SYMBOL ICC IIL VOL1 VOL2 3mA sink current 6mA sink current At factory setting (Note 4) At factory setting (Note 5) CONDITIONS (Note 3) -200 0 0 2.4875 6.5208 2.5 6.5536 MIN TYP 1 MAX 2 +200 0.4 0.6 2.5125 6.5864 10 2.2 2.6 UNITS mA nA V V V pF V V 2 _____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection ANALOG RESISTOR CHARACTERISTICS (VCC = 2.85V to 5.5V, TA = -40C to +95C, unless otherwise noted.) PARAMETER Position 00h Resistance (50k) Position FFh Resistance (50k) Position 00h Resistance (30k) Position FFh Resistance (30k) Position 00h Resistance (20k) Position FFh Resistance (20k) Position 00h Resistance (10k) Position FFh Resistance (10k) Position 00h Resistance (2.5k) Position FFh Resistance (2.5k) Absolute Linearity Relative Linearity Temperature Coefficient TA = +25C TA = +25C TA = +25C TA = +25C TA = +25C TA = +25C TA = +25C TA = +25C TA = +25C TA = +25C (Note 6) (Note 7) (Note 8) 0.1 2.0 -2 -1 50 0.20 15 CONDITIONS MIN 0.65 40 TYP 1.0 50 0.40 30 0.40 20 0.40 10 0.175 2.50 0.250 3.0 +2 +1 0.55 25 MAX 1.35 60 UNITS k k k k k k k k k k LSB LSB ppm/C DS1856 ANALOG VOLTAGE MONITORING (VCC = 2.85V to 5.5V, TA = -40C to +95C, unless otherwise noted.) PARAMETER Input Resolution Supply Resolution Input/Supply Accuracy (MON1, MON2, MON3, VCC) Update Rate for MON1, MON2, MON3, Temp, or VCC Input/Supply Offset (MON1, MON2, MON3, VCC) SYMBOL VMON VCC ACC tframe VOS (Note 14) At factory setting CONDITIONS MIN TYP 610 1.6 0.25 47 0 0.5 60 5 MAX UNITS V mV % FS (full scale) ms LSB DIGITAL THERMOMETER (VCC = 2.85V to 5.5V, TA = -40C to +95C, unless otherwise noted.) PARAMETER Thermometer Error SYMBOL TERR CONDITIONS -40C to +95C MIN TYP MAX 3.0 UNITS C NONVOLATILE MEMORY CHARACTERISTICS (VCC = 2.85V to 5.5V) PARAMETER EEPROM Writes SYMBOL CONDITIONS +70C (Note 14) MIN 50,000 TYP MAX UNITS Writes _____________________________________________________________________ 3 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 AC ELECTRICAL CHARACTERISTICS (VCC = 2.85V to 5.5V, TA = -40C to +95C, unless otherwise noted. See Figure 6.) PARAMETER SCL Clock Frequency (Note 9) Bus Free Time Between STOP and START Condition (Note 9) Hold Time (Repeated) START Condition (Notes 9, 10) LOW Period of SCL Clock (Note 9) HIGH Period of SCL Clock (Note 9) Data Hold Time (Notes 9, 11, 12) Data Setup Time (Note 9) START Setup Time (Note 9) Rise Time of Both SDA and SCL Signals (Note 13) Fall Time of Both SDA and SCL Signals (Note 13) Setup Time for STOP Condition Capacitive Load for Each Bus Line EEPROM Write Time SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB tW Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode (Note 13) 10 CONDITIONS MIN 0 0 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0 0 100 250 0.6 4.7 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 0.6 4.0 400 20 300 1000 300 300 0.9 TYP MAX 400 100 UNITS kHz s s s s s ns s ns ns s pF ms Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: All voltages are referenced to ground. I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VCC is switched off. SDA and SCL are connected to VCC and all other input signals are connected to well-defined logic levels. Full scale is user programmable. The maximum voltage that the MON inputs read is approximately full scale, even if the voltage on the inputs is greater than full scale. This voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum V CC voltage. Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a straight line from measured minimum position to measured maximum position. Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change is the slope of the straight line from measured minimum position to measured maximum position. See the Typical Operating Characteristics. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released. 4 _____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection Note 10: After this period, the first clock pulse is generated. Note 11: The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 12: A device must internally provide a hold time of at least 300ns for the SDA signal (see the VIH MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 13: CB--total capacitance of one bus line, timing referenced to 0.9 x VCC and 0.1 x VCC. Note 14: Guaranteed by design. DS1856 Typical Operating Characteristics (VCC = 5.0V, TA = +25C, for both 50k and 20k versions, unless otherwise noted.) SUPPLY CURRENT vs. TEMPERATURE DS1856 toc01 SUPPLY CURRENT vs. VOLTAGE DS1856 toc02 RESISTANCE vs. SETTING 50k VERSION 50 RESISTANCE (k) 40 30 20 10 0 DS1856 toc03 800 SDA = SCL = VCC SUPPLY CURRENT (A) 750 800 750 SUPPLY CURRENT (A) 700 650 600 550 500 450 SDA = SCL = VCC 60 700 650 600 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) 400 3.0 3.5 4.0 4.5 5.0 5.5 VOLTAGE (V) 0 50 100 150 200 250 SETTING (DEC) RESISTANCE vs. SETTING DS1856 toc04 ACTIVE SUPPLY CURRENT vs. SCL FREQUENCY DS1856 toc05 RESISTOR 0 INL (LSB) 0.8 0.6 RESISTOR 0 INL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 DS1856 toc06 20 20k VERSION 15 RESISTANCE (k) 800 SDA = VCC ACTIVE SUPPLY CURRENT (A) 780 1.0 760 10 740 5 720 0 0 50 100 150 200 250 SETTING (DEC) 700 0 100 200 300 400 SCL FREQUENCY (kHz) -1.0 0 25 50 75 100 125 150 175 200 225 250 SETTING (DEC) _____________________________________________________________________ 5 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Typical Operating Characteristics (continued) (VCC = 5.0V, TA = +25C, for both 50k and 20k versions, unless otherwise noted.) RESISTOR 0 DNL (LSB) DS1856 toc07 RESISTOR 1 INL (LSB) DS1856 toc08 RESISTOR 1 DNL (LSB) 0.8 0.6 RESISTOR 1 DNL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 DS1856 toc09 1.0 0.8 0.6 RESISTOR 0 DNL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1.0 0.8 0.6 RESISTOR 1 INL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 1.0 25 50 75 100 125 150 175 200 225 250 SETTING (DEC) 0 25 50 75 100 125 150 175 200 225 250 SETTING (DEC) 0 25 50 75 100 125 150 175 200 225 250 SETTING (DEC) RESISTANCE vs. POWER-UP VOLTAGE DS1856 toc10 RESISTANCE vs. POWER-UP VOLTAGE DS1856 toc11 POSITION 00h RESISTANCE vs. TEMPERATURE 50k VERSION 1.00 RESISTANCE (k) DS1856 toc12 120 110 100 RESISTANCE (k) 90 80 70 60 50 40 30 20 10 0 0 1 2 3 4 5 POWER-UP VOLTAGE (V) PROGRAMMED RESISTANCE (80h) >1M 50k VERSION 120 110 100 RESISTANCE (k) 90 80 70 60 50 40 30 20 10 0 0 1 2 3 4 5 POWER-UP VOLTAGE (V) PROGRAMMED RESISTANCE (80h) >1M 20k VERSION 1.01 0.99 0.98 0.97 0.96 -40 -25 -10 5 20 35 50 65 80 95 TEMPERATURE (C) 6 _____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Typical Operating Characteristics (continued) (VCC = 5.0V, TA = +25C, for both 50k and 20k versions, unless otherwise noted.) POSITION 00h RESISTANCE vs. TEMPERATURE DS1856 toc13 POSITION FFh RESISTANCE vs. TEMPERATURE DS1856 toc14 POSITION FFh RESISTANCE vs. TEMPERATURE 20k VERSION 19.80 RESISTANCE (k) DS1856 toc15 0.38 20k VERSION 0.37 RESISTANCE (k) 50.00 49.75 49.50 RESISTANCE (k) 50k VERSION 20.00 0.36 49.25 49.00 48.75 48.50 19.60 0.35 19.40 0.34 19.20 48.25 0.33 -40 -25 -10 5 20 35 50 65 80 95 TEMPERATURE (C) 48.00 -40 -25 -10 5 20 35 50 65 80 95 TEMPERATURE (C) 19.00 -40 -25 -10 5 20 35 50 65 80 95 TEMPERATURE (C) TEMPERATURE COEFFICIENT vs. SETTING DS1856 toc16 TEMPERATURE COEFFICIENT vs. SETTING TEMPERATURE COEFFICIENT (ppm/C) 700 600 500 400 300 200 100 0 -100 0 50 100 150 200 250 SETTING (DEC) +25C TO +95C +25C TO -40C 20k VERSION DS1856 toc17 400 TEMPERATURE COEFFICIENT (ppm/C) 350 300 250 200 150 100 50 0 -50 -100 0 50 100 150 200 +25C TO +95C +25C TO -40C 50k VERSION 800 250 SETTING (DEC) LSB ERROR vs. FULL-SCALE INPUT 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 0 25 DS1856 toc18 LSB ERROR vs. FULL-SCALE INPUT +3 SIGMA 2 1 DS1856 toc19 3 +3 SIGMA LSB ERROR MEAN LSB ERROR 0 -1 -2 MEAN -3 SIGMA -3 -4 -3 SIGMA 0 3.125 6.250 9.375 12.500 50 75 100 NORMALIZED FULL SCALE (%) NORMALIZED FULL SCALE (%) _______________________________________________________________________________________ 7 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Pin Description PIN 1 2 3 4 5 6 7 8 9 10 11 12 BALL B2 A2 C3 A1 B1 C2 C1 D1 D3 D4 C4 D2 NAME SDA SCL OUT1 IN1 OUT2 IN2 N.C. GND MON1 MON2 MON3 L0 FUNCTION 2-Wire Serial Data I/O Pin. Transfers serial data to and from the device. 2-Wire Serial Clock Input. Clocks data into and out of the device. Open-Drain Buffer Output TTL/CMOS-Compatible Input to Buffer Open-Drain Buffer Output TTL/CMOS-Compatible Input to Buffer No Connection Ground External Analog Input External Analog Input External Analog Input Low-End Resistor 0 Terminal. It is not required that the low-end terminals be connected to a potential less than the high-end terminals of the corresponding resistor. Voltage applied to any of the resistor terminals cannot exceed the power-supply voltage, VCC, or go below ground. High-End Resistor 0 Terminal. It is not required that the high-end terminals be connected to a potential greater than the low-end terminals of the corresponding resistor. Voltage applied to any of the resistor terminals cannot exceed the power-supply voltage, VCC, or go below ground. Low-End Resistor 1 Terminal High-End Resistor 1 Terminal Supply Voltage 13 14 15 16 B3 B4 A4 A3 H0 L1 H1 VCC Detailed Description The user can read the registers that monitor the VCC, MON1, MON2, MON3, and temperature analog signals. After each signal conversion, a corresponding bit is set that can be monitored to verify that a conversion has occurred. The signals also have alarm and warning flags that notify the user when the signals go above or below the user-defined value. Interrupts can also be set for each signal. The position values of each resistor can be independently programmed. The user can assign a unique value to each resistor for every 2C increment over the -40C to +102C range. Two buffers are provided to convert logic-level inputs into open-drain outputs. Typically, these buffers are used to implement transmit (Tx) fault and loss-of-signal (LOS) functionality. Additionally, OUT1 can be asserted in the event that one or more of the monitored values go beyond user-defined limits. 8 _____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 AD MD MD MD AD (AUXILIARY DEVICE ENABLE A0h) TABLE SELECT MD (MAIN DEVICE ENABLE) DEVICE ADDRESS ADDRESS R/W ADEN ADFIX SDA 2-WIRE INTERFACE SCL R/W Tx FAULT OUT1 ADDRESS MINT EEPROM 96 x 8 BIT 00h-5Fh LIMITS REGISTER MONITORS LIMIT HIGH MONITORS LIMIT LOW RESISTOR 0 256 POSITIONS L0 TxF MD H0 EEPROM 128 x 8 BIT STANDARDS IF ADEN = 0, [00h - 7Fh OF AD] IF ADEN = 1, [80h-FFh OF MD, TABLE 00/01h] TABLE SELECT EEPROM 72 x 8 BIT 80h-C7h TABLE 04 RESISTOR 0 LOOK-UP TABLE TABLE SELECT EEPROM 72 x 8 BIT 80h-C7h TABLE 05 RESISTOR 1 LOOK-UP TABLE DEVICE ADDRESS ADDRESS R/W ADDRESS R/W ADDRESS ADEN (BIT) DATA BUS TEMP INDEX TEMP INDEX R/W TEMP INDEX INV1 RxL OUT2 LOS TxF MINT (BIT) REGISTER IN1 SRAM 32 x 8 BIT 60h-7Fh RESISTOR 1 256 POSITIONS H1 TABLE SELECT MEASUREMENT INV2 RIGHT SHIFTING L1 WARNING FLAGS MD R/W INV1 (BIT) ALARM FLAGS IN2 TABLE SELECT VCC INTERNAL TEMP INTERNAL CALIBRATION ADDRESS TABLE 03 EEPROM 80h-B7h VENDOR ADFIX (BIT) MASKING (TMP, VCC, MON1, MON2, MON3) INV2 (BIT) DS1856 MON1 MON2 MON3 MUX CTRL A/D CTRL VCC VCC GND COMP CTRL WARNING FLAGS ALARM FLAGS COMPARATOR MONITORS LIMIT HIGH MONITORS LIMIT LOW MEASUREMENT MUX ADC 12-BIT DEVICE ADDRESS ADEN (BIT) MINT INTERRUPT Figure 1. Block Diagram _____________________________________________________________________ 9 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Table 1. Scales for Monitor Channels at Factory Setting SIGNAL +FS SIGNAL 6.5528V 2.4997V 2.4997V 2.4997V +FS (hex) 7FFC FFF8 FFF8 FFF8 FFF8 -FS SIGNAL -128C 0V 0V 0V 0V -FS (hex) 8000 0000 0000 0000 0000 Table 3. Look-Up Table Address for Corresponding Temperature Values TEMPERATURE (C) <-40 -40 -38 -36 -34 -- +98 CORRESPONDING LOOK-UP TABLE ADDRESS 80h 80h 81h 82h 83h -- C5h C6h C7h C7h Temperature +127.984 VCC MON1 MON2 MON3 Table 2. Signal Comparison SIGNAL VCC MON1 MON2 MON3 Temperature FORMAT Unsigned Unsigned Unsigned Unsigned Two's complement +100 +102 >+102 Monitor Conversion Example MSB (BIN) 11000000 10000000 LSB (BIN) 00000000 10000000 VOLTAGE (V) 1.875 1.255 Monitored Signals Each signal (VCC, MON1, MON2, MON3, and temperature) is available as a 16-bit value with 12-bit accuracy (left-justified) over the serial bus. See Table 1 for signal scales and Table 2 for signal format. The four LSBs should be masked when calculating the value. The 3 LSBs are internally masked with 0s. The signals are updated every frame rate (tframe) in a round-robin fashion. The comparison of all five signals with the high and low user-defined values are done automatically. The corresponding flags are set to 1 within a specified time of the occurrence of an out-of-limit condition. Calculating Signal Values The LSB = 100V for VCC, and the LSB = 38.147V for the MON signals when using factory default settings. To calculate VCC, convert the unsigned 16-bit value to decimal and multiply by 100V. To calculate MON1, MON2, or MON3, convert the unsigned 16-bit value to decimal and multiply by 38.147V. To calculate the temperature, treat the two's complement value binary number as an unsigned binary number, then convert to decimal and divide by 256. If the result is greater than or equal to 128, subtract 256 from the result. Temperature: high byte: -128C to +127C signed; low byte: 1/256C. Temperature Bit Weights S 26 2-2 25 2-3 24 2-4 23 2-5 22 2-6 21 2-7 20 2-8 2-1 Monitor/VCC Bit Weights MSB LSB 215 27 214 26 213 25 212 24 211 23 210 22 29 21 28 20 Temperature Conversion Examples MSB (BIN) LSB (BIN) 00000000 00001111 00000000 00000000 00000000 TEMPERATURE (C) +64 +64.059 +95 -10 -40 01000000 VCC Conversion Examples MSB (BIN) 10000000 11000000 LSB (BIN) 10000000 11111000 VOLTAGE (V) 3.29 4.94 01000000 01011111 11110110 11011000 10 ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Table 4. ADEN Address Configuration ADEN (ADDRESS ENABLE) 0 1 NO. OF SEPARATE DEVICE ADDRESSES 2 1 (Main Device Only) ADDITIONAL INFORMATION See Figure 2 See Figure 3 Table 5. ADEN and ADFIX Bits ADEN 0 0 1 1 ADFIX 0 1 0 1 AUXILIARY ADDRESS A0h A0h -- -- MAIN ADDRESS A2h EEPROM (Table 03, 8Ch) A2h EEPROM (Table 03, 8Ch) DEC HEX 2-WIRE ADDRRESS A0h 0 0 00h AUXILIARY DEVICE AUXILIARY DEVICE MAIN DEVICE DEC HEX 0 0 2-WIRE ADDRESS A2h (DEFAULT) 00h MAIN DEVICE NOTE 1: ADEN BIT = 0. AUXILIARY MEMORY IS ADDRESSED USING THE AUXILIARY DEVICE NOTE 1. 2-WIRE SLAVE ADDRESS OF A0h, AND THE REMAINDER OF THE MEMORY IS NOTE 1. ADDRESSED USING THE MAIN DEVICE 2-WIRE SLAVE ADDRESS OF A2h NOTE 1. (WHEN ADFIX = 0). NOTE 2: TABLES 00h, 01h, AND 02h DO NOT EXIST. EEPROM AUXILIARY MEMORY (128 BYTES) LOWER MEMORY PASSWORD ENTRY (PWE) (4 BYTES) 127 7F 7Fh 127 128 7F 80 TABLE SELECT BYTE 7Fh 80h TABLE 03h CONFIGURATION TABLE 183 199 200 B7 C7 C8 F0h RESERVED AND CALIBRATION CONSTANTS 255 FF FFh B7h 80h TABLE 04h RESISTOR 0 LOOK-UP TABLE (72 BYTES) C7h F0h RESERVED AND CALIBRATION CONSTANTS FFh 80h TABLE 05h RESISTOR 1 LOOK-UP TABLE (72 BYTES) C7h Figure 2. Memory Organization, ADEN = 0 Variable Resistors The value of each variable resistor is determined by a temperature-addressed look-up table, which can assign a unique value (00h to FFh) to each resistor for every 2C increment over the -40C to +102C range (see Table 3). See the Temperature Conversion section for more information. The variable resistors can also be used in manual mode. If the TEN bit equals 0, the resistors are in manual mode and the temperature indexing is disabled. The user sets the resistors in manual mode by writing to addresses 82h and 83h in Table 03 to control resistors 0 and 1, respectively. Memory Description The memory of the DS1856 is divided into two areas referred to as the Main Device and the Auxiliary Device. The Main Device comprises all of the DS1856 specific memory while the Auxiliary Device consists of 128 bytes of general-purpose EEPROM and is especially useful in GBIC applications. Main and Auxiliary 11 ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 DEC HEX 2-WIRE ADDRRESS A2h (DEFAULT) 0 0 00h LOWER MEMORY NOTE 1: ADEN BIT = 1. ALL MEMORY (INCLUDING THE AUXILIARY MEMORY) IS ADDRESSED USING THE NOTE 1: MAIN DEVICE 2-WIRE SLAVE ADDRESS. NOTE 2: TABLES 00h AND 01h ACCESS THE SAME PHYSICAL MEMORY. NOTE 3: TABLE 02h DOES NOT EXIST. PASSWORD ENTRY (PWE) (4 BYTES) 127 128 7F TABLE SELECT BYTE 7Fh 80h TABLE 00h/01h TABLE 03h CONFIGURATION TABLE 183 199 200 B7 C7 C8 EEPROM AUXILIARY MEMORY (128 BYTES) B7h 80h TABLE 04h RESISTOR 0 LOOK-UP TABLE (72 BYTES) C7h F0h RESERVED AND CALIBRATION CONSTANTS 255 FF FFh FFh F0h RESERVED AND CALIBRATION CONSTANTS FFh 80h TABLE 05h RESISTOR 1 LOOK-UP TABLE (72 BYTES) C7h 80 80h Figure 3. Memory Organization, ADEN = 1 memories can be accessed by two separate 2-wire slave addresses (see Table 4). The Main Device address is A2h (or determined by the value in Table 03, byte 8Ch, when ADFIX = 1) and the Auxiliary Device address is A0h (fixed). A configuration bit, ADEN (Table 03, byte 89h, bit 5), determines whether the DS1856 uses one or two 2-wire slave addresses. This feature can be used to save component count in SFF applications or other applications where both GBIC and monitoring functions are implemented and two device addresses are needed. The memory organization for ADEN = 0 is shown in Figure 2. In this configuration, the 128 bytes of Auxiliary Device EEPROM are located at memory locations 00h to 7Fh and accessed using the Auxiliary Device 2-wire slave address of A0h (fixed). The remainder of the DS1856's memory is accessed using the Main Device address. The memory organization of the second configuration, ADEN = 1, is shown in Figure 3. In this configuration, all of the DS1856's memory including the Auxiliary memory is accessed using only the Main Device address. The Auxiliary Device memory is mapped into Table 00 and Table 01 in the Main Device. Both tables map to the same block of physical memory. This is done to improve the compatibility between previous members of this IC family such as the DS1858/DS1859 and the DS1852. In this configuration, the DS1856 ignores communication using the Auxiliary Device address. The value of the Main Device address can be changed to a value other than the default value of A2h (see data sheet Table 5). There can be up to 128 devices sharing a common 2-wire bus, with each device having its own unique address. To change the Main Device address, first write the desired value to the Chip Address byte (Table 03, byte 8Ch). Then, enable the new address by setting ADFIX to a 1. Subsequent 2-wire communication must be performed using the new Main Device address. When ADFIX = 0, the Chip Address byte is ignored, and the Main Device address is set to A2h. 12 ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 The DS1856 2-wire interface uses 8-bit addressing, which allows up to 256 bytes to be addressed traditionally on a given 2-wire slave address. However, since the Main Device contains more than 256 bytes, a table scheme is used. The lower 128 bytes of the Main Device, memory locations 00h to 7Fh, function as expected and are independent of the currently selected table. Byte 7Fh is the Table Select byte. This byte determines which memory table will be accessed by the 2-wire interface when address locations 80h to FFh are accessed. Memory locations 80h to FFh are accessible only through the Main Device address. The Auxiliary Device address has no access to the tables, but the Auxiliary Device memory can be mapped into the Main Device's memory space (by setting ADEN = 1). Valid values for the Table Select byte are shown in the table below. (PWE) bytes located in the Main Device at 7Bh to 7Eh. The value entered is compared to both the PW1 and PW2 settings located in Table 03, bytes B0h to B3h and Table 03, bytes B4h to B7h, respectively, to determine if access should be granted. Access is granted until the password is changed or until power is cycled. Writing PWE can be done with any level of access, although PWE can never be read. Writing PW1 and PW2 requires PW2 access. However, PW1 and PW2 can never be read, even with PW2 access. On power-up, PWE is set to all 1s (FFFFh). As long as neither of the passwords are ever changed to FFFFh, then User access is the power-up default. Likewise, password protection can be intentionally disabled by setting the PW2 password to FFFFh. Table 6. Table Select Byte TABLE SELECT BYTE 00 01 02 03 04 05 TABLE NAME Auxiliary Device Memory (When ADEN = 1) Does Not Exist Configuration Resistor 0 Look-up Table Resistor 1 Look-up Table Memory Map The following table is the legend used in the memory map to indicate the access level required for read and write access. Each table in the following memory map begins with a higher level view of a particular portion of the memory showing information such as row (8 bytes) and byte names. The tables are then followed, where applicable, by an Expanded Bytes table, which shows bit names and values. Furthermore, both tables use the permission legend to indicate the access required on a row, byte, and bit level. The memory map is followed by a Register Description section, which describes bytes and bits in further detail. Before attempting to read and write any of the bits or bytes mentioned in this section, it is important to look at the memory map provided in a subsequent section to verify what level of password is required. Password protection is described in the following section. Table 7. Password Permission PERMISSION <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> READ WRITE At least one byte in the row is different than the rest of the row, so look at each byte separately for permissions. all all all PW2 all NA PW1 PW2 NA PW2 all PW2 NA all (The part also writes to this byte.) PW2 + mode_bit all all PW1 PW2 PW2 NA PW1 Password Protection The DS1856 uses two 4-byte passwords to achieve three levels of access to various memory locations. The three levels of access are: User Access: This is the default state after power-up. It allows read access to standard monitoring and status functions. Level 1 Access: This allows access to customer data table (Tables 00 and 01) in addition to everything granted by User access. This level is granted by entering Password 1 (PW1). Level 2 Access: This allows access to all memory, settings, and features, in addition to everything granted by Level 1 and User access. This level is granted by entering Password 2 (PW2). To obtain a particular level of access, the corresponding password must be entered in the Password Entry ____________________________________________________________________ 13 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Memory Map LOWER MEMORY Row (hex) 00 08 10 18 20 28 30 38 40 48 50 58 60 68 70 78 Byte (hex) <1> <1> <1> <1> <1> Row Name Threshold0 Threshold1 Threshold2 Threshold3 Threshold4 user ROM user ROM user ROM user ROM user ROM user ROM user ROM Values0 Values1 Word 0 Byte 0/8 Byte 1/9 Temp Alarm Hi VCC Alarm Hi Mon1 Alarm Hi Mon2 Alarm Hi Mon3 Alarm Hi EE EE EE EE EE EE EE Temp Value <2> Word 1 Byte 2/A Byte 3/B Temp Alarm Lo VCC Alarm Lo Mon1 Alarm Lo Mon2 Alarm Lo Mon3 Alarm Lo EE EE EE EE EE EE EE Vcc Value <2> Word 2 Byte 4/C Byte 5/D Temp Warn Hi VCC Warn Hi Mon1 Warn Hi Mon2 Warn Hi Mon3 Warn Hi EE EE EE EE EE EE EE <2> Word 3 Byte 6/E Byte 7/F Temp Warn Lo VCC Warn Lo Mon1 Warn Lo Mon2 Warn Lo Mon3 Warn Lo EE EE EE EE EE EE EE <0> <1> <1> <1> <1> <1> <1> <1> EE EE EE EE EE EE EE Mon3 Value Alarm0 <6> EE EE EE EE EE EE EE Reserved Reserved <6> EE EE EE EE EE EE EE Reserved Warn0 <6> EE EE EE EE EE EE EE <3> <2> <0> <2> <0> Mon1 Value Warn1 Mon2 Value Status Update Tbl Sel Bit0 bit1 EE 2-6 2 -6 Alrm Wrn <6> Alarm1 Reserved Bit7 bit15 EE S S 215 2 15 Reserved <6> Reserved PWE lsb Bit1 bit3 EE 2-5 2 -5 Reserved <5> Table Select Byte Name User EE Reserved Bit6 Reserved Bit5 PWE msb Bit3 bit7 EE 2-1 2 -1 EXPANDED BYTES Bit4 bit9 EE 22 2 2 EE EE EE EE EE EE EE 2 Bit2 bit5 EE 2-2 2 -2 bit14 26 2 2 6 bit13 25 2 2 5 bit12 24 2 2 4 bit11 23 2 2 3 bit10 bit8 20 2 2 EE EE EE EE EE EE EE 0 bit6 bit4 2-4 2 -4 bit2 bit0 2-8 2-8 20 20 EE EE EE EE EE EE EE EE EE 21 2 2 1 Temp Alarm Temp Warn Volt Alarm Volt Warn 28 30 38 40 48 50 58 User ROM User ROM User ROM User ROM User ROM User ROM User ROM 2-3 2 -3 2-7 2 -7 214 14 213 13 212 12 211 11 210 10 29 9 28 8 27 2 7 26 2 EE EE EE EE EE EE EE 6 25 2 5 24 2 EE EE EE EE EE EE EE 4 23 2 3 22 2 EE EE EE EE EE EE EE 2 21 2 1 EE EE EE EE EE EE EE EE EE EE EE EE EE EE 14 ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Memory Map (continued) 60 62 64 66 68 6E 6F 70 71 74 75 7B 7D 7F Temp Value VCC Value Mon1 Value Mon2 Value Mon3 Value Status Update Alarm1 Alarm0 Warn1 Warn0 PWE msb PWE lsb Tbl Sel S 215 2 2 2 15 15 15 <2> 26 214 2 2 2 Rhiz 14 14 14 25 213 2 2 2 13 13 13 24 212 2 2 2 12 12 12 23 211 2 2 2 <2> 11 11 11 22 210 2 2 2 10 10 10 21 29 2 2 2 <2> 9 9 9 20 28 2 2 2 8 8 8 2-1 27 2 2 2 <2> 7 7 7 2-2 26 2 2 2 6 6 6 2-3 25 2 2 2 5 5 5 <2> 2-4 24 2 2 2 TxF 4 4 4 2-5 23 2 2 2 3 3 3 <2> 2-6 22 2 2 2 RxL 2 2 2 2-7 21 2 2 2 1 1 1 2-8 20 20 20 20 Rdyb <11> SoftHiz Reserved VCC Hi Reserved VCC Lo Reserved <2> Temp Rdy Temp Hi Mon3 Hi Temp Hi Mon3 Hi 231 2 15 VCC Rdy Temp Lo Mon3 Lo Temp Lo Mon3 Lo 229 2 13 Mon1 Rdy Reserved VCC Hi Reserved 227 2 11 Mon2 Rdy Reserved VCC Lo Reserved 225 2 9 Mon3 Rdy Mon1 Hi Reserved Mon1 Hi Reserved 223 2 7 Reserved Mon1 Lo Reserved Mon1 Lo Reserved 221 2 5 Reserved Mon2 Hi Reserved Mon2 Hi Reserved 219 2 3 Reserved Mon2 Lo Mint Mon2 Lo Reserved 217 2 1 230 2 27 14 228 2 26 12 226 2 25 10 224 2 24 8 222 2 23 6 220 2 22 4 218 2 21 2 216 20 20 AUXILIARY (VALID WHEN ADEN = 0) Row (hex) 00-7F Row (hex) 80-FF Row Name <1> Word 0 Byte 0/8 EE Word 0 Byte 0/8 EE Byte 1/9 EE EE Byte 1/9 EE EE Word 1 Byte 2/A Byte 3/B EE Word 1 Byte 2/A Byte 3/B EE EE EE Word 2 Byte 4/C Byte 5/D EE Word 2 Byte 4/C Byte 5/D EE EE EE Word 3 Byte 6/E Byte 7/F EE Word 3 Byte 6/E Byte 7/F EE EE TABLE 00/01 (VALID WHEN ADEN = 1) Row Name <7> EE ____________________________________________________________________ 15 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Memory Map (continued) TABLE 03 (CONFIGURATION) Row (hex) 80 88 90 98 A0 A8 B0 Byte (hex) 80 81 82 83 88 89 8C 8E 8F 92 94 96 98 A2 A4 A6 A8 AE B0 B2 B4 B6 Row Name <0> <8> Word 0 Byte 0/8 <8> Word 1 Byte 2/A <4> Word 2 Byte 4/C <8> Word 3 Byte 6/E <8> Byte 1/9 <4> Byte 3/B <4> Byte 5/D <8> Byte 7/F <8> Config0 Config1 Scale0 Scale1 Mode Tindex Res0 Res1 Reserved Reserved Reserved Rshift1 Reserved Rshift0 Int Enable Config Reserved Reserved chip addr Reserved <8> <8> <8> <8> <9> Reserved Mon3 Scale Reserved MON3 Offset PW1 msb Bit7 bit15 27 2 2 7 7 Vcc Scale Reserved Vcc Offset Reserved PW1 lsb EXPANDED BYTES Bit6 Bit5 bit11 25 2 2 5 5 Mon1 Scale Reserved MON1 Offset Reserved PW2 msb Bit4 Bit3 bit7 23 2 2 3 3 Mon2 Scale Reserved MON2 Offset Internal Temp Offset* PW2 lsb Offset0 Offset1 Pwd Value Byte Name Mode Tindex Res0 Res1 Bit2 bit6 bit5 22 2 2 2 2 Bit1 bit4 bit3 21 2 2 1 1 Bit0 bit1 20 20 20 Reserved Inv 2 20 Mon20 Reserved 21 2 2 2 2 2 2 2 2 2 1 1 1 3 bit14 bit13 26 2 2 6 6 bit12 bit10 bit9 24 2 2 4 4 bit8 bit2 TEN bit0 AEN Reserved Reserved Reserved Reserved Reserved Reserved Int Enable Config Chip Addr Rshift1 Rshift0 VCC Scale Mon1 Scale Mon2 Scale Mon3 Scale VCC Offset Mon1 Offset Mon2 Offset Mon3 Offset Temp Offset* PW1 msb PW1 lsb PW2 msb PW2 lsb Temp Reserved 27 Reserved Reserved 215 2 2 2 15 15 15 Vcc Reserved 26 Mon12 Mon3 213 2 2 2 2 2 2 2 2 2 13 13 13 15 2 Mon1 ADEN 25 Mon11 Mon3 211 2 2 2 2 2 2 2 2 2 11 11 11 13 12 12 12 14 1 Mon2 ADFIX 24 Mon10 Mon3 29 2 2 2 2 2 2 2 2 9 9 9 10 10 10 12 0 Mon3 Reserved 23 Reserved Reserved 27 2 2 2 2 2 2 2 2 2 2 7 7 7 9 Reserved Reserved 22 Mon22 Reserved 25 2 2 2 2 2 2 2 2 2 5 5 5 7 Reserved Inv 1 21 Mon21 Reserved 23 2 2 2 2 2 2 2 2 2 3 3 3 5 214 2 2 2 14 14 14 212 2 2 2 2 2 2 2 2 2 210 2 2 2 2 2 2 2 2 2 28 2 2 2 2 2 2 2 2 8 8 8 26 2 2 2 2 2 2 2 2 2 2 6 6 6 8 24 2 2 2 2 2 2 2 2 2 4 4 4 6 22 2 2 2 2 2 2 2 2 2 2 2 2 4 20 20 20 20 22 22 22 22 2-6 216 20 216 20 S S S S S 2 2 2 31 15 31 S S S S 2 2 2 2 8 30 14 30 11 10 215 15 15 7 214 14 14 6 213 13 13 5 212 12 12 4 211 11 11 3 210 10 10 2 29 9 9 1 28 8 8 0 27 7 7 26 6 6 25 5 5 24 4 4 23 3 3 2 2 2 2 2 2 2 2 -1 -2 -3 -4 -5 29 13 29 28 12 28 27 11 27 26 10 26 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 2 2 2 2 2 25 24 23 22 21 20 19 18 17 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 *The final result must be XOR'ed with BB40h. 16 ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Memory Map (continued) TABLE 04 (LOOKUP TABLE FOR RESISTOR 0) Row (hex) 80 88 90 98 A0 A8 B0 B8 C0 C8 D0 D8 E0 E8 F0 F8 Byte (hex) 80-C7 F8-FF <10> Row Name <8> <8> <8> <8> <8> <8> <8> <8> <8> Word 0 Byte 0/8 Byte 1/9 Word 1 Byte 2/A Byte 3/B Word 2 Byte 4/C Byte 5/D Word 3 Byte 6/E Byte 7/F LUT LUT LUT LUT LUT LUT LUT LUT LUT Empty Empty Empty Empty Empty Reserved Empty Empty Empty Empty Empty Reserved Empty Empty Empty Empty Empty Reserved Empty Empty Empty Empty Empty Reserved Empty Empty Empty Empty Empty Reserved Empty Empty Empty Empty Empty Reserved Empty Empty Empty Empty Empty Reserved Empty Empty Empty Empty Empty Reserved Res0 data Byte Name Res0 Resistor 0 Calibration Constants (see data sheet Table 8) EXPANDED BYTES Bit7 27 Bit6 26 Bit5 25 Bit4 24 Bit3 23 Bit2 22 Bit1 21 Bit0 20 Res0 data Resistor 0 Calibration Constants (see data sheet Table 8 for weighting) ____________________________________________________________________ 17 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Memory Map (continued) TABLE 05 (LOOKUP TABLE FOR RESISTOR 1) Row (hex) 80 88 90 98 A0 A8 B0 B8 C0 C8 D0 D8 E0 E8 F0 F8 Byte (hex) 80-C7 F8-FF <10> Row Name <8> <8> <8> <8> <8> <8> <8> <8> <8> Word 0 Byte 0/8 Byte 1/9 Word 1 Byte 2/A Byte 3/B Word 2 Byte 4/C Byte 5/D Word 3 Byte 6/E Byte 7/F LUT LUT LUT LUT LUT LUT LUT LUT LUT Empty Empty Empty Empty Empty Reserved Empty Empty Empty Empty Empty Reserved Empty Empty Empty Empty Empty Reserved Empty Empty Empty Empty Empty Reserved Empty Empty Empty Empty Empty Reserved Empty Empty Empty Empty Empty Reserved Empty Empty Empty Empty Empty Reserved Empty Empty Empty Empty Empty Reserved Res1 data Byte Name Res1 Resistor 1 Calibration Constants (see data sheet Table 8) EXPANDED BYTES Bit7 27 Bit6 26 Bit5 25 Bit4 24 Bit3 23 Bit2 22 Bit1 21 Bit0 20 Res1 data Resistor 1 Calibration Constants (see data sheet Table 8 for weighting) 18 ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Register Descriptions Name of Row * * * Name of Byte............. Threshold0 Temp High Alarm ..... * * * Threshold1 * * * * Threshold2 * * * * ____________________________________________________________________ 19 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Register Descriptions (continued) Threshold3 * Mon2 High Alarm ..... * * * Threshold4 * Mon3 High Alarm ..... * * * User ROM * User ROM ................. A2D Value0 * * * Temp Meas ................ * 20 ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Register Descriptions (continued) A2D Value1 * * * Mon3 Meas................ Reserved .................... Status ......................... a) Rhiz.................... b) Soft Hiz.............. c) Reserved ............ d) TxF ................... e) RxL ................... f) Rdyb................... 21 * Update ....................... Temp Rdy .......... VCC Rdy............. Mon1 Rdy.......... Mon2 Rdy.......... e) Mon3 Rdy.......... a) b) c) d) Status * Alarm0 ....................... a) Temp Hi............. b) Temp Lo ............ c) VCC Hi .............. d) VCC Lo .............. e) MON1 Hi........... f) MON1 Lo .......... g) MON2 Hi........... h) MON2 Lo .......... Alarm1 ....................... a) MON3 HI........... b) MON3 Lo .......... c) Mint ................... Reserved .................... Warning0 ................... a) Temp Hi............. b) Temp Lo ............ c) VCC Hi ............. * * * ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Register Descriptions (continued) d) VCC Lo .............. Low Warning Status for VCC measurement. This bit is set when the VCC supply is below the POA trip point value. It clears itself when a VCC measurement is completed and the value is above the low threshold. e) MON1 Hi........... High Warning Status for MON1 measurement. f) MON1 Lo .......... Low Warning Status for MON1 measurement. g) MON2 Hi........... High Warning Status for MON2 measurement. h) MON2 Lo .......... Low Warning Status for MON2 measurement. * Warning1 ................... Table Select * * * Config0 * * 22 ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Register Descriptions (continued) * . Res0 ........................... ____________________________________________________________________ 23 * * Config 1 * * * * * Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Register Descriptions (continued) Scale0 * * VCC Scale ................... * Scale1 * MON3 Scale .............. Offset0 * * * Offset1 * * MON3 Offset ............. PWD Value * Password 1................ * LUT * * Res0 ........................... The unsigned value for Resistor 0. Res1 ........................... The unsigned value for Resistor 1. 24 ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection Programming the Look-up Table (LUT) The following equation can be used to determine which resistor position setting, 00h to FFh, should be written in the LUT to achieve a given resistance at a specific temperature. 2 R - u x 1 + v x (C - 25) + w x (C - 25) - pos(, R, C) = 1 + y x C - 25 + z x C - 25 2 (x) x ( ) ( ) R = the resistance desired at the output terminal C = temperature in degrees Celsius u, v, w, x1, x0, y, z, and are calculated values found in the corresponding look-up tables. The variable x from the equation above is separated into x1 (the MSB of x) and x0 (the LSB of x). Their addresses and LSB values are given below. The variable y is assigned a value. All other variables are unsigned. Resistor 0 variables are found in Table 04, and Resistor 1 variables are found in Table 05. When shipped from the factory, all other memory locations in the LUTs are programmed to FFh. Table 8. Calibration Constants ADDRESS F8h F9h FAh FBh FCh FDh FEh FFh VARIABLE u v w x1 x0 y z LSB 20 20E-6 100E-9 21 2-7 2E-6 (signed) 8E-6 (signed) for 2.5k resistor 10E-9 2-2 To scale the gain and offset of the converter for a specific input, you must first know the relationship between the analog input and the expected digital result. The input that would produce a digital result of all zeros is the null value (normally this input is GND). The input that would produce a digital result of all ones is the fullscale (FS) value. The FS value is also found by multiplying an all-ones digital answer by the weighted LSB (e.g., since the digital reading is a 16-bit register, let us assume that the LSB of the lowest weighted bit is 50V, then the FS value is 65,535 x 50V = 3.27675V). A binary search is used to scale the gain of the converter. This requires forcing two known voltages to the input pin. It is preferred that one of the forced voltages is the null input and the other is 90% of FS. Since the LSB of the least significant bit in the digital reading register is known, the expected digital results are also known for both inputs (null/LSB = CNT1 and 90%FS/ LSB = CNT2). The user might not directly force a voltage on the input. Instead they have a circuit that transforms light, frequency, power, or current to a voltage that is the input to the DS1856. In this situation, the user does not need to know the relationship of voltage to expected digital result but instead knows the relationship of light, frequency, power, or current to the expected digital result. An explanation of the binary search used to scale the gain is best served with the following example pseudocode: /* Assume that the null input is 0.5V. */ /* In addition, the requirement for LSB is 50V. */ FS = 65535 x 50E-6; /* 3.27675 */ CNT1 = 0.5 / 50E-6; CNT2 = 0.90 x FS / 50E-6; /* 10000 */ /* 58981.5 */ DS1856 /* Thus the null input 0.5V and the 90% of FS input is 2.949075V. */ Set the trim-offset-register to zero; Set Right-Shift register to zero (typically zero. See the Right-Shifting section); gain_result = 0h; Clamp = FFF8h/2^(Right_Shift_Register); For n = 15 down to 0 begin Internal Calibration The DS1856 has two methods for scaling an analog input to a digital result. The two methods are gain and offset. Each of the inputs (V CC, MON1, MON2, and MON3) has a unique register for the gain and the offset found in Table 03h, 92h to 99h, and A2h to A9h. ____________________________________________________________________ 25 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection gain_result = gain_result + 2^n; Force the 90% FS input (2.949075V); Meas2 = read the digital result from the part; If Meas2 >= Clamp then gain_result = gain_result - 2^n; Else Force the null input (0.5V); Meas1 = read the digital result from the part; if (Meas2 - Meas1) > (CNT2 - CNT1) then gain_result = gain_result - 2^n; end; Set the gain register to gain_result; The gain register is now set and the resolution of the conversion will best match the expected LSB. The next step is to calibrate the offset of the DS1856. With the correct gain value written to the gain register, again force the null input to the pin. Read the digital result from the part (Meas1). The offset value is equal to the negative value of Meas1. Meas1 Offset _Re gister = 4 The calculated offset is now written to the DS1856 and the gain and offset scaling is now complete. DS1856 value can be right-shifted four times without losing resolution. Table 9 shows when the right-shifting method can be used. Temperature Conversion The direct-to-digital temperature sensor measures temperature through the use of an on-chip temperature measurement technique with a -40C to +102C operating range. Temperature conversions are initiated upon power-up, and the most recent conversion is stored in memory locations 60h and 61h of the Main Device, which are updated every tframe. Temperature conversions do not occur during an active read or write to memory. The value of each resistor is determined by the temperature-addressed look-up table. The look-up table assigns a unique value to each resistor for every 2C increment with a 1C hysteresis at a temperature transition over the operating temperature range (see Figure 4). Table 9. Right Shifting OUTPUT RANGE USED WITH ZERO RIGHT-SHIFTS 0h....FFFFh 0h....7FFFh 0h....3FFFh 0h....1FFFh 0h....0FFFh NUMBER OF RIGHT-SHIFTS NEEDED 0 1 2 3 4 Right-Shifting A/D Conversion Result (Scalable Dynamic Ranging) The right-shifting method is used to regain some of the lost ADC range of a calibrated system. If a system is calibrated so the maximum expected input results in a digital output value of less than 7FFFh (1/2 FS), then it is a candidate for using the right-shifting method. If the maximum desired digital output is less than 7FFFh, then the calibrated system is using less than 1/2 of the ADC's range. Similarly, if the maximum desired digital output is less than 1FFFh, then the calibrated system is only using 1/8 of the ADC's range. For example, if using a zero for the right-shift during internal calibration and the maximum expected input results in a maximum digital output less than 1FFCh, only 1/8 of the ADC's range is used. If left like this, the three MS bits of the ADC will never be used. In this example, a value of 3 for the rightshifting maximizes the ADC range. No resolution is lost since this is a 12-bit converter that is left justified. The 26 M6 M5 DECREASING TEMPERATURE MEMORY LOCATION M4 M3 M2 INCREASING TEMPERATURE M1 2 4 6 8 10 12 TEMPERATURE (C) Figure 4. Look-Up Table Hysteresis ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection Power-Up and Low-Voltage Operation During power-up, the device is inactive until V CC exceeds the digital power-on-reset voltage (POD). At this voltage, the digital circuitry, which includes the 2-wire interface, becomes functional. However, EEPROMbacked registers/settings cannot be internally read (recalled into shadow SRAM) until VCC exceeds the analog power-on-reset voltage (POA), at which time the remainder of the device becomes fully functional. Once VCC exceeds POA, the RDYB bit in byte 6Eh of the Main Device memory is timed to go from a 1 to a 0 and indicates when analog-to-digital conversions begin. If VCC ever dips below POA, the RDYB bit reads as a 1 again. Once a device exceeds POA and the EEPROM is recalled, the values remain active (recalled) until VCC falls below POD. For 2-wire device addresses sourced from EEPROM (ADFIX = 1), the device address defaults to A2h until VCC exceeds POA and the EEPROM values are recalled. The Auxiliary Device (A0h) is always available within this voltage window (between POD and the EEPROM recall) regardless of the programmed state of ADEN. Furthermore, as the device powers up, the VCClo alarm flag (bit 4 of 70h in Main Device) defaults to a 1 until the first VCC analog-to-digital conversion occurs and sets or clears the flag accordingly. Standby Mode: The DS1856 features a low-power mode that is automatically enabled after power-on, after a STOP command, and after the completion of all internal operations. Device Addressing: The DS1856 must receive an 8-bit device address, the slave address byte, following a START condition to enable a specific device for a read or write operation. The address is clocked into this part MSB to LSB. The address byte consists of either A2h or the value in Table 03, 8Ch for the Main Device or A0h for the Auxiliary Device, then the R/W bit. This byte must match the address programmed into Table 03, 8Ch or A0h (for the Auxiliary Device). If a device address match occurs, this part will output a zero for one clock cycle as an acknowledge and the corresponding block of memory is enabled (see the Memory Organization section). If the R/W bit is high, a read operation is initiated. If the R/W is low, a write operation is initiated (see the Memory Organization section). If the address does not match, this part returns to a lowpower mode. DS1856 Write Operations After receiving a matching address byte with the R/W bit set low, if there is no write protect, the device goes into the write mode of operation (see the Memory Organization section). The master must transmit an 8bit EEPROM memory address to the device to define the address where the data is to be written. After the byte has been received, the DS1856 transmits a zero for one clock cycle to acknowledge the address has been received. The master must then transmit an 8-bit data word to be written into this address. The DS1856 again transmits a zero for one clock cycle to acknowledge the receipt of the data. At this point, the master must terminate the write operation with a STOP condition. The DS1856 then enters an internally timed write process tw to the EEPROM memory. All inputs are disabled during this byte write cycle. Page Write The DS1856 is capable of an 8-byte page write. A page is any 8-byte block of memory starting with an address evenly divisible by eight and ending with the starting address plus seven. For example, addresses 00h through 07h constitute one page. Other pages would be addresses 08h through 0Fh, 10h through 17h, 18h through 1Fh, etc. 2-Wire Operation Clock and Data Transitions: The SDA pin is normally pulled high with an external resistor or device. Data on the SDA pin may only change during SCL-low time periods. Data changes during SCL-high periods will indicate a START or STOP condition depending on the conditions discussed below. See the timing diagrams in Figures 5 and 6 for further details. START Condition: A high-to-low transition of SDA with SCL high is a START condition that must precede any other command. See the timing diagrams in Figures 5 and 6 for further details. STOP Condition: A low-to-high transition of SDA with SCL high is a STOP condition. After a read or write sequence, the stop command places the DS1856 into a low-power mode. See the timing diagrams in Figures 5 and 6 for further details. Acknowledge: All address and data bytes are transmitted through a serial protocol. The DS1856 pulls the SDA line low during the ninth clock pulse to acknowledge that it has received each word. ____________________________________________________________________ 27 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 A page write is initiated the same way as a byte write, but the master does not send a STOP condition after the first byte. Instead, after the slave acknowledges the data byte has been received, the master can send up to seven more bytes using the same nine-clock sequence. The master must terminate the write cycle with a STOP condition or the data clocked into the DS1856 will not be latched into permanent memory. The address counter rolls on a page during a write. The counter does not count through the entire address space as during a read. For example, if the starting address is 06h and 4 bytes are written, the first byte goes into address 06h. The second goes into address 07h. The third goes into address 00h (not 08h). The fourth goes into address 01h. If 9 bytes or more are written before a STOP condition is sent, the first bytes sent are overwritten. Only the last 8 bytes of data are written to the page. Acknowledge Polling: Once the internally timed write has started and the DS1856 inputs are disabled, acknowledge polling can be initiated. The process involves transmitting a START condition followed by the device address. The R/W bit signifies the type of operation that is desired. The read or write sequence will only be allowed to proceed if the internal write cycle has completed and the DS1856 responds with a zero. address read by sending the device address with the R/W bit set high. The DS1856 acknowledges the device address and serially clocks out the data byte. Sequential Address Read Sequential reads are initiated by either a current address read or a random address read. After the master receives the first data byte, the master responds with an acknowledge. As long as the DS1856 receives this acknowledge after a byte is read, the master can clock out additional data words from the DS1856. After reaching address FFh, it resets to address 00h. The sequential read operation is terminated when the master initiates a STOP condition. The master does not respond with a zero. The following section provides a detailed description of the 2-wire theory of operation. 2-Wire Serial-Port Operation The 2-wire serial-port interface supports a bidirectional data transmission protocol with device addressing. A device that sends data on the bus is defined as a transmitter, and a device that receives data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1856 operates as a slave on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The following I/O terminals control the 2-wire serial port: SDA, SCL. Timing diagrams for the 2-wire serial port can be found in Figures 5 and 6. Timing information for the 2-wire serial port is provided in the AC Electrical Characteristics table for 2-wire serial communications. The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. Start data transfer: A change in the state of the data line from high to low while the clock is high defines a START condition. Read Operations After receiving a matching address byte with the R/W bit set high, the device goes into the read mode of operation. There are three read operations: current address read, random read, and sequential address read. Current Address Read The DS1856 has an internal address register that maintains the address used during the last read or write operation, incremented by one. This data is maintained as long as VCC is valid. If the most recent address was the last byte in memory, then the register resets to the first address. Once the device address is clocked in and acknowledged by the DS1856 with the R/W bit set to high, the current address data word is clocked out. The master does not respond with a zero, but does generate a STOP condition afterwards. Single Read A random read requires a dummy byte write sequence to load in the data byte address. Once the device and data address bytes are clocked in by the master and acknowledged by the DS1856, the master must generate another START condition. The master now initiates a current 28 ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Stop data transfer: A change in the state of the data line from low to high while the clock line is high defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line can be changed during the low period of the clock signal. There is one clock pulse per bit of data. Figures 5 and 6 detail how data transfer is accomplished on the 2-wire bus. Depending on the state of the R/W bit, two types of data transfer are possible. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. SDA MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 START CONDITION 2 6 7 8 9 ACK REPEATED IF MORE BYTES ARE TRANSFERRED 1 2 3-7 8 9 ACK STOP CONDITION OR REPEATED START CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER Figure 5. 2-Wire Data Transfer Protocol SDA tBUF tLOW tR tF tHD:STA tSP SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO Figure 6. 2-Wire AC Characteristics ____________________________________________________________________ 29 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 Within the bus specifications, a standard mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS1856 works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse, which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition. 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the command/control byte) to the slave. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge can be returned. The master device generates all serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. The DS1856 can operate in the following two modes: 1) Slave Receiver Mode: Serial data and clock are received through SDA and SCL, respectively. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after the slave (device) address and direction bit have been received. 2) Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1856, while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. 30 ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection Ordering Information (continued) PART DS1856B-050/T&R DS1856E-050+ DS1856E-050+T&R DS1856B-050+ DS1856B-050+T&R DS1856E-020* DS1856E-020/T&R* DS1856B-020* DS1856B-020/T&R* DS1856E-020+* DS1856E-020+T&R* DS1856B-020+* DS1856B-020+T&R* DS1856E-030* DS1856E-030/T&R* DS1856B-030* DS1856B-030/T&R* DS1856E-030+* RES0/RES1 RESISTANCE (k) 50/50 50/50 50/50 50/50 50/50 20/20 20/20 20/20 20/20 20/20 20/20 20/20 20/20 30/10 30/10 30/10 30/10 30/10 PIN-PACKAGE 16-Ball CSBGA 16 TSSOP 16 TSSOP 16-Ball CSBGA 16-Ball CSBGA 16 TSSOP 16 TSSOP 16-Ball CSBGA 16-Ball CSBGA 16 TSSOP 16 TSSOP 16-Ball CSBGA 16-Ball CSBGA 16 TSSOP 16 TSSOP 16-Ball CSBGA 16-Ball CSBGA 16 TSSOP PART DS1856E-030+T&R* DS1856B-030+* DS1856B-030+T&R* DS1856E-002 DS1856E-002/T&R DS1856B-002 DS1856B-002/T&R DS1856E-002+ DS1856E-002+T&R DS1856B-002+ DS1856B-002+T&R DS1856E-025 DS1856E-025/T&R DS1856B-025 DS1856B-025/T&R DS1856E-025+ DS1856E-025+T&R DS1856B-025+ DS1856B-025+T&R RES0/RES1 RESISTANCE (k) 30/10 30/10 30/10 10/2.5 10/2.5 10/2.5 10/2.5 10/2.5 10/2.5 10/2.5 10/2.5 2.5/2.5 2.5/2.5 2.5/2.5 2.5/2.5 2.5/2.5 2.5/2.5 2.5/2.5 2.5/2.5 PIN-PACKAGE 16 TSSOP 16-Ball CSBGA 16-Ball CSBGA 16 TSSOP 16 TSSOP 16-Ball CSBGA 16-Ball CSBGA 16 TSSOP 16 TSSOP 16-Ball CSBGA 16-Ball CSBGA 16 TSSOP 16 TSSOP 16-Ball CSBGA 16-Ball CSBGA 16 TSSOP 16 TSSOP 16-Ball CSBGA 16-Ball CSBGA DS1856 Chip Information TRANSISTOR COUNT: 51,061 SUBSTRATE CONNECTED TO GROUND +Denotes lead free. *Future product--contact factory for availability. T&R denotes tape-and-reel. All parts operate at the -40C to +95C temperature range. Package Information For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. DALLAS is a registered trademark of Dallas Semiconductor Corporation. |
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