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| INTEGRATED CIRCUITS GTL2002 Dual open drain voltage translator Product specification 2000 Aug 16 Philips Semiconductors Philips Semiconductors Product specification Dual open drain voltage translator GTL2002 FEATURES * Direct interface with TTL level * 6.5 ON-state connection between port Sn and Dn DESCRIPTION The GTL2002 is a high speed dual voltage translator. The low ON-state resistance of the clamp allows connections to be made with minimal propagation delay. The device is organized as one 2-bit voltage clamp. When S or D is low, the clamp is in the ON-state and a low resistance connection exists between the S and D ports. When S port and D port are high, the clamp is in the OFF-state and a very high impedance exists between the S and D ports. When port D is high, the voltage on the S port is clamped to the applied reference voltage on the GREF port. PIN CONFIGURATION GND 1 SREF 2 S1 3 S2 4 8 7 6 5 GREF DREF D1 D2 SA00539 FUNCTION TABLE GREF H H H H L DREF H H H H L SREF4 0V VTT VTT VTT 0 - VTT Switch off nearly off nearly off on off Driven Input5 >0V H VTT L X Output of Driven Input H2 VTT1 H2 L2,3 H2 H = High voltage level L = Low voltage level X = Don't Care VTT = Termination voltage, typically 1.5 V NOTES: 1. The output is not pulled up or pulled down. 2. The output is pulled up to VCC through an external resistor. 3. The output of driven input follows the input low. 4. GREF must be at least 1.5 V higher than SREF for proper switch operation. 5. Either Sn or Dn can be chosen as the input; the corresponding Dn or Sn will be the output. QUICK REFERENCE DATA SYMBOL tPLH COFF PARAMETER Propagation delay Sn to Dn Channel capacitance (OFF-state) CONDITIONS Tamb = 25C; GND = 0V VDD1 = 3.3 V; VDD2 = 2.5 V; VREF = 1.5 V; unloaded VS = 1.5 V TYPICAL 1.5 7.5 UNIT ns pF ORDERING INFORMATION PACKAGES 8-Pin Plastic SO 8-Pin Plastic TSSOP TEMPERATURE RANGE 0C to +85C 0C to +85C ORDER CODE GTL2002D GTL2002DP DWG NUMBER SOT96-1 SOT505-1 2000 Aug 16 2 853-2214 24367 Philips Semiconductors Product specification Dual open drain voltage translator GTL2002 PIN DESCRIPTION PIN NUMBER 1 2 3, 4 5, 6 7 8 SYMBOL GND SREF Sn Dn DREF GREF NAME AND FUNCTION Ground (0V) Source of reference transistor Port S1 to Port S2 Port D1 to Port D2 Drain of reference transistor Gate of reference transistor CLAMP SCHEMATIC DREF GREF D1 D2 SREF S1 S2 SA00540 ABSOLUTE MAXIMUM RATINGS1, 2, 3 SYMBOL VS_REF VD_REF VG_REF VSn VDn IREFK ISK IDK IMAX Tstg PARAMETER DC source reference voltage DC drain reference voltage DC gate reference voltage DC voltage Port Sn DC voltage Port Dn DC reference diode current DC diode current Port Sn DC diode current Port Dn DC clamp current per channel Storage temperature range VI < 0 VI < 0 VI < 0 Channel in ON-state CONDITIONS RATING -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50 -50 35 -65 to +150 UNIT V V V V V mA mA mA mA C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VS_REF VD_REF VG_REF VSn VSn VDn VDn IS II Tamb PARAMETER DC source reference voltage DC drain reference voltage DC gate reference voltage DC voltage Port Sn (OFF-state) DC voltage Port Sn (ON-state) DC voltage Port Dn (OFF-state) DC voltage Port Dn (ON-state) Switch input leakage current (OFF-state) for Sn and Dn I/O GREF input leakage current Operating ambient temperature range VS, VD = 5 V VG = 5 V In free air 0 CONDITIONS LIMITS Min 1.0 VS_REF + 0.6 VS_REF + 0.6 VS_REF 0 VS_REF 0 Max 4.4 5 5 5 0.2 5 0.4 15 2.5 +85 UNIT V V V V V V V A A C 2000 Aug 16 3 Philips Semiconductors Product specification Dual open drain voltage translator GTL2002 DC CHARACTERISTICS for VDD1 = 3.0 to 3.6 V; VDD2 = 2.36 to 2.64 V; VREF = 1.365 to 1.635 V range Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). Refer to the Test Circuit diagram. LIMITS SYMBOL VOL PARAMETER LOW level output voltage TEST CONDITIONS VS = 0.175 V; ICLAMP = 15.2 mA Tamb = 0C to +85C Min NOTE: 1. All typical values are measured at VDD1 = 3.3 V, VDD2 = 2.5 V, VREF = 1.5 V and Tamb = 25C. Typ1 260 Max 350 mV UNIT AC CHARACTERISTICS for VDD1 = 3.0 to 3.6 V; VDD2 = 2.36 to 2.64 V; VREF = 1.365 to 1.635 V range GND = 0 V; tr = tf 3.0 ns. Refer to the Test Circuit diagram. SYMBOL PARAMETER Propagation delay Sn to Dn; Dn to Sn LIMITS WAVEFORM MIN tPLH2 0.5 Tamb = 0 to +85C TYP1 1.5 MAX 5.5 ns UNIT NOTES: 1. All typical values are measured at VDD1 = 3.3 V, VDD2 = 2.5 V, VREF = 1.5 V and Tamb = 25C. 2. Propagation delay guaranteed by characterization. 3. CON,MAX of 30 pF and a COFF,MAX of 15 pF is guaranteed by design. AC WAVEFORMS VI INPUT GND TEST CIRCUIT VDD1 200 K VDD2 150 VDD2 150 VDD2 150 VM tPHL VM tPLH DUT VDD2 OUTPUT HIGH-to-LOW LOW-to-HIGH VOL 0 0 VM tPHL tPHL 1 DREF VM tPLH tPLH 1 GREF D1 D2 VDD2 OUTPUT HIGH-to-LOW LOW-to-HIGH VOL VM SREF VM S1 S2 SA00524 VREF Waveform 1. The Input (Sn) to Output (Dn) Propagation Delays PULSE GENERATOR SA00541 Waveform 2. Load circuit 2000 Aug 16 4 Philips Semiconductors Product specification Dual open drain voltage translator GTL2002 SO8: plastic small outline package; 8 leads; body width 3.9mm SOT96-1 2000 Aug 16 5 Philips Semiconductors Product specification Dual open drain voltage translator GTL2002 TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 2000 Aug 16 6 Philips Semiconductors Product specification Dual open drain voltage translator GTL2002 NOTES 2000 Aug 16 7 Philips Semiconductors Product specification Dual open drain voltage translator GTL2002 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 08-00 Document order number: 9397 750 07417 Philips Semiconductors 2000 Aug 16 8 |
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