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Integrated Circuit Systems, Inc.
ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
FEATURES
* 6 differential 3.3V LVPECL outputs * Crystal oscillator interface * Output frequency range: 106.25MHz to 250MHz * Crystal input frequency: 25MHz and 25.5MHz * Output skew: 60ps (maximum) * RMS phase jitter at 212.5MHz, using a 25.5MHz crystal (637KHz to 10MHz): 2.76ps * Phase noise: Typical at 212.5MHz Offset Noise Power 100Hz ................. -92 dBc/Hz 1KHz ................. -112 dBc/Hz 10KHz ................. -120 dBc/Hz 100KHz ................. -122 dBc/Hz * 3.3V supply voltage * 0C to 70C ambient operating temperature * Lead-Free package available.
GENERAL DESCRIPTION
The ICS84325 is a Crystal-to-3.3V LVPECL Frequency Synthesizer with Fanout Buffer and a HiPerClockSTM member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The output frequency can be programmed using frequency select pins. The low phase noise characteristics of the ICS84325 make it an ideal clock source for Fibre Channel 1, Fibre Channel 2, Infiniband and Gigabit Ethernet applications.
ICS
FUNCTION TABLE
Inputs MR 1 0 0 0 0 F_SEL1 X 0 0 1 1 F_SEL0 X 0 1 0 1 25.5MHz 25.5MHz 25MHz 25MHz XTAL Output Frequency F_OUT LOW 106.25MHz 212.5MHz 125MHz 250MHz
* Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCCO F_SEL0 F_SEL1 MR XTAL1 XTAL2 VEE VCCA VCC PLL_SEL VEE VCCO
XTAL1
OSC
XTAL2
0 1
6 Output Divider 6
PLL
/ /
Q0:Q5 nQ0:nQ5
Feedback Divider
ICS84325
24-Lead, 300-MIL SOIC 7.5mm x 15.33mm x 2.3mm body package M Package Top View
F_SEL1 MR PLL_SEL F_SEL0
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Integrated Circuit Systems, Inc.
ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
Type Output Output Output Output Output Output Power Power Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Output supply pins. Core supply pin. Negative supply pins. Input Power Input Input Input Input Pullup Selects between the PLL and cr ystal inputs as the input to the dividers. When HIGH, selects PLL. When LOW, selects XTAL1, XTAL2. LVCMOS / LVTTL interface levels. Analog supply pin. Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs Pulldown nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Pulldown Feedback frequency select pin. LVCMOS / LVTTL interface levels. Pullup Output select pin. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 8 9, 10 11, 12 13, 24 16 14, 18 15 17 19, 20 21 22 23 Name Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3 Q4, nQ4 Q5, nQ5 VCCO VCC VEE PLL_SEL VCCA XTAL2, XTAL1 MR F_SEL1 F_SEL0
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
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ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 50C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA I EE ICCA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 210 27 Units V V mA mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current PLL_SEL, MR, F_SEL0, F_SEL1 PLL_SEL, MR, F_SEL0, F_SEL1 MR, F_SEL1 PLL_SEL, F_SEL0 MR, F_SEL1 PLL_SEL, F_SEL0 Test Conditions Minimum 2 -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A A
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.8 VCCO - 1.7 1.2 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
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ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
Test Conditions Minimum 25 Typical Maximum 25.5 50 7 Units MHz pF
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Fundamental
TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter FOUT Output Frequency Output Skew; NOTE 1, 2 Output Rise/Fall Time 20% to 80% fOUT = 106.25MHz odc Output Duty Cycle fOUT = 125MHz fOUT = 212.5MHz fOUT = 250MHz 300 48 46 43 40 Test Conditions Minimum 106.25 Typical Maximum 250 60 800 52 54 57 60 1 Units MHz ps ps % % % % ms
tsk(o)
tR / tF
tLOCK PLL Lock Time See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VCCO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
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ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TYPICAL PHASE NOISE
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k
Fibre Channel 1
Bandpass Filter
Jitter BW Source Mode Jitter Filter Process Result Noise only 106.250M Hz Stop Freq. 40.000M Hz Jitter 2.62 ps Diff. Jitter
PHASE NOISE
Freq. carrier Start Freq. 10.000
(dBc) HZ
OFFSET FREQUENCY (HZ)
0 -10 -20 -30 -40 -50 -60 -70
PHASE NOISE
()
dBc HZ
-80 -90 -100
-130 -140 -150 -160 -170 -180 -190 100 1k 10k
OFFSET FREQUENCY (HZ)
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-110 -120
Raw phase noise data
Raw phase noise data
Phase noise result by adding Bandpass Filter to raw data
100k
1M
10M
100M
Fibre Channel 2
Bandpass Filter
Jitter BW Source Mode Jitter Filter Process Result Noise only 212.500M Hz Stop Freq. 40.000M Hz Jitter 2.76 ps Diff. Jitter
Freq. carrier Start Freq. 10.000
Phase noise result by adding Bandpass Filter to raw data
100k
1M
10M
100M
REV. B OCTOBER 11, 2004
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ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC, VCCA
Qx
SCOPE
nQx
Qx
LVPECL
VEE
nQx
nQy
Qy
tsk(o)
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
nQ0:nQ5
Q0:Q5
Pulse Width t
PERIOD
80% 20%
tR
80% 20% tF
Clock Outputs
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
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ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84325 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 24 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F V CCA .01F 10 F 24
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50 FOUT FIN
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
Zo = 50 84 84
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
CRYSTAL INPUT INTERFACE
The ICS84325 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using a 25MHz, 18pF parallel resonant crystal and
XTAL2
C1 22p
X1 18pF Parallel Cry stal
XTAL1
C2 22p
Figure 4. CRYSTAL INPUt INTERFACE
SCHEMATIC EXAMPLE
Figure 5A shows a schematic example of using an ICS84325. In this example, the input is a 25MHz parallel resonant crystal with load capacitor CL=18pF. The frequency fine tuning capacitors C1 and C2 are 22pF respectively. This example also shows logic control input handling. The configuration is set at F_SEL[1:0]=11
VCC
therefore the output frequency is 250MHz. It is recommended to have one decouple capacitor per power pin. Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R7, C11 and C16 for clean analog supply should also be located as close to the VCCA pin as possible.
VCC
R7 24
R4 1K
VCC
U7
Zo = 50
13 14 15 16 17 18 19 20 21 22 23 24
VCC VEE PLL_SEL VCC VCCA VEE XTAL2 XTAL1 MR F_SEL1 F_SEL0 VCC nQ5 Q5 nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 nQ0 Q0
VCCA 22p
C11 0.1u
C16 10u
C1
X1 25MHz,18pF
F_SEL1 R5 F_SEL0 1K
12 11 10 9 8 7 6 5 4 3 2 1
-
Zo = 50
+
R2 50
R1 50
C2
R3 50
VCC
22p
ICS84325
RU2 1K
RU3 1K
F_SEL1 F_SEL0
VCC=3.3V
(U1,13)
VCC
(U1,16)
(U1,24)
RD2 SP
RD3 SP
e.g. F_SEL[1:0]=11
C6 0.1u
C5 0.1u
C3 0.1u
SP = Spare, Not Installed
FIGURE 5A. ICS84325 SCHEMATIC EXAMPLE
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The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
* The differential 100 output traces should have the same length. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. * Make sure no other signal traces are routed between the clock trace pair. * The matching termination resistors should be located as close to the receiver input pins as possible.
POWER
AND
GROUNDING
Place the decoupling capacitors C3, C5 and C6, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible.
CLOCK TRACES
AND
TERMINATION
Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins 20 (XTAL1) and 19 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.
C6
GND
VCC
C1
C5
R7
Signals
VCCA
C16
C11
VIA
X1
C2
C3
U1
ICS84325
Pin1
FOR
50 Ohm Traces
FIGURE 5B. PCB BOARD LAYOUT
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ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84325. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS84325 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 210mA = 727.7mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30.2mW = 181mW
Total Power_MAX (3.465V, with all outputs switching) = 727.7mW + 181mW = 908.7mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.909W * 43C/W = 113.9C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
24-PIN SOIC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 50C/W
200
43C/W
500
38C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 1V)/50) * 1V = 20.0mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50) * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
24 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 50C/W
200
43C/W
500
38C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84325 is: 3500
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CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
24 LEAD SOIC
PACKAGE OUTLINE - M SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 15.20 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 24 2.65 -2.55 0.51 0.32 15.85 7.60 Maximum
Reference Document: JEDEC Publication 95, MS-013, MO-119
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CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
Marking ICS84325EM ICS84325EM ICS84325EMLN ICS84325EMLN Package 24 Lead SOIC 24 Lead SOIC on Tape and Reel 24 Lead "Lead-Free" SOIC 24 Lead "Lead-Free" SOIC on Tape and Reel Count 30 per tube 1000 30 per tube 1000 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS84325EM ICS84325EMT ICS84325EMLN ICS84325EMLNT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84325EM
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ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
REVISION HISTORY SHEET Description of Change LVPECL DC Characteristics Table Changed VOH max. from VCCO - 1.0V to VCCO - 0.8V. Changed VSWING max. from 1.0V to 1.2V. Corrected Units. Ordering Information Table - added Lead-Free par t number. Date 10/1/03 10/11/04
Rev B
Table T3
Page 3
T9
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