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Integrated Circuit Systems, Inc.
ICS87008I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
FEATURES
* 8 LVCMOS/LVTTL outputs (2 banks of 4 outputs) * Selectable differential CLK1, nCLK1 or LVCMOS clock input * CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * CLK0 supports the following input types: LVCMOS, LVTTL * Maximum output frequency: 250MHz * Independent bank control for /1 or /2 operation * Glitchless, asynchronous clock enable/disable * Output skew: 105ps (maximum) @ 3.3V core/3.3V output * Bank skew: 70ps (maximum) @ 3.3V core/3.3V output * 3.3V or 2.5V core/3.3V, 2.5V, or 1.8V output operating supply * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS87008I is a low skew, 1:8 LVCMOS/LVTTL Clock Generator and is a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions. The device has 2 banks of 4 outputs and each bank can be independently selected for /1 or /2 frequency operation. Each bank also has its own power supply pins so that the banks can operate at the following different voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines.
ICS
The divide select inputs, DIV_SELA and DIV_SELB, control the output frequency of each bank. The output banks can be independently selected for /1 or /2 operation. The bank enable inputs, CLK_ENA and CLK_ENB, support enabling and disabling each bank of outputs individually. The CLK_ENA and CLK_ENB circuitry has a synchronizer to prevent runt pulses when enabling or disabling the clock outputs. The master reset input, nMR/OE, resets the /1//2 flip flops and also controls the active and high impedance states of all outputs. This pin has an internal pull-up resistor and is normally used only for test purposes or in systems which use low power modes. The ICS87008I is characterized to operate with the core at 3.3V or 2.5V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank, output, and part-to-part skew characteristics make the 87008I ideal for those clock applications demanding well-defined performance and repeatability.
BLOCK DIAGRAM
nMR/OE DIV_SELA CLK1 nCLK1 CLK0 CLK_ENA
1 0
/1 /2
PIN ASSIGNMENT
CLK1 nCLK1 VDDOA QA0 QA1 GND QA2 QA3 VDDOA DIV_SELA CLK_ENA VDD 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLK0 CLK_SEL VDDOB QB0 QB1 GND QB2 QB3 VDDOB DIV_SELB CLK_ENB nMR/OE
1
4
0
LE
QA0:QA3
D
CLK_SEL
1 4 0
LE
QB0:QB3
ICS87008I
24-Lead TSSOP 4.4mm x 7.8mm x 0.92mm body package G Package Top View
REV. A SEPTEMBER 10, 2004
CLK_ENB
D
DIV_SELB
87008AGI
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Integrated Circuit Systems, Inc.
ICS87008I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Type Input Input Power Output Power Input Input Power Input Input Input Power Output Input Input Pulldown Pullup Pullup Pullup Pullup Pullup Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 9 4, 5, 7, 8 6, 19 10 11 12 13 14 15 16, 22 17, 18, 20, 21 23 24 Name CLK1 nCLK1 VDDOA QA0, QA1, QA2, QA3 GND DIV_SELA CLK_ENA VDD nMR/OE CLK_ENB DIV_SELB VDDOB QB3, QB2, QB1, QB0 CLK_SEL CLK0 Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Output Bank A supply pins. Bank A outputs. LVCMOS / LVTTL interface levels. Supply ground. Controls frequency division for Bank A outputs. LVCMOS / LVTTL interface levels. Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Core supply pin. Master reset. When LOW, resets the /1//2 flip flops and sets the outputs to high impedance. LVCMOS / LVTTL interface levels. Output enable for Bank B outputs. Active HIGH. If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Controls frequency division for Bank B outputs LVCMOS / LVTTL interface levels.. Output Bank B supply pins. Bank C outputs. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. Pulldown LVCMOS / LVTTL clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor VDD, VDDOx = 3.465V; NOTE 1 C PD Power Dissipation Capacitance (per output) VDD, VDDOx = 2.625V; NOTE 1 VDD = 3.465, VDDOx = 2.625V; NOTE 1 VDD = 3.465, VDDOx = 1.89V; NOTE 1 VDD = 2.625, VDDOx = 1.89V; NOTE 1 ROUT Output Impedance 7 NOTE 1: VDDOx denotes VDDOA and VDDOB. Test Conditions Minimum Typical 4 51 51 18 20 20 30 20 Maximum Units pF K K pF pF pF pF pF
TABLE 3. FUNCTION TABLE
nMR/OE 0 1 1 1
87008AGI
Inputs CLK_ENx X 1 1 0
DIV_SELx X 0 1 X
Bank X Hi Z Active Active Low
Outputs Qx Frequency N/A fIN/2 fIN N/A
REV. A SEPTEMBER 10, 2004
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Integrated Circuit Systems, Inc.
ICS87008I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 70C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum 3.135 2.375 3.135 VDDOx IDD IDDOx Output Supply Voltage; NOTE 1 Power Supply Current Output Supply Current; NOTE 2 2.375 1.71 Typical 3.3 2.5 3.3 2.5 1.8 Maximum 3.465 2.625 3.465 2.625 1.89 54 6.5 Units V V V V V mA mA
NOTE 1: VDDOx denotes VDDOA and VDDOB. NOTE 2: IDDOx denotes IDDOA and IDDOB.
87008AGI
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Integrated Circuit Systems, Inc.
ICS87008I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Test Conditions Minimum Typical 2 2 -0.3 -0.3 VDD = VIN = 3.465V, VDD = VIN = 2.625V VDD = VIN = 3.465V, VDD = VIN = 2.625V VDD = 3.465V, VIN = 0V VDD = 2.625V, VIN = 0V VDD = 3.465V, VIN = 0V VDD = 2.625V, VIN = 0V VDDOx = 3.3V 5%; NOTE 2 VDDOx = 2.5V 5%; NOTE 2 VDDOx = 1.8V 5%; NOTE 2 VDDOx = 3.3V 5%; NOTE 2 -150 -5 2.6 1.8 1.5 0.5 0.5 0.4 -5 Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 5 150 Units V V V V A A A A V V V V V V A
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol Parameter VIH Input High Voltage DIV_SELA, DIV_SELB, CLK_ENA, CLK_ENB, nMR/OE, CLK_SEL CLK0 DIV_SELA, DIV_SELB, CLK_ENA, CLK_ENB, nMR/OE, CLK_SEL CLK0 DIV_SELA, DIV_SELB, CLK_ENA, CLK_ENB, nMR/OE CLK0, CLK_SEL DIV_SELA, DIV_SELB, CLK_ENA, CLK_ENB, nMR/OE CLK0, CLK_SEL
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
VOH
Output High Voltage; NOTE 1
VOL IOZL
Output Low Voltage; NOTE 1 Output Tristate Current Low
VDDOx = 2.5V 5%; NOTE 2 VDDOx = 1.8V 5%; NOTE 2
Output Tristate Current High 5 A IOZH NOTE 1: Outputs terminated with 50 to VDDOX/2. See Parameter Measurement Information, Output Load Test Circuits. NOTE 2: VDDOx denotes VDDOA, and VDDOB.
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDD = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol Parameter nCLK1 IIH Input High Current CLK1 nCLK1 IIL Input Low Current CLK1 VPP Test Conditions VIN = VDD = 3.465V, VIN = VDD = 2.625V VIN = VDD = 3.465V, VIN = VDD = 2.625V VIN = 0V, VDD = 3.465V, VIN = 0V, VDD = 2.625V VIN = 0V, VDD = 3.465V, VIN = 0V, VDD = 2.625V -150 -5 1.3 VDD - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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REV. A SEPTEMBER 10, 2004
Integrated Circuit Systems, Inc.
ICS87008I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Test Conditions Minimum 1.9 3.0 Typical 3.5 3.7 Maximum 250 5.1 4.5 70 105 650 20% to 80% f 133MHz 300 45 1100 55 10 Units MHz ns ns ps ps ps ps % ns ns
TABLE 5A. AC CHARACTERISTICS, VDD = VDDOX = 3.3V5%, TA = -40C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay, Low to High CLK0; NOTE 1A CLK1, nCLK1; NOTE 1B Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 5
t sk(b) t sk(o) t sk(pp)
tR / tF odc t EN
Output Disable Time; NOTE 5 10 tDIS All parameters measured at 250MHz using CLK1, nCLK1 unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDOX = 2.5V5%, TA = -40C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay, Low to High CLK0; NOTE 1A CLK1, nCLK1; NOTE 1B Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 5 20% to 80% f 125MHz 300 45 2.0 3 3.8 4 Test Conditions Minimum Typical Maximum 250 5.5 5 35 130 1 1000 55 10 Units MHz ns ns ps ps ns ps % ns ns
t sk(b) t sk(o) t sk(pp)
tR / tF odc t EN
Output Disable Time; NOTE 5 10 tDIS All parameters measured at 250MHz using CLK1, nCLK1 unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
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Integrated Circuit Systems, Inc.
ICS87008I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Test Conditions Minimum 2.25 3.1 Typical 3.6 3.8 Maximum 250 5.0 4.4 60 130 900 20% to 80% f 133MHz 290 45 950 55 10 Units MHz ns ns ps ps ps ps % ns ns
TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V5%, VDDOX = 2.5V5%, TA = -40C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay, Low to High CLK0; NOTE 1A CLK1, nCLK1; NOTE 1B Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 5
t sk(b) t sk(o) t sk(pp)
tR / tF odc tEN
Output Disable Time; NOTE 5 10 tDIS All parameters measured at 250MHz using CLK1, nCLK1 unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5D. AC CHARACTERISTICS, VDD = 3.3V5%, VDDOX = 1.8V5%, TA = -40C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay, Low to High CLK0; NOTE 1A CLK1, nCLK1; NOTE 1B Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 5 20% to 80% f 133MHz 280 45 3.0 3.3 4.5 4.1 Test Conditions Minimum Typical Maximum 250 4.9 5.0 55 150 1.1 850 55 10 Units MHz ns ns ps ps ns ps % ns ns
t sk(b) t sk(o) t sk(pp)
tR / tF odc t EN
Output Disable Time; NOTE 5 10 tDIS All parameters measured at 250MHz using CLK1, nCLK1 unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
87008AGI
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REV. A SEPTEMBER 10, 2004
Integrated Circuit Systems, Inc.
ICS87008I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Test Conditions Minimum 2.6 3.3 Typical 4.1 4.4 Maximum 250 5.6 5.4 45 150 1.2 20% to 80% f 100MHz 325 45 900 55 10 Units MHz ns ns ps ps ns ps % ns ns
TABLE 5E. AC CHARACTERISTICS, VDD = 2.5V5%, VDDOX = 1.8V5%, TA = -40C TO 85C
Symbol Parameter fMAX tpLH Output Frequency CLK0; NOTE 1A Propagation Delay, CLK1, nCLK1; Low to High NOTE 1B Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 5
t sk(b) t sk(o) t sk(pp)
tR / tF odc tEN
Output Disable Time; NOTE 5 10 tDIS All parameters measured at 250MHz using CLK1, nCLK1 unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
87008AGI
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Integrated Circuit Systems, Inc.
ICS87008I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V5% 1.25V5%
VDD, VDDOx
SCOPE
Qx
VDD, VDDOx
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.4V5% +0.9V5%
2.05V5%
1.25V5%
VDD VDDOx
SCOPE
Qx
V DD VDDOx
SCOPE
Qx
LVCMOS
LVCMOS
GND
GND
-1.25V5%
-0.9V5%
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.6V5% +0.9V5%
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
VDD
V DD VDDOx
SCOPE
Qx
nCLK1
V
CLK1
LVCMOS
PP
Cross Points
V
CMR
GND
GND
-0.9V5%
2.5V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
87008AGI
DIFFERENTIAL INPUT LEVEL
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Integrated Circuit Systems, Inc.
ICS87008I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
PART 1 Qx
V
DDOX
V
DDOX
2
Qx
2
PART 2 Qy
V
DDOX
V
DDOX
2 tsk(pp)
Qy
2 tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
CLK0
VDD 2
nCLK1 QX0:QX0 VDDOX 2 CLK1
QX0:QX0
VDDOX 2
BANK SKEW (where X denotes outputs in the same bank)
PROPAGATION DELAY
80% 20%
tR
80%
QAx, QBx, QCx, QDx
Clock Outputs
20% tF
OUTPUT RISE/FALL TIME
87008AGI
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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tsk(b)
QAx,QBx, QCx, QDx
VDDOX 2 tPD
V
DDOX
2 Pulse Width t
PERIOD
odc =
t PW t PERIOD
Integrated Circuit Systems, Inc.
ICS87008I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD VCC R1 1K CLK + V_REF V_REF C1 C1 0.1u 0.1uF R2 1K nCLK
Single Ended Clock Input CLK_IN
R1 1K
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
87008AGI
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REV. A SEPTEMBER 10, 2004
Integrated Circuit Systems, Inc.
ICS87008I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 2A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 2B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
Zo = 50 Ohm
LVDS_Driv er
CLK
R1 100
nCLK
Receiv er
Zo = 50 Ohm
FIGURE 2C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 2D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
87008AGI
BY
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Integrated Circuit Systems, Inc.
ICS87008I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 70C/W 200 63C/W 500 60C/W
Multi-Layer PCB, JEDEC Standard Test Boards
TRANSISTOR COUNT
The transistor count for ICS87008I is: 1262
87008AGI
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REV. A SEPTEMBER 10, 2004
Integrated Circuit Systems, Inc.
ICS87008I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
FOR
PACKAGE OUTLINE - G SUFFIX
24 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MS-153
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Integrated Circuit Systems, Inc.
ICS87008I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS87008AGI ICS87008AGIT Marking ICS87008AGI ICS87008AGI Package 24 Lead TSSOP 24 Lead TSSOP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87008AGI
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REV. A SEPTEMBER 10, 2004
Integrated Circuit Systems, Inc.
ICS87008I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
REVISION HISTORY SHEET
Rev A
Table T8
Page 14
Description of Change Ordering Information Table - added "T" (for tape and reel) Par t/Order Number.
Date 9/10/04
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