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| M68HC08M68H C08M68HC08M 68HC08M68HC MC68HC05PV8/D REV 1.9 MC68HC05PV8 MC68HC805PV8 MC68HC05PV8A Technical Data HCMOS Microcontroller Unit Technical Data -- Rev 1.9 Motorola and are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. (c) Motorola, Inc., 2001 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data 3 NONDISCLOSURE Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. AGREEMENT MC68HC05PV8 MC68HC805PV8 MC68HC05PV8A REQUIRED Technical Data NONDISCLOSURE Technical Data 4 AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data -- MC68HC(8)05PV8/A Revision History Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes from Rev 1.5 published on September 9th, 1999 to Rev 1.6 published on May 4th, 2000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes from Rev 1.6 published on May 4th, 2000 to Rev 1.7 published on December 1st, 2000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes from Rev 1.7 published on December 1st, 2000 to Rev 1.8 published on February 20th, 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes from Rev 1.8 published on February 20th, 2001 to Rev 1.9 published on September 3th, 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Introduction This section contains the revision history for the MC68HC(8)05PV8/A data book. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Revision History Technical Data 5 NONDISCLOSURE AGREEMENT REQUIRED Technical Data Changes from Rev 1.5 published on September 9th, 1999 to Rev 1.6 published on May 4th, 2000 Section Page (in Rev 1.6) Description of change added PV8A functionality, initial release REQUIRED AGREEMENT Changes from Rev 1.6 published on May 4th, 2000 to Rev 1.7 published on December 1st, 2000 Section 2 Page (in Rev 1.7) 33 added note 3 Description of change Changes from Rev 1.7 published on December 1st, 2000 to Rev 1.8 published on February 20th, 2001 Section 16.15.1 16.15.1 Page (in Rev 1.8) 185 185 Description of change removed PC4 input hysteresis for PV8A added PC4 input debounce time for PV8A NONDISCLOSURE Changes from Rev 1.8 published on February 20th, 2001 to Rev 1.9 published on September 3th, 2001 Section 1.5 1.7 16.5 16.5 16.12 Page (in Rev 1.9) 30 33 176 176 185 Description of change added mechanical specification added ordering information filled in typical value for ISUP12 added ISUP4A added rise time specification on VDD Technical Data 6 Revision History MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA List of Sections Technical Data -- MC68HC(8)05PV8/A List of Sections Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 CPU and Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . 43 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 16-Bit Programmable Timer . . . . . . . . . . . . . . . . . . . . . 123 Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . 137 Pulse Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . . 147 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA List of Sections Technical Data 7 NONDISCLOSURE AGREEMENT REQUIRED Technical Data EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Program EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Fast Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . 173 NONDISCLOSURE Technical Data 8 List of Sections AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Table of Contents Technical Data -- MC68HC(8)05PV8/A Table of Contents Section 1. General Description 1.1 1.2 1.3 1.4 1.5 1.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.8 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Section 2. Memory 2.1 2.2 2.3 2.4 2.5 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Table of Contents Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Technical Data 9 NONDISCLOSURE 1.7 Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.7.1 VSUP, VSS and PVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.2 VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.3 OSC1, OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.5 IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.7.6 PA0-PA7/VREFH, VREFL, AN1-6, IN, IIN, OUT . . . . . . . . 32 1.7.7 PB0-PB4/TCMP1, TCMP2, TCAP1, TCAP2, PWM . . . . . . 32 1.7.8 PTC0-PTC6/TCMP1, TCMP2, TCAP1, TCAP2, PWM. . . . 33 AGREEMENT REQUIRED Technical Data 2.6 2.7 Program EEPROM/ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 REQUIRED Section 3. CPU and Instruction Set 3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 AGREEMENT 3.2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.4 Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3 3.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Instruction Set Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 NONDISCLOSURE 3.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.5.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.5.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.5.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.6 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.6.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . 52 3.6.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . 53 3.6.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.6.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . 56 3.6.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Technical Data 10 Table of Contents MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Table of Contents 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.8 8-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.8.1 16-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.9 Ambient Exception Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.10 High Temperature Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.10.1 High Voltage Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.10.2 Low Voltage Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.10.3 Power Driver Short Circuit Interrupt . . . . . . . . . . . . . . . . . . 75 4.11 4.12 4.13 Keyboard Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Port C Contact Sense Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 75 STOP and WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Section 5. Resets 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Reset status register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . .78 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Computer Operating Properly Reset (COPR). . . . . . . . . . . . . . 82 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Table of Contents Technical Data 11 NONDISCLOSURE AGREEMENT REQUIRED Section 4. Interrupts Technical Data 5.7.1 5.7.2 5.7.3 5.7.4 5.7.5 5.8 5.9 5.10 5.11 Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 COP During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 COP During STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 83 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . 83 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Disabled STOP Instruction Reset . . . . . . . . . . . . . . . . . . . . . . .84 High Temperature Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 High Voltage Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Operation in STOP and WAIT Mode . . . . . . . . . . . . . . . . . . . .85 AGREEMENT REQUIRED 5.12 5.13 5.14 Clock Monitor Reset (CMR) . . . . . . . . . . . . . . . . . . . . . . . . . . .85 5.14.1 Clock Monitor in STOP mode . . . . . . . . . . . . . . . . . . . . . . . 86 Section 6. Operating Modes 6.1 6.2 6.3 6.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 User mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 NONDISCLOSURE 6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 6.5.1 STOP Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 6.5.1.1 Ultra Low Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.5.2 STOP Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.6 WAIT Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Technical Data 12 Table of Contents MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Table of Contents 7.1 7.2 7.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 General Input/Output Programming . . . . . . . . . . . . . . . . . . . . . 94 7.5 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.5.1 Port B Timer Channels and XOR Function . . . . . . . . . . . . 100 7.5.2 Port B PWM Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.5.3 I/O Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . 101 7.6 Port C (High Voltage Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.6.1 Port C Timer Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.6.2 Port C PWM Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.6.3 Port C Contact Sense Circuitry . . . . . . . . . . . . . . . . . . . . . 103 7.6.4 Port C ISO9141 Interface . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.6.5 Port C Low Side Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.6.6 Port C Configuration Register 0 . . . . . . . . . . . . . . . . . . . . 109 7.6.7 Port C Configuration Register 1 . . . . . . . . . . . . . . . . . . . . 113 7.6.8 Port C Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.6.9 MFTEST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Section 8. Core Timer 8.1 8.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.3.1 Core Timer Status & Control Register (CTSCR) . . . . . . . .119 8.3.2 Computer Operating Properly (COP) Watchdog Reset. . . 121 8.3.3 Core Timer Counter Register (CTCR). . . . . . . . . . . . . . . . 121 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Table of Contents Technical Data 13 NONDISCLOSURE AGREEMENT 7.4 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.4.1 Port A Keyboard Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.4.2 Port A Pull-up Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.4.3 Port A Voltage Reference for A/D Converter. . . . . . . . . . . . 96 7.4.4 Port A Configuration Register . . . . . . . . . . . . . . . . . . . . . . . 97 7.4.5 Port A Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . 98 7.4.6 Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 REQUIRED Section 7. Input/Output Ports Technical Data 8.4 8.5 Core Timer During WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Core Timer During STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 REQUIRED Section 9. 16-Bit Programmable Timer 9.1 9.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 AGREEMENT 9.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.3.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.3.2 Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . 127 9.3.2.1 Output Compare Register 1 . . . . . . . . . . . . . . . . . . . . . .127 9.3.2.2 Output Compare Register 2 . . . . . . . . . . . . . . . . . . . . . .128 9.3.3 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . .129 9.3.3.1 Input Capture Register 1 . . . . . . . . . . . . . . . . . . . . . . . . 129 9.3.3.2 Input Capture Register 2 . . . . . . . . . . . . . . . . . . . . . . . . 130 9.3.4 Timer Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.3.5 Timer Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.3.6 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.4 9.5 Timer During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Timer During STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 NONDISCLOSURE Section 10. Analog to Digital Converter 10.1 10.2 10.3 10.4 10.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 A/D Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 A/D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Internal and Master Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 139 10.6 A/D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.6.1 A/D Status and Control Register (ADSCR) . . . . . . . . . . . . 140 10.6.2 A/D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.7 10.8 Technical Data 14 Table of Contents A/D During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 A/D During STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Table of Contents 10.9 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.10 Conversion Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . 144 10.10.1 Transfer Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 10.10.2 Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.10.3 Quantization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.10.4 Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.10.5 Gain Scale Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.10.6 Differential Linearity Error . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.10.7 Integral Linearity Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.10.8 Total Unadjusted Error . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Section 11. Pulse Width Modulator 11.1 11.2 11.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.4.1 PWM Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.4.2 PWM Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 11.4.3 PWM Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.5 11.6 11.7 11.8 PWM During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 PWM During STOP Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 PWM During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Frame Frequency Examples. . . . . . . . . . . . . . . . . . . . . . . . . . 153 Section 12. Voltage Regulator 12.1 12.2 12.3 12.4 12.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Internal Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 5V Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Trimming the Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . 156 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Table of Contents Technical Data 15 NONDISCLOSURE AGREEMENT REQUIRED Technical Data Section 13. EEPROM 13.1 13.2 13.3 13.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 EEPROM Control Register (EEPCR) . . . . . . . . . . . . . . . . . . . 158 EEPROM Options Register (EEOPR) . . . . . . . . . . . . . . . . . . 159 REQUIRED AGREEMENT 13.5 EEPROM READ, ERASE and Programming Procedures . . . 160 13.5.1 READ Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.5.2 ERASE Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.5.3 Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.6 Operation in STOP and WAIT Modes. . . . . . . . . . . . . . . . . . . 161 Section 14. Program EEPROM 14.1 14.2 14.3 14.4 14.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 EEPROM Protection Mechanism . . . . . . . . . . . . . . . . . . . . . . 165 Options Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 NONDISCLOSURE Section 15. Fast Parallel Interface 15.1 15.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.3.1 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Section 16. Electrical Specifications 16.1 16.2 16.3 Technical Data 16 Table of Contents Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Table of Contents 16.4 16.5 16.6 16.7 16.8 Program and Data EEPROM Characteristics . . . . . . . . . . . . . 175 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 VDD Referenced Pins Electrical Characteristics . . . . . . . . . . . 178 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.9 Power Supply Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.9.1 VSUP related Reset and Interrupts . . . . . . . . . . . . . . . . . . 183 16.10 Down Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.11 Die Temperature Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.12 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 16.13 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 187 16.14 Fast Peripheral Interface Timing. . . . . . . . . . . . . . . . . . . . . . . 188 16.15 PORT C Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 16.15.1 High Voltage Input/Output (PC0-4). . . . . . . . . . . . . . . . . . 189 16.15.2 Contact Sense Circuitry to Vbattery (PC0-3) and to Ground (PC1-4 MC68HC(8)05PV8)/(PC1-3 MC68HC05PV8A) . . 189 16.15.3 ISO9141 Driver (PC4) MC68HC(8)05PV8 . . . . . . . . . . . .190 16.15.4 ISO9141 Driver (PC4) MC68HC05PV8A . . . . . . . . . . . . . 190 16.15.5 Low Side Driver (PC5/6, PVSS) . . . . . . . . . . . . . . . . . . . . 191 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Table of Contents Technical Data 17 NONDISCLOSURE AGREEMENT REQUIRED Technical Data NONDISCLOSURE Technical Data 18 Table of Contents AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA List of Figures Technical Data -- MC68HC(8)05PV8/A List of Figures Figure 1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 4-4 5-1 5-2 5-3 5-4 6-1 6-2 7-1 7-2 7-3 7-4 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA List of Figures Title Page Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . .69 System Control Register (SYSCTRL) . . . . . . . . . . . . . . . . . 71 Interrupt Control Register (INTCR). . . . . . . . . . . . . . . . . . . . 73 Interrupt Status Register (INTSR) . . . . . . . . . . . . . . . . . . . .73 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . 78 RESET and POR Timing Diagram . . . . . . . . . . . . . . . . . . . . 81 COP Watchdog Timer Location Register (COPR) . . . . . . . . 84 Interrupt Status Register (INTSR) . . . . . . . . . . . . . . . . . . . .86 Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 90 STOP and WAIT Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . 91 Port I/O Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Port A Configuration Register (PACFG). . . . . . . . . . . . . . . .97 Port A Interrupt Status Register (PAISR) . . . . . . . . . . . . . . . 98 Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Technical Data 19 NONDISCLOSURE AGREEMENT MC68HC(8)05PV8/A Block Diagram . . . . . . . . . . . . . . . . . . 28 MC68HC(8)05PV8/A Pin Assignments . . . . . . . . . . . . . . . . 29 28-pin SOIC mechanical dimensions . . . . . . . . . . . . . . . . . . 30 MC68HC(8)05PV8/A Memory Map . . . . . . . . . . . . . . . . . . . 36 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 I/O Registers $0000-$000F . . . . . . . . . . . . . . . . . . . . . . . . . 39 I/O Registers $0010-$001F . . . . . . . . . . . . . . . . . . . . . . . . . 40 I/O Registers $0020-$002F . . . . . . . . . . . . . . . . . . . . . . . . . 41 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 REQUIRED Technical Data 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 8-1 8-2 8-3 9-1 9-2 9-3 9-4 10-1 10-3 10-4 10-5 11-1 11-2 11-3 11-4 11-5 11-6 12-1 13-1 Technical Data 20 List of Figures AGREEMENT Typical application: positive Vgain amplifier. . . . . . . . . . . . . 99 Mapping Ports to Timer Capture Channels . . . . . . . . . . . .100 I/O Configuration Register (IOCFG) . . . . . . . . . . . . . . . . . . 101 PC0 Contact Sense Circuitry . . . . . . . . . . . . . . . . . . . . . . . 103 PC1-3 Contact Sense Circuitry . . . . . . . . . . . . . . . . . . . . . 104 PC4 Contact Sense Circuitry 68HC(8)05PV8 . . . . . . . . . . 104 PC4 Circuitry 68HC05PV8A. . . . . . . . . . . . . . . . . . . . . . . . 105 Principal Characteristic of the Contact Sense Circuitry . . . 106 Interrupt Status Register (INTSR) . . . . . . . . . . . . . . . . . . .107 Principle of Port C Low Side Driver . . . . . . . . . . . . . . . . . . 108 Short Circuit Diagnostic of Port C Low Side Driver . . . . . . 109 Port C Configuration Register 0 (PCCFG0) . . . . . . . . . . . . 109 Port C Special Signal Routing . . . . . . . . . . . . . . . . . . . . . . 112 Port C Configuration Register 1 (PCCFG1) . . . . . . . . . . . . 113 Port C Status Register (PCSTR) . . . . . . . . . . . . . . . . . . . . 114 MFTEST Register (MFTEST). . . . . . . . . . . . . . . . . . . . . . . 116 Core Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 118 Core Timer Status and Control Register (CTSCR) . . . . . . 119 Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . . 121 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Timer Control Register 1 (TCR1) . . . . . . . . . . . . . . . . . . . . 131 Timer Control Register 2 (TCR2) . . . . . . . . . . . . . . . . . . . . 132 Timer Status Register 1 (TSR) . . . . . . . . . . . . . . . . . . . . . .134 A/D Status and Control Register (ADSCR) . . . . . . . . . . . .140 A/D Data Register (ADDR). . . . . . . . . . . . . . . . . . . . . . . . . 142 Electrical Model of an A/D Input Pin. . . . . . . . . . . . . . . . . . 144 Transfer Curve of an Ideal 8-Bit A/D Converter . . . . . . . . . 145 PWM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 PWM Waveforms (POL = 0, active low), PWMPR = $FF. . 149 PWM Waveforms (POL = 1, active high), PWMPR = $CF.149 PWM Control Register (PWMCR) . . . . . . . . . . . . . . . . . . .150 PWM Data Register (PWMDAT) . . . . . . . . . . . . . . . . . . . . 151 PWM Period Register (PWMPR) . . . . . . . . . . . . . . . . . . . . 152 MFTEST Register (MFTEST). . . . . . . . . . . . . . . . . . . . . . . 156 EEPROM Control Register (EEPCR) . . . . . . . . . . . . . . . . . 158 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA NONDISCLOSURE REQUIRED List of Figures MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA List of Figures Technical Data 21 NONDISCLOSURE AGREEMENT REQUIRED 13-2 14-1 14-2 15-1 15-2 16-1 16-2 16-3 16-4 EEPROM Options Register (EEOPR) . . . . . . . . . . . . . . . . 159 Program EEPROM Control Register (PEECR) . . . . . . . . . 164 Options Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Basic Fast Peripheral Interface Timing . . . . . . . . . . . . . . . 170 System Control Register (SYSCR). . . . . . . . . . . . . . . . . . . 171 Low Voltage Reset waveform. . . . . . . . . . . . . . . . . . . . . . . 181 VSUP related Reset and Interrupts waveforms . . . . . . . . . 183 Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . 186 Timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Technical Data NONDISCLOSURE Technical Data 22 List of Figures AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA List of Tables Technical Data -- MC68HC(8)05PV8/A List of Tables Table 1-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 4-1 4-2 6-1 7-1 7-2 7-3 8-1 8-2 10-2 10-1 11-1 11-2 11-3 12-1 13-1 Title Page Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . . . 52 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . 53 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . 55 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 56 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . . 67 IRQ sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Operating Mode Entry Conditions . . . . . . . . . . . . . . . . . . . . . 87 I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 PWM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Timer Channel 1 Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 RTI Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Minimum COP Reset Times . . . . . . . . . . . . . . . . . . . . . . . . . 121 A/D Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 A/D Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .141 PWM Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 Frame Frequency for fOSC = 4.2MHz . . . . . . . . . . . . . . . . . 153 Frame Frequency for fOSC = 2MHz. . . . . . . . . . . . . . . . . . . 153 Trimming Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Erase Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA List of Tables Technical Data 23 NONDISCLOSURE AGREEMENT REQUIRED Technical Data NONDISCLOSURE Technical Data 24 List of Tables AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data -- MC68HC(8)05PV8/A Section 1. General Description 1.1 Contents 1.2 1.3 1.4 1.5 1.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.8 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA General Description Technical Data 25 NONDISCLOSURE 1.7 Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.7.1 VSUP, VSS and PVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.2 VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.3 OSC1, OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.5 IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.7.6 PA0-PA7/VREFH, VREFL, AN1-6, IN, IIN, OUT . . . . . . . . 32 1.7.7 PB0-PB4/TCMP1, TCMP2, TCAP1, TCAP2, PWM . . . . . . 32 1.7.8 PTC0-PTC6/TCMP1, TCMP2, TCAP1, TCAP2, PWM. . . . 33 AGREEMENT REQUIRED Technical Data 1.2 Introduction The MC68HC05PV8, MC68HC805PV8 and MC68HC05PV8A microcontrollers are members of Motorola's 68HC05 family, designed for low-cost and single-chip systems in automotive applications. They combine an HC05 core with a shell of high-voltage peripherals. Throughout this book, the term MC68HC(8)05PV8/A is used to refer to all three MCUs. The ROM (MC68HC05PV8) version of the MCU contains the HC05 CPU with integrated voltage regulator, RAM, ROM, EEPROM, core timer, COP watchdog, power-on reset, 16-bit programmable timer, PWM generator, standard parallel I/O, and special I/O for the automotive voltage range, including relay driver and contact monitors. Bootloader and test modes are supported. The package is 28-pin SOIC for the ROM and development version. In the flash-like development version (MC68HC805PV8), the ROM is replaced by a program EEPROM. Each MCU is fabricated in a low-cost double-layer poly, single-layer metal, 40V, 1.2m CMOS technology. AGREEMENT NONDISCLOSURE 1.3 Features REQUIRED Features of the MC68HC(8)05PV8/A include: * * * HC05 Core 28 Pin SOIC Package Program EEPROM or ROM - MC68HC805PV8: 7936 Bytes of Program EEPROM + 240 Bytes of Monitor ROM + 16 Bytes User Vectors - MC68HC05PV8: 7936 Bytes of ROM + 240 Bytes of Monitor ROM + 16 Bytes User Vectors * * 192 Bytes of RAM Including Stack 128 Bytes of Data EEPROM Technical Data 26 General Description MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA General Description Features * * * * * * * * * On-Chip Oscillator with External Resonator. Internal bus Frequency in Run and Wait Mode is fOSC/2. Multipurpose Core Timer, Real Time Interrupt (RTI), (Window) COP Watchdog Timer 16-Bit Timer With Two Input Captures and Two Output Compares 1 Channel High-Speed PWM With Adjustable Frame Frequency 8 bit 6 Channel A/D Converter Port A: 8 Channel 5V I/O, with Pull-Ups, Shared with A/D Converter Port B: 5 Channel 5V I/O Shared with Timer and PWM Port C: 7 channel 40V I/O - 5 Channel 10mA Contact Monitor, 1 for a Switch to Ground, 1 for a Switch to Battery and 3 of Universal Type. Contact Monitoring Requires a 1K External Resistor. Contact Monitor Pins May Alternatively be Configured as High-Voltage I/O Relative to VSUP. Pins are Shared with Timer and PWM. - 2 Channel 2 LS Relay Driver. The Pins are Shared with the PWM. * * * * * * * Break-Down Voltage of High-Voltage Pins is greater than 40V. High-Voltage Interrupt/Reset (HVI/HVR) and Low-Voltage Reset (LVR). -40C to 125C Junction Temperature. Operational Amplifier, Connected to PA4-6 Keyboard Wake-Up Interrupt on Port A and PC4-0 ISO9141 Compatible Transceiver on Port C4 Ultra Low Power Mode on 68HC05PV8A MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA General Description Technical Data 27 NONDISCLOSURE AGREEMENT REQUIRED On-Chip 5V (5%) Voltage Regulator including Power-On Reset, with 20mA supply for External Devices. VSUP Range is 6V to 16V. Limited operation above and below that range. Breakdown Voltage above 40V. Technical Data REQUIRED PROGRAM EEPROM/USER ROM -- 8K USER VECTORS --16 BYTES PA7/VREFH PA6/AN6/IN MONITOR ROM -- 240 BYTES DDR A PA5/AN5/IIN PA4/AN4/OUT PA3/AN3 PORT A PA2/AN2 PA1/AN1 PA0/VREFL EEPROM -- 128BYTES USER RAM -- 192BYTES AGREEMENT CPU CONTROL IRQ M68HC05 MCU RESET PORT B ARITHMETIC/LOGIC UNIT ACCUMULATOR IOCNF PB4/PWM PB3/TCMP2 PB2/TCAP2 PB1/TCMP1 PB0/TCAP1 INDEX REGISTER RESET STACK POINTER 0000000011 PROGRAM COUNTER PCFRC DDRB PVSS PC6/PWM PC5/PWM/TCMP1 PORT C PC4/PWM/TCMP1/ TCAP1 PC3/TCMP2 PC2/TCAP2 PC1/TCMP1 PC0/TCAP1/TCMP1/ PWM CONDITION CODE REGISTER 111HI CPU CLOCK OSC1 INTERNAL OSCILLATOR DIVIDE by 2 CORE TIMER, COP NCZ DDR C 16-BIT TIMER PWM VSS VSUP LOW VOLTAGE RESET ON-CHIP VOLTAGE REGULATOR 8-BIT A/D CONVERTER NONDISCLOSURE OSC2 VDD Figure 1-1 MC68HC(8)05PV8/A Block Diagram Technical Data 28 General Description MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA General Description Mask Options 1.4 Mask Options There are five mask options on the MC68HC(8)05PV8/A: * * * * * STOP Instruction (enable/disable) COP Watchdog Timer (enable/disable) Clock Monitor (enable/disable) High Temperature Reset (enable/disable) High Voltage Reset (enable/disable) 1.5 Pin Assignments Figure 1-2 shows the 28-pin SOIC pin assignments. PA0/VREFL PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4/OUT PA5/AN5/IIN PA6/AN6/IN PA7/VREFH VDD VSUP PC0/TCAP1/TCMP1/PWM PC1/TCMP1 PC2/TCAP2 PC3/TCMP2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 IRQ PB0/TCAP1 PB1/TCMP1 PB2/TCAP2 PB3/TCMP2 PB4/PWM RESET OSC2 OSC1 VSS PC6/PWM PVSS PC5/TCMP1/PWM PC4/TCMP1/PWM/TCAP1 Figure 1-2 MC68HC(8)05PV8/A Pin Assignments MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA General Description Technical Data 29 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 1.6 Mechanical Specifications REQUIRED -A- Case 751F-03 1 -B- P 14 PL 0.25 MBM AGREEMENT R x 45 G J C D 28 PL 0.25 M TBS AS -T- Seating Plane K M F Dim. A B C D F G Min. 17.80 7.40 2.35 0.35 0.41 Max. 18.05 7.60 2.65 0.49 0.90 1. 2. 3. 4. 5. Notes Dimensions `A' and `B' are datums and `T' is a datum surface. Dimensioning and tolerancing per ANSI Y14.5M, 1982. All dimensions in mm. Dimensions `A' and `B' do not include mould protrusion. Maximum mould protrusion is 0.15 mm per side. Dim. J K M P R -- Min. 0.229 0.127 0 10.05 0.25 -- Max. 0.317 0.292 8 10.55 0.75 -- NONDISCLOSURE 1.27 BSC Figure 1-3 28-pin SOIC mechanical dimensions Technical Data 30 General Description MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA General Description Functional Pin Descriptions 1.7 Functional Pin Descriptions The following paragraphs give a description of the general function for each pin. 1.7.1 VSUP, VSS and PVSS The microcontroller is operated from a single power supply. VSUP is connected to the positive supply, VSS to ground. The on-chip voltage regulator uses VSUP to derive the VDD supply for the MCU and external components. PVSS is a separate ground for the relay drivers. 1.7.2 VDD This pin is driven by the on-chip voltage regulator. It can be used to provide a regulated voltage to external devices. A capacitor must be attached to this pin in order to stabilize the regulator. 1.7.3 OSC1, OSC2 The OSC1 and OSC2 pins are the connections for the on-chip oscillator. A crystal connected across these pins or an external signal connected to OSC1 provides the oscillator clock. The frequency, fOSC, of the oscillator or external clock source is divided by two to produce the internal operating frequency, fOP. 1.7.4 RESET This pin can be used as an input to reset the MCU to a known start-up state by pulling it to the low state. The RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. The RESET pin has an internal pull-down device that pulls the RESET pin low when there is an internal COP watchdog reset, power-on reset (POR), illegal address reset, internal high voltage or an internal low voltage reset. Refer to Section 5. Resets. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA General Description Technical Data 31 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 1.7.5 IRQ The interrupt triggering sensitivity of this pin can be programmed as rising/falling edge sensitive or high/low level sensitive.The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. See Section 4. Interrupts for more details on the interrupts. REQUIRED 1.7.6 PA0-PA7/VREFH, VREFL, AN1-6, IN, IIN, OUT These eight I/O lines comprise port A. The state of any pin is software programmable and all port A lines are configured as inputs during power-on or reset. The eight I/O lines are shared with the A/D converter function (see Section 10. Analog to Digital Converter). The internal operational amplifier is connected to PA4/OUT (output), PA5/IIN (inverting input) and PA6/IN (input) (see 7.4.6 Operational Amplifier). See Section 7. Input/Output Ports for more details on the I/O ports. AGREEMENT 1.7.7 PB0-PB4/TCMP1, TCMP2, TCAP1, TCAP2, PWM These five I/O lines comprise port B. The state of any pin is software programmable and all port B lines are configured as inputs during power-on or reset. The port pins PB0-PB3 are shared with the 16-bit timer (TCAP1-2, TCMP1-2). See Section 9. 16-Bit Programmable Timer for more details on the operation of the 16-bit timer. Pin PB4 is shared with the PWM system (see Section 11. Pulse Width Modulator). See Section 7. Input/Output Ports for more details on the I/O ports. NONDISCLOSURE Technical Data 32 MC68HC(8)05PV8/A -- Rev. 1.9 General Description MOTOROLA General Description Ordering Information 1.7.8 PTC0-PTC6/TCMP1, TCMP2, TCAP1, TCAP2, PWM These seven high voltage I/O lines comprise port C. The state of any pin is software programmable and all port C lines are configured as inputs during power-on or reset. The port pins PC0-PC5 are shared with the 16-bit timer (TCAP1-2, TCMP1-2). See Section 9. 16-Bit Programmable Timer for more details on the operation of the 16-Bit Timer. Pins PC0, PC4-6 are shared with the PWM system. PC5-6 are intended to drive relays. See Section 7. Input/Output Ports for more details on the I/O ports. 1.8 Ordering Information Table 1-1 Ordering Information Device MC68HC05PV8 MC68HC805PV8 MC68HC05PV8A 28-pin SOIC -40C to +125C Package Type Temperature range (JUNCTION) Order Number(1) MC68HC05PV8YDW MC68HC805PV8YDW MC68HC05PV8AYDW MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA General Description Technical Data 33 NONDISCLOSURE 1. The Y in the device order number indicates that this is the junction temperature of the device, not the ambient temperature. AGREEMENT REQUIRED Technical Data NONDISCLOSURE Technical Data 34 General Description AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data -- MC68HC(8)05PV8/A Section 2. Memory 2.1 Contents 2.2 2.3 2.4 2.5 2.6 2.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Program EEPROM/ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Memory Technical Data 35 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 2.2 Introduction The MC68HC(8)05PV8/A has a 16K byte memory map consisting of registers (for I/O, control and status), user RAM, user ROM (or program EEPROM), EEPROM, Monitor ROM, and reset and interrupt vectors as shown in Figure 2-1. REQUIRED $0000 $001F $0020 $002F $0030 $003F $0040 I/O Registers 32 Bytes I/O Registers 16 Bytes Externally Mapped 4-bit I/O, If enabled User RAM 192 Bytes Stack RAM 64 Bytes AGREEMENT $00C0 $00FF $00FF $0100 $017F $0180 $01FF $0200 $1FFF $2000 $2001 $3EFF $3F00 $3FEF $3FF0 $3FFF Unused 128 Bytes EEPROM 128 Bytes Unused 7680 Bytes Mask Option Register - 1 Byte Program EEPROM/User ROM 7935 Bytes Monitor ROM 240 Bytes User Vectors 16 Bytes NONDISCLOSURE Figure 2-1 MC68HC(8)05PV8/A Memory Map Technical Data 36 Memory MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Memory Registers 2.3 Registers The I/O and control registers reside in locations $0000-$002F. The overall organization of these registers is shown in Figure 2-2. The bit assignments for each register are shown in Figure 2-3, Figure 2-4 and Figure 2-4. Addr $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A Register Name Port A data register Port B data register Unused Port A data direction register Port B data direction register Port C data direction register Unused Core timer control/status (CTCSR) Core timer counter (CTCR) System control register Unused EEPROM programming register Program EEPROM programming register(1) A/D data A/D status/control Timer capture 1 high Timer capture 1 low Timer compare 1 high Timer compare 1 low Timer capture 2 high Timer capture 2 low Timer compare 2 high Timer compare 2 low Timer counter high Timer counter low Timer alternate counter high Port C data register Figure 2-2 I/O Register Summary MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Memory Technical Data 37 NONDISCLOSURE AGREEMENT REQUIRED Technical Data REQUIRED Addr $001B $001C $001D $001E $001F $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B $002C $002D $002E $002F Register Name Timer alternate counter low Timer control 1 Timer control 2 Timer status TEST Port A configuration register I/O configuration register Port C configuration register 0 Unused Port A interrupt status Unused Port C configuration register 1 Port C status register Interrupt control register Interrupt status register Reset status register Unused PWM period PWM control PWM data MFTEST AGREEMENT NONDISCLOSURE Figure 2-2 I/O Register Summary 1. Implemented in MC68HC805PV8 only; unused in MC68HC05PV8 Technical Data 38 Memory MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Memory Registers Addr $0000 $0001 $0002 $0003 Register Port A Data Port B Data Port C Data Unused R/W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 PA7 0 0 6 PA6 0 5 PA5 TCAP1 4 PA4 PB4 PC4 3 PA3 PB3 PC3 2 PA2 PB2 PC2 1 PA1 PB1 PC1 Bit 0 PA0 PB0 PC0 PC6 PC5 $0004 Port A Data Direction $0005 Port B Data Direction $0006 Port C Data Direction $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F Unused CTSCR CTCR System Control Unused EEPROG Program EEPROM Control A/D Data A/D Status/Control DDRA7 0 0 DDRA6 0 0 DDRA5 0 0 DDRA4 DDRB4 DDRA3 DDRB3 DDRA2 DDRB2 DDRA1 DDRB1 DDRA0 DDRB0 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 TOF bit 7 RTIF bit 6 TOFE bit 5 RTIE bit 4 0 RTOF bit 3 0 RTIF bit 2 WCP RT1 bit 1 RT0 bit 0 POR INTP INTN INTE WCOP* FPIE FPICLK 0 0 0 EEOSC RCON EER1 BULK bit 3 EER0 EELAT EEPGM EEPERA EEPLAT EEPPGM bit 2 bit 1 bit 0 bit 7 COCO bit 6 bit 5 bit 4 ADRC ADON ADTEST CH3 CH2 CH1 CH0 Figure 2-3 I/O Registers $0000-$000F NOTE: * WCOP Bit is write once MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Memory Technical Data 39 NONDISCLOSURE AGREEMENT REQUIRED Technical Data REQUIRED Addr $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B Register Timer Input Capture1 High Timer Input Capture1 Low Timer Output Compare1 High Timer Output Compare1 Low Timer Input Capture2 High Timer Input Capture2 Low Timer Output Compare2 High Timer Output Compare2 Low Timer Counter High Timer Counter Low Timer Alternate Counter High Timer Alternate Counter Low Timer Control1 Timer Control2 Timer Status TEST R/W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 bit 15 bit 7 6 bit 14 bit 6 5 bit 13 bit 5 4 bit 12 bit 4 3 bit 11 bit 3 2 bit 10 bit 2 1 bit 9 bit 1 Bit 0 bit 8 bit 0 bit 15 bit 7 bit 15 bit 7 bit 14 bit 6 bit 14 bit 6 bit 13 bit 5 bit 13 bit 5 bit 12 bit 4 bit 12 bit 4 bit 11 bit 3 bit 11 bit 3 bit 10 bit 2 bit 10 bit 2 bit 9 bit 1 bit 9 bit 1 bit 8 bit 0 bit 8 bit 0 AGREEMENT bit 15 bit 7 bit 15 bit 7 bit 15 bit 7 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 NONDISCLOSURE $001C $001D $001E $001F ICI1E ICI2E OCI1E CLK21 OC1F 0 - TOIE 0 FOLV1 TOF 0 - OCI2E OLVL1 OC2F 0 - CLK12 SI1 0 - 0 FOLV2 SI2 0 - TOFF OLVL2 0 0 - IEDGE1 IEDGE2 IC1F 0 - IC2F 0 - Figure 2-4 I/O Registers $0010-$001F Technical Data 40 Memory MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Memory Registers $0020 Port A Configuration $0021 I/O Configuration R W R W R W R W R W R R W R W R W R W R W R W R W R W R W R W W VRHEN PUHEN EDGEH TXOR ISOM* OPAMP 0 PAHIE PULEN EDGEL PB2IC TS2 PALIE PB1OC TS1 VRLEN PB0IC TS0 PB4PW PB3OC $0022 Port C Configuration 0 $0023 Unused PC6PW PWMS1 PWMS0 PC3OC $0024 Port A Interrupt Status $0025 Unused PAIF7 PAIF6 PAIF5 PAIF4 PAIF3 PAIF2 PAIF1 PAIF0 $0026 Port C Configuration 1 $0027 $0028 $0029 $002A $002B $002C $002D $002E $002F Port C Status Interrupt Control Register Interrupt Status Register Reset Status Register Unused PWM Period PWM Control PWM Data MFTEST CSIE CSIF ULPM RCON SCIE6 SCIF6 0 PC4CL SCIE5 SCIF5 0 0 PC4CS CSD4 0 0 PC3CS CSD3 0 0 PC2CS CSD2 PC1CS CSD1 PC0CS CSD0 HTIE HTIF HTR HVIE HVIF HVR LVIE LVIF LVR PINR STOPR COPR ILINR CMR PWMON bit 7 HVTOFF POL bit 6 0 - 0 CYCLE bit 4 VSCAL PRA3 bit 3 LSOFF PRA2 bit 2 VT2 PRA1 bit 1 VT1 PRA0 bit 0 VT0 bit 5 0 - Figure 2-5 I/O Registers $0020-$002F NOTE:ISOM bit is without function on 68HC05PV8A NOTE:ULPM bit is only available on 68HC05PV8A NOTE:PC4CL is reversed on 68HC05PV8A K20R MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Memory Technical Data 41 NONDISCLOSURE bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 AGREEMENT REQUIRED Addr Register R/W Bit 7 6 5 4 3 2 1 Bit 0 Technical Data 2.4 RAM The user RAM consists of 192 bytes ranging from $0040 to $00FF. The stack begins at address $00FF. The stack pointer can access 64 bytes of RAM in the range $00FF to $00C0. The stack is located in the RAM address space. Data written to addresses within the stack address range could be overwritten during stack activity. REQUIRED AGREEMENT 2.5 Monitor ROM The monitor ROM ranges from $3F00 to $3FEF. The vectors for the bootloader are located from $3FE0 to $3FEF. 2.6 Program EEPROM/ROM The program EEPROM holds 7952 bytes in total. The mask option register is located at address $2000. The 7935 bytes of the program EEPROM are located from $2001 to $3EFF, plus 16 bytes of user vectors from $3FF0 to $3FFF. The user programs the EEPROM on a 4 byte erase basis by manipulating the programming register located at address $000D. Refer to Section 14. Program EEPROM for details. This EEPROM is replaced by an 8K ROM in the MC68HC05PV8, ranging from $2000 to $3EFF and $3FF0 to $3FFF. Mask options are controlled by the contents of location $2000. Refer to Section 14. Program EEPROM for coding details. NONDISCLOSURE 2.7 EEPROM The 128 bytes of EEPROM are located from $0180 to $01FF. The user programs the EEPROM on a single-byte basis by manipulating the programming register, located at address $000C. Refer to Section 13. EEPROM for programming details. Technical Data 42 Memory MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data -- MC68HC(8)05PV8/A Section 3. CPU and Instruction Set 3.1 Contents 3.2 3.3 3.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Instruction Set Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.5.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.5.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.5.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.6 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.6.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . 52 3.6.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . 53 3.6.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.6.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . 56 3.6.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Technical Data 43 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 3.2 CPU Registers Figure 3-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 A 0 ACCUMULATOR (A) REQUIRED 7 X 0 INDEX REGISTER (X) AGREEMENT 15 0 0 0 0 0 0 0 0 1 6 1 5 SP 0 STACK POINTER (SP) 15 10 PCH 8 7 PCL 0 PROGRAM COUNTER (PC) 7 1 1 5 1 4 H I N Z 0 C CONDITION CODE REGISTER (CCR) HALF-CARRY FLAG INTERRUPT MASK NEGATIVE FLAG NONDISCLOSURE ZERO FLAG CARRY/BORROW FLAG Figure 3-1 Programming Model 3.2.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and results of arithmetic and non-arithmetic operations. Bit 7 Reset: 6 5 4 3 2 1 Bit 0 Unaffected by reset Figure 3-2 Accumulator Technical Data 44 CPU and Instruction Set MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set CPU Registers 3.2.2 Index Register In the indexed addressing modes, the CPU uses the byte in the index register to determine the conditional address of the operand. Bit 7 Reset: 6 5 4 3 2 1 Bit 0 Unaffected by reset Figure 3-3 Index Register The 8-bit index register can also serve as a temporary data storage location. 3.2.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset or after the reset stack pointer (RSP) instruction, the stack pointer is preset to $00FF. The address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. Bit 15 14 0 Reset 0 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 1 1 6 1 1 5 4 3 2 1 Bit 0 1 1 1 1 1 1 Figure 3-4 Stack Pointer The ten most significant bits of the stack pointer are permanently fixed at 000000011, so the stack pointer produces addresses from $00C0 to $00FF. If subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00FF and begins writing over the previously stored data. A subroutine uses two stack locations. An interrupt uses five locations. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Technical Data 45 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 3.2.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. The two most significant bits of the program counter are ignored internally. Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. AGREEMENT REQUIRED Bit 15 14 - Reset - - - 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 Loaded with vector from $3FFE AND $3FFF Figure 3-5 Program Counter 3.2.5 Condition Code Register The condition code register is an 8-bit register whose three most significant bits are permanently fixed at 111. The condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. The following paragraphs describe the functions of the condition code register. NONDISCLOSURE Bit 7 1 Reset 1 6 1 1 5 1 1 4 H U 3 I 1 2 N U 1 C U Bit 0 Z U Figure 3-6 Condition Code Register Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an ADD or ADC operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. Technical Data 46 CPU and Instruction Set MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Arithmetic/Logic Unit (ALU) Interrupt Mask Setting the interrupt mask disables interrupts. If an interrupt request occurs while the interrupt mask is logic zero, the CPU saves the CPU registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. If an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the CPU processes the latched interrupt as soon as the interrupt mask is cleared again. A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its cleared state. After any reset, the interrupt mask is set and can be cleared only by a software instruction. Negative Flag The CPU sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result. Zero Flag The CPU sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a result of $00. Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some logical operations and data manipulation instructions also clear or set the carry/borrow flag. 3.3 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logical operations defined by the instruction set. The binary arithmetic circuits decode instructions and set up the ALU for the selected operation. Most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. Multiplication is not performed as a discrete operation but as a chain of addition and shift MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Technical Data 47 NONDISCLOSURE AGREEMENT REQUIRED Technical Data operations within the ALU. The multiply instruction (MUL) requires 11 internal clock cycles to complete this chain of operations. REQUIRED 3.4 Instruction Set Overview The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator. AGREEMENT 3.5 Addressing Modes The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: * * * * * * * * Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative NONDISCLOSURE 3.5.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and Technical Data 48 CPU and Instruction Set MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Addressing Modes 3.5.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte. 3.5.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. 3.5.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. 3.5.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000-$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Technical Data 49 NONDISCLOSURE AGREEMENT REQUIRED increment accumulator (INCA). Inherent instructions require no operand address and are one byte long. Technical Data 3.5.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000-$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. AGREEMENT REQUIRED 3.5.7 Indexed,16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. NONDISCLOSURE 3.5.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two's complement byte that gives a branching range of -128 to +127 bytes from the address of the next location after the branch instruction. Technical Data 50 CPU and Instruction Set MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Instruction Types 3.6 Instruction Types The MCU instructions fall into the following five categories: * * * * * Register/Memory Instructions Read-Modify-Write Instructions Jump/Branch Instructions Bit Manipulation Instructions Control Instructions MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Technical Data 51 NONDISCLOSURE AGREEMENT REQUIRED When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. Technical Data 3.6.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 3-1 Register/Memory Instructions Instruction Add Memory Byte and Carry Bit to Accumulator Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB REQUIRED AGREEMENT Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator NONDISCLOSURE Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator Technical Data 52 CPU and Instruction Set MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Instruction Types 3.6.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. Table 3-2 Read-Modify-Write Instructions Instruction Arithmetic Shift Left (Same as LSL) Arithmetic Shift Right Bit Clear Bit Set Clear Register Complement (One's Complement) Decrement Increment Logical Shift Left (Same as ASL) Logical Shift Right Negate (Two's Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero Mnemonic ASL ASR BCLR(1) BSET(1) CLR COM DEC INC LSL LSR ROL ROR TST(2) 1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Technical Data 53 NONDISCLOSURE NEG AGREEMENT REQUIRED Technical Data 3.6.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from -128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. NONDISCLOSURE Technical Data 54 CPU and Instruction Set AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Instruction Types Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRN BRSET BSR JMP JSR MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Technical Data 55 NONDISCLOSURE BRCLR AGREEMENT REQUIRED Table 3-3 Jump and Branch Instructions Technical Data 3.6.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 3-4 Bit Manipulation Instructions Instruction Bit Clear Mnemonic BCLR BRCLR BRSET BSET REQUIRED AGREEMENT Branch if Bit Clear Branch if Bit Set Bit Set NONDISCLOSURE Technical Data 56 CPU and Instruction Set MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Instruction Types 3.6.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Table 3-5 Control Instructions Instruction Clear Carry Bit Clear Interrupt Mask No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Technical Data 57 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 3.7 Instruction Set Summary Table 3-6 Instruction Set Summary Address Mode Opcode Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel REQUIRED Operation Description H I NZC Add with Carry A (A) + (M) + (C) -- IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL ii A9 2 B9 dd 3 C9 hh ll 4 D9 ee ff 5 E9 ff 4 F9 3 AB ii 2 BB dd 3 CB hh ll 4 DB ee ff 5 EB ff 4 FB 3 ii A4 2 B4 dd 3 C4 hh ll 4 D4 ee ff 5 E4 ff 4 F4 3 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 28 29 22 24 dd 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 3 3 3 3 AGREEMENT Add without Carry A (A) + (M) -- Logical AND A (A) (M) -- -- -- Arithmetic Shift Left (Same as LSL) C b7 b0 0 -- -- ff dd NONDISCLOSURE Arithmetic Shift Right b7 b0 C -- -- ff rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr Branch if Carry Bit Clear PC (PC) + 2 + rel ? C = 0 ---------- BCLR n opr Clear Bit n Mn 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- ---------- ---------- ---------- REL REL REL REL REL REL BCS rel BEQ rel BHCC rel BHCS rel BHI rel BHS rel Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? Z = 1 PC (PC) + 2 + rel ? H = 0 PC (PC) + 2 + rel ? H = 1 PC (PC) + 2 + rel ? C = 0 PC (PC) + 2 + rel ? C Z = 0 -- -- -- -- -- ---------- Technical Data 58 CPU and Instruction Set MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Cycles Effect on CCR Operand CPU and Instruction Set Instruction Set Summary Table 3-6 Instruction Set Summary (Continued) Address Mode Opcode Source Form BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel Operation Branch if IRQ Pin High Branch if IRQ Pin Low Description PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0 H I NZC ---------- ---------- REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL 2F 2E rr rr Bit Test Accumulator with Memory Byte (A) (M) -- -- -- ii A5 2 B5 dd 3 C5 hh ll 4 D5 ee ff 5 E5 ff 4 F5 3 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd 3 Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? I = 0 PC (PC) + 2 + rel ? N = 1 PC (PC) + 2 + rel ? I = 1 PC (PC) + 2 + rel ? Z = 0 PC (PC) + 2 + rel ? N = 0 PC (PC) + 2 + rel ? 1 = 1 ---------- ---------- ---------- ---------- ---------- ---------- ---------- 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BRCLR n opr rel Branch if Bit n Clear PC (PC) + 2 + rel ? Mn = 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) -- -- -- -- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- REL BRN rel Branch Never PC (PC) + 2 + rel ? 1 = 0 BRSET n opr rel Branch if Bit n Set PC (PC) + 2 + rel ? Mn = 1 DIR (b0) DIR (b1) DIR (b2) DIR (b3) -- -- -- -- DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) BSET n opr Set Bit n Mn 1 BSR rel Branch to Subroutine PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel C0 I0 ---------- REL AD rr 6 CLC CLI Clear Carry Bit Clear Interrupt Mask -------- 0 -- 0 ------ INH INH 98 9A 2 2 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Technical Data 59 NONDISCLOSURE AGREEMENT PC (PC) + 2 + rel ? C Z = 1 -- -- -- -- -- Cycles 3 3 3 Effect on CCR REQUIRED Operand Technical Data Table 3-6 Instruction Set Summary (Continued) Address Mode Opcode Source Form CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X REQUIRED Operation Description M $00 A $00 X $00 M $00 M $00 H I NZC Clear Byte ---- 0 1 -- DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR EXT IX2 IX1 IX 3F 4F 5F 6F 7F dd ff Compare Accumulator with Memory Byte (A) - (M) -- -- AGREEMENT ii A1 2 B1 dd 3 C1 hh ll 4 D1 ee ff 5 E1 ff 4 F1 3 33 43 53 63 73 dd 5 3 3 6 5 Complement Byte (One's Complement) M (M) = $FF - (M) A (A) = $FF - (A) X (X) = $FF - (X) M (M) = $FF - (M) M (M) = $FF - (M) -- -- 1 ff Compare Index Register with Memory Byte (X) - (M) -- -- ii A3 2 B3 dd 3 C3 hh ll 4 D3 ee ff 5 E3 ff 4 F3 3 3A 4A 5A 6A 7A dd 5 3 3 6 5 Decrement Byte NONDISCLOSURE M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 -- -- -- ff EXCLUSIVE OR Accumulator with Memory Byte A (A) (M) -- -- -- ii 2 A8 B8 dd 3 C8 hh ll 4 D8 ee ff 5 4 E8 ff F8 3 3C 4C 5C 6C 7C dd 5 3 3 6 5 Increment Byte M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 -- -- -- ff Unconditional Jump PC Jump Address ---------- BC dd 2 CC hh ll 3 DC ee ff 4 EC ff 3 FC 2 Technical Data 60 CPU and Instruction Set MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Cycles 5 3 3 6 5 Effect on CCR Operand CPU and Instruction Set Instruction Set Summary Table 3-6 Instruction Set Summary (Continued) Address Mode Opcode Source Form JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X Operation Description H I NZC PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Effective Address Jump to Subroutine ---------- DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX BD dd 5 CD hh ll 6 DD ee ff 7 ED ff 6 FD 5 ii A6 2 B6 dd 3 C6 hh ll 4 D6 ee ff 5 E6 ff 4 F6 3 AE ii 2 BE dd 3 CE hh ll 4 DE ee ff 5 EE ff 4 FE 3 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D dd dd 5 3 3 6 5 5 3 3 6 5 11 5 3 3 6 5 2 Load Accumulator with Memory Byte A (M) -- -- -- Cycles 5 3 3 6 5 Effect on CCR Load Index Register with Memory Byte X (M) -- -- -- Logical Shift Left (Same as ASL) C b7 b0 0 -- -- ff dd Logical Shift Right 0 b7 b0 C ---- 0 ff Unsigned Multiply X : A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) 0 ------ 0 Negate Byte (Two's Complement) -- -- ff No Operation ---------- Logical OR Accumulator with Memory A (A) (M) -- -- -- AA ii 2 BA dd 3 CA hh ll 4 DA ee ff 5 EA ff 4 FA 3 39 49 59 69 79 dd Rotate Byte Left through Carry Bit C b7 b0 -- -- ff MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Technical Data 61 NONDISCLOSURE AGREEMENT REQUIRED Operand Technical Data Table 3-6 Instruction Set Summary (Continued) Address Mode Opcode Source Form ROR opr RORA RORX ROR opr,X ROR ,X RSP REQUIRED Operation Description H I NZC Rotate Byte Right through Carry Bit b7 b0 C -- -- DIR INH INH IX1 IX INH 36 46 56 66 76 9C dd ff Reset Stack Pointer SP $00FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) ---------- RTI Return from Interrupt INH 80 AGREEMENT RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Return from Subroutine ---------- INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX 81 Subtract Memory Byte and Carry Bit from Accumulator A (A) - (M) - (C) -- -- ii A2 2 B2 dd 3 C2 hh ll 4 D2 ee ff 5 E2 ff 4 F2 3 99 9B 2 2 Set Carry Bit Set Interrupt Mask C1 I1 -------- 1 -- 1 ------ Store Accumulator in Memory M (A) -- -- -- B7 dd 4 C7 hh ll 5 D7 ee ff 6 E7 ff 5 F7 4 8E 2 NONDISCLOSURE Stop Oscillator and Enable IRQ Pin -- 0 ------ Store Index Register In Memory M (X) -- -- -- BF dd 4 CF hh ll 5 DF ee ff 6 EF ff 5 FF 4 ii A0 2 B0 dd 3 C0 hh ll 4 D0 ee ff 5 E0 ff 4 F0 3 Subtract Memory Byte from Accumulator A (A) - (M) ---- SWI Software Interrupt PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) -- 1 ------ SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte X (A) ---------- INH 83 10 TAX Transfer Accumulator to Index Register INH 97 Technical Data 62 CPU and Instruction Set MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Cycles 5 3 3 6 5 2 9 6 2 Effect on CCR Operand CPU and Instruction Set Instruction Set Summary Table 3-6 Instruction Set Summary (Continued) Address Mode Opcode Source Form TST opr TSTA TSTX TST opr,X TST ,X TXA WAIT Operation Description H I NZC Test Memory Byte for Negative or Zero (M) - $00 ---- -- DIR INH INH IX1 IX INH INH 3D 4D 5D 6D 7D 9F 8F dd ff Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts A (X) ---------- -- 0 ------ MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA CPU and Instruction Set Technical Data 63 NONDISCLOSURE A Accumulatoropr C Carry/borrow flagPC CCRCondition code registerPCH ddDirect address of operandPCL dd rrDirect address of operand and relative offset of branch instructionREL DIRDirect addressing moderel ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingrr EXTExtended addressing modeSP ff Offset byte in indexed, 8-bit offset addressingX H Half-carry flagZ hh llHigh and low bytes of operand address in extended addressing# I Interrupt mask ii Immediate operand byte IMMImmediate addressing mode INHInherent addressing mode( ) IXIndexed, no offset addressing mode-( ) IX1Indexed, 8-bit offset addressing mode IX2Indexed, 16-bit offset addressing mode? MMemory location: N Negative flag n Any bit-- Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected Cycles 4 3 3 5 4 2 2 Effect on CCR AGREEMENT REQUIRED Operand NONDISCLOSURE AGREEMENT REQUIRED 64 Table 3-7 Opcode Map Read-Modify-Write DIR 3 3 6 5 NEGX NEG NEG 1 INH 2 IX1 1 IX 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 2 3 3 3 3 2 3 3 3 3 3 2 3 3 3 2 MSB LSB 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 2 3 2 Bit Manipulation INH 4 5 6 7 8 9 A B C D E F 3 SUB IX 3 CMP IX 3 SBC IX 3 CPX IX 3 AND IX 3 BIT IX 3 LDA IX 4 STA IX 3 EOR IX 3 ADC IX 3 ORA IX 3 ADD IX 2 JMP IX 5 JSR IX 3 LDX IX 4 STX IX Branch INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX Control Register/Memory Technical Data MSB LSB DIR DIR REL Technical Data MSB LSB 0 1 2 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 1 9 RTI INH 6 RTS 1 INH 2 3 4 3 6 5 10 COMX COM COM SWI 1 INH 2 IX1 1 IX 1 INH 3 6 5 LSRX LSR LSR 1 INH 2 IX1 1 IX 5 6 2 SUB IMM 2 2 CMP IMM 2 2 SBC IMM 2 2 CPX IMM 2 2 AND IMM 2 2 BIT IMM 2 2 LDA IMM 2 7 CPU and Instruction Set 3 6 5 RORX ROR ROR INH 2 IX1 1 IX 3 6 5 ASRX ASR ASR 1 INH 2 IX1 1 IX 3 6 5 ASLX/LSLX ASL/LSL ASL/LSL 1 INH 2 IX1 1 IX 3 6 5 ROLX ROL ROL 1 INH 2 IX1 1 IX 3 6 5 DECX DEC DEC 1 INH 2 IX1 1 IX 2 EOR IMM 2 2 ADC IMM 2 2 ORA IMM 2 2 ADD IMM 2 3 6 5 INCX INC INC 1 INH 2 IX1 1 IX 3 5 4 TSTX TST TST 1 INH 2 IX1 1 IX 2 TAX INH 2 CLC INH 2 2 SEC INH 2 2 CLI INH 2 2 SEI INH 2 2 RSP INH 2 NOP INH 2 6 BSR REL 2 2 LDX 2 IMM 2 2 STOP INH 3 6 5 2 2 CLRX CLR CLR WAIT TXA 1 INH 2 IX1 1 IX 1 INH 1 INH 8 9 A B C D Instruction Set Summary E F 5 5 BRSET0 BSET0 3 DIR 2 DIR 5 5 BRCLR0 BCLR0 3 DIR 2 DIR 5 5 BRSET1 BSET1 3 DIR 2 DIR 5 5 BRCLR1 BCLR1 3 DIR 2 DIR 5 5 BRSET2 BSET2 3 DIR 2 DIR 5 5 BRCLR2 BCLR2 3 DIR 2 DIR 5 5 BRSET3 BSET3 3 DIR 2 DIR 5 5 BRCLR3 BCLR3 3 DIR 2 DIR 5 5 BRSET4 BSET4 3 DIR 2 DIR 5 5 BRCLR4 BCLR4 3 DIR 2 DIR 5 5 BRSET5 BSET5 3 DIR 2 DIR 5 5 BRCLR5 BCLR5 3 DIR 2 DIR 5 5 BRSET6 BSET6 3 DIR 2 DIR 5 5 BRCLR6 BCLR6 3 DIR 2 DIR 5 5 BRSET7 BSET7 3 DIR 2 DIR 5 5 BRCLR7 BCLR7 3 DIR 2 DIR 3 5 3 BRA NEG NEGA 2 REL 2 DIR 1 INH 3 BRN 2 REL 3 11 BHI MUL 2 REL 1 INH 3 5 3 BLS COM COMA 2 REL 2 DIR 1 INH 3 5 3 BCC LSR LSRA 2 REL 2 DIR 1 INH 3 BCS/BLO 2 REL 3 5 3 BNE ROR RORA 2 REL 2 DIR 1 INH 3 5 3 BEQ ASR ASRA 2 REL 2 DIR 1 INH 3 5 3 BHCC ASL/LSL ASLA/LSLA 2 REL 2 DIR 1 INH 3 5 3 BHCS ROL ROLA 2 REL 2 DIR 1 INH 3 5 3 BPL DEC DECA 2 REL 2 DIR 1 INH 3 BMI 2 REL 3 5 3 BMC INC INCA 2 REL 2 DIR 1 INH 3 4 3 BMS TST TSTA 2 REL 2 DIR 1 INH 3 BIL 2 REL 3 5 3 BIH CLR CLRA 2 REL 2 DIR 1 INH 3 SUB DIR 3 3 CMP DIR 3 3 SBC DIR 3 3 CPX DIR 3 3 AND DIR 3 3 BIT DIR 3 3 LDA DIR 3 4 STA DIR 3 3 EOR DIR 3 3 ADC DIR 3 3 ORA DIR 3 3 ADD DIR 3 2 JMP DIR 3 5 JSR DIR 3 3 LDX DIR 3 4 STX DIR 3 4 SUB EXT 4 CMP EXT 4 SBC EXT 4 CPX EXT 4 AND EXT 4 BIT EXT 4 LDA EXT 5 STA EXT 4 EOR EXT 4 ADC EXT 4 ORA EXT 4 ADD EXT 3 JMP EXT 6 JSR EXT 4 LDX EXT 5 STX EXT 5 SUB IX2 5 CMP IX2 5 SBC IX2 5 CPX IX2 5 AND IX2 5 BIT IX2 5 LDA IX2 6 STA IX2 5 EOR IX2 5 ADC IX2 5 ORA IX2 5 ADD IX2 4 JMP IX2 7 JSR IX2 5 LDX IX2 6 STX IX2 4 SUB IX1 1 4 CMP IX1 1 4 SBC IX1 1 4 CPX IX1 1 4 AND IX1 1 4 BIT IX1 1 4 LDA IX1 1 5 STA IX1 1 4 EOR IX1 1 4 ADC IX1 1 4 ORA IX1 1 4 ADD IX1 1 3 JMP IX1 1 6 JSR IX1 1 4 LDX IX1 1 5 STX IX1 1 0 LSB of Opcode in Hexadecimal MSB of Opcode in Hexadecimal MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA INH = InherentREL = Relative IMM = ImmediateIX = Indexed, No Offset DIR = DirectIX1 = Indexed, 8-Bit Offset EXT = ExtendedIX2 = Indexed, 16-Bit Offset 0 5 Number of Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes/Addressing Mode Technical Data -- MC68HC(8)05PV8/A Section 4. Interrupts 4.1 Contents 4.2 4.3 4.4 4.5 4.6 4.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.8 8-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.8.1 16-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.9 Ambient Exception Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.11 4.12 4.13 Keyboard Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Port C Contact Sense Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 75 STOP and WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Interrupts Technical Data 65 NONDISCLOSURE 4.10 High Temperature Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.10.1 High Voltage Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.10.2 Low Voltage Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.10.3 Power Driver Short Circuit Interrupt . . . . . . . . . . . . . . . . . . 75 AGREEMENT REQUIRED Technical Data 4.2 Introduction The MCU can be interrupted in different ways: 1. Nonmaskable Software Interrupt Instruction (SWI) 2. External Asynchronous Interrupt (IRQ) 3. External Asynchronous Interrupt on Port A 4. External Asynchronous Interrupt on Port C 5. Internal 8-bit Timer Interrupt (CTIMER) 6. Internal 16-bit Timer1 Interrupt (TIMER) 7. Low Voltage Interrupt 8. Port C5 & C6 Short Circuit Interrupt 9. High Voltage Interrupt 10. High Temperature Interrupt AGREEMENT REQUIRED 4.3 CPU Interrupt Processing Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. If interrupts are not masked (I-bit in the CCR is clear) and the corresponding interrupt enable bit is set, then the processor proceeds with interrupt processing. Otherwise, the next instruction is fetched and executed. If an interrupt occurs, the processor completes the current instruction, then stacks the current CPU register states, sets the I-bit to inhibit further interrupts, and finally checks the pending hardware interrupts. If more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location shown in Table 4-1 is serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state. NONDISCLOSURE Technical Data 66 MC68HC(8)05PV8/A -- Rev. 1.9 Interrupts MOTOROLA Interrupts CPU Interrupt Processing Table 4-1 Reset/Interrupt Vector Addresses Function Source Power-On Logic RESET Pin None COP Watchdog Low Voltage Reset High Voltage High Temperature Clock Monitor Illegal STOP Inst. Illegal Address Software Interrupt (SWI) External Interrupt Core Timer Interrupts TOF ICF Bits 16-Bit Timer Interrupts OCF Bits TOF Bit TOFE Bit ICIE Bits OCIE Bits TOIE Bit I-Bit 4 $3FF6-$3FF7 User Code IRQ Pin RTIF None None INTE Bit RTIE Bit I-Bit 3 $3FF8-$3FF9 None I-Bit Same Priority As Instruction 2 $3FFC-$3FFD $3FFA-$3FFB Mask Options None 1 $3FFE-$3FFF Local Mask Global Mask Priority (1 = Highest) Vector Address MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Interrupts Technical Data 67 NONDISCLOSURE AGREEMENT REQUIRED When an interrupt is to be processed, the CPU fetches the address of the appropriate interrupt software service routine from the vector table at locations $3FF0 through $3FFF as defined in Table 4-1. Technical Data Table 4-1 Reset/Interrupt Vector Addresses Function Source HTI Bit Voltage, Temperature and Port C Short circuit Interrupts HVI Bit LVI Bit SCIF6 SCIF5 Port A High Nibble Interrupt Port A Low Nibble Interrupt Port C Contact Sense/HV Inputs Port A4-7 Port A0-3 CSIF Local Mask HTIM Bit HVIM Bit LVIM Bit SCIE6 SCIE5 PAHIE Bit I-Bit PALIE Bit CSIE I-Bit 7 $3FF0-$3FF1 6 $3FF2-$3FF3 I-Bit 5 $3FF4-$3FF5 Global Mask Priority (1 = Highest) Vector Address AGREEMENT REQUIRED The M68HC05 CPU does not support interruptible instructions, therefore, the maximum latency to the first instruction of the interrupt service routine must include the longest instruction execution time plus stacking overhead. Latency = (Longest instruction execution time + 10) x tCYC An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. Figure 4-1 shows the sequence of events that occur during interrupt processing. NONDISCLOSURE Technical Data 68 MC68HC(8)05PV8/A -- Rev. 1.9 Interrupts MOTOROLA Interrupts CPU Interrupt Processing Y I-BIT IN CCR SET? N Y IRQ? N INTERNAL 8 BIT CORE TIMER INTERRUPT? N INTERNAL 16 BIT TIMER INTERRUPT? N HIGH TEMP LOW/HIGH VOLT, SC INTERRUPT? N PORT A WIRED OR INTERRUPT? N PORT C0-4 CONTACT SENSE INTERRUPT? N Y Y Load PC from: SWI: $3FFC - $3FFD IRQ: $3FFA - $3FFB Core Timer: $3FF8 - $3FF9 16-Bit Timer: $3FF6 - $3FF7 T, V, SC: $3FF4 - $3FF5 PTA: $3FF2 - $3FF3 Contact Sense: $3FF0 - $3FF1 Y STACK PC,X,A,CCR SET I-BIT IN CC REGISTER Y Y CLEAR IRQ REQUEST LATCH FETCH NEXT INSTRUCTION SWI INSTRUCTION ? N Y RTI INSTRUCTION ? N RESTORE REGISTERS FROM STACK: CCR,A,X,PC EXECUTE INSTRUCTION Y Figure 4-1 Interrupt Processing Flowchart MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Interrupts Technical Data 69 NONDISCLOSURE AGREEMENT REQUIRED FROM RESET Technical Data 4.4 Reset Interrupt Sequence The reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in Figure 4-1. A low level input on the RESET pin or internally generated RST signal causes the program to vector to its starting address which is specified by the contents of memory locations $3FFE and $3FFF. The I-bit in the condition code register is also set. The MCU is configured to a known state during this type of reset as described in Section 5. Resets. REQUIRED AGREEMENT 4.5 Software Interrupt (SWI) The SWI is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), the SWI instruction executes after interrupts which were pending before the SWI was fetched, or before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $3FFC and $3FFD. 4.6 Hardware Interrupts All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I-bit enables the hardware interrupts. There are two types of hardware interrupts which are explained in the following sections. NONDISCLOSURE 4.7 External Interrupt (IRQ) If the interrupt mask bit (I-bit) of the CCR has been cleared and the interrupt enable bit is set (INTE bit) and the signal of the external interrupt pin (IRQ) satisfies the condition selected by the option control bits (INTP and INTN), then the external interrupt is recognized. INTE, INTP and INTN are all bits contained in the system control register located at $000A. When the interrupt is recognized, the current state of Technical Data 70 Interrupts MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Interrupts External Interrupt (IRQ) $000A Read: Bit 7 POR 6 INTP 0 5 INTN 0 4 INTE 0 3 WCOP 0 2 WCP 1 FPIE Bit 0 FPICLK 0 Write: Reset: NA 0 0 Figure 4-2 System Control Register (SYSCTRL) INTP, INTN - External interrupt sensitivity options These two bits allow the user to select which edge of the IRQ pin is sensitive as shown in Table 4-1. Both bits can be written only while the I-bit is set, and are cleared by power-on or external reset. Therefore the device is initialized with negative edge and low level sensitivity. Table 4-2 IRQ sensitivity INTP 0 0 1 1 INTN 0 1 0 1 IRQ sensitivity Negative edge and low level sensitive Negative edge only Positive edge only Positive and negative edge sensitive INTE - External interrupt enable 1 = External interrupt function (IRQ) enabled. 0 = External interrupt function (IRQ) disabled. The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset, thus enabling the external interrupt function. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Interrupts Technical Data 71 NONDISCLOSURE AGREEMENT REQUIRED the CPU is pushed onto the stack and the I-bit is set. This masks further interrupts until the present one is serviced. The interrupt service routine address is specified by the contents of memory locations $3FFA and $3FFB. Technical Data Table 4-1 describes the various triggering options available for the IRQ pin, however it is important to re-emphasize here that in order to avoid any conflict and spurious interrupt, it is only possible to change the external interrupt options while the I-bit is set. Any attempt to change the external interrupt option while the I-bit is clear will be unsuccessful. If an external interrupt is pending, it will automatically be cleared when selecting a different interrupt option. REQUIRED NOTE: AGREEMENT If the external interrupt function is disabled by the INTE bit and an external interrupt is sensed by the edge detection circuitry, then the interrupt request is latched and the interrupt stays pending until the INTE bit is set. The external latch of the external interrupt is cleared in the first part of the service routine (except for the low level interrupt which is not latched); therefore only one external interrupt pulse can be latched during tILIL and serviced as soon as the I-bit is cleared. 4.8 8-Bit Timer Interrupt This timer can create two types of interrupts. A timer overflow interrupt occurs whenever the 8 bit timer rolls over from $FF to $00 and the enable bit TOFE is set. A real time interrupt occurs whenever the programmed time elapses and the enable bit RTIE is set. This interrupt vector to the interrupt service routine located at the address specified by the contents of memory location $3FF8 and $3FF9. For details see Section 8. Core Timer. NONDISCLOSURE 4.8.1 16-Bit Timer Interrupt There are five different timer interrupt flags that cause a 16-bit timer interrupt whenever they are set and enabled. The interrupt flags are in the timer status register (TSR), and the enable bits are in the timer control register1 (TCR1). Any of these interrupts vectors to the same interrupt service routine, located at the address specified by the contents of memory location $3FF6 and $3FF7. For details see Section 9. 16-Bit Programmable Timer. Technical Data 72 Interrupts MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Interrupts Ambient Exception Interrupts 4.9 Ambient Exception Interrupts There are three different interrupt flags that cause an environmental exception interrupt whenever they are set and enabled. The interrupt flags are in the reset/interrupt status register (INTSR), and the enable bits are in the interrupt control register (INTCR). Any of these interrupts vectors to the same interrupt service routine, located at the address specified by the contents of memory location $3FF4 and $3FF5. $0028 Read: Bit 7 ULPM 6 0 5 0 4 0 3 0 2 HTIE 1 HVIE 0 Bit 0 LVIE 0 Write: Reset: 0 0 0 0 0 0 Figure 4-3 Interrupt Control Register (INTCR) $0029 Read: Write: Reset: Bit 7 RCON 6 PC4CL 5 0 4 0 3 0 2 HTIF 1 HVIF Bit 0 LVIF Figure 4-4 Interrupt Status Register (INTSR) 4.10 High Temperature Interrupt HTIF - High Temperature Interrupt Flag This bit is set if the die temperature is higher than the upper trip point and cleared again if the die temperature falls below the lower trip point of the HTI. 1 = The die temperature is higher than THTION 0 = The die temperature is lower than THTIOFF MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Interrupts Technical Data 73 NONDISCLOSURE NA 0 0 0 0 ? 0 0 AGREEMENT REQUIRED Technical Data HTIE - High Temperature Interrupt Enable This bit enables/disables the high temperature interrupt. Once this interrupt is acknowledged, the enable bit should be cleared and the high temperature interrupt flag should be monitored until the bit is cleared. 1 = High temperature interrupt enabled 0 = High temperature interrupt disabled REQUIRED 4.10.1 High Voltage Interrupt HVIF - High Voltage Interrupt Flag This bit is set if the supply voltage VSUP is higher than the upper trip point and cleared again if the voltage falls below the lower trip point of the HVI. 1 = The supply voltage is higher than VHVION 0 = The supply voltage is lower than VHIOFF HVIE - High Voltage Interrupt Enable This bit enables/disables the high voltage interrupt. Once this interrupt is acknowledged, the enable bit should be cleared and the high voltage interrupt flag should be monitored until the bit is cleared. 1 = High voltage interrupt enabled 0 = High voltage interrupt disabled NONDISCLOSURE AGREEMENT 4.10.2 Low Voltage Interrupt LVIF - Low Voltage Interrupt Flag This bit is set if the supply voltage VSUP is lower than the lower trip point and cleared again if the voltage rises above the upper trip point of the LVI. 1 = The supply voltage is lower than VLVION 0 = The supply voltage is higher than VLVIOFF Technical Data 74 Interrupts MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Interrupts Keyboard Interrupts LVIE - Low Voltage Interrupt Enable This bit enables/disables the low voltage interrupt. Once this interrupt is acknowledged, the enable bit should be cleared and the low voltage interrupt flag should be monitored until the bit is cleared. 1 = Low voltage interrupt enabled 0 = Low voltage interrupt disabled 4.10.3 Power Driver Short Circuit Interrupt There are two different interrupt flags that cause a power driver short circuit interrupt whenever they are set and enabled. The interrupt flags are located in the port C status register, and the enable bits are located in the port C configuration register 1. Any of these interrupts vector to the same interrupt service routine, located at the address specified by the contents of memory location $3FF4 and $3FF5. For details see 7.6 Port C (High Voltage Port). 4.11 Keyboard Interrupts When configured as input pins, PA0-7 provide a wired-OR keyboard interrupt facility and generate an interrupt provided the interrupt enable bits (PALIE or PAHIE) in the port A configuration register are set. The interrupt vector for this interrupt is located at $3FF2 and $3FF3. Further information on the keyboard interrupt facility can be found in 7.4 Port A. 4.12 Port C Contact Sense Interrupt There is an interrupt flag that causes a contact sense interrupt whenever it is set and enabled. This interrupt flag is a wired-OR of the active contact sense inputs. The interrupt flag is located in the port C status register, and the enable bit is located in the port C configuration register 1. This interrupt vectors to the memory location $3FF0 and $3FF1. Whenever a PCxCS bit is set, but the corresponding pin is not configured MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Interrupts Technical Data 75 NONDISCLOSURE AGREEMENT REQUIRED Technical Data as an output, the signal for the corresponding CSDx bit, and therefore for the contact sense interrupt, is derived from the high-voltage input circuit. For details see 7.6 Port C (High Voltage Port). REQUIRED 4.13 STOP and WAIT Modes All modules that are capable of generating interrupts in STOP or WAIT mode can only do so when configured properly. The I-bit is automatically cleared when STOP or WAIT mode is entered. Environmental exception interrupts and interrupts detected on port A and port C are recognized in STOP or WAIT modes. On 68HC05PV8A, when ultra low power mode is selected by setting the ULPM bit, there will be no LVI, HVI, HTI even if all conditions for an asserted interrupt are beeing met. NONDISCLOSURE Technical Data 76 Interrupts AGREEMENT MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data -- MC68HC(8)05PV8/A Section 5. Resets 5.1 Contents 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Reset status register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . .78 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Computer Operating Properly Reset (COPR). . . . . . . . . . . . . . 82 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Disabled STOP Instruction Reset . . . . . . . . . . . . . . . . . . . . . . .84 High Temperature Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 High Voltage Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Operation in STOP and WAIT Mode . . . . . . . . . . . . . . . . . . . .85 5.14 Clock Monitor Reset (CMR) . . . . . . . . . . . . . . . . . . . . . . . . . . .85 5.14.1 Clock Monitor in STOP mode . . . . . . . . . . . . . . . . . . . . . . . 86 5.2 Introduction The MCU can be reset from nine sources: one external input and eight internal restart conditions. The RESET pin is an input with a Schmitt trigger. All the internal peripheral modules are reset by the internal reset signal (RST). Refer to Figure 5-2 for reset timing details. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Resets Technical Data 77 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 5.3 Reset status register (RSR) This register contains eight flags that show the source of the last reset. A power-on reset sets the POR bit in the system control register and clears all other bits in the reset status register. All bits can be cleared by writing a one to the corresponding bit. Uncleared bits remain set as long as they are not cleared by a power-on reset or by software. $002A Read: PINR Write: STOPR 0 COPR 0 ILINR 0 CMR 0 HTR 0 HVR 0 LVR 0 Bit 7 6 5 4 3 2 1 Bit 0 AGREEMENT REQUIRED POR: 0 Figure 5-1 Reset Status Register (RSR) PINR - External Reset Bit 1 = Last reset caused by external reset pin (RESET) 0 = No pin reset since PINR was cleared by software or POR STOPR - Illegal STOP Instruction Reset Bit Indicates the last reset was caused by a disabled STOP instruction. 1 = Last reset caused by a disabled STOP instruction 0 = No illegal STOP instruction since STOPR was cleared by software or POR COPR - COP (Computer Operating Properly) Reset Bit 1 = Last reset caused by COP 0 = No COP reset since COPR was cleared by software or POR ILINR - Illegal Instruction Reset Bit 1 = Last reset caused by an instruction fetch from an illegal address 0 = No illegal instruction fetch reset since ILINR was cleared by software or POR CMR - Clock Monitor Reset Bit 1 = Last reset caused by the clock monitor due to a failure on system clock or system clock is back. Refer to RCON status bit in the interrupt status register 0 = No clock monitor reset since CMR was cleared by software or POR Technical Data 78 Resets MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA NONDISCLOSURE Resets External Reset (RESET) HVR - High Voltage Reset Bit 1 = Last reset caused by high voltage detect circuitry 0 = No high voltage reset since HVR is cleared by software or POR LVR - Low Voltage Reset Bit 1 = Last reset caused by low voltage detect circuitry 0 = No low voltage reset since LVR was cleared by software or POR Note: If the cause of an environmental reset only lasts for a short time and if there is an external capacitor on the RESET pin, the corresponding bit in the reset status register may be set without occurrence of a reset. 5.4 External Reset (RESET) The RESET pin is the only external source of a reset. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active low input generates the RST signal and resets the CPU and peripherals. Activation of the RST signal is generally referred to as reset of the device, unless otherwise specified. The RESET pin can also act as an open drain output. It is pulled to a low state by an internal pull-down that is activated by any reset source. This RESET pull-down device is asserted until the internal reset source is deasserted and the reset is internally recognized. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Resets Technical Data 79 NONDISCLOSURE AGREEMENT REQUIRED HTR - High Temperature Reset Bit 1 = Last reset caused by high temperature detect circuitry 0 = No high temperature reset since HTR was cleared by software or POR Technical Data 5.5 Internal Resets The eight internally generated resets are the initial power-on reset function, the COP watchdog timer reset, the illegal address detector, clock-monitor, the high temperature reset, high voltage reset, low-voltage reset, and the disabled STOP instruction. When forcing RESET externally to VDD, all temperature, voltage and clock-monitor dependent reset sources are disabled. In this case, the internal pull-down device tries to pull down the pin until the next recognized internal reset, which leads to some power-consumption. AGREEMENT REQUIRED VDD INTERNAL PULLUP RESET PIN INTERNAL RESETS INTERNAL RESET LOGIC NONDISCLOSURE 5.6 Power-On Reset (POR) The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilization delay of tPORLafter the oscillator becomes active. See Figure 5-2 for details. TPORLis 4064 internal processor clock cycles. The POR generates the RST signal which resets the CPU. If any other reset function is active at the end of this tPORL delay, the RST signal remains in the reset condition until the other reset condition(s) ends. POR activates the RESET pin pull-down device connected to the pin. VDD must drop below VPOR in order for the internal POR circuit to detect the next rise of VDD. Technical Data 80 Resets MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA MOTOROLA VDD > VPOR 4 t cyc 3FFE NEW PC NEW PC 3FFE 3FFE 3FFE 3FFE 3FFF 3FFF NEW PC NEW PC NEW PCH PCH t RL 3 NEW PCL OP CODE PCL OP CODE VDD MC68HC(8)05PV8/A -- Rev. 1.9 0v OSC12 tporl INTERNAL PROCESSOR 1 CLOCK INTERNAL ADDRESS 1 BUS Figure 5-2 RESET and POR Timing Diagram Resets INTERNAL DATA 1 BUS RESET NOTES: 1. Internal timing signal and bus information not available externally. 2. OSC1 line is not meant to represent frequency. It is only used to represent time. 3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence. 4. VDD must fall to a level lower than VPOR in order to be recognized as a power on reset. Resets Power-On Reset (POR) Technical Data 81 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 5.7 Computer Operating Properly Reset (COPR) The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. If the COP watchdog timer is allowed to time-out, an internal reset is generated to reset the MCU. Regardless of an internal or external reset, the MCU comes out of a COP reset according to the pin conditions that determine mode selection. The COP reset function is enabled or disabled by the MOR[COPE] bit and is verified during production testing. The COP watchdog reset activates the internal pull-down device connected to the RESET pin. The window COP function can be enabled via the WCOP bit in the system control register. This bit is a write once bit, e.g. the WCOP feature stays enabled until the next system reset. In case of WCOP bit enabled, the COP timer is only reset when the write to the COPEN bit in the mask option register occurs in the second half of the COP watchdog time. A write in the first half causes a system reset with the COPR bit set. The phase of the COP timer can be monitored via the WCP (window COP phase) in the system control register. A 0 indicates that writing to the MOR bit causes system reset. A 1 indicates that writing to the MOR bit causes a reset of the COP timer cycle. NONDISCLOSURE AGREEMENT REQUIRED 5.7.1 Resetting the COP A COP reset is prevented by writing a 0 to the COPR bit. This action resets the counter and begin the time-out period again. The COPR bit is bit 0 of address $3FF0. A read of address $3FF0 returns user data programmed at that location. 5.7.2 COP During WAIT Mode The COP continues to operate normally during WAIT mode. The system should be configured to pull the device out of WAIT mode periodically and reset the COP by writing to the COPR bit to prevent a COP reset. Technical Data 82 Resets MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Resets Computer Operating Properly Reset (COPR) 5.7.3 COP During STOP Mode When the STOP enable mask option is selected, STOP mode disables the oscillator circuit and thereby turns the clock off for the entire device. The COP counter is reset when STOP mode is entered. If a reset is used to exit STOP mode, the COP counter is held in reset during the 4064 cycles of start up delay. If any operable interrupt is used to exit STOP mode, the COP counter is not reset during the 4064 cycle start-up delay and has the number of cycles already counted when control is returned to the program. 5.7.4 COP Watchdog Timer Considerations The COP watchdog timer is active in user mode if enabled by the COPEN bit in the mask option register. If the COP watchdog timer is selected, any execution of the STOP instruction (either intentional or inadvertent due to the CPU being disturbed) causes the oscillator to halt and prevent the COP watchdog timer from timing out. Therefore, it is recommended that the STOP instruction should be disabled if the COP watchdog timer is enabled. If the COP watchdog timer is selected, the COP resets the MCU when it times out. Therefore, it is recommended that the COP watchdog be disabled for a system that must use the WAIT mode for periods longer than the COP time-out period. 5.7.5 COP Register The COP register is shared with the MSB of the contact sense interrupt vector as shown in Figure 5-3. Reading this location returns whatever user data has been programmed at this location. Writing a 0 to the COPR bit in this location clears the COP watchdog timer. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Resets Technical Data 83 NONDISCLOSURE AGREEMENT REQUIRED Technical Data REQUIRED $3FF0 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 COPR Figure 5-3 COP Watchdog Timer Location Register (COPR) 5.8 Illegal Address Reset AGREEMENT An illegal address reset is generated when the CPU attempts to fetch an instruction from either unimplemented address space ($0100 to $017F, $0200 to $1FFF) monitor ROM ($3F00 to $3FEF) or I/O address space ($0000 to $003F). The illegal address reset activates the internal pull-down device connected to the RESET pin. 5.9 Disabled STOP Instruction Reset When the mask option is selected to disable the STOP instruction, execution of a STOP instruction results in an internal reset. This activates the internal pull-down device connected to the RESET pin. NONDISCLOSURE 5.10 High Temperature Reset The internal high temperature (HTR) reset is generated when the die temperature rises above the high temperature threshold THTON. This condition remains active until the temperature falls below the threshold THTOFF. This reset can be disabled by using a mask option. Technical Data 84 Resets MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Resets High Voltage Reset 5.11 High Voltage Reset The internal high voltage (HVR) reset is generated when the supply voltage VSUP rises above the high voltage reset threshold VHVRON. This condition remains active until the supply voltage falls below the threshold VHVROFF. This reset can be disabled by using a mask option. 5.12 Low Voltage Reset The internal low voltage (LVR) reset is generated when the supply voltage VDD falls below the low voltage threshold VLVRON. This condition remains active until the voltage rises above the threshold VLVROFF or a proper power-on sequence occurs. 5.13 Operation in STOP and WAIT Mode If enabled, all reset sources remain active during STOP and WAIT. Any reset source can bring the MCU out of STOP or WAIT modes. Since no instructions are executed in WAIT or STOP mode the illegal address reset and the stop disabled reset cannot become active in STOP or WAIT mode. Since the core timer is not active in STOP mode, the COP reset cannot become active in STOP mode. On 68HC05PV8A, generation of HVR and HTR are suppressed if the ultra low power mode is selected by setting the ULPM bit. 5.14 Clock Monitor Reset (CMR) The clock monitor reset is based on an internal RC time delay. If no MCU clock edges are detected within this RC time delay, the clock monitor can optionally generate a system reset. The system clock is then automatically switched to an on-chip RC oscillator. The clock monitor function is enabled via a mask option bit. Clock monitor is used as a MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Resets Technical Data 85 NONDISCLOSURE AGREEMENT REQUIRED Technical Data backup for the COP system. Because the COP needs a clock to function it is disabled when the clock stops. Therefore, the clock monitor system can detect clock failures not detected by the COP system. Semiconductor wafer processing causes variations of the RC timeout values between individual devices. A processor clock frequency below 10 KHz is detected as a clock monitor error. A processor clock frequency of 400 KHz or more prevents clock monitor errors. Using the clock monitor when the processor clock is below 400 KHz is not recommended. The oscillator used for deriving the system clock can be determined by the RCON Bit in the interrupt status register. AGREEMENT REQUIRED $0029 Read: Write: Reset: Bit 7 RCON 6 PC4CL 5 0 4 0 3 0 2 HTIF 1 HVIF Bit 0 LVIF U 0 0 0 0 0 0 0 Figure 5-4 Interrupt Status Register (INTSR) NONDISCLOSURE 5.14.1 Clock Monitor in STOP mode If STOP mode is entered, the clock monitor function is frozen. If the device is woken from STOP mode, it continues to use the same oscillator as before entering STOP. For the STOP mode recovery time of 4064 clock cycles, the clock monitor function is also suspended. If the device uses an external oscillator before entering STOP mode and this oscillator breaks during STOP, the device will no longer restart. Technical Data 86 Resets MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data -- MC68HC(8)05PV8/A Section 6. Operating Modes 6.1 Contents 6.2 6.3 6.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 User mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 6.5.1 STOP Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 6.5.1.1 Ultra Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.5.2 STOP Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.6 WAIT Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.2 Introduction The normal operating mode of the MC68HC(8)05PV8/A is user (or single chip) mode. There is also a monitor mode, primarily for programming and evaluation purposes. In addition to these modes, there are two low power modes which may be entered and exited at will from user mode: STOP and WAIT. Table 6-1 shows the conditions required to enter the modes of operation on the rising edge of RESET, where VTST = 2 x VDD. Table 6-1 Operating Mode Entry Conditions IRQ VSS to VDD VTST PB0 VSS to VDD VDD Mode User Monitor MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Operating Modes Technical Data 87 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 6.3 User mode Intended mode of operation for executing user firmware. REQUIRED 6.4 Monitor Mode Used for programming the on-chip Program or Data EEPROM (68HC805PV8) and Data EEPROM (68HC05PV8) if desired. AGREEMENT 6.5 Low Power Modes The MC68HC(8)05PV8/A is capable of running in one of several low-power operational modes. The WAIT and STOP instructions provide two modes that reduce the power required for the MCU by stopping various internal clocks and/or the on-chip oscillator. The flows of the STOP and WAIT modes are shown in Figure 6-2. 6.5.1 STOP Mode The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the internal oscillator is turned off, halting all internal processing, including timer (and COP watchdog timer) operation. During STOP mode, the core timer interrupt flags and interrupt enable bits of the CTCSR register are cleared by internal hardware to remove any pending timer interrupt requests and to disable any further timer interrupts. The timer pre-scaler is also cleared. The I bit in the CCR is cleared to enable external interrupts. All other registers, including the remaining bits in the CTCSR, and memory remain unaltered. All input/output lines remain unchanged. The processor can be brought out of the STOP mode only by an external interrupt or RESET. The STOP instruction can be disabled by a mask option. When disabled, the STOP instruction causes a system reset. NONDISCLOSURE Technical Data 88 MC68HC(8)05PV8/A -- Rev. 1.9 Operating Modes MOTOROLA Operating Modes Low Power Modes 6.5.1.1 Ultra Low Power Mode The Ultra Low Power Mode is only available on the 68HC05PV8A. It is a submode to STOP mode. The ULPM bit in the Interrupt Control Register influences the onchip analogue circuits. On setting the ULPM bit, PC0 .. PC4 is forced to input state, PC5/6 is switched off, opamp is debiased, downscaler, power supply and die temperature monitors are disabled. It is mandatory to set the ULPM bit in the last instruction prior to executing the STOP instruction and should be reset immediately after recovering from stop to utilize the ultra low power mode. When the mcu is stopped, the main voltage regulator is switched off and the mcu is supplied by a standby regulator. On any interrupt or reset, the main regulator is switched on again and the normal STOP mode recovery procedure is started as soon as VDD has reached the low voltage reset threshold. 6.5.2 STOP Recovery The processor can be brought out of the STOP mode by an external interrupt, an environmental exception interrupt, a walk-up interrupt or RESET. See Figure 6-1. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Operating Modes Technical Data 89 NONDISCLOSURE AGREEMENT REQUIRED Technical Data REQUIRED 1 OSC1 tRL RESET 2 IRQ tLIH AGREEMENT 3 IRQ tILCH 4064 tcyc INTERNAL CLOCK INTERNAL ADDRESS BUS 3FFE 3FFE 3FFE 3FFE 3FFF Notes: 1. Represents the internal gating of the OSC1 pin. 2. IRQ pin edge-sensitive mask option or Port A pin. 3. IRQ pin level and edge sensitive mask option. RESET OR INTERRUPT VECTOR FETCH (RESET SHOWN) NONDISCLOSURE Figure 6-1 Stop Recovery Timing Diagram Technical Data 90 Operating Modes MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Operating Modes WAIT Mode STOP WAIT STOP OSCILLATOR AND ALL CLOCKS CLEAR I BIT OSCILLATOR ACTIVE TIMER CLOCK ACTIVE PROCESSOR CLOCKS STOPPED N RESET OR HVR OR LVR RESET OR HVR OR LVR N N IRQ PORT A OR C HVI, LVI Y Y Y IRQ PORT A OR C HVI, LVI Y N 16B TIMER, CORE TIMER Y INTERRUPT Y N TURN ON OSCILLATOR WAIT FOR TIME DELAY TO STABILIZE RESTART PROCESSOR CLOCK Figure 6-2 STOP and WAIT Flowcharts 6.6 WAIT Mode The WAIT instruction places the MCU in a low-power consumption mode. All CPU action is suspended, but the core timer, the 16-bit timer (controlled by TOFF bit) and the PWM will or can remain active. An interrupt, if enabled, from the core timer or any peripheral still active in WAIT mode causes the MCU to exit WAIT mode. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Operating Modes Technical Data 91 NONDISCLOSURE 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE AGREEMENT REQUIRED Technical Data During WAIT mode the I bit in the CCR is cleared to enable interrupts. All other registers, memory and input/output lines remain in their previous state. The core timer may be enabled to allow a periodic exit from the WAIT mode. WAIT mode consumes more power than STOP mode. NONDISCLOSURE Technical Data 92 Operating Modes AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data -- MC68HC(8)05PV8/A Section 7. Input/Output Ports 7.1 Contents 7.2 7.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 General Input/Output Programming . . . . . . . . . . . . . . . . . . . . . 94 7.4 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.4.1 Port A Keyboard Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.4.2 Port A Pull-up Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.4.3 Port A Voltage Reference for A/D Converter. . . . . . . . . . . . 96 7.4.4 Port A Configuration Register . . . . . . . . . . . . . . . . . . . . . . . 97 7.4.5 Port A Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . 98 7.4.6 Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.5 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.5.1 Port B Timer Channels and XOR Function . . . . . . . . . . . . 100 7.5.2 Port B PWM Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.5.3 I/O Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . 101 7.6 Port C (High Voltage Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.6.1 Port C Timer Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.6.2 Port C PWM Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.6.3 Port C Contact Sense Circuitry . . . . . . . . . . . . . . . . . . . . . 103 7.6.4 Port C ISO9141 Interface . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.6.5 Port C Low Side Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.6.6 Port C Configuration Register 0 . . . . . . . . . . . . . . . . . . . . 109 7.6.7 Port C Configuration Register 1 . . . . . . . . . . . . . . . . . . . . 113 7.6.8 Port C Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.6.9 MFTEST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Technical Data 93 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 7.2 Introduction In single chip mode there are 20 lines arranged as one 8-bit I/O port (port A), one 5-bit I/O port (port B), and one 7-bit high-voltage I/O port (port C). The I/O ports are programmable as either inputs or outputs under software control of the data direction registers (see 7.3 General Input/Output Programming). Port A is shared with A/D channels. Ports B and C are shared with timer and PWM channels. Port C comprises 5 lines with contact sensors and 2 lines with low side drivers. AGREEMENT REQUIRED 7.3 General Input/Output Programming Bidirectional port lines may be programmed as an input or an output under software control. The direction of the pins is determined by the state of the corresponding bit in the port data direction register (DDR). Each port has an associated DDR. Any I/O port pin is configured as an output if its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding DDR bit is cleared to a logical zero (see Table 7-1 and Figure 7-1). At power-on or reset, all DDRs are cleared, thus configuring all port pins as inputs. Reset does not affect the state of the data bits, thus after power-on reset their state is unknown. The data direction registers are capable of being written to or read by the processor. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin. Table 7-1 I/O Pin Functions R/W(1) 0 0 1 1 DDR 0 1 0 1 I/O Pin Function The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch and output to the I/O pin. The state of the I/O pin is read. The I/O pin is in output mode. The output data latch is read. NONDISCLOSURE 1. R/W is an internal signal Technical Data 94 Input/Output Ports MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Port A Data Direction Register Bit Internal HC05 Connections Latched Output Data Bit Output I/O Pin Input Reg Bit Input I/O Figure 7-1 Port I/O Circuitry NOTE: NOTE: To avoid a glitch on the output pins, write data to the I/O port data register before writing a one to the corresponding data direction register. If the I/O pin is an input and a read-modify-write (RMW) instruction is executed, the I/O pin will be read into the HC05 CPU and the computed result will then be written to the data latch. 7.4 Port A Port A is an 8-bit bidirectional port (PA0-7) with interrupt capability, shared with the A/D converter (AN1-6, VREFL, VREFH). The port A data register is located at $0000 and the data direction register (DDR) at $0004. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. When the A/D converter is turned on, one of the channels AN1-6 may be selected through the A/D status and control register for conversion. The input lines of port A include software programmable pull-up resistors. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Technical Data 95 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 7.4.1 Port A Keyboard Interrupt The keyboard interrupt consists of 8 individual edge-sensitive interrupts with 8 interrupt flags. The keyboard interrupt is generated by a logical OR function of the 8 interrupt flags. The interrupt inputs are connected to PA0-7. All interrupts are maskable. If the interrupt mask bit (I bit) in the condition code register is set, all interrupts are disabled. The interrupts are split in two groups of four lines each (PA0-3 and PA4-7). All interrupts of one group can be simultaneously masked by the corresponding PAIE bits in the port A configuration register. The trigger edges of the interrupt lines are selectable for each group with the EDGE bits in the port A configuration register. The port A interrupt status register indicates which interrupt request is pending. AGREEMENT REQUIRED 7.4.2 Port A Pull-up Resistors The PA0-7 input lines have internal pull-up resistors. The port A lines form two groups with four lines each (PA0-3 and PA4-7). All pull-ups of one group can be switched on with the PULEN or PUHEN bits of the port A configuration register by resetting the bit to 0. They are disabled * * when the enable bit is set to 1 when a line is configured as output. NONDISCLOSURE 7.4.3 Port A Voltage Reference for A/D Converter The lines PA0 and PA7 can be connected to the reference inputs for the A/D converter (VREFL and VREFH). In order to connect the reference inputs, the corresponding VRHEN or VRLEN bits of the port A configuration register have to be set. In addition, the corresponding lines (PA0 or PA7) must be configured as inputs. The pull-up resistor should be disabled when a line is used as A/D input or A/D reference channel. Technical Data 96 Input/Output Ports MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Port A 7.4.4 Port A Configuration Register $0020 Read: VRHEN Write: Reset: 0 0 0 0 0 0 0 0 PUHEN EDGEH PAHIE PULEN EDGEL PALIE VRLEN Bit 7 6 5 4 3 2 1 Bit 0 Figure 7-2 Port A Configuration Register (PACFG) VRHEN - Enable A/D High Reference Channel Those bits connect the PA7 pin with the A/D high reference channel. 1 = A/D high reference channel connected to external VREFH. 0 = A/D high reference channel connected to internal voltage supply. PUHEN - PA4-7 Pull-Up Resistor Enable Higher Nibble This bit disables/enables the pull-up resistors of the PA4-7 pins. 1 = PA4-7 pull-up resistors disabled 0 = PA4-7 pull-up resistors enabled EDGEH - PA4-7 Interrupt Edge Higher Nibble This bit selects the trigger edges of the interrupt lines PA4-7. 1 = Rising edge sensitive 0 = Falling edge sensitive PAHIE - PA4-7 Interrupt Enable Higher Nibble This bit disables/enables the PA4-7 pins as an interrupt group. 1 = PA4-7 interrupt enabled 0 = PA4-7 interrupt disabled PULEN - PA0-3 Pull-Up Resistor Enable Lower Nibble This bits disables/enables the pull-up resistors of the PA0-3 pins. 1 = PA0-3 pull-up resistors disabled 0 = PA0-3 pull-up resistors enabled EDGEL - PA0-3 Interrupt Edge Lower Nibble This bit selects the trigger edges of the interrupt lines PA0-3. 1 = Rising edge sensitive 0 = Falling edge sensitive MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Technical Data 97 NONDISCLOSURE AGREEMENT REQUIRED Technical Data PALIE - PA0-3 Interrupt Enable Lower Nibble This bit disables/enables the PA0-3 pins as interrupt group. 1 = PA0-3 interrupt enabled 0 = PA0-3 interrupt disabled VRLEN - Enable A/D Low Reference Channel This bit connects the PA0 pin with the A/D low reference channel. 1 = A/D low reference channel connected to external VREFL. 0 = A/D low reference channel connected to internal ground. 7.4.5 Port A Interrupt Status Register $0024 Read: PAIF7 Write: Reset: 0 0 0 0 0 0 0 0 PAIF6 PAIF5 PAIF4 PAIF3 PAIF2 PAIF1 PAIF0 Bit 7 6 5 4 3 2 1 Bit 0 AGREEMENT REQUIRED Figure 7-3 Port A Interrupt Status Register (PAISR) PAIF0-7 - Port A Interrupt Flags These flags indicate which of the port A interrupt requests is pending. The 8 interrupt flags can be reset individually if a 1 is written to the bit position. 1 = Flag set when corresponding transition is sensed (if interrupt enabled). Writing a 1 clears the flag 0 = No interrupt. Writing a 0 has no effect 7.4.6 Operational Amplifier Pins PA4-6 are connected to an operational amplifier. The operational amplifier is intended for amplifying small signals over VSS to increase the resolution of the A/D converter. The output stage of this operational amplifier is asymmetrical and thus optimized for driving loads to VSS while keeping the quiescent current low. The output of the operational amplifier is connected to channel 4 of the A/D converter. The amplifier is enabled by the I/O configuration register Bit6. As long as IOCFG Bit6 is 0, the presence of the operational amplifier is without any effect. If the opamp is enabled, first ensure that the PA4 is switched to input mode. Technical Data 98 Input/Output Ports MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA NONDISCLOSURE Input/Output Ports Port A NOTE: PA6 + PA5 - IOCFG Bit6 PA4 Figure 7-4 Operational Amplifier PA6 M Vin + PA5 - Shunt Resistor to A/D Vout PA4 VSS again= R2 + R1 R1 Figure 7-5 Typical application: positive Vgain amplifier * * * * Keep Vin limited between VSS and VDD For precise measurements, R1 + R2 should be in the range of 50k and the Vout should not reach VDD External loads should be connected to ground, due to small current sinking capability. In case of Vin x gain >= VDD (i.e. the output of the operational amplifier cannot follow the input anymore) channel 6 (input) should be converted to read the input voltage Vin directly. Technical Data Input/Output Ports 99 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA NONDISCLOSURE AGREEMENT R1 R2 REQUIRED Pull-up resistors on PA4-6 should be disabled when using the operational amplifier. Technical Data 7.5 Port B Port B is a 5-bit bidirectional port, shared with timer and PWM channels (TCAP, TCMP, PWM). An XOR function is provided for one timer capture channel. The port B data register is at $0001 and the data direction register (DDR) is at $0005. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. AGREEMENT REQUIRED 7.5.1 Port B Timer Channels and XOR Function The port pins PB0-PB3 are shared with the 16-bit timer channels (TCAP1-2, TCMP1-2). The timer capture channel TCAP1 can be driven by the XOR of two channels if TXOR bit in the I/O Configuration Register is set (see Figure 7-6).TCAP1 status can be read by the CPU by polling bit 5 of the Port B Data Register. FROM PC0 OR C4 0 NONDISCLOSURE 1 PB0 PB0IC 0 Capture 1 TCAP1 TXOR 0 Capture 1 PB2 PB2IC Channel 2 Channel 1 PC2 Figure 7-6 Mapping Ports to Timer Capture Channels Technical Data 100 Input/Output Ports MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Port B 7.5.2 Port B PWM Channel The port pin PB4 is shared with the PWM channel. In order to connect this pin to the PWM channel, the corresponding bit PWM4 of the I/O configuration register must be set. 7.5.3 I/O Configuration Register $0021 Read: TXOR Write: Reset: 0 0 0 0 0 0 0 0 OPAMP PB4PW PB3OC PB2IC PB1OC PB0IC Bit 7 6 5 4 3 2 1 Bit 0 Figure 7-7 I/O Configuration Register (IOCFG) TXOR - Timer EXOR Enable This bit enables the EXOR of the TCAP1 channel 1 = EXOR enabled 0 = EXOR disabled OPAMP - Enable Operational Amplifier This bit enables the operational amplifier on PA6 1 = Opamp enabled 0 = Opamp disabled PB4PW - PB4 PWM Enable This bit enables the PB4 pin as PWM output. 1 = PB4 PWM enabled. PBDD4 bit must be set in order to drive the output 0 = PB4 PWM disabled PB3OC - PB3 Output Compare Enable This bit enables the PB3 pin for output compare channel 2. 1 = PB3 output compare channel 2 enabled. PBDD3 bit must be set in order to drive the output 0 = PB3 output compare channel 2 disabled MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Technical Data 101 NONDISCLOSURE AGREEMENT REQUIRED Technical Data PB2IC - PB2 Input Capture Enable This bit enables the PB2 pin to drive the input capture channel 2. 1 = PB2 drives the input capture channel 2 0 = PC2 drives the input capture channel 2 PB1OC - PB1 Output Compare Enable This bit enables the PB1 pin for output compare channel 1. 1 = PB1 output compare channel 1 enabled. PBDD1 bit must be set in order to drive the output 0 = PB1 output compare channel 1disabled PB0IC - PB0 Input Capture Enable This bit enables the PB0 pin to drive the input capture channel 1. 1 = PB0 drives the input capture channel 1 0 = PC0 or PC4 drives the input capture channel 1 AGREEMENT REQUIRED 7.6 Port C (High Voltage Port) Port C is a 7-bit multifunctional and bidirectional port (PC0-6) with high voltage capability. The port is shared with timer and PWM channels (TCAP, TCMP, PWM) and provides a special contact sense feature with interrupt capability. In addition, port C comprises a low ohmic two channel low side driver with internal Zener diode turn-off for switching inductive loads. The port C data register is at $0002 and the data direction register (DDR) is at $0006. Reset does not affect the data registers, but clears the data direction registers, thereby returning the PC0-4 to high voltage inputs, PC5 and PC6 are switched to the off state. Writing a one to a DDR bit sets the corresponding port bit to output or contact sense mode. The port C pins PC5-6 are open drain outputs only without internal pull-ups. The voltage levels of PC0-4 I/O signals are related to the VSUP and VSS levels respectively. PC5-6 have an additional power supply pin for VSS (PVSS) to which the low side drivers relate. NONDISCLOSURE Technical Data 102 MC68HC(8)05PV8/A -- Rev. 1.9 Input/Output Ports MOTOROLA Input/Output Ports Port C (High Voltage Port) 7.6.1 Port C Timer Channels The port pins PC0-5 are shared with the 16-bit timer channels (TCAP1-2, TCMP1-2). 7.6.2 Port C PWM Channel The port pins PC0, 4-6 are shared with the PWM channel. In order to connect those pins, please refer to 7.6.6 Port C Configuration Register 0 for details. 7.6.3 Port C Contact Sense Circuitry The port C pins PC0-4 have a special contact sense circuit (see Figure 7-8, Figure 7-9, Figure 7-10). This feature allows, for example, the monitoring of mechanical contacts in automotive applications (switch monitor). VSUP CSDT IPIN DDR PC0 DATA Contact CSEN&DATA&DDRC Sense VSS Figure 7-8 PC0 Contact Sense Circuitry MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Technical Data 103 NONDISCLOSURE Interrupt REXT AGREEMENT REQUIRED Technical Data REQUIRED VSUP CSEN&DATA&DDRC CSDT Contact Sense Interrupt IPIN DDR PC1-3 DATA REXT AGREEMENT Contact CSEN&DATA&DDRC Sense VSS Figure 7-9 PC1-3 Contact Sense Circuitry VSUP CSEN&DATA&DDRC CSDT Interrupt Contact Sense NONDISCLOSURE ISOMODE IPIN REXT DDR PC4 DATA VSS Figure 7-10 PC4 Contact Sense Circuitry 68HC(8)05PV8 Technical Data 104 Input/Output Ports MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Port C (High Voltage Port) CSDT Interrupt PC4 DDR DATA VSS Figure 7-11 PC4 Circuitry 68HC05PV8A Port pin PC0 comprises a circuit that senses the outside resistance RPIN to VSUP. PC4 has a different circuit, which senses the outside resistance RPIN to VSS (only on 68HC(8)05PV8). PC1, PC2 and PC3 have an universal one, which senses the outside resistance either to VSS or to VSUP, depending on the state of the corresponding data register bit. The contact sense circuitry is enabled by setting the corresponding bits PC4CS, PC3CS, PC2CS, PC1CS or PC0CS of the port C configuration register to 1. In addition, the pin has to be configured as an output by setting the corresponding DDR bit to 1 and the data bit to 0 (for RPIN to VSUP, e.g. external switch to VSUP) or to 1 (for RPIN to VSS, e.g. external switch to VSS). If the outside resistance RPIN is lower than the specified value, the contact sense circuitry interprets this as a logical 1. The principal sense characteristic is given in Figure 7-12. The result of this sense operation is given by the bits CSD4, CSD3, CSD2, CSD1 and CSD0 of the port C status register. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Technical Data 105 NONDISCLOSURE AGREEMENT REQUIRED Technical Data REQUIRED Contact Sense Data Bit CSD4-0 1 0 Outside Resistance Figure 7-12 Principal Characteristic of the Contact Sense Circuitry When setting PCXCS and clearing the corresponding DDR bit, the signal generated by the high voltage input block is used instead of the one of the contact sense block to drive the CSD bits. The CSD bits will in this case reflect a logical 1 if the corresponding input voltage is below HVIL, and a logical 0 if the input voltage is above HVIH. A contact sense interrupt is generated if the status of any CSD bit changes with the corresponding PCXCS bit set. The interrupt trigger occurs on both edges of the CSD bit change and sets the CSIF flag in the port C status register. The interrupt can be masked by the CSIE bit of the port C configuration register. An external resistor has to be placed in serial to PC0-4 because of two reasons: * * limit internal power dissipation, internal substrate current injection may occur if the pin voltage is out of the supply voltage range. NONDISCLOSURE AGREEMENT 7.6.4 Port C ISO9141 Interface To use Port C4 as an ISO9141 physical interface, Port C4 must be always programmed as an output. This automatically enables the biasing circuit for the ISO9141 driver. Furthermore, the ISOM bit in the Port C Configuration Register 0 has to be set. This driver incorporates an overcurrent limitation circuit. Because of excessive power dissipation Technical Data 106 Input/Output Ports MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Port C (High Voltage Port) $0029 Read: Write: Reset: Bit 7 RCON 6 PC4CL 5 0 4 0 3 0 2 HTIF 1 HVIF Bit 0 LVIF NA 0/1 0 0 0 ? 0 0 Figure 7-13 Interrupt Status Register (INTSR) MC68HC(8)05PV8 (maskset J47D and J31D): PC4CL - Port C4 in current limit mode 1 = current on PC4 exceeds limit 0 = current on PC4 below limit MC68HC05PV8A (maskset K20R): PC4CL - Port C4 in current limit mode 1 = current on PC4 below limit 0 = current on PC4 exceeds limit If the timer input capture 1 is configured to Port C4, the state of the PC4 pin is transfered to the timer module input capture, the input status can be polled by reading the TCAP1 bit in the Port B Data Register. 7.6.5 Port C Low Side Driver The port C pins PC5-6 comprise of two low side driver channels which are shared with the PWM function. The channels can either be controlled directly by the data register or are linked to the PWM function (see 7.6.2 Port C PWM Channel). The low side driver channels are open-drain outputs with an internal Zener diode. The diode clamps the maximum output voltage and limits the turn-off time of inductive loads (see Figure 7-14). MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Technical Data 107 NONDISCLOSURE AGREEMENT REQUIRED the software should take care to switch off the driver as soon as possible whenever a short-circuit occurs. To detect such a condition the PC4CL (Bit 6) in the Interrupt Status Register should be polled. Technical Data REQUIRED VSUP Solenoid Fast Turn-Off Zener Diode PC5-6 LDMOS AGREEMENT PVSS Figure 7-14 Principle of Port C Low Side Driver A permanent external pin voltage above the minimum Zener break-down voltage can destroy the driver. The low side drivers have a short circuit protection feature. Whenever the drain current of the LDMOS transistor exceeds a fixed value, the output is automatically switched off (i.e. the LDMOS is in the high impedance state) and the corresponding short circuit flag is set (SCIF5 or SCIF6). If the SCIE5/6 bits are enabled, an interrupt occurs. As long as the SCIF5/6 bits are set, the output cannot be switched on. These bits are cleared by writing a logical 1 to the corresponding bit location. The outputs are also protected by a common over temperature detection. See Figure 7-15 for details. NONDISCLOSURE Technical Data 108 MC68HC(8)05PV8/A -- Rev. 1.9 Input/Output Ports MOTOROLA Input/Output Ports Port C (High Voltage Port) PORT C DATA PC6-5 SOUT DRIVE CONTROL SCIF5/6 OVERCURRENT DETECTION PVSS Figure 7-15 Short Circuit Diagnostic of Port C Low Side Driver 7.6.6 Port C Configuration Register 0 $0022 Read: ISOM Write: Reset: 0 0 0 0 0 0 0 0 PC6PW PWMS1 PWMS0 PC3OC TS2 TS1 TS0 Bit 7 6 5 4 3 2 1 Bit 0 Figure 7-16 Port C Configuration Register 0 (PCCFG0) ISOM - Driver Mode of PC4 This bit selects the driver mode of PC4. The ISOM bit is without function on 68HC05PV8A. 1 = ISO9141 compatible output (low side driver only) 0 = PC4 is a push-pull output PC6PW - PC6 PWM Enable This bit enables the PC6 pin as PWM output. 1 = PC6 PWM enabled. 0 = PC6 PWM disabled MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Technical Data 109 NONDISCLOSURE AGREEMENT REQUIRED Technical Data PWMS1, PWMS0 - PWM Select Bits These bits select the output pin for the PWM on PC0, PC4 or PC5. Table 7-2 PWM Select PWMS1 0 0 1 1 PWMS0 0 1 0 1 PWM Output at Port C none PC0 PC4 PC5 AGREEMENT REQUIRED PC3OC - PC3 Output Compare Enable This bit enables the PC3 pin for output compare channel 2. 1 = PC3 output compare channel 2 enabled. PC3 DDR bit must be set in order to drive the output 0 = PC3 output compare channel 2 disabled TS2, TS1, TS0 - Timer Channel 1 Select Bits These bits select the input and output pins for the timer channel 1. Table 7-3 Timer Channel 1 Select NONDISCLOSURE TS2 0 0 0 0 1 1 1 1 TS1 0 0 1 1 0 0 1 1 TS0 0 1 0 1 0 1 0 1 Output Compare at PCX none, Bit I/O none, Bit I/O PC0 PC0 PC1 PC1 PC4 PC5 Input Capture at PCX PC0 PC4 PC0 PC4 PC0 PC4 PC4 PC4 NOTE: If PC0, PC1, PC4 and PC5 are neither switched to PWM nor to timer output compare, the output states of these pins follow the states of their data register bits. MC68HC(8)05PV8/A -- Rev. 1.9 Input/Output Ports MOTOROLA Technical Data 110 Input/Output Ports Port C (High Voltage Port) If PWM and timer output compare functions are routed to the same pin, PC0 and PC4 would be connected to the output compare signal, PC5 would be connected to the PWM signal. For using the input capture be sure that the PB0IC bit in the I/O configuration register is set to 0, and the corresponding pin PC0 or PC4 is switched to input mode. PC4 may also be in the ISO9141 compatible mode. For using the contact sense function, it is not recommended to route any special signal to the corresponding pins. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Technical Data 111 NONDISCLOSURE AGREEMENT REQUIRED To enable either PWM or output compare function the corresponding DDR bit must be set to 1. Technical Data REQUIRED TXOR TIC1 PB0OC PB0 TS2,1,0 PC0 PB2OC PB2 TIC2 PC1 PC2 PC3 AGREEMENT PC4 PC3OC TOC2 PC6PW PWM PWMS1,0 PC6 PC5 TS2,1,0 NONDISCLOSURE TOC1 DDRC, TS2,1,0, PWS1,0 Port C Data 0 Port C Data 1 Port C Data 2 Port C Data 3 Port C Data 4 Port C Data 5 Port C Data 6 Figure 7-17 Port C Special Signal Routing Technical Data 112 Input/Output Ports MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Port C (High Voltage Port) 7.6.7 Port C Configuration Register 1 $0026 Read: CSIE Write: Reset: 0 0 0 0 0 0 0 0 SCIE6 SCIE5 PC4CS PC3CS PC2CS PC1CS PC0CS Bit 7 6 5 4 3 2 1 Bit 0 Figure 7-18 Port C Configuration Register 1 (PCCFG1) CSIE - Port C Contact Sense Interrupt Enable This bit enables contact sense interrupt of the lines PC4-0. 1 = Port C contact sense interrupt enabled 0 = Port C contact sense interrupt disabled SCIE6 - Low Side Driver Short Circuit Interrupt Enable This bit enables short circuit interrupt of the low side driver PC6. 1 = Low side driver short circuit interrupt enabled 0 = Low side driver short circuit interrupt disabled SCIE5 - Low Side Driver Short Circuit Interrupt Enable This bit enables short circuit interrupt of the low side driver PC5. 1 = Low side driver short circuit interrupt enabled 0 = Low side driver short circuit interrupt disabled PC4CS - PC4 Contact Sense Enable This bit enables the PC4 contact sense circuitry. 1 = PC4 contact sense circuitry enabled 0 = PC4 contact sense circuitry disabled PC3CS - PC3 Contact Sense Enable This bit enables the PC3 contact sense circuitry. 1 = PC3 contact sense circuitry enabled 0 = PC3 contact sense circuitry disabled PC2CS - PC2 Contact Sense Enable This bit enables the PC2 contact sense circuitry. 1 = PC2 contact sense circuitry enabled 0 = PC2 contact sense circuitry disabled MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Technical Data 113 NONDISCLOSURE AGREEMENT REQUIRED Technical Data PC1CS - PC1 Contact Sense Enable This bit enables the PC1 contact sense circuitry. 1 = PC1 contact sense circuitry enabled 0 = PC1 contact sense circuitry disabled PC0CS - PC0 Contact Sense Enable This bit enables the PC0 contact sense circuitry. 1 = PC0 contact sense circuitry enabled 0 = PC0 contact sense circuitry disabled AGREEMENT REQUIRED 7.6.8 Port C Status Register $0027 Read: CSIF Write: Reset: 0 0 0 0 0 0 0 0 SCIF6 SCIF5 Bit 7 6 5 4 CSD4 3 CSD3 2 CSD2 1 CSD1 Bit 0 CSD0 Figure 7-19 Port C Status Register (PCSTR) CSIF - Port C Contact Sense Interrupt Flag This flag indicates that a contact sense transition has occurred and an interrupt request is pending. The flag can be cleared by writing a 1 to it. 1 = Flag set when a transition is sensed by the contact sense circuitry 0 = No interrupt SCIF6 - Low Side Driver Short Circuit Interrupt Flag This flag indicates a short circuit on PC6 is active and an interrupt request is pending. 1 = Short circuit at the PC6 pin; PC6 is switched to high impedance 0 = No short circuit at the PC6 pin NONDISCLOSURE Technical Data 114 MC68HC(8)05PV8/A -- Rev. 1.9 Input/Output Ports MOTOROLA Input/Output Ports Port C (High Voltage Port) SCIF5 - Low Side Driver Short Circuit Interrupt Flag This flag indicates a short circuit on PC5 is active and an interrupt request is pending. 1 = Short circuit at the PC5 pin; PC5 is switched to high impedance 0 = No short circuit at the PC5 pin CSD4 - PC4 Contact Sense Data This data bit represents the result of the PC4 contact sense circuitry. 1 = Low resistance sensed (see Figure 7-12), or input PC4 is 0. 0 = High resistance sensed CSD3 - PC3 Contact Sense Data This data bit represents the result of the PC3 contact sense circuitry. 1 = Low resistance sensed (see Figure 7-12), or input PC3 is 0. 0 = High resistance sensed CSD2 - PC2 Contact Sense Data This data bit represents the result of the PC2 contact sense circuitry. 1 = Low resistance sensed (see Figure 7-12), or input PC2 is 0. 0 = High resistance sensed CSD1 - PC1 Contact Sense Data This data bit represents the result of the PC1 contact sense circuitry. 1 = Low resistance sensed (see Figure 7-12), or input PC1 is 0. 0 = High resistance sensed CSD0 - PC0 Contact Sense Data This data bit represents the result of the PC0 contact sense circuitry. 1 = Low resistance sensed (see Figure 7-12), or input PC0 is 0. 0 = High resistance sensed MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Input/Output Ports Technical Data 115 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 7.6.9 MFTEST Register $002F Read: HVTOFF Write: Reset: 0 0 0 0 0 0 0 0 VSCAL LSOFF VT2 VT1 VT0 Bit 7 6 5 4 3 2 1 Bit 0 REQUIRED Figure 7-20 MFTEST Register (MFTEST) HVTOFF - Disable of Port C Inputs This data bit controls the operation of the Port C Inputs 1 = Port C High Voltage Inputs (PC0 - PC4) disabled 0 = Port C High Voltage Inputs enabled VSCAL - Disable of VSUP Scaler Circuit This data bit controls the operation of the VSUP scaler circuit 1 = VSUP scaler disabled, this mode saves power consumption 0 = VSUP scaler enabled, VSUP can be measured using the A/D converter channel 7 LSOFF - Low Side Drivers Off This data bit controls the operation of PC5-6 and the temperature sensor block 1 = PC5-6 and temperature block disabled to minimize power consumption 0 = PC5-6 and and temperature block enabled VT2, VT1, VT0 - Voltage Regulator Trimming Bits Refer to 12.5 Trimming the Voltage Regulator. NONDISCLOSURE Technical Data 116 AGREEMENT MC68HC(8)05PV8/A -- Rev. 1.9 Input/Output Ports MOTOROLA Technical Data -- MC68HC(8)05PV8/A Section 8. Core Timer 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.4 8.5 Core Timer During WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Core Timer During STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.2 Introduction The core timer for this device is a 15-stage multi-functional ripple counter. The features include timer over flow, power-on reset (POR), real time interrupt (RTI), and COP watchdog timer. As seen in Figure 8-1, the timer is driven by the output of the clock select circuit followed by a fixed divide by four pre-scaler. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by accessing the timer counter register (TCR) at address $09. A timer overflow function is implemented on the last stage of this counter, giving a possible interrupt at the rate of fop/1024. Two additional stages produce the POR function after 4064 clks (if selected). The timer counter bypass circuitry (available only in test mode) is at this point in the timer chain. This circuit is followed by two more stages, with the resulting clock (fop/16384) driving the real time interrupt circuit. The RTI circuit consists of three divider stages with a 1 of 4 selector. The output of the RTI circuit is further divided by eight to drive the mask optional COP watchdog timer circuit. The RTI rate selector bits, and the MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Core Timer Technical Data 117 NONDISCLOSURE AGREEMENT 8.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.3.1 Core Timer Status & Control Register (CTSCR) . . . . . . . .119 8.3.2 Computer Operating Properly (COP) Watchdog Reset. . . 121 8.3.3 Core Timer Counter Register (CTCR). . . . . . . . . . . . . . . . 121 REQUIRED Technical Data RTI and TOF enable bits and flags are located in the timer status and control register at location $08. REQUIRED INTERNAL BUS 8 8 8 Internal Processor Clock COP Clear $9 TCR Timer Counter Register (TCR) TCR fop fop/22 /4 AGREEMENT fop/210 7-bit counter POR TCBP RTI Select Circuit Overflow Detect Circuit NONDISCLOSURE $08 TCSR Timer Control/Status Register TCSR TOF RTIF TOFE RTIE RTOF RRTIF RT1 RT0 COP Watchdog Interrupt Circuit Timer (/8) To Interrupt Logic To Reset Logic Figure 8-1 Core Timer Block Diagram Technical Data 118 Core Timer MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Core Timer Registers 8.3 Registers 8.3.1 Core Timer Status & Control Register (CTSCR) The CTSCR contains the timer interrupt flag, the timer interrupt enable bits, and the real time interrupt rate select bits. Figure 8-2 shows the value of each bit in the CTSCR when coming out of reset. $0008 Read: Write: Reset: 0 0 0 0 Bit 7 TOF 6 RTIF TOFE RTIE RTOF 0 RRTIF 0 1 1 5 4 3 0 2 0 RT1 RT0 1 Bit 0 Figure 8-2 Core Timer Status and Control Register (CTSCR) TOF - Timer Over Flow TOF is a read-only status bit and is set when the 8-bit ripple counter rolls over from $FF to $00. A CPU interrupt request will be generated if TOFE is set. Reset clears TOF. RTIF - Real Time Interrupt Flag The real time interrupt circuit consists of a three stage divider and a 1 of 4 selector. The clock frequency that drives the RTI circuit is fop/213 (or fop/8192) with three additional divider stages giving a maximum interrupt period of about 250ms at a crystal frequency of 1 MHz. RTIF is a read-only status bit and is set when the output of the chosen (1 of 4 selection) stage goes active. A CPU interrupt request will be generated if RTIE is set. Reset clears RTIF. TOFE - Timer Over Flow Enable When this bit is set, a CPU interrupt request is generated when the TOF bit is set. Reset clears this bit. RTIE - Real Time Interrupt Enable When this bit is set, a CPU interrupt request is generated when the RTIF bit is set. Reset clears this bit. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Core Timer Technical Data 119 NONDISCLOSURE AGREEMENT REQUIRED Technical Data RTOF - Reset TOF This bit always reads 0. Setting this bit clears the timer overflow flag (TOF). Clearing this bit has no effect. RRTIF - Reset RTIF This bit always reads 0. Setting this bit clears the real time interrupt flag (RTIF). Clearing this bit has no effect. RT1, RT0 - Real Time Interrupt Rate Select These two bits select one of four taps from the real time interrupt circuit. Table 8-1 shows the available interrupt rates with several fop values. Reset sets these RT0 and RT1, selecting the lowest periodic rate and therefore the maximum time in which to alter these bits if necessary. Care should be taken when altering RT0 and RT1 if the time-out period is imminent or uncertain. If the selected tap is modified during a cycle in which the counter is switching an RTIF could be missed or an additional one could be generated. To avoid problems the COP should be cleared before changing RTI taps. AGREEMENT REQUIRED Table 8-1 RTI Rates RTI Rates at Bus Frequency fOP specified: RT1:RT0 00 01 10 11 NONDISCLOSURE 500 kHz 32.768ms 65.536ms 131.072ms 262.144ms 1.000 MHz 16.384ms 32.768ms 65.536ms 131.072ms 2.000 MHz 8.192ms 16.384ms 32.768ms 65.536ms 2.4576 MHz 6.667ms 13.333ms 26.667ms 53.333ms RATIO 214/fop 215/fop 216/fop 217/fop Technical Data 120 Core Timer MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Core Timer Registers 8.3.2 Computer Operating Properly (COP) Watchdog Reset The COP watchdog timer function is implemented on this device by using the output of the RTI circuit and further dividing it by eight. The minimum COP reset rates are listed in Table 8-2. If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched. A COP time-out is prevented by clearing bit 0 of address $3FF0. When the COP is cleared, only the final divide by eight stage (output of the RTI) is cleared. Table 8-2 Minimum COP Reset Times Minimum COP Reset Bus Frequency at fOP specified: RT1:RT0 00 01 10 11 500 kHz 229.376ms 458.752ms 917.504ms 1835.000ms 1.000 MHz 114.689ms 229.376ms 458.752ms 917.504ms 2.000 MHz 57.344ms 114.689ms 229.376ms 458.752ms 2.4576 MHz 46.666ms 93.333ms 186.666ms 373.333ms RATIO 7*214/fop 7*215/fop 7*216/fop 7*217/fop 8.3.3 Core Timer Counter Register (CTCR) The timer counter register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at fop divided by 4 and can be used for various functions including a software input capture. Extended time periods can be attained using the TOF function to increment a temporary RAM storage location thereby simulating a 16-bit (or more) counter. $0009 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 7 bit 7 6 bit 6 5 bit 5 4 bit 4 3 bit 3 2 bit 2 1 bit 1 Bit 0 bit 0 Figure 8-3 Core Timer Counter Register (CTCR) MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Core Timer Technical Data 121 NONDISCLOSURE AGREEMENT REQUIRED Technical Data The power-on cycle clears the entire counter chain and begins clocking the counter. After 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. At this point, if RESET is not asserted, the timer will start counting up from zero and normal device operation will begin. When RESET is asserted anytime during operation (other than POR), the counter chain will be cleared. REQUIRED 8.4 Core Timer During WAIT The CPU clock halts during the WAIT mode but the core timer remains active. If the CTIMER interrupts are enabled, then a CTIMER interrupt will cause the processor to exit the WAIT mode. AGREEMENT 8.5 Core Timer During STOP The timer and the interrupt mask and enable flags are cleared when going into STOP mode. When STOP is exited by an external interrupt or an external reset the internal oscillator will restart, followed by an internal processor stabilization delay (tPORL). The timer is then cleared and the operation resumes. NONDISCLOSURE Technical Data 122 Core Timer MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data -- MC68HC(8)05PV8/A Section 9. 16-Bit Programmable Timer 9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.4 9.5 Timer During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Timer During STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA 16-Bit Programmable Timer Technical Data 123 NONDISCLOSURE AGREEMENT 9.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.3.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.3.2 Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . 127 9.3.3 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . .129 9.3.4 Timer Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.3.5 Timer Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.3.6 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 REQUIRED Technical Data 9.2 Introduction The MC68HC(8)05PV8/A has one 16-bit timer with two channels. The timer consists of a 16-bit free running counter driven by a fixed divide-by-four pre-scaler. This timer can be used for many purposes including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from several microseconds to many seconds. The output compare is improved so that it is now possible to link the two output compares to one output in order to generate pulses as short as E/4. Refer to Figure 9-1 for a timer block diagram. Because the timer has a 16-bit architecture each specific functional segment is represented by two registers. These registers contain the high and low byte of that functional segment. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. The I bit in the CCR should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does not occur. NONDISCLOSURE Technical Data 124 16-Bit Programmable Timer AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA 16-Bit Programmable Timer Introduction Internal Bus Clock 8-BIT BUFFER 4 High Byte 16-BIT FREE RUNNING COUNTER COUNTER ALTERNATE REGISTER Low Byte $18 $19 $1A $1B High Byte OUTPUT COMPARE 1 Low Byte $12 $13 High Byte OUTPUT COMPARE 2 Low Byte $16 $17 High Byte INPUT CAPTURE 1 Low Byte $10 $11 High Byte INPUT CAPTURE 2 Low Byte $14 $15 Internal Timer Bus OVERFLOW DETECT OUTPUT COMPARE OUTPUT COMPARE EDGE DETECT 1 EDGE DETECT 2 TCAP2 TCAP1 ICI1E ICI2E OCI1E TOFIE OCI2E TOFF TCR1 $1C Interrupt D Latch C TCAP1 D Latch C Q D Latch C Q TCMP2 Q IC1F IC2F OC1F TOF OC2F SI1 SI2 TSR $1E TCAP2 IEDG1 IEDG2 CLK21 FOLV1 OLVL1 CLK12 FOLV2 OLVL2 TCR2 $1D D Latch C Q TCMP1 Figure 9-1 Timer Block Diagram MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA 16-Bit Programmable Timer Technical Data 125 NONDISCLOSURE AGREEMENT REQUIRED 68HC05 Internal Bus Technical Data 9.3 Registers 9.3.1 Counter The key element in the programmable timer is a 16-bit free-running counter or counter register, preceded by a pre-scaler that divides the internal processor clock by four. The pre-scaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value. The double-byte free-running counter can be read from either of two locations, $18-$19 (counter register) or $1A-$1B (counter alternate register). A read from only the least significant byte (LSB) of the free-running counter ($19, $1B) receives the count value at the time of the read. If a read of the free-running counter, or counter alternate register first addresses the most significant byte ($18, $1A), the LSB ($19, $1B) is transferred to a buffer. This buffer value remains fixed after the first MSB read even if the user reads the MSB several times. This buffer is accessed when reading the free-running counter or counter alternate register, LSB ($19 or $1B) and thus completes a read sequence of the total counter value. In reading either the free-running counter or counter alternate register, if the MSB is read, the LSB must also be read to complete the sequence. The counter alternate register differs from the counter register in one respect: a read of the counter register MSB can clear the timer overflow flag (TOF). Therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the TOF. NONDISCLOSURE Technical Data 126 AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 16-Bit Programmable Timer MOTOROLA 16-Bit Programmable Timer Registers 9.3.2 Output Compare Registers There are two output compare registers: Output compare register 1 and output compare register 2. Output compare registers can be used for several purposes such as controlling an output waveform or indicating when a period of time has elapsed. All bits are readable and writeable and are not altered by the timer hardware or reset. If the compare function is not needed the two bytes of the output compare register can be used as storage locations. 9.3.2.1 Output Compare Register 1 The 16-bit output compare register 1 is made up of two 8-bit registers at locations $12 (MSB) and $13 (LSB). The output compare register contents are compared with the contents of the free-running counter once every four internal processor clock cycles. If a match is found, the output compare flag OC1F (bit 5 of the timer status register ($1E)) is set and the corresponding output level OLVL1 bit is clocked to TCMP1 output. The output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed time-out. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (OCI1E) is set. After a processor write cycle to the output compare register 1 containing the MSB ($12), the output compare function is inhibited until the LSB ($13) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($13) will not inhibit the compare function. The free-running counter is updated every four internal bus clock cycles. The minimum time required to update the output compare register is a function of the program rather than the internal hardware. The processor can write to either byte of the output compare register 1 without affecting the other byte. The output level (OLVL1) bit is clocked to the output level register regardless of whether the output compare flag (OC1F) is set or clear. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA 16-Bit Programmable Timer Technical Data 127 NONDISCLOSURE AGREEMENT REQUIRED Technical Data Because the output compare flag OC1F and the output compare register 1 are undetermined at power-on, and are not affected by external reset, care must be exercised when initializing the output compare function. The following procedure is recommended. Write the high byte to the compare register 1 to inhibit further compares until the low byte is written. Read the status register to arm the OC1F if it is already set. Write the output compare register 1 low byte to enable the output compare 1 function with the flag clear. The purpose of this procedure is to prevent the OC1F bit from being set between the time it is read and the write to the corresponding output compare register. 9.3.2.2 Output Compare Register 2 The 16-bit output compare register 2 is made up of two 8-bit registers at locations $16 (MSB) and $17 (LSB). The output compare register contents are compared with the contents of the free-running counter once every four internal processor clock cycles. If a match is found, the output compare flag OC2F (bit 3 of the timer status register ($1E)) is set and the corresponding output level OLVL2 bit is clocked to TCMP2 output. The output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed time-out. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (OCI2E) is set. After a processor write cycle to the output compare register 2 containing the MSB ($16), the output compare function is inhibited until the LSB ($17) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare function. The free-running counter is updated every four internal bus clock cycles. The minimum time required to update the output compare register is a function of the program rather than the internal hardware. NONDISCLOSURE Technical Data 128 AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 16-Bit Programmable Timer MOTOROLA 16-Bit Programmable Timer Registers Because the output compare flag OC2F and the output compare register 2 are undetermined at power-on, and are not affected by external reset, care must be exercised when initializing the output compare function. A procedure as recommended for compare register 1 should be followed. There are two identical input capture registers: Input capture register 1 and input capture register 2. The two following sections describe these two registers. 9.3.3.1 Input Capture Register 1 Two 8-bit registers, which make up the 16-bit input capture register 1, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition on the TCAP1 pin. The level transition which triggers the counter transfer is defined by the corresponding input edge bit (IEDG1). Reset does not affect the contents of the input capture register except when exiting stop mode. IEDG1 - Capture on Negative/Positive Edge 1 = Capture on positive edge 0 = Capture on negative edge An interrupt can also accompany a capture provided the corresponding interrupt enable bit, ICI1E, is set. The result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter which is four internal bus clock cycles. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA 16-Bit Programmable Timer Technical Data 129 NONDISCLOSURE AGREEMENT 9.3.3 Input Capture Registers REQUIRED The processor can write to either byte of the output compare register 2 without affecting the other byte. The output level (OLVL2) bit is clocked to the output level register regardless of whether the output compare flag (OC2F) is set or clear. Technical Data The free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (IC1F) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. After a read of the input capture register most significant byte ($10), the counter transfer is inhibited until the least significant byte ($11) is also read. This characteristic causes the time used in the input capture software routine, and its interaction with the main program, to determine the minimum pulse period. A read of the input capture register LSB ($11) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. 9.3.3.2 Input Capture Register 2 Two 8-bit registers, which make up the 16-bit input capture register 2, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition on the TCAP2 pin. The level transition which triggers the counter transfer is defined by the corresponding input edge bit (IEDG2). Reset does not affect the contents of the input capture register except when exiting stop mode. IEDG2 - Capture on Negative/Positive Edge 1 = Capture on positive edge 0 = Capture on negative edge An interrupt can also accompany a capture provided the corresponding interrupt enable bit, ICI2E, is set. The result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. NONDISCLOSURE Technical Data 130 AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 16-Bit Programmable Timer MOTOROLA 16-Bit Programmable Timer Registers After a read of the input capture register most significant byte ($14), the counter transfer is inhibited until the least significant byte ($15) is also read. This characteristic causes the time used in the input capture software routine, and its interaction with the main program, to determine the minimum pulse period. A read of the input capture register LSB ($15) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. 9.3.4 Timer Control Register 1 $001C Read: ICI1E Write: Reset: 0 0 0 0 0 U U 0 ICI2E OCI1E TOIE OCI2E TOFF Bit 7 6 5 4 3 2 1 Bit 0 ICI1E - Input Capture 1 Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled ICI2E - Input Capture 2 Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled OCI1E - Output Compare 1 Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled TOIE - Timer Overflow Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA 16-Bit Programmable Timer Technical Data 131 NONDISCLOSURE Figure 9-2 Timer Control Register 1 (TCR1) AGREEMENT REQUIRED The free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (IC2F) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. Technical Data OCI2E - Output Compare 2 Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled TOFF - Shut Off Timer 1 = Timer is disabled. This can be used to save power if timer is not used 0 = Timer is enabled REQUIRED AGREEMENT 9.3.5 Timer Control Register 2 $001D Read: IEDG1 Write: Reset: U U 0 IEDG2 CLK21 FOLV1 0 U 0 Bit 7 6 5 4 0 OLVL1 CLK12 FOLV2 0 U 3 2 1 0 OLVL2 Bit 0 Figure 9-3 Timer Control Register 2 (TCR2) IEDG1 - Input Edge Value of input edge determines which level transition on TCAP1 pin will trigger free running counter transfer to the input capture register 1. 1 = Positive edge 0 = Negative edge IEDG2 - Input Edge Value of input edge determines which level transition on TCAP2 pin will trigger free running counter transfer to the input capture register 2. 1 = Positive edge 0 = Negative edge CLK21 - Output Compare 2 clocks output latch 1 If this bit is set to 1, a successful compare of compare register 2 loads the OLVL2 bit to the output latch 1. This feature can be used to get output pulses as short as E/4 while using only one interrupt. NONDISCLOSURE Technical Data 132 MC68HC(8)05PV8/A -- Rev. 1.9 16-Bit Programmable Timer MOTOROLA 16-Bit Programmable Timer Registers FOLV1 - Force Output Level 1 The FOLV1 bit always reads as zero. Writing a zero at this position has no effect. Writing a one at this position will force the OLVL1 bit to the corresponding output level latch, thus appearing at pin TCMP1. Note that the force output compare 1 does not affect the OCF1 bit of the status register. OLVL1 - Output Level 1 Value of output level is clocked into output level register by the next successful output compare 1 and will appear on the TCMP1 pins. 1 = High output 0 = Low output CLK12 - Output Compare 1 clocks output latch 2 If this bit is set to 1, a successful compare of compare register 1 loads the OLVL1 bit to the output latch 2. This feature can be used to get output pulses as short a E/4 while using only one interrupt. FOLV2 - Force Output Level 2 The FOLV2 bit always reads as zero. Writing a zero at this position has no effect. Writing a one at this position will force the OLVL2 bit to the corresponding output level latch thus appearing at pin TCMP2. Note that the force output compare 2 does not affect the OCF2 bit of the status register. OLVL2 - Output Level 2 Value of output level is clocked into output level register by the next successful output compare 2, and will appear on the TCMP2 pin. 1 = High output 0 = Low output MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA 16-Bit Programmable Timer Technical Data 133 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 9.3.6 Timer Status Register The timer status register is a read-only register containing timer status flags. $001E Read: Write: Reset: U U U U U U U 0 Bit 7 IC1F 6 IC2F 5 OC1F 4 TOF 3 OC2F 2 SI1 1 SI2 Bit 0 0 REQUIRED Figure 9-4 Timer Status Register 1 (TSR) AGREEMENT IC1F - Input Capture 1 Flag 1 = Flag set when selected polarity edge is sensed by input capture 1 edge detector 0 = Flag cleared when TSR and input capture 1 registers low byte is accessed IC2F - Input Capture 2 Flag 1 = Flag set when selected polarity edge is sensed by input capture 2 edge detector 0 = Flag cleared when TSR and input capture 2 registers low byte is accessed OC1F - Output Compare 1 Flag 1 = Flag set when output compare register 1 contents match the free-running counter contents 0 = Flag cleared when TSR and output compare register 1 low byte are accessed TOF - Timer Overflow Flag 1 = Flag set when free-running counter transition from $FFFF to $0000 occurs 0 = Flag cleared when TSR and counter low register are accessed OC2F - Output Compare 2 Flag 1 = Flag set when output compare register 2 contents match the free-running counter contents 0 = Flag cleared when TSR and output compare register 2 low byte are accessed NONDISCLOSURE Technical Data 134 MC68HC(8)05PV8/A -- Rev. 1.9 16-Bit Programmable Timer MOTOROLA 16-Bit Programmable Timer Registers SI2 - Sample Input 2 1 = Bit set when input capture 2 input is sampled high while output compare register 2 matches the free running counter 0 = Bit cleared when input capture 2 input is sampled low while output compare register 2 matches the free running counter Accessing the timer status registers satisfies the first condition required to clear status bits. The remaining step is to access the registers corresponding to the status bit. A problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. Without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. The timer status register is read or written when TOF is set, and 2. The LSB of the free-running counter is read but not for the purpose of servicing the flag The counter alternate register contains the same value as the free-running counter; therefore this alternate register can be read at any time without affecting the timer overflow flag in the timer status register. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA 16-Bit Programmable Timer Technical Data 135 NONDISCLOSURE AGREEMENT REQUIRED SI1 - Sample Input 1 1 = Bit set when input capture 1 input is sampled high while output compare register 1 matches the free running counter 0 = Bit cleared when input capture 1 input is sampled low while output compare register 1 matches the free running counter Technical Data 9.4 Timer During WAIT Mode The CPU clock halts during WAIT mode but the timer keeps on running. If any reset is used to exit WAIT mode the counters are forced to $FFFC. If interrupts are enabled a timer interrupt will cause the processor to exit WAIT mode. REQUIRED 9.5 Timer During STOP Mode In STOP mode the timer stops counting and holds the last count value if STOP is exited by an interrupt. If any reset is used the counters are forced to $FFFC. Note: During STOP, if at least one valid input capture edge occurs at the TCAP pins, the input capture detect circuit is armed. This does not set any timer flags nor wake up the MCU, but when the MCU does wake up, there is an active input capture flag and data from the first valid edge that occurred during STOP mode. If any reset is used to exit STOP mode then no input capture flag or data remains even if a valid input capture edge occurred. NONDISCLOSURE Technical Data 136 16-Bit Programmable Timer AGREEMENT MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data -- MC68HC(8)05PV8/A Section 10. Analog to Digital Converter 10.1 Contents 10.2 10.3 10.4 10.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 A/D Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 A/D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Internal and Master Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 139 10.6 A/D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.6.1 A/D Status and Control Register (ADSCR) . . . . . . . . . . . . 140 10.6.2 A/D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.7 10.8 10.9 A/D During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 A/D During STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Analog to Digital Converter Technical Data 137 NONDISCLOSURE 10.10 Conversion Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . 144 10.10.1 Transfer Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 10.10.2 Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.10.3 Quantization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.10.4 Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.10.5 Gain Scale Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.10.6 Differential Linearity Error . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.10.7 Integral Linearity Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.10.8 Total Unadjusted Error . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 AGREEMENT REQUIRED Technical Data 10.2 Introduction The analog to digital converter system consists of a single 8-bit successive approximation converter and a channel multiplexer. There is one 8-bit result data register and one 8-bit status/control register. The reference supply can be switched by software either to the internal VDD and VSS supplies or to external pins individually. An internal RC type oscillator is activated by the ADRC bit in the A/D status and control register (ADSCR). This RC oscillator is used to provide a sufficiently high clock rate to the A/D when the bus speed is too low for the A/D to be accurate. Additionally, the ADON bit allows the user to save power by disconnecting the A/D when not in use. This is particularly useful to reduce current consumption (typically by 100A) when going into WAIT mode. The A/D is ratiometric to the internal reference voltages VREFH and VREFL which can be derived from either VDD/VSS or external pins. An input voltage equal to or greater than VREFH converts to $FF (full scale) with no overflow indication (if greater). An input voltage equal to VREFL converts to $00. For ratiometric conversions, the source of each analog input should use VREFH as the supply voltage and be referenced to VREFL. NONDISCLOSURE AGREEMENT 10.3 A/D Principle REQUIRED The A/D reference inputs are applied to a precision internal digital to analog converter. Control logic drives this D/A and the analog output is successively compared to the selected analog input which was sampled at the beginning of the conversion time. The conversion is monotonic with no missing codes. Technical Data 138 Analog to Digital Converter MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Analog to Digital Converter A/D Operation 10.4 A/D Operation The A/D is an 8-bit successive approximation register (SAR) type A/D converter with continuous conversion per given channel. The result of a conversion is loaded into the read-only result data register and a conversion complete flag COCO is set in the A/D status/control register. Any write to the A/D status/control register will abort the current conversion, reset the conversion complete flag and start a new conversion on the selected channel. At power-on or external reset both the ADRC and ADON bits are cleared. Thus the A/D is disabled. Each conversion takes 32 clock cycles which must be at a frequency equal to or greater than 1 MHz. A multiplexer allows the single A/D converter to select one of six external analog signals two internal signal sources and three internal reference sources. 10.5 Internal and Master Oscillator If the MCU bus (E clock) frequency is less than 1.0 MHz, an internal RC oscillator (nominally 1.5 MHz) must be used for the A/D conversion clock. This selection is made by setting the ADRC bit in the A/D status and control register to 1. When the internal RC oscillator is being used as the conversion clock three limitations apply: 1. The conversion complete flag (COCO) must be used to determine when a conversion sequence has been completed, due to the frequency tolerance of the RC oscillator and its asynchronism with regard to the MCU bus clock. 2. The conversion process runs at the nominal 1.5 MHz rate but the conversion results must be transferred to the MCU result registers synchronously with the MCU bus clock so conversion time is limited to a maximum of one channel per bus cycle. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Analog to Digital Converter Technical Data 139 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 3. If the system clock is running faster than the RC oscillator, the RC oscillator should be turned off, and the system clock used as the conversion clock. REQUIRED 10.6 A/D Registers 10.6.1 A/D Status and Control Register (ADSCR) The following paragraphs describe the function of the A/D status and control register. $000F Read: Write: Reset: U U U U U U U U AGREEMENT Bit 7 COCO 6 ADRC 5 ADON 4 ADTST 3 CH3 2 CH2 1 CH1 Bit 0 CH0 Figure 10-1 A/D Status and Control Register (ADSCR) COCO - Conversion Complete This read-only status bit is set when a conversion is completed, indicating that the A/D data register contains valid results. This bit is cleared whenever the A/D status and control register is written and a new conversion automatically started, or whenever the A/D register is read. Once a conversion has been started by writing to the A/D status and control register, conversions of the selected channel will continue every 32 cycles until the A/D status and control register is written again. In this continuous conversion mode, the A/D data register will be filled with new data, and the COCO bit set, every 32 cycles. Data from the previous conversion will be overwritten regardless of the state of the COCO bit prior to writing. ADRC - RC Oscillator On When ADRC is set, the A/D section runs on the internal RC oscillator instead of the CPU clock. The RC oscillator requires a time tRCON to stabilize and results can be inaccurate during this time. See 10.5 Internal and Master Oscillator. NONDISCLOSURE Technical Data 140 MC68HC(8)05PV8/A -- Rev. 1.9 Analog to Digital Converter MOTOROLA Analog to Digital Converter A/D Registers ADON - A/D On When the A/D is turned on (ADON = 1), it requires a time tADON for the current sources to stabilize, and results can be inaccurate during this time. This bit turns on the charge pump. ADTST This bit is for test purposes only. Write only 0. Table 10-2. A/D Clock Selection ADRC 0 0 1 1 ADON 0 1 0 1 Comments RC oscillator off, A/D converter off. RC oscillator off, A/D converter on. RC oscillator on, A/D converter off. Gives time for the RC osc to stabilize. RC oscillator on, A/D converter on. A/D using RC osc clocks CH3:0 - Channel Select Bit CH3, CH2, CH1 and CH0 form a four bit field which is used to select one of sixteen A/D channels. Channels 8-15 are used for internal reference points. The following table shows the signals selected by the channel select field. Table 10-1 A/D Channel Assignments CH3 0 0 0 0 0 0 0 0 CH2 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 0 1 CH0 0 1 0 1 0 1 0 1 Channel 0 1 2 3 4 5 6 7 Signal TJ PA1 PA2 PA3 PA4 PA5 PA6 VSUP / [100mV/bit] Technical Data Analog to Digital Converter 141 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA NONDISCLOSURE AGREEMENT REQUIRED Technical Data Table 10-1 A/D Channel Assignments CH3 1 1 1 1 1 CH2 0 0 0 0 1 CH1 0 0 1 1 X CH0 0 1 0 1 X Channel 8 9 10 11 12-15 Signal VREFH (VREFH+VREFL)/2 VREFL VREFL VREFL REQUIRED NOTE: AGREEMENT Channel 0 and 7-15 convert internal signals which cannot be accessed externally. 10.6.2 A/D Data Register One 8-bit result register is provided. This register is updated each time COCO is set. $000E Read: Write: Reset: U U U U U U U U Bit 7 bit 7 6 bit 6 5 bit 5 4 bit 4 3 bit 3 2 bit 2 1 bit 1 Bit 0 bit 0 NONDISCLOSURE Figure 10-3 A/D Data Register (ADDR) 10.7 A/D During WAIT Mode The A/D converter continues normal operation during WAIT mode. To decrease power consumption during WAIT it is recommended that both the ADON and ADRC bits in the A/D status and control registers be cleared if the A/D converter is not being used. If the A/D converter is in use and the system clock rate is above 1.0 MHz it is recommended that the ADRC bit be cleared. As the A/D converter continues to function normally in WAIT mode the COCO bit is not cleared. Technical Data 142 Analog to Digital Converter MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Analog to Digital Converter A/D During STOP Mode 10.8 A/D During STOP Mode In STOP mode the comparator and charge pump are turned off and the A/D ceases to function. Any pending conversion is aborted. When the clocks begin oscillation upon leaving the STOP mode, a finite amount of time passes before the A/D circuits stabilize enough to provide conversions to the specified accuracy. Normally the delays built into the device when coming out of STOP mode are sufficient for this purpose therefore no explicit delays need to be built into the software. Although the comparator and charge pump are disabled in STOP mode the A/D data and status/control registers are not modified. Disabling the A/D prior to entering STOP mode will not affect the STOP mode current consumption. 10.9 Analog Input The external analog voltage value to be converted by the A/D converter is sampled on an internal capacitor through a resistive path provided by input-selection switches and a sampling aperture time switch. Sampling time is limited to 12 bus clock cycles. After sampling, the analog value is stored on a capacitor and held until the end of conversion. During this hold time, the analog input is disconnected from the internal A/D system and the external voltage source sees a high impedance input. The equivalent analog input during sampling is a RC low-pass filter with resistance around 50 k and a capacitance of around 8pF. (It should be noted that these are typical values measured at room temperature). MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Analog to Digital Converter Technical Data 143 NONDISCLOSURE AGREEMENT REQUIRED Technical Data REQUIRED INPUT PROTECTION VDD PA1... PA6 DIFFUSION * < 10pF ~ 50 K DAC CAPACITANCE VSS 8pF AGREEMENT VREFL / VSS * THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME Figure 10-4 Electrical Model of an A/D Input Pin Be sure that pins used as analog inputs are configured as inputs with their appropriate pull-up resistors disabled (enabled after reset). 10.10 Conversion Accuracy Definitions NONDISCLOSURE This section explains the terminology used to specify the analog characteristics of the A/D converter. 10.10.1 Transfer Curve The ideal transfer curve can be thought of as a staircase of uniform step size with perfect positioning of the endpoints. Figure 10-5 shows the ideal transfer curve of an 8-bit A/D converter. Technical Data 144 Analog to Digital Converter MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Analog to Digital Converter Conversion Accuracy Definitions $FF $FE CONVERSION RESULT $FD 1-BIT ACCURACY $03 $02 $01 $00 1 2 3 253 254 255 INPUT VOLTAGE (LSB) 1LSB = VREFH / 255 Figure 10-5 Transfer Curve of an Ideal 8-Bit A/D Converter 10.10.2 Monotonicity The characteristic of the transfer function whereby increasing the input signal results in the output never decreasing. 10.10.3 Quantization Error Also known as digitization error or uncertainty. It is the inherent error involved in digitizing an analog signal due to the finite number of steps at the digital output versus the infinite number of values at the analog input. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Analog to Digital Converter Technical Data 145 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 10.10.4 Offset Error The offset error is the DC shift of the entire transfer curve of an ideal converter. REQUIRED 10.10.5 Gain Scale Error The gain error is an error in the input to output transfer ratio. Gain error causes an error in the slope of the transfer curve. AGREEMENT 10.10.6 Differential Linearity Error The differential linearity error is the difference between actual analog voltage change and the ideal (1LSB) voltage change at any code change. 10.10.7 Integral Linearity Error The integral linearity error is the deviation from the best fitting line through all A/D code changes. NONDISCLOSURE 10.10.8 Total Unadjusted Error The total unadjusted error is the maximum error that occurs without adjusting offset and gain errors. This error is a combination of offset, scale and integral linearity errors. Technical Data 146 Analog to Digital Converter MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data -- MC68HC(8)05PV8/A Section 11. Pulse Width Modulator 11.1 Contents 11.2 11.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.4.1 PWM Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.4.2 PWM Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 11.4.3 PWM Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.6 11.7 11.8 PWM During STOP Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 PWM During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Frame Frequency Examples. . . . . . . . . . . . . . . . . . . . . . . . . . 153 The pulse width modulator (PWM) system has one channel. The PWM has a programmable period of PWMPRxT = PWMPR / fPWM, where PWMPR is a programmable period (1... 256) and T = 1 / fPWM can be 1/fOSC, 1.5/fOSC, 2/fOSC, 3/fOSC and so on. fOSC is the oscillator frequency. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Pulse Width Modulator Technical Data 147 NONDISCLOSURE 11.2 Introduction AGREEMENT REQUIRED Technical Data REQUIRED Loadable Counter OSC1 HC05 DATA BUS Clock Generator fPWM Comparator PWM Pin Logic PWM Buffer PWMON PRA0-3 Cycle POL AGREEMENT PWM Control Register Figure 11-1 PWM Block Diagram 11.3 Functional Description The PWM is capable of generating signals from 0% to 100% duty cycle. A $00 in the PWM data register yields an OFF output (0%), but an $FF yields a duty of 255/256 (assuming the PWM period register is set to $FF). To achieve the 100% duty (ON output), the polarity control bit is set while the data register contains $00. When not in use the PWM system can be shut off to save power by clearing the PWMON bit in the PWM control register. The PWM starts conversion immediately after setting PWMON. The PWM output can have an active high or an active low pulse under software control. NONDISCLOSURE Technical Data 148 MC68HC(8)05PV8/A -- Rev. 1.9 Pulse Width Modulator MOTOROLA Pulse Width Modulator Functional Description (PWMPR + 1) / fPWM A0 FF PWMDAT = $00 conversion n-1 complete conversion n complete Figure 11-2 PWM Waveforms (POL = 0, active low), PWMPR = $FF (PWMPR + 1) / fPWM A0 PWMDAT = $FF ( > PWMPR, -> output permanent low) (PWMPR - PWMDAT) / fPWM PWMDAT / fPWM PWMDAT = $00 conversion n-1 complete conversion n complete Figure 11-3 PWM Waveforms (POL = 1, active high), PWMPR = $CF MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Pulse Width Modulator Technical Data 149 NONDISCLOSURE AGREEMENT 80 REQUIRED Technical Data 11.4 Registers Associated with the PWM system, there are a PWM data register, a PWM period register and a PWM control register. These registers can be written to and read at any time. Writing to the data or the period register takes effect when the whole PWM system is started by switching on the PWMON bit or when a conversion cycle is complete. After reset the user should write to the prescaler bits prior to enabling the PWM system. This prevents an erroneous duty cycle from being driven. REQUIRED AGREEMENT 11.4.1 PWM Control Register $002D Read: PWMON Write: Reset: 0 0 0 0 0 0 0 0 POL 0 CYCLE PRA3 PRA2 PRA1 PRA0 Bit 7 6 5 4 3 2 1 Bit 0 Figure 11-4 PWM Control Register (PWMCR) PWMON - PWM Module On 1 = PWM module operating 0 = PWM module stopped POL - PWM Polarity When set, this bit makes the active PWM pulse high. When cleared, the output is active low (e.g. $00 in the data register yields an all high signal for POLA = 0). The programmed polarity bit is copied into a shadow polarity bit when the PWM data register is written. At the end of the current conversion, the shadow polarity bit takes effect. 1 = PWM polarity active high 0 = PWM polarity active low CYCLE - PWM Cycle Completed This bit indicates the completion (reload of PWM data and period) of a PWM cycle. This flag is cleared by writing a 1 to the bit position. 1 = PWM registers were reloaded after last flag clear 0 = PWM registers were not reloaded after last flag clear NONDISCLOSURE Technical Data 150 MC68HC(8)05PV8/A -- Rev. 1.9 Pulse Width Modulator MOTOROLA Pulse Width Modulator Registers PRA3, PRA2, PRA1, PRA0 - PWM Clock Rate Bits These bits select the input clock rate fPWM. For exact values see Table 11-1. The PWM clock rate bits are not latched until the end of conversion. They affect the PWM output immediately. For proper operation these control bits must not be changed during conversion. Table 11-1 PWM Clock Rate PRA3:PRA0 0000 0001 0010 0011 0100 0101 0110 0111 fPWM fosc fosc/1.5 fosc/2 fosc/3 fosc/4 fosc/6 fosc/8 fosc/12 PRA3:PRA0 1000 1001 1010 1011 1100 1101 1110 1111 fPWM fosc/16 fosc/24 fosc/32 fosc/48 fosc/64 fosc/96 fosc/128 fosc/192 11.4.2 PWM Data Register The PWM system has an 8-bit data register that holds the duty cycle for the PWM output. This register can be changed at any time. When the PWMDAT register is updated, the programmed value, as well as the POL bit, take effect in the following conversion cycle. Note that if the contents of PWMDAT are higher than the contents of PWMPR the output will be permanently switched to the passive state (i.e. the same result as PWMDAT = $00). $002E Read: bit 7 Write: Reset: 0 0 0 0 0 0 0 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Figure 11-5 PWM Data Register (PWMDAT) MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Pulse Width Modulator Technical Data 151 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 11.4.3 PWM Period Register The PWM system has an 8-bit period register that holds the PWM period. The frame frequency of the PWM system is defined as fframe=fPWM/(PWMPR + 1). This register can be written at any time. The period of the output changes after the current cycle. $002C Read: Bit 7 bit 7 Write: Reset: 1 1 1 1 1 1 1 1 6 bit 6 5 bit 5 4 bit 4 3 bit 3 2 bit 2 1 bit 1 Bit 0 bit 0 AGREEMENT REQUIRED Figure 11-6 PWM Period Register (PWMPR) 11.5 PWM During WAIT Mode The PWM continues normal operation during WAIT mode. To decrease power consumption during WAIT it is recommended to shut off the PWM by clearing the PWMON bit if the PWM system is not used. NONDISCLOSURE 11.6 PWM During STOP Mode In STOP mode the oscillator is stopped, causing the PWM to cease functioning. Any signal in process is aborted in whatever phase the signal happens to be in. 11.7 PWM During Reset Upon reset the PWMON and PRA3-0 bits in the PWM control register are cleared, the data register is written with $00 and the polarity bit is reset. This in effect disables the PWM system and sets the output driving high. The user should write to the data register, the period register, the polarity bit and the clock rate bits prior to enabling the PWM system (i.e. prior to setting PWMON). This prevents an erroneous duty cycle from being driven. Technical Data 152 Pulse Width Modulator MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Pulse Width Modulator Frame Frequency Examples 11.8 Frame Frequency Examples REQUIRED NONDISCLOSURE MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Pulse Width Modulator Technical Data 153 Table 11-2 Frame Frequency for fOSC = 4.2MHz PRA3-PRA0 0000 0001 0010 0111 PWMPR = $10 247KHz 165KHz 123KHz 20.6KHz PWMPR = $40 64.5KHz 43KHz 32.3KHz 5.38KHz PWMPR= $C7 21KHz 14KHz 10.5KHz 1.75KHz PWMPR = $FF 16.4KHz 10.9KHz 8.2KHz 1.37KHz Table 11-3 Frame Frequency for fOSC = 2MHz PRA3-PRA0 0000 0001 0010 0111 PWMPR = $10 118KHz 78.4KHz 58.8KHz 9.8KHz PWMPR = $40 30.8KHz 20.5KHz 15.4KHz 1.28KHz PWMPR= $C7 10KHz 6.67KHz 5KHz 833Hz PWMPR = $FF 7.81KHz 5.21KHz 3.91KHz 651Hz AGREEMENT Technical Data NONDISCLOSURE Technical Data 154 Pulse Width Modulator AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data -- MC68HC(8)05PV8/A Section 12. Voltage Regulator 12.1 Contents 12.2 12.3 12.4 12.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Internal Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 5V Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Trimming the Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . 156 12.2 Introduction The MC68HC(8)05PV8/A contains a low-power, low-drop CMOS on-chip fixed voltage regulator to provide internal power to the MCU from an external DC source. The MC68HC05PV8A contains on top of that a selectable standby regulator to achieve lower standby current. 12.3 Internal Power Supply The on-chip voltage regulation and power supply control circuitry is comprised of two elements: the regulator and the low voltage reset (LVR) circuitry on the MC68HC(8)05PV8. In addition to that, the voltage regulator on MC68HC05PV8A comprises a standby regulator and a standby low voltage reset block. 12.4 5V Regulator The 5V regulator accepts an unregulated input supply and provides a regulated 5V supply to all the digital sections of the device. The output of this regulator is also connected to the VDD pin to allow for decoupling and to provide an external power source. The voltage regulator handles the generation of low voltage resets. For details refer to 5.12 Low Voltage Reset. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Voltage Regulator Technical Data 155 NONDISCLOSURE AGREEMENT REQUIRED Technical Data Any loss of VDD sufficient to trigger an LVR causes the device to be reset. The device remains in the reset state for the duration of the LVR condition or until the internal VDD drops below the functional level of the device, at which point reset no longer has meaning. If the drop in VDD that triggers an LVR is transient, then an internal RST is asserted for a minimum 4064 cycles of the CPU bus clock, PH2 (the POR delay). On the MC68HC05PV8A, the low voltage reset is generated by a second low voltage reset generator with a lower threshold as long as the ULPM bit is set. For this reason, it is mendatory to have the ULPM bit cleared as long as the mcu is in normal operation. AGREEMENT REQUIRED 12.5 Trimming the Voltage Regulator The output of the voltage regulator can be trimmed to reach a higher accuracy. This is performed by setting the VT2, VT1 and VT0 bits in the MFTEST register $002F Read: Write: Reset: Bit 7 HVTOFF 0 6 0 - 0 5 0 - 0 4 VSCAL 0 3 LSOFF 0 2 VT2 0 1 VT1 0 Bit 0 VT0 0 Figure 12-1 MFTEST Register (MFTEST) Table 12-1 illustrates the effect of the trimming bits to VDD in increase or decrease of the output voltage by trimming steps (typically 40mV). Table 12-1 Trimming Effect VT2 0 0 0 0 1 1 1 1 VT1 0 0 1 1 0 0 1 1 VT0 0 1 0 1 0 1 0 1 Effect NONDISCLOSURE 0 -1 -2 -3 +4 +3 +2 +1 Technical Data 156 Voltage Regulator MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data -- MC68HC(8)05PV8/A Section 13. EEPROM 13.1 Contents 13.2 13.3 13.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 EEPROM Control Register (EEPCR) . . . . . . . . . . . . . . . . . . . 158 EEPROM Options Register (EEOPR) . . . . . . . . . . . . . . . . . . 159 13.5 EEPROM READ, ERASE and Programming Procedures . . . 160 13.5.1 READ Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.5.2 ERASE Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.5.3 Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.6 Operation in STOP and WAIT Modes. . . . . . . . . . . . . . . . . . . 161 13.2 Introduction The EEPROM on this device is 128 bytes and is located from address $0180 to $01FF. The user programs the EEPROM on a single-byte basis by manipulating the EEPROM control register (EEPCR). An erased byte reads as $FF and any programmed bit reads as 0. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA EEPROM Technical Data 157 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 13.3 EEPROM Control Register (EEPCR) $000C Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 7 0 6 0 5 0 EEOSC EER1 EER0 EELAT EEPGM 4 3 2 1 Bit 0 REQUIRED Figure 13-1 EEPROM Control Register (EEPCR) EEOSC - EEPROM RC Oscillator Control When this bit is set, the EEPROM section uses the internal RC oscillator instead of the CPU clock. The user must wait a time tRCON after setting the EEOSC bit to allow the RC oscillator to stabilize. EEOSC is readable and writable. It should be set by the user when the internal bus frequency falls below 1.5 MHz. Reset clears this bit. EER1, EER0 - Erase Select Bits EER1 and EER0 form a 2-bit field that is used to select one of three erase modes: byte, block, or bulk erase. Table 13-1 shows the modes selected for each bit configuration. These bits are readable and writable and are cleared by reset. In byte erase mode, only the selected byte is erased. In block mode, a 128-byte block of EEPROM is erased. The EEPROM memory space is divided into two 64-byte blocks ($0180-$01BF, $01C0-$01FF) and performing a block erase on any address within a block will erase the entire block. In bulk erase mode, the entire 128 byte EEPROM section is erased. A block protect function applies on block2 of the EEPROM memory space. See 13.4 EEPROM Options Register (EEOPR) for more details. Table 13-1 Erase Mode Select EER1 0 0 1 1 EER0 0 1 0 1 No erase Byte erase Block erase (block1 or block2) Bulk erase (block1 & block2) MODE NONDISCLOSURE Technical Data 158 AGREEMENT MC68HC(8)05PV8/A -- Rev. 1.9 EEPROM MOTOROLA EEPROM EEPROM Options Register (EEOPR) EELAT - EEPROM Programming Latch The EELAT bit is the EEPROM programming latch enable. When EELAT is at 0, the EER1, EER0 and EEPGM bits are reset to zero. When the EELAT bit is clear, data can be read from the EEPROM. When set, this bit allows the address and data to be latched into the EEPROM for further programming or erase operation. Address and data can only be latched when the EEPGM bit is at 0. STOP, reset and power-on reset reset the EELAT bit. EEPGM - EEPROM Programming Power Enable EEPGM must be written to enable (or disable) the EEPGM function. When set, EEPGM turns on the charge pump and enables the programming (or erasing) power to the EEPROM array. When clear, this power is switched off. This allows pulsing of the programming voltage to be controlled internally. This bit can be read at any time, but can only be written to if EELAT = 1. If EELAT is not set, then EEPGM cannot be set. This bit is cleared by reset or when EELAT = 0. 13.4 EEPROM Options Register (EEOPR) This register contains the secure and protect functions for the EEPROM and allows the user to select options in a non-volatile manner. The contents of the EEOPR register are loaded into data latches with each power-on or external reset. The register is implemented in EEPROM, therefore reset has no effect on the individual bits. $0180 Read: EEPRT Write: Reset: NA NA NA NA NA NA NA NA Bit 7 6 5 4 3 2 1 Bit 0 Figure 13-2 EEPROM Options Register (EEOPR) EEPRT - EEPROM Protect Bit In order to achieve a higher degree of protection, the EEPROM is split into two 64-byte blocks. Block 1 ($0180 - $01BF) cannot be protected. Block 2 ($01C0 - $01FF) is protected by the EEPRT bit of the options MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA EEPROM Technical Data 159 NONDISCLOSURE AGREEMENT REQUIRED Technical Data register. When this bit is set from 0 to 1 (erased) the protection remains until the next power-on or external reset. EEPRT can only be written to 0 when the ELAT bit in the EEPROM control register is set. 1 = Block 2 of the EEPROM array is not protected; all 128 bytes of EEPROM can be accessed for any read, erase or programming operations 0 = Block 2 of the EEPROM array is protected; any attempt to erase or program a location will be unsuccessful REQUIRED AGREEMENT 13.5.1 READ Procedure 13.5 EEPROM READ, ERASE and Programming Procedures To read data from EEPROM the EELAT bit must be clear. EEPGM, EER1 and EER0 are forced to zero. The EEPROM is read as if it were a normal ROM. The charge pump generator is off since EEPGM is zero. If a read is performed while ELAT is set, data will be read as $FF. 13.5.2 ERASE Procedure There are three types of ERASE operation mode (see Table 13-1 Erase Mode Select), byte erase, block erase or bulk erase. To erase a byte of EEPROM set EELAT = 1, ER1 = 0 and ER0 = 1, write to the address to be erased and set EEPGM for a time tEBYTE. To erase a block of EEPROM set EELAT = 1, ER1 = 1 and ER0 = 0, write to any address in the block and set EEPGM for a time tEBLOC. For a bulk erase set EELAT = 1, ER1 = 1, and ER0 = 1, write to an address in the array with A0 or A1 = 1, and set EEPGM for a time tEBULK. 13.5.3 Programming Procedure To program the content of EEPROM, set EELAT bits, write data to the desired address and set the EEPGM bit. After the required programming delay tEEPGM, EELAT must be cleared. This also resets EEPGM. During Technical Data 160 EEPROM MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA NONDISCLOSURE EEPROM Operation in STOP and WAIT Modes 13.6 Operation in STOP and WAIT Modes The RC oscillator for the EEPROM is automatically disabled when entering STOP mode. The user may want to ensure that the RC oscillator is disabled before entering WAIT mode to help conserve power. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA EEPROM Technical Data 161 NONDISCLOSURE AGREEMENT REQUIRED a programming operation, any access of EEPROM will return $FF. To program a second byte, EELAT must be cleared before it is set, otherwise the programming will have no effect. Technical Data NONDISCLOSURE Technical Data 162 EEPROM AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data -- MC68HC(8)05PV8/A Section 14. Program EEPROM 14.1 Contents 14.2 14.3 14.4 14.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 EEPROM Protection Mechanism . . . . . . . . . . . . . . . . . . . . . . 165 Options Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 14.2 Introduction The Program EEPROM on the MC68HC805PV8 is 7936 bytes and is located from address $2000 to $3EFF. It also holds 16 bytes of user vectors ranging from $3FF0 to $3FFF. Programming circuitry embedded in the EEPROM block allows a group of up to four different bytes to be written or erased simultaneously. These four bytes must be located in the set of addresses which differ only in the two least significant bits. An internal charge pump is provided, avoiding the necessity to supply a high voltage for erase and programming functions. In order to achieve a higher degree of security for stored data, there is no capability for bulk or row erase in single chip mode. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Program EEPROM Technical Data 163 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 14.3 Programming Register Three bits of the program EEPROM programming register have been provided in order to control the EEPROM operations. $000D Read: RCON Write: Reset: - - - 1 0 1 1 1 BULK ERAB LATB PGMB Bit 7 6 5 4 3 2 1 Bit 0 REQUIRED Figure 14-1 Program EEPROM Control Register (PEECR) AGREEMENT RCON - RC Oscillator On This bit determines the state of the RC oscillator. This oscillator should be switched on when the device is operated below 1MHz bus clock. On higher bus speeds, this bit can be switched off to reduce power consumption 1 = RC oscillator switched on 0 = RC oscillator switched off BULK - Bulk Erase Enable This bit determines the selection of 4-byte or bulk erase mode. For programming the array, this bit must be cleared. 1 = Bulk erase mode selected 0 = 4-byte erase mode selected ERAB - Write/Erase Mode Selection The status of this bit is latched on the first store to EEPROM following the clearing of the LATB bit. 1 = EEPROM write mode 0 = EEPROM erase mode LATB - Programming Latch Enable When cleared, this bit allows data and address to be latched into the corresponding EEPROM flip-flops during the first store access to the same EEPROM address. Any subsequent EEPROM store instruction modifies the data register defined by address bits 0 and 1. For normal access to the EEPROM, this bit must be set in order to force the EEPROM address latch to the transparent mode. This bit also Technical Data 164 Program EEPROM MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA NONDISCLOSURE Program EEPROM EEPROM Protection Mechanism or tPROG programming time in WAIT mode. The EEPROM is set to read mode when entering STOP mode. 1 = EEPROM read state 0 = Activate charge pump; address and data may be latched for EEPROM write. PGMB - Programming enable When cleared, this bit allows programming of the EEPROM. It can only be cleared if the LATB is already cleared and at least one EEPROM write has occurred. This bit must be set when changing the address and data for programming new data. It is automatically set when LATB is set. 1 = EEPROM programming is inhibited 0 = EEPROM programming is enabled 14.4 EEPROM Protection Mechanism In order to achieve a higher degree of protection, inadvertent programming of the EEPROM can be avoided by use of the EEPRT bit of the options register. As long as this bit is not active (= 0), the whole array, except the first 4 bytes, can be erased or programmed. As soon as the EEPRT bit is active (= 1), the EEPROM is protected and becomes a read-only memory in single chip mode. Note that programming cannot be done by software executed from this EEPROM array! Any attempt to erase or program a location in single-chip mode will then be unsuccessful. Then the EEPROM can be programmed only in bootloader mode. If the EEPRT bit is then cleared (not protected), the EEPROM will stay protected until the next power-on or external reset. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Program EEPROM Technical Data 165 NONDISCLOSURE AGREEMENT REQUIRED controls the activation of the charge pump. The charge pump is not affected by WAIT mode, thus it is possible to wait the tERA erase time Technical Data 14.5 Options Register The options register (OPTR), which also contains the protect function for the Program EEPROM in the MC68HC805PV8 version, is located at $2000 and allows the user to select options in a non-volatile manner. The contents of the OPTR register are loaded into data latches with each reset. REQUIRED BIT 7 OPTR R W NA BIT 6 HVRE NA BIT 5 HTRE NA BIT 4 STOPR NA BIT 3 BIT 2 CME BIT 1 EEPRT NA BIT 0 COPD NA AGREEMENT $2000 RESET NA NA Figure 14-2 Options Register EEPRT - Program EEPROM Protect (only MC68HC805PV8) The EEPRT bit allows the Program EEPROM ($2004-$3EFF, $3FF0-$3FFF) to be protected. If the EEPRT bit is in the erased state (logic 0), the EEPROM is not protected and can be used as a regular byte erasable EEPROM. As soon as the EEPRT bit is programmed to 1, the EEPROM is hardware protected. The EEPROM can still be read, but any attempt to erase or program will be unsuccessful. When this bit is cleared, protection remains until the next power-on or external reset occurs. In single chip mode, addresses $2000-$2003 are always write protected. 1 = EEPROM protected 0 = EEPROM erasable and writable COPD - COP (Computer Operating Properly) Reset Disabled The COPD bit allows the COP (computer operating properly timer) to be disabled. If the COPD bit is in an erased state (logic 0), the COP is enabled. Programming this bit (logic 1) disables the COP. Changes to this bit do not take effect until the next power-on or external reset occurs. 1 = COP disabled 0 = COP enabled NONDISCLOSURE Technical Data 166 MC68HC(8)05PV8/A -- Rev. 1.9 Program EEPROM MOTOROLA Program EEPROM Options Register CME - Clock Monitor Enable The CME bit enables a watchdog for the oscillator circuit. When the frequency drops below a threshold (due to a brown-out or a defective element), when enabled, the clock monitor will reset the MCU and switch to an internal RC oscillator. 1 = Clock monitor enabled 0 = Clock monitor disabled STOPR - STOP Reset When enabled, the MCU will be reset when a STOP instruction is to be executed. 1 = STOP instruction causes reset 0 = STOP instruction executes normally HTRE - High Temperature Reset Enable The HTRE bit allows the high temperature reset to be enabled. If the HTRE bit is in erased state (logic 0), the HTR is disabled. Programming this bit (logic 1) enables the HTR. Changes to this bit do not take effect until the next power-on or external reset occurs. See Section 5. Resets for details. 1 = HTR enabled 0 = HTR disabled HVRE - High Voltage Reset Enable The HVRE bit allows the high voltage reset to be enabled. If the HVRE bit is in erased state (logic 0), the HVR is disabled. Programming this bit (logic 1) enables the HVR. Changes to this bit do not take effect until the next power-on or external reset occurs. See Section 5. Resets for details. 1 = HVR enabled 0 = HVR disabled MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Program EEPROM Technical Data 167 NONDISCLOSURE AGREEMENT REQUIRED Technical Data NONDISCLOSURE Technical Data 168 Program EEPROM AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data -- MC68HC(8)05PV8/A Section 15. Fast Parallel Interface 15.1 Contents 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.2 Introduction The MC68HC(8)05PV8/A includes a fast parallel interface to access external peripheral components as fast as internal ones. The external address space ranges from $0030 to $003F and all 68HC05 instructions can be applied to this memory. Since the data path is only 4-bits wide either the lines PA7-PA4 or the corresponding data bits in the port A data register are read depending on the state of the DDRA7-DDRA4 bits. 15.3 Description If this interface is enabled by setting the FPIE bit in the system control register PA0-3 and PB0-3 lines provide a 4 bit address, multiplexed with 4 bit wide data and timing control lines. The interface uses the lower port A lines (PA0-3) to provide a 4 bit address multiplexed with 4 bit wide data. The timing is controlled by port B lines. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Fast Parallel Interface Technical Data 169 NONDISCLOSURE AGREEMENT 15.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.3.1 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 171 REQUIRED Technical Data REQUIRED PB0 AS PB1 RW PB2 DEN PB3 CS AGREEMENT PA0-3 A0-3 D0-3 Figure 15-1 Basic Fast Peripheral Interface Timing The basic timing as shown in Figure 15-1 is similar to the timing used on the HC11 parts in expanded multiplex mode. At the falling edge of the address strobe signal (AS/PB0) the addresses on PA0-3, the read/write signal (RW/PB1) and the chip select (CS/PB3) signal are valid. A high DEN/PB2 signal indicates that data are driven on the bus in CPU write cycles or that the peripheral IC can drive data in read cycles. Whenever the FPICLK bit in the system control register is set the signals become only active when the range from $0030-$003F is addressed by the CPU thus significantly reducing electromagnetic noise. When using the A/D converter in conjunction with the fast peripheral interface the VRLEN bit of port A configuration register must be cleared. See 7.4.4 Port A Configuration Register. NONDISCLOSURE Technical Data 170 MC68HC(8)05PV8/A -- Rev. 1.9 Fast Parallel Interface MOTOROLA Fast Parallel Interface Description 15.3.1 System Control Register The following paragraphs describe the FPIE and FPICLK bit function of the system control register. $000A Read: POR Write: Reset: U 0 0 1 0 0 0 0 INTP INTN INTE WCOP Bit 7 6 5 4 3 2 WCP FPIE FPICLK 1 Bit 0 Figure 15-2 System Control Register (SYSCR) FPIE - Fast Peripheral Interface Enable If this bit is set the fast peripheral interface is enabled. PA0-3 and PB0-3 are no longer available as I/Os. 1 = Fast peripheral interface enabled 0 = Fast peripheral interface disabled FPICLK - Fast Peripheral Clock If this bit is set, the FPI clocks are free running 1 = AS and DEN only become active when CPU accesses $0030-$003F 0 = AS and DEN always active MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Fast Parallel Interface Technical Data 171 NONDISCLOSURE AGREEMENT REQUIRED Technical Data NONDISCLOSURE Technical Data 172 Fast Parallel Interface AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data -- MC68HC(8)05PV8/A Section 16. Electrical Specifications 16.1 Contents 16.2 16.3 16.4 16.5 16.6 16.7 16.8 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Program and Data EEPROM Characteristics . . . . . . . . . . . . . 175 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 VDD Referenced Pins Electrical Characteristics . . . . . . . . . . . 178 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.9 Power Supply Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.9.1 VSUP related Reset and Interrupts . . . . . . . . . . . . . . . . . . 183 16.10 Down Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.11 Die Temperature Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.12 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 16.13 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 187 16.14 Fast Peripheral Interface Timing. . . . . . . . . . . . . . . . . . . . . . . 188 16.15 PORT C Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 16.15.1 High Voltage Input/Output (PC0-4). . . . . . . . . . . . . . . . . . 189 16.15.2 Contact Sense Circuitry to Vbattery (PC0-3) and to Ground (PC1-4 MC68HC(8)05PV8)/(PC1-3 MC68HC05PV8A) . . 189 16.15.3 ISO9141 Driver (PC4) MC68HC(8)05PV8 . . . . . . . . . . . .190 16.15.5 Low Side Driver (PC5/6, PVSS) . . . . . . . . . . . . . . . . . . . . 191 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications Technical Data 173 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 16.2 Maximum Ratings (Voltages referenced to VSS) Rating Supply Voltage Supply Voltage without using the Voltage Regulator (VSUP = VDD) Input Voltage (PA0-7, PB0-4, OSC1) Input Voltage (IRQ, RESET) Input Voltage (PC0-3) REQUIRED Symbol VSUP VDD LVIN1 LVIN2 HVIN1 HVIN2 HVIN3 HVIN4 IOUT1 IOUT2 IOUT3 TJ TSTG Value -0.3 to +40.0 -0.3 to +7.0 VSS -0.3 to VDD +0.3 VSS -0.3 to 12 VSS -0.3 to VSUP +0.3 VSS -5 to VSUP +0.3 40 VSS to VDD 25 110 700 -40 to +125 -65 to +150 Unit V V V V V V V V mA mA mA C C AGREEMENT Input Voltage (PC4) Applied Voltage (PC5/6) Applied Voltage (PVSS) Current Drain per Pin (all I/O, except PC4-6) Current Drain per Pin (VSUP, VDD, VSS, PC4) Current Drain per Pin (PC5/6, PVSS) Operating Junction Temperature Range Storage Temperature Range NONDISCLOSURE This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, it is recommended that LVIN is constrained to the range VSS LVIN VDD. Reliability of operation could be affected if unused inputs are not connected to an appropriate logic voltage level (e.g., either VSS or VDD, or VSS for the high voltage pins). Technical Data 174 Electrical Specifications MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications Thermal Characteristics 16.3 Thermal Characteristics Characteristic Thermal Resistance SOIC28 Symbol JA Value 60 Unit C/W 16.4 Program and Data EEPROM Characteristics (VDD = 5.0Vdc 10%, VSS = 0Vdc, TJ = -40C to +125C, unless otherwise noted) Rating Write/Erase Cycles Program EEPROM @ 10ms write time, TJ = +125C Write/Erase Cycles Data EEPROM @ 10ms write time, TJ = +125C Data Retention EEPROMs Program EEPROM Programming Time per 4 Bytes Program EEPROM Erase Time per 4 Bytes Program EEPROM Bulk Erase Time Data EEPROM Programming Time per Byte Data EEPROM Erase Time per Byte Data EEPROM Erase Time per Block Data EEPROM Bulk Erase Time RC Oscillators Stabilization Time (Program & Data EEPROM) tPEEPGM tPEBYT tPEBULK tEEPGM tEBYT tEBLOCK tEBULK tRCON Symbol Min 100 10000 10 5 5 400 5 5 5 5 5 Max 10 10 500 10 10 10 10 - Unit Cycles Cycles Years ms ms ms ms ms ms Comment See note 1 See note 1 See note 1 See note 1 tCYC NOTES: 1. Not applicable for MC68HC05PV8 MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications Technical Data 175 NONDISCLOSURE ms AGREEMENT REQUIRED Technical Data 16.5 Supply Current (6V VSUP 16V, device untrimmed, VSS = 0Vdc, TJ = -40C to +125C, unless otherwise noted) Characteristic Full circuit in Run mode TIMER, A/D, PWM, COP on Full circuit in Wait mode TIMER, A/D, PWM, COP on TIMER, A/D, PWM, COP off Full circuit in Stop mode (PV8) Port C, Op Amp, Power Supply Monitor, Temperature Sensor disabled Full circuit in Stop mode (PV8A) Port C, Op Amp, Power Supply Monitor, Temperature Sensor disabled Down Scaler Biasing Current Low Side Driver Biasing Current Contact Sense Circuitry Internal Reference Biasing Current Contact Sense Circuitry to VBAT Biasing Current per Output Contact Sense Circuitry to Ground Biasing Current per Output ISO9141 Driver Biasing Current On State ISO9141 Driver Biasing Current Off State Port C Input Biasing Current Ultra Low Power Mode NOTES: 1. Typical values reflect average measurements at mid point of supply voltage range (VSUP = 12V, VDD = 5V) and TJ = 25C (applies to all tables). 2. Run (Operating), Wait ISUP: measured using external square wave clock source to OSC1 (FOSC = 4.2 MHz), all inputs 0.2 Vdc from rail; no DC load, all programmable outputs are static, CL = 20 pF on OSC2. 3. Wait, Stop ISUP: all ports configured as inputs, LVIL = 0.2Vdc, LVIH = VDD-0.2Vdc, HVI = 0.2Vdc. 4. ISUP1/2/3 are affected by the OSC2 capacitance. 5. Stop ISUP4 measured with OSC1 = PA0-7 = PB0-4 = IRQ = VSS. RESET open. 6. The down scaler is automatically enabled after any reset and can be disabled by setting REQUIRED Symbol ISUP1 Typ 4.4 Max 9 Unit mA Comment See note 2,4 ISUP2 ISUP3 1.95 1.45 - mA mA See notes 2, 3 & 4 ISUP4 485 650 A See note 5 AGREEMENT ISUP4A 510 750 A See note 5 ISUP5 ISUP6 ISUP7 ISUP8B ISUP8G ISUP9 ISUP10 ISUP11 ISUP12 100 280 600 60 120 280 35 10 35 100 A A A A A A A A A See note 6 See notes 7, 8, 13 See notes 9 & 10 See note 14 NONDISCLOSURE See note 11 See note 12 See note 15, 16, 17 Technical Data 176 Electrical Specifications MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications Supply Current the VSCAL bit in the MFTEST register. 7. Low Side Drivers and Die Temperature Monitor can be disabled by setting LSOFF bit in the MFTEST register. 8. The Die Temperature Monitor is only disabled when the LSOFF bit is set and the Port C4 DDR bit is cleared as well. 9. There are two common reference blocks for PC0-4, one for contacts to Vbat and one for contacts to ground. 10. This current is proportional to VSUP. 11. The ISO9141 driver can be disabled by clearing the PCDDR4 bit. 12. The Port C Inputs can be disabled by setting the HVTOFF bit in the MFTEST register. 13. Low Side Drivers must be switched off. 15. Ultra Low Power Mode is only available on MC68HC05PV8A. All I/O pins must be pulled to levels near VSS or VDD/VSUP resp.. 16. 6V < VSUP < 12V. 17. In Ultra Low Power Mode, no external load on VDD, Port A or Port B is allowed. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications Technical Data 177 NONDISCLOSURE AGREEMENT 14. Comparators are automatically enabled with the corresponding output. REQUIRED Technical Data 16.6 VDD Referenced Pins Electrical Characteristics (VDD = 5.0Vdc 10%, VSS = 0Vdc, TJ = -40C to +125C, unless otherwise noted) Characteristic Output Low Voltage Port A, Port B Output Low Voltage RESET Output High Voltage Port A, Port B Input High Voltage Port A, Port B, IRQ, RESET, OSC1 Input Low Voltage Port A, Port B, IRQ, RESET,OSC1 Schmitt Trigger Hysteresis Port A, Port B, IRQ, RESET Input Pull-up Current PA0-3 Input Pull-up Current PA4-7 Input Pull-up Current PA0-3 Input Pull-up Current PA4-7 Internal Pull-up Resistor RESET Input Current IRQ, OSC1 I/O Ports Hi-Z Leakage Current Port A, Port B Pin Capacitance Port A, Port B, RESET, IRQ Oscillator Transconductance (IOSC2/VOSC2) Injection Current PA1-5 Injection Current PA0, PA6, PA7 Injection Current PB2-4 REQUIRED Symbol VOL1 VOL2 VOL3 VOH1 VOH2 VIH VIL VHYS IIN1 IIN2 IIN3 IIN4 RRSTPU IIN6 ILEAK CPIN gM IINJ IINJ IINJ Min - - - VDD- 0.1 VDD- 0.8 0.7xVDD VSS - - - - - 5 - -1 - 0.9 -5 -2 -1 Typ - - - - - - - 1 80 0.8 50 0.5 19 - - - - - - - Max 0.1 0.4 1 - - VDD 0.3xVDD 250 2.5 250 2.5 50 1 1 10 - 5 2 1 Unit V V V V V V V V A mA A mA K A A pF mA/V mA mA mA Comment ILOAD = 10A ILOAD = 1.6mA ILOAD = 1.6mA ILOAD = -10A ILOAD =-0.8mA AGREEMENT VIN = VSS, see notes VIN = 0.7xVDD, see notes NONDISCLOSURE VSS VIN VDD Not tested Not production tested. See note 3. Technical Data 178 Electrical Specifications MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications VDD Referenced Pins Electrical Characteristics (see next page) 1. The pull-up structures on Port A0-7 can be disabled by software, they are automatically enabled by each reset. 2. The pull-up structures on Port A consist of enabled PMOS devices. For input voltages near VSS they act like a constant current source. 3. A simple protection can be built with a series resistor: R > VMAX /IINJ. The sum of currents during multiple injection should be limited below the maximum values for a single pin: R > (VMAX /IINJ)*(number of pins). Positive injection current can raise the supply voltage (VDD). Care must be taken in the application to ensure votages do not exceed the maximum ratings. Characterized on the HC805PV8 and HC05PV8. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications Technical Data 179 NONDISCLOSURE AGREEMENT REQUIRED NOTES: Technical Data 16.7 Voltage Regulator (6V VSUP 16V, device untrimmed, VSS = 0Vdc, TJ = -40C to +125C, unless otherwise noted) Characteristic Output Voltage (6V VSUP 16V) Output Voltage (9V VSUP 16V) in Ultra Low Power Mode Output Voltage (5.5V < VSUP 40V) Total Output Current REQUIRED Symbol VDD VDD VDD IOUT VLIR VLOR VSTEPTRIM VLVRON VLVRH VULVRON Min 4.75 Typ 5.0 3.7 Max 5.25 Unit V V Comment IOUT 20mA only on MC68HC05PV8A IOUT 30mA See notes 1 & 2 IOUT = 1mA 1mA IOUT 20mA See chapter 12 See notes 3, 4 & Figure 16-1 only on MC68HC05PV8A 4.5 - - - 4.15 40 5.0 - 10 50 40 4.40 100 2.6 5.5 30 35 100 4.65 200 V mA mV mV mV V mV V AGREEMENT Line Regulation (6V VSUP 16V) Load Regulation Output Voltage Trimming Step Low Voltage Reset Low Threshold Low Voltage Reset Hysteresis Low Voltage Reset Low Threshold in Ultra Low Power Mode NOTES: 1. The current sourcing capability includes the current for the MCU core, for the ports and also for any external load. 2. Refer to the maximum power dissipation. 3. The Low Voltage Reset thresholds and hysteresis are measured relative to VDD with VT2..VT0 cleared in the MFTEST register (POR condition, TRIM 0 configuration). 4. As the voltage regulator and the low voltage reset are using the same internal voltage reference, it is ensured that the low voltage reset will only occur when the voltage regulator is out of regulation. 5. The stability is ensured with a decoupling capacitor between VDD and VSS: COUT 10F with ESR 10. Capacitor value and type should be choosen under consideration of the allowable VDD ripple in the particular application. NONDISCLOSURE Technical Data 180 MC68HC(8)05PV8/A -- Rev. 1.9 Electrical Specifications MOTOROLA Electrical Specifications Voltage Regulator VDD VLVRON + VLVRH VLVRON RESET MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications Technical Data 181 NONDISCLOSURE AGREEMENT Figure 16-1 Low Voltage Reset waveform REQUIRED Technical Data 16.8 Operational Amplifier (device untrimmed, VSS = 0Vdc, TJ = -40C to +125C, unless otherwise noted) Characteristic Input Offset Voltage Input Common Mode Voltage Range Large Signal Gain REQUIRED Symbol VIO VICR AVOL Min - VSS - Typ 1 - 30 VSS .. VDD - 0.2 Max 20 VDD - 1.2 - Unit mV V V/mV Comment Output Voltage Swing VOH V RLOAD= 50K to VSS AGREEMENT Output Short Circuit Current to VSS Output Short Circuit Current to VDD ISCG ISCP - - 5 50 - - mA A VID = 1V, VO = VSS, TJ = 25C VID = -1V, VO = VDD, TJ = 25C VIN = 0.5V to 4.5V, RLOAD= 50K to VSS, CLOAD = 25pF f = 10KHz Slew Rate Gain Bandwidth Product SR GBW - - 1 1 - - V/s MHz NONDISCLOSURE Technical Data 182 Electrical Specifications MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications Power Supply Monitor 16.9 Power Supply Monitor 16.9.1 VSUP related Reset and Interrupts (device untrimmed, VSS = 0Vdc, TJ = -40C to +125C, unless otherwise noted) Characteristic High Voltage Reset On High Voltage Reset Hysteresis High Voltage Interrupt On High Voltage Interrupt Hysteresis Low Voltage Interrupt On Low Voltage Interrupt Hysteresis NOTE: See chapter 16.7 for the Low Voltage Reset function. Symbol VHVRON VHVRH VHVION VHVIH VLVION VLVIH Min 34.5 29 6.5 - Typ 36 1.5 30.5 1.5 7.5 0.6 Max 37.5 32 8.5 - Unit V V V Comment SEE Figure 16-2 V V V VHVRON VHVRON - VHVRH VHVION VHVION - VHVIH VSUP VLVION + VLVIH VLVION High Voltage Reset High Voltage Interrupt Low Voltage Interrupt Figure 16-2 VSUP related Reset and Interrupts waveforms MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications Technical Data 183 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 16.10 Down Scaler (device untrimmed, VSS = 0Vdc, TJ = -40C to +125C, unless otherwise noted) Characteristic Voltage Ratio = VSUP/VAD7 NOTE: 1. The Down Scaler output is internally clamped at 5.3V typical. 2. The Down Scaler can only be observed by the A/D. The errors of the A/D has to be taken into account. REQUIRED Symbol Min 4.85 Typ 5.1 Max 5.35 Unit - Comment 6V VSUP 25.5V, See note 1,2 and chapter 10 AGREEMENT 16.11 Die Temperature Monitor (device untrimmed, VSS = 0Vdc, unless otherwise noted) Characteristic High Temperature Reset On High Temperature Reset Hysteresis High Temperature Interrupt On High Temperature Interrupt Hysteresis Temperature Sensor A/D Reading Temperature Sensor A/D Reading Temperature Sensor Output Sensitivity (A/D Reading) NOTE: 1. By design the High Temperature Reset threshold is guaranteed to be (typically 25C) above the High Temperature Interrupt threshold. 2. Functionality of the device is not guaranteed for TJ 125C. See absolute maximum ratings. 3. Measured on final test with VDD forced to 5.0V and ATD switched to internal reference. Ptot ~ 100mW. Symbol THTRON THTRH THTION THTIH NTSOUT NTSOUT S Min - - - - - 171 - Typ 150 7 125 7 142 Max - - - - - 202 Unit C C C C 1/C Comment See note 1 & 2 NONDISCLOSURE TJ = 25C TA = 125C, note 3 -40C TJ +125C 0.45 - Technical Data 184 Electrical Specifications MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications Control Timing 16.12 Control Timing (VDD = 5.0Vdc 10%, VSS = 0Vdc, TJ = -40C to +125C, unless otherwise noted) Characteristic Frequency of Operation Crystal Oscillator Option (i.e. using the oscillator with a crystal) External Clock Source Oscillator Frequency With Enabled Clock Monitor Cycle Time (2/fOSC) Frequency Detected As Clock Monitor Error Clock Monitor Backup-Oscillator Frequency Crystal Oscillator Start-up Time Stop Recovery Start-up Time RESET Pulse Width Low Interrupt Pulse Width Low (Edge-Triggered) Interrupt Pulse Period OSC1 Pulse Width Supply rise slew rate for POR detection 16 bit Timer Resolution (note 2) Input Capture Pulse Width Input Capture Period NOTES: 1. The minimum period tILIL or tIHIH should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tCYC. 2. The 2-bit timer prescaler is the limiting factor in determining timer resolution. 3. The minimum period tTLTL should not be less than the number of cycles it takes to execute the capture interrupt service routine plus 24 tCYC. Symbol fOSC fOSC fOSC tCYC fOSC fOSC tOXON tILCH tRL tILIH tILIL tOSC1 SRISE tRESL tTH, tTL tTLTL Min 0.1 dc 0.4 476 dc 0.8 - - 120 120 note 1 90 0.1 4.0 85 note 3 Max 4.2 4.2 4.2 - 10 4.2 100 100 - - - - - - - - Unit MHz MHz MHz ns KHz MHz ms ms ns ns tCYC ns V/s tCYC ns tCYC MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications Technical Data 185 NONDISCLOSURE AGREEMENT REQUIRED Technical Data REQUIRED OSC11 tRL RESET t IRQ 2 ILIH tILCH 4064 t CYC AGREEMENT IRQ 3 Internal Clock Internal Address Bus 3FFE 3FFE 3FFE 3FFE 3FFF NOTES: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive selected. 3. IRQ pin level and edge-sensitive selected. 4.RESET vector address shown for timing example. RESET or Interrupt Vector Fetch NONDISCLOSURE Figure 16-3 Stop Recovery Timing Diagram Technical Data 186 Electrical Specifications MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications A/D Converter Characteristics 16.13 A/D Converter Characteristics (VREFH = VDD = 5.0Vdc 10%, VREFL = 0Vdc, TJ = -40C to +125C, unless otherwise noted) Characteristic Resolution Absolute Accuracy Conversion Range Voltage Reference High Level Voltage Reference Low Level Analog Input Voltage Zero Input Reading Full-scale Reading Conversion Time (Including Sampling Time) Sampling Time Power-up Time A/D On Current Stabilization Time RC Oscillator Stabilization Time A/D Capacitance NOTE: 1. tAD is either the bus clock period or the RC oscillator period (600ns typical). Symbol - - VREFH VREFL - - - TCONV TSAMP - tADON tRCON CAD Min 8 1.5 VREFL VREFL VSS VREFL 00 FE 32 12 - - - - Max Unit bit LSB Comment Including quantization error A/D accuracy may decrease proportionately as VREFH is reduced below VDD Must be within VSS and VDD VIN = VREFL VIN = VREFH VREFH VDD VREFH VREFH 01 FF V V V V Hex Hex tAD tAD See note 100 100 5 8 s s s pF Not tested MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications Technical Data 187 NONDISCLOSURE AGREEMENT REQUIRED Technical Data 16.14 Fast Peripheral Interface Timing (VDD = 5.0Vdc 10%, VSS = 0Vdc, TJ = -40C to +125C, unless otherwise noted) Characteristic DEN/AS Rise and Fall Time Pulse Width AS, DEN high Address, CS, RW setup time Address, CS, RW hold time Read data setup time Read data hold time Write data setup time Write data hold time NOTES: 1. The first cycle denotes a read, the second a write cycle. 2. Unlike in the HC11 AS and DEN occur only when accessing the external memory if not enabled continuously. 3. OSC1/OSC2 input clock other than 50% duty cycle affect bus performance. 4. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted. REQUIRED Symbol tR tF PW tAS tAH tDSR tDHR tDSW tDHW Min 210 49 22 100 50 30 30 Max 25 25 - Unit ns ns ns ns ns ns ns ns ns Comment See See See See See See See See NONDISCLOSURE AGREEMENT 1 PB0/AS 2 3 PB2/DEN 1 4 1 5 1 7 6 8 PB3/CS PB1/RW R/W R/W PA3:0 A3:0 D3:0 A3:0 D3:0 Figure 16-4 Timing definition Technical Data 188 Electrical Specifications MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications PORT C Characteristics 16.15 PORT C Characteristics 16.15.1 High Voltage Input/Output (PC0-4) (6V VSUP 16V, device untrimmed, VSS = 0Vdc, TJ = -40C to +125C, unless otherwise noted), Characteristic Input Low Voltage Input High Voltage Input Hysteresis Voltage (PC0-3, PC4 on MC68HC(8)05PV8) Leakage Current Input Pull-Down Current Output Low Voltage (PC0-3) Output High Voltage (PC0-4) Symbol HVIL HVIH VHYS Min 0 0.65 x VSUP 0.1 Typ - - 0.1 x VSUP Max 0.35 x VSUP VSUP - Unit V V V Comment ILEAK IPULLDOWN VOL VOH COUT tDB -10 - - 0.8 x VSUP - - 2.5 - 1.5 10 10 0.2 x VSUP - 10 A A V V pF s Inputs disabled Inputs enabled, VIN = VSUP ILOAD = 1mA ILOAD = -1mA Not tested Not tested (PC0-3 MC68HC05PV8A) Pin Capacitance Debounce Time (PC4 on MC68HC05PV8A) (9V VSUP 16V, device untrimmed, VSS = 0Vdc, TJ = -40C to +125C, unless otherwise noted) Characteristic Effective Internal Input Resistance Total Path Resistance for Low Threshold Total Path Resistance for High Threshold Total Path Resistance Hysteresis Symbol RIN RLT RHT RLT/RHT Min - 2.5 - - Typ - 4.0 6.0 0.75 Max 600 - 10.0 - Unit K K - Comment |ILOAD| = 5mA Injection Current IINJ -5 - 5 mA Not production tested. See also note 3 on page 179. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications Technical Data 189 NONDISCLOSURE 16.15.2 Contact Sense Circuitry to Vbattery (PC0-3) and to Ground (PC1-4 MC68HC(8)05PV8)/(PC1-3 MC68HC05PV8A) AGREEMENT REQUIRED Technical Data 16.15.3 ISO9141 Driver (PC4) MC68HC(8)05PV8 (6V VSUP 16V, device untrimmed, VSS = 0Vdc, TJ = -40C to +125C, unless otherwise noted Characteristic Output Falling Edge Slew Rate Output Rising Edge Slew Rate Rise Fall Slew Rates Symmetry Output Low Voltage Leakage Current (driver switched recessive) Current Limitation Threshold REQUIRED Symbol SRF SRR SR VOL ILEAK ILIM NOTES: Min 3 3 -1 - -10 40 Typ 5 5 0 1 Max 7 7 1 1.3 10 Unit V/s V/s V/s V A mA Comment RPull-up = 510, See note 2 ILOAD = 25mA -5V VIN VSUP See note 3 55 - AGREEMENT 1. The ISOMODE bit in PORTC CONFIG0 register must be set. 2. Calculated from 20% to 80% of the output swing. 3. PC4 is not short circuit protected to VSUP. 16.15.4 ISO9141 Driver (PC4) MC68HC05PV8A (6V VSUP 16V, device untrimmed, VSS = 0Vdc, TJ = -40C to +125C, unless otherwise noted Characteristic Output Falling Edge Slew Rate Output Rising Edge Slew Rate Symbol SRF SRR VOL ILEAK ILEAK ILIM Min -3.25 1.5 - -10 -10 40 Typ -2.25 2.25 1 Max -1.5 3.25 1.4 10 Unit V/s V/s V A mA mA Comment RPull-up = 510, See note 2 ILOAD = 25mA 0V VIN VSUP -16V VIN 0V Device powered See note 3 NONDISCLOSURE Output Low Voltage Leakage Current (driver switched recessive) Input Current (driver switched recessive) Current Limitation Threshold VIN/5K 55 0.01 - Technical Data 190 Electrical Specifications MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications PORT C Characteristics 16.15.5 Low Side Driver (PC5/6, PVSS) (6V VSUP 16V, device untrimmed, Vss = 0 Vdc, TJ = -40C to +125C, unless otherwise noted) Characteristic Output Resistance Leakage Current Positive Output Clamp Voltage Over Current Threshold Shutdown Symbol RDS_ON ILEAK VCLAMP ISHUTDOWN Min - -10 40 300 Typ 2 - 42.5 500 Max 4 10 45 700 Unit A V mA Comments ILOAD = 100mA 0V VIN 16V MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Electrical Specifications Technical Data 191 NONDISCLOSURE AGREEMENT REQUIRED Technical Data NONDISCLOSURE Technical Data 192 Electrical Specifications AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA B.1 Current Interface (PC5 or 6, PVSS) (6V VSUP 16V, device untrimmed, Vss = 0 Vdc, TJ = -40oC to +125oC, unless otherwise noted) Characteristic Output Current Symbol ILIM2 Min 30 Typ 35 Max 40 Unit mA Comments See note 1 NOTE : 1. With an external serial resistor 82.6 1%(typically) between PVSS and VSS. MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA Technical Data 193 NONDISCLOSURE AGREEMENT REQUIRED APPENDIX B ELECTRICAL SPECIFICATION FOR CURRENT COMMUNICATION INTERFACE Technical Data NONDISCLOSURE Technical Data 194 AGREEMENT REQUIRED MC68HC(8)05PV8/A -- Rev. 1.9 MOTOROLA How to Reach Us: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1-303-675-2140 1-800-441-2447 TECHNICAL INFORMATION CENTER: 1-800-521-6274 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://www.motorola.com/semiconductors/ MC68HC05PV8/D REV 1.9 |
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