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| 4M x 1-Bit Dynamic RAM HYB 514100BJ-50/-60 Advanced Information * 4 194 304 words by 1-bit organization * 0 to 70 C operating temperature * Fast Page Mode Operation * Performance: -50 -60 60 15 30 110 40 ns ns ns ns ns tRAC RAS access time tCAC CAS access time tAA tRC tPC Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 95 35 * Single + 5 V ( 10 %) supply with a built-in VBB generator * Low power dissipation max. 660 mW active (-50 version) max. 605 mW active (-60 version) * Standby power dissipation: 11 mW max. standby (TTL) 5.5 mW max. standby (CMOS) * Output unlatched at cycle end allows two-dimensional chip selection * Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode capability * All inputs and outputs TTL-compatible * 1024 refresh cycles/16 ms * Plastic Packages: P-SOJ-26/20-2 with 300 mil width Semiconductor Group 1 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM The HYB 514100BJ is the new generation dynamic RAM organized as 4 194 304 words by 1-bit. The HYB 514100BJ utilizes CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514100BJ to be packed in a standard plastic P-SOJ-26/20 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 5 V ( 10 %) power supply, direct interfacing with high performance logic device families such as Schottky TTL. Type HYB 514100BJ-50 HYB 514100BJ-60 Ordering Code Q67100-Q971 Q67100-Q759 Package P-SOJ-26/20-2 300 mil P-SOJ-26/20-2 300 mil Descriptions DRAM (access time 50 ns) DRAM (access time 60 ns) P-SOJ-26/20-2 V SS DO CAS N.C. A9 DI WE RAS N.C. A10 1 2 3 4 5 26 25 24 23 22 A0 A1 A2 A3 V CC 9 10 11 12 13 18 17 16 15 14 A8 A7 A6 A5 A4 SPP02808 Pin Configuration Pin Names A0 - A10 RAS CAS WE DI DO Address Input Row Address Strobe Column Address Strobe Read/Write Input Data In Data Out Power Supply (+ 5 V) Ground (0 V) No Connection VCC VSS N.C. Semiconductor Group 2 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM WE CAS & Data In Buffer DI No.2 Clock Generator Data Out Buffer DO 11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 11 Column Address Buffers (11) 11 Column Decoder Refresh Controller Sense Amplifier I/O Gating Refresh Counter (10) 10 Row Address Buffers (11) 10 Row Decoder . . . 1024 . . . 4096 Memory Array . . . . . . RAS No.1 Clock Generator Substrate Bias Generator V CC V SS SPB02847 Block Diagram Semiconductor Group 3 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM Absolute Maximum Ratings Operating temperature range ........................................................................................... 0 to 70 C Storage temperature range.................................................................................... - 55 to + 150 C Input/output voltage ....................................................................................................... - 1 to + 7 V Power Supply voltage .................................................................................................... - 1 to + 7 V Data out current (short circuit) ............................................................................................... 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 5 10 %, tT = 5 ns Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current, any input (0 V < VIN < 7, all other input = 0 V) Output leakage current (DO is disabled, 0 < VOUT < VCC) Average VCC supply current -50 version -60 version Standby VCC supply current (RAS = CAS = WE = VIH) Symbol Limit Values min. max. 0.8 - 0.4 10 10 2.4 - 1.0 2.4 - - 10 - 10 Unit Test Condition 1 1 1 1 1 VIH VIL VOH VOL II(L) IO(L) ICC1 VCC + 0.5 V V V V A A 1 - - 120 110 2 mA mA mA 2, 3 ICC2 - Average VCC supply current during RAS-only ICC3 refresh cycles -50 version -60 version Average VCC supply current during fast page ICC4 mode operation -50 version -60 version - - 120 110 mA mA 2 - - 80 70 mA mA 2, 3 Semiconductor Group 4 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM DC Characteristics (cont'd) TA = 0 to 70 C, VSS = 0 V, VCC = 5 10 %, tT = 5 ns Parameter Standby VCC supply current Average VCC supply current during CAS-before-RAS refresh mode -50 version -60 version Capacitance TA = 0 to 70 C, VCC = 5.0 V 10 %, f = 1 MHz Parameter Input capacitance (A0 to A10, DI) Input capacitance (RAS, CAS, WE) Output capacitance (DO) AC Characteristics 5, 6 TA = 0 to 70 C, VCC = 5 V 10 %, tT = 5 ns Parameter Symbol Limit Values -50 min. max. Common Parameters Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time -60 min. max. Unit Note Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit Symbol Limit Values min. max. 1 - Unit Test Condition mA 1 2 ICC5 ICC6 - - 120 110 mA mA CI1 CI2 CIO tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH 5 95 35 50 13 0 8 0 10 18 13 13 50 - - 10k 10k - - - - 37 25 110 40 60 15 0 10 0 15 20 15 15 60 - - 10k 10k - - - - 45 30 - - ns ns ns ns ns ns ns ns ns ns ns ns Semiconductor Group 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM AC Characteristics (cont'd) 5, 6 TA = 0 to 70 C, VCC = 5 V 10 %, tT = 5 ns Parameter Symbol Limit Values -50 min. max. CAS to RAS precharge time Transition time (rise and fall) Refresh period Read Cycle Access time from RAS Access time from CAS Access time from column address Column addr. to RAS lead time Read command setup time Read command hold time CAS to output in low-Z Output buffer turn-off delay Write Cycle Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time Read-Modify-Write Cycle Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time -60 min. max. 5 3 - - 50 16 ns ns ms 7 Unit Note tCRP tT tREF 5 3 - - 50 16 tRAC tCAC tAA tRAL tRCS tRCH tCLZ tOFF - - - 25 0 0 0 0 0 50 13 25 - - - - - 13 - - - 30 0 0 0 0 0 60 15 30 - - - - - 15 ns ns ns ns ns ns ns ns ns 8, 9 8, 9 8, 10 11 11 8 12 Read command hold time referenced to RAS tRRH tWCH tWP tWCS tRWL tCWL tDS tDH 8 8 0 13 13 0 10 - - - - - - - 10 10 0 15 15 0 10 - - - - - - - ns ns ns ns ns ns ns 14 14 13 tRWC tRWD tCWD tAWD 115 50 13 25 - - - - 130 60 15 30 - - - - ns ns ns ns 13 13 13 Semiconductor Group 6 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM AC Characteristics (cont'd) 5, 6 TA = 0 to 70 C, VCC = 5 V 10 %, tT = 5 ns Parameter Symbol Limit Values -50 min. max. Fast Page Mode Cycle Fast page mode cycle time CAS precharge time Access time from CAS precharge RAS pulse width CAS precharge to RAS Delay Fast Page Mode Read-Modify-Write Cycle Fast page mode read-write cycle time CAS precharge to WE CAS-before-RAS Refresh Cycle CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS CAS-before-RAS Counter Test Cycle CAS precharge time Test Mode Write command setup time Write command hold time -60 min. max. Unit Note tPC tCP tCPA tRAS tRHCP 35 10 - 50 30 - - 30 200k - 40 10 - 60 35 - - 35 - ns ns ns ns 7 200k ns tPRWC tCPWD 55 30 - - 60 35 - - ns ns tCSR tCHR tRPC tWRP tWRH 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns tCPT 35 - 40 - ns tWTS tWTH 10 10 - - 10 10 - - ns ns Semiconductor Group 7 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM Notes All voltages are referenced to VSS. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5. An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6. AC measurements assume tT = 5 ns. 7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8. Measured with a load equivalent to 2 TTL loads and 100 pF. 9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as a reference point only: If tRCD is greater than the specified tRCD (MAX.) limit, then access time is controlled by tCAC. 10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as a reference point only: If tRAD is greater than the specified tRAD (MAX.) limit, then access time is controlled by tAA. 11.Either tRCH or tRRH must be satisfied for a read cycle. 12.tOFF (MAX.) defines the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13.tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle and the data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (MIN.), tCWD > tCWD (MIN.), tAWD > tAWD(MIN.) and tCPWD > tCPWD (MIN.), the cycle is a readwrite cycle and DO will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the DO pin (at access time) is indeterminate. 14.These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 1. 2. 3. 4. Semiconductor Group 8 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM t RC t RAS VIH RAS t RP VIL t CSH t RCD VIH CAS t RSH t CAS t RAL t CAH t CRP VIL t RAD t ASR VIH A0 - A10 t ASC t ASR Column Address Row Address VIL Row Address t RAH t RCS t RRH t AA t CAC t CLZ Hi Z t RCH VIH WE VIL t OFF Valid Data OUT Hi Z VOH DO (Output) V OL t RAC "H" or "L" SPT03013 Read Cycle Semiconductor Group 9 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM t RC t RAS VIH RAS t RP VIL t CSH t RCD VIH CAS t RSH t CAS t RAL t CAH t CRP VIL t RAD t ASR VIH A0 - A10 t ASC t ASR Column Address Row Address VIL Row Address t RAH t WCS VIH WE t CWL t WP t WCH t RWL t DH VIL t DS DI (Input) VIH Valid Data IN VIL Hi Z VOH DO (Output) V OL "H" or "L" SPT03014 Write Cycle (Early Write) Semiconductor Group 10 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM t RWC t RAS VIH RAS VIL t CSH t RCD VIH CAS t CAS t RSH t RP t CRP VIL t ASR VIH A0 - A10 t RAH t ASC t CAH Column Address t ASR Row Address VIL Row Address t CWL t AWD t RAD t RWD VIH WE t CWD t RWL t WP VIL t AA t RCS DI (Input) t DS t DH Valid Data IN VIH VIL t CAC t CLZ t OFF Data OUT DO (Output) V OL VOH t RAC "H" or "L" SPT03015 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 11 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM t RASP VIH RAS VIL t CSH t RP t CP t RCD VIH CAS t PRWC t CAS t CAS t RSH t CRP t CAS VIL t RAD t ASR VIH A0 - A10 t RAH t ASC t CAH t CAH t ASC Column Address t CAH t ASC Column Address t RAL t ASR Row Address VIL Row Address Column Address t RWD t CWD t RCS VIH WE t CWL t CPWD t CWD t CWL t CPWD t CWD t RWL t CWL VIL t AWD t WP t AA VIH Data IN Data IN Data IN t AWD t WP t AA t DS t DH t AA t DS t AWD t WP t DS t DH t DH DI (Input) VIL t CLZ t CAC t RAC t OFF Data OUT Data OUT t CPA t CLZ t CAC t CPA t CLZ t OFF Data OUT t OFF VOH DO (Output) V OL "H" or "L" SPT03016 Fast Page Mode Read-Modify-Write Cycle Semiconductor Group 12 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM t RASP VIH RAS VIL t RCD t PC t CP t CAS VIH CAS t RP t RHCP t RSH t CAS t CAS t CRP VIL t RAH t ASR VIH A0 - A10 Row Addr t ASC t CSH t CAH t ASC t CAH t ASC t CAH t ASR Row Address t RCH VIL Column Address Column Address Column Address t RCS VIH WE t RAD t RCH t RCS t RCS t RRH VIL t RAC t AA t CAC t OFF t CLZ VOH DO (Output) V OL Valid Data OUT t CPA t AA t CAC t OFF t CLZ Valid Data OUT t CPA t AA t CAC t OFF t CLZ Valid Data OUT "H" or "L" SPT03017 Fast Page Mode Read Cycle Semiconductor Group 13 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM t RASP VIH RAS VIL t PC t CAS t RCD VIH CAS t RP t CAS t CP t RSH t CAS t CRP VIL t RAH t ASR VIH A0 - A10 Row Addr t ASC t CAH t ASC t CAH t ASC t RAL t CAH t ASR Row Address VIL Column Address Column Address Column Address t RAD t WCS t CWL t WCH t WP VIH WE t WCS t CWL t WCH t WP t WCS t RWL t CWL t WCH t WP VIL t DS DI (Input) t DH Valid Data IN t DS t DH Valid Data IN Hi Z t DS t DH Valid Data IN VIH VIL VOH DO (Output) V OL "H" or "L" SPT03018 Fast Page Mode Early Write Cycle Semiconductor Group 14 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM t RC t RAS VIH RAS t RP VIL t CRP t RPC VIH CAS VIL VIH A0 - A10 t ASR t RAH t ASR Row Address Hi Z Row Address VIL VOH DO (Output) V OL "H" or "L" SPT03019 RAS-Only Refresh Cycle Semiconductor Group 15 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM t RC t RP VIH RAS t RAS t RP VIL t RPC t CSR t CP VIH CAS t CRP t CHR t RPC VIL t WRP t WRH VIH WE VIL t OFF VOH DO (Output) V OL Hi Z "H" or "L" SPT03020 CAS-Before-RAS Refresh Cycle Semiconductor Group 16 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM t RC t RAS VIH RAS t RC t RP t RAS t RP VIL t RCD VIH CAS t RSH t CHR t CRP VIL t RAD t ASC t RAH t ASR VIH A0 - A10 Row Addr. t WRH t CAH Column Address t WRP t ASR Row Address VIL VIH WE t RCS t RRH VIL t CLZ t RAC VOH DO (Output) V OL Valid Data OUT t AA t CAC t OFF Hi Z "H" or "L" SPT03021 Hidden Refresh Cycle (Read) Semiconductor Group 17 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM t RC t RAS VIH RAS t RC t RP t RAS t RP VIL t RCD VIH CAS t RSH t CHR t CRP VIL t RAD t ASC t RAH t ASR VIH A0 - A10 Row Addr t CAH Column Address t ASR Row Address VIL t WCS t WCH t WP VIH WE VIL t DS t DH DI (Input) VIN Valid Data VIL Hi Z VOH DO (Output) V OL "H" or "L" SPT03022 Hidden Refresh Cycle (Early Write) Semiconductor Group 18 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM t RAS VIH RAS t RP VIL t CHR t CSR VIH CAS t RSH t CPT t CAS t RAL t CAH t ASC t ASR Row Address VIL VIH A0 - A10 VIL t WRP Column Address Read Cycle VIH WE t WRH t RCS t AA t CAC t RRH t RCH VIL t CLZ VOH DO (Output) V OL t WRP t WCS t WRH t RWL t CWL t WCH t DH t OFF Valid Data OUT Write Cycle VIH WE VIL t DS DI (Input) VIH Valid Data IN VIL Hi Z VOH DO (Output) VOL t CWL t RWL t WRP t WRH t RCS t AWD t CWD t WP t CAC t AA Read-ModifyWrite Cycle VIH WE VIL t DS t DH Data IN DI (Input) VIH VIL VOH t CLZ Valid Data OUT "H" or "L" t OFF DO (Output) V OL t CAC SPT03023 CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group 19 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM t RC t RP VIH RAS t RAS t RP VIL t RPG t CSR t CP VIH CAS t RPC t CHR t CRP VIL t ASR VIH A0 - A10 Row Address VIL t WTH t WTS VIH WE VIL t OFF VOH DO (Output) V OL Hi Z "H" or "L" SPT03024 Test Mode Entry Test Mode The HYB 514100BJ is organized 4 194 304 words by 1-bit but can internally be configured as 524 288 words by 8-bits. A WE, CAS-before-RAS cycle puts the device into Test Mode. In Test Mode, data is written into 8 sectors in parallel and retrieved the same way. If, upon reading, all bits are equal, the data output pin indicates a "1". If any of the bits differ, the data output pin indicates a "0". In Test Mode the 4M DRAM can be tested as if it were a 512K DRAM. Test Mode is exited by any refresh operation which is not a WE, CAS-before-RAS cycle. Addresses A10R, A10C and A0C do not care during Test Mode. Semiconductor Group 20 1998-10-01 HYB 514100BJ-50/-60 4M x 1 DRAM Package Outlines Plastic Package, P-SOJ-26/20-2 (SMD) (Plastic small outline J-leaded) 0.8 min 2.75 3.75 -0.5 B 0.6 1.27 0.51-0.1 0.85 max 0.2 20x 15.24 0.1 0.25 A 0.3 30 6.80.3 8.63 -0.25 0.2 +0.1 0.25 B 0.18 B GPJ09100 7.75 -0.25 o1 26 22 18 14 1.4 1 1 5 9 13 17.27 -0.25 Index Marking A Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 21 Dimensions in mm 1998-10-01 |
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