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Integrated Circuit Systems, Inc.
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS /1, /2, /4 CLOCK GENERATOR
FEATURES
* 6 HCSL outputs * 2 LVCMOS/LVTTL outputs * 1 Differential LVPECL clock input pair * PCLK, nPCLK supports the following input types: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency: 600MHz (maximum) * Output skew: 100ps (maximum) * Propagation delay: 4ns (maximum) * 3.3V operating supply * 0C to 85C ambient operating temperature * Lead-Free package available * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS87158 is a high performance 1-to-6 LVPECL-to-HCSL/LVCMOS Clock Generator and HiPerClockSTM is a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS87158 has one differential input (which can accept LVDS, LVPECL, LVHSTL, SSTL, HCSL), six differential HCSL output pairs and two complementary LVCMOS/LVTTL outputs. The six HCSL output pairs can be individually configured for divide-by-1, 2, and 4 or high impedance by use of select pins. The two complementary LVCMOS/LVTTL outputs can be configured for divide by 2, divide by 4, high impedance, or driven low for low power operation.
ICS
The primary use of the ICS87158 is in Intel (R) E8870 chipsets that use Intel (R) Pentium 4 processors. The ICS87158 converts the differential clock from the main system clock into HCSL clocks used by Intel (R) Pentium 4 processors. However, the ICS87158 is a highly flexible, general purpose device that operates up to 600MHz and can be used in any situation where Differential-toHCSL translation is required.
BLOCK DIAGRAM
MULT_0 MULT_1 IREF
PIN ASSIGNMENT
GND VDD VDD_R PCLK nPCLK GND_R VDD_M MREF nMREF GND_M VDD GND VDD_L VDD GND_L SEL_T MULT_0 MULT_1 VDD_L GND_L SEL_A SEL_B SEL_U PWR_DWN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD GND_H VDD_H HOST_P1 HOST_N1 GND_H HOST_P2 HOST_N2 VDD_H HOST_P3 HOST_N3 GND_H HOST_P4 HOST_N4 VDD_H HOST_P5 HOST_N5 GND_H HOST_P6 HOST_N6 VDD_H IREF GND_I VDD_I
CURRENT ADJUST
+ /1,2,4
PWR_DWN# SEL_T
VDD HOST_P1 HOST_N1 GND_H VDD HOST_P6 HOST_N6 GND_H VDD HOST_P2 HOST_N2 GND_H VDD HOST_P3 HOST_N3 GND_H VDD HOST_P4 HOST_N4 GND_H VDD HOST_P5 HOST_N5 GND_H VDD MREF nMREF GND_H
PCLK nPCLK
/1,2,4
SEL_A SEL_B SEL_U
DIVIDER CONTROL
48-Lead TSSOP 6.1mm x 12.5mm x .92mm body package G Package Top View 48-Lead SSOP 7.5mm x 15.9mm x 2.3mm body package F Package Top View
/2,4
NOTE: Intel and Pentium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
87158AG
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REV. B JULY 8, 2004
Integrated Circuit Systems, Inc.
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS /1, /2, /4 CLOCK GENERATOR
Type Power Power Power Input Input Power Power Output Power Power Power Input Input Description Power supply ground. Positive supply pins. Power supply pin for differential reference clock inputs. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Power supply ground for differential inputs. Power supply pin for MREF clock outputs. Single ended clocks provided as a reference clock to a memor y clock driver. LVCMOS / LVTTL interface levels. Power supply ground for MREF clock outputs. Power supply pin for logic input pins. Power supply ground for logic input pins. Active high input tristates all outputs. Pulldown LVCMOS / LVTTL interface levels. The logic setting on these two pins selects the multiplying factor Pulldown of the IREF reference current for the HOST pair outputs. LVCMOS / LVTTL interface levels. The logic setting on these two pins selects the multiplying factor of the IREF reference current for the HOST pair outputs. Pullup LVCMOS / LVTTL interface levels. Power supply pin for logic input pins. Pulldown Selects desired output frequencies. LVCMOS / LVTTL interface levels. Asynchronous active-low LVTTL power-down signal forces MREF outputs low, tristates HOST_N outputs, and drives HOST_P output currents to 2xIREF. LVCMOS / LVTTL interface levels. Power supply pin for IREF current reference input. Power supply ground for IREF current reference input. A fixed precision resistor from this pin to ground provides a reference current used for differential current-mode HOST clock outputs. Power supply pins for the differential HOST clock outputs. Differential output pairs. HCSL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 12 2, 11, 14, 48 3 4 5 6 7 8, 9 10 13 15, 20 16 17 Name GND VDD VDD_R PCLK nPCLK GND_R VDD_M MREF, nMREF GND_M VDD_L GND_L SEL_T MULT_0
18 19 21, 22, 23
MULT_1 VDD_L SEL_A, SEL_B, SEL_U PWR_DWN# VDD_I GND_I IREF VDD_H HOST_N6, HOST_P6
Input Power Input
24 25 26 27 28, 34, 40, 46 29, 30 31, 37, 43, 47
Input Power Power Input Power Output
Pullup
GND_H Power Power supply ground for the differential HOST clock outputs. HOST_N5, 32, 33 Output Differential output pairs. HCSL interface levels. HOST_P5 HOST_N4, Output 35, 36 Differential output pairs. HCSL interface levels. HOST_P4 HOST_N3, Output Differential output pairs. HCSL interface levels. 38, 39 HOST_P3 HOST_N2, Output Differential output pairs. HCSL interface levels. 41, 42 HOST_P2 HOST_N1, Output 44, 45 Differential output pairs. HCSL interface levels. HOST_P1 NOTE: Pullup and Puddown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87158AG
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REV. B JULY 8, 2004
Integrated Circuit Systems, Inc.
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS /1, /2, /4 CLOCK GENERATOR
Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor
TABLE 3A. CONTROL INPUT FUNCTION TABLE
PWR _DWN# 1 1 1 1 1 1 1 1 1 0 Inputs SEL SEL _T _A 0 0 0 0 0 0 0 0 0 1 X 0 0 0 1 1 1 1 X X SEL _B 0 0 1 1 0 0 1 1 X X SEL _U 0 1 0 1 0 1 0 1 X X HST_P1 HST_N1 /2 Hi Z /4 /4 /1 Hi Z /2 /2 Hi Z HST_P1 =2 x IREF HST_N1 = Hi Z HST_P2 HST_N2 /2 /2 /2 /4 /1 /1 /1 /2 Hi Z HST_P2 =2 x IREF HST_N2 = Hi Z HST_P3 HST_N3 /2 /2 /2 /4 /1 /1 /1 /2 Hi Z HST_P3 =2 x IREF HST_N3 = Hi Z Outputs HST_P4 HST_N4 /2 /2 /2 /4 /1 /1 /1 /2 Hi Z HST_P4 =2 x IREF HST_N4 = Hi Z HST_P5 HST_N5 /2 /2 /2 /4 /1 /1 /1 /2 Hi Z HST_P5 =2 x IREF HST_N5 = Hi Z HST_P6 HST_N6 /2 Hi Z /4 /4 /1 Hi Z /2 /2 Hi Z HST_P6 =2 x IREF HST_N6 = Hi Z MREF_P MREF_N /4 /4 /4 /4 /4 /4 /4 /2 Hi Z MREF_P = low MREF_N = low
TABLE 3B. FUNCTION TABLE
Inputs MULT_0 0 0 1 1 MULT_1 0 1 0 1 Board Target Trace/Term Z 50 50 50 50 Device Configurations Reference R, IREF = VDD/ (3*Rr) Rr = 475 1%, IREF = 2.32mA Rr = 475 1%, IREF = 2.32mA Rr = 475 1%, IREF = 2.32mA Rr = 475 1%, IREF = 2.32mA Output Current IOH = 5*IREF IOH = 6*IREF IOH = 4*IREF IOH = 7*IREF VOH @ 50 Environment 0.6V 0.7V 0.5V 0.8V
87158AG
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REV. B JULY 8, 2004
Integrated Circuit Systems, Inc.
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS /1, /2, /4 CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 58.3C/W (0 lfpm) 52.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA 48 Lead TSSOP 48 Lead SSOP Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 85C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 65 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 85C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage MULT_1, PWR_DWN# Input High Current SEL_A, SEL_B, SEL_T, SEL_U, MULT_0 MULT_1, PWR_DWN# Input Low Current SEL_A, SEL_B, SEL_T, SEL_U MULT_0 Output High Voltage; NOTE 1 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 2.6 0.5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 5 150 Units mV mV A A A A V V
IIL VOH
Output Low Voltage; NOTE 1 VOL All parameters measured at 200MHz in, 100MHz out on HOST_XX and 50MHz out on MREF. Current adjust set for VOH = 0.7V. Measurements refer to HOST_XX outputs only. NOTE 1: Outputs terminated with 50 to VDD/2. See Paramter Measurement Information Section, "3.3V Output Load Test Circuit".
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 85C
Symbol IIH IIL V PP Parameter Input High Current Input Low Current PCLK, nPCLK PCLK, nPCLK Test Conditions VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -5 0.15 1.3 VDD - 0.85 Minimum Typical Maximum 5 Units A A V V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VCMR All parameters measured at 200MHz in, 100MHz out on HOST_XX and 50MHz out on MREF. Current adjust set for VOH = 0.7V. Measurements refer to HOST_XX outputs only. NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
87158AG
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4
REV. B JULY 8, 2004
Integrated Circuit Systems, Inc.
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS /1, /2, /4 CLOCK GENERATOR
Test Conditions RREF = 475, RLOAD = 50 IOH = 6*IREF RREF = 475, RLOAD = 50 IOH = 6*IREF -10 280 Minimum 12.9 0.7 0.03 10 430 Typical Maximum 14.9 Units mA V V A mV
TABLE 4D. HCSL DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 85C
Symbol IOH VOH VOL IOZ VOX Parameter Output Current Output High Voltage Output Low Voltage High Impedance Leakage Current Output Crossover Voltage
All parameters measured at 200MHz in, 100MHz out on HOST_XX and 50MHz out on MREF. Current adjust set for VOH = 0.7V. Measurements refer to HOST_XX outputs only.
TABLE 5A. HCSL AC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4, 5 Par t-to-Par t Skew; NOTE 3, 5 Cycle-to-Cycle Jitter Output Rise Time Output Fall Time 20% to 80% 20% to 80% 175 175 3.7 60 Test Conditions Minimum Typical Maximum 600 4.0 100 500 150 700 700 Units MHz ns ps ps ps ps ps
tsk(o) tsk(pp) tjit(cc)
tR tF
o dc Output Duty Cycle 48 52 % All parameters measured at 200MHz in, 100MHz out on HOST_XX and 50MHz out on MREF. Current adjust set for VOH = 0.7V. Measurements refer to HOST_XX outputs only. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: Maximum value calculated at +3 from typical. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. LVCMOS / LVTTL AC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 85C
Symbol fMAX Parameter Output Frequency Cycle-to-Cycle Jitter Output Rise Time Output Fall Time CL = 10pF/30pF 0.4V to 2.4V, CL = 10pF 0.4V to 2.4V, CL = 30pF 0.4V to 2.4V, CL = 10pF 0.4V to 2.4V, CL = 30pF 0.4 2 52 0.4 1.8 Test Conditions Minimum Typical Maximum 300 150 Units MHz ps ns ns ns ns %
tjit(cc)
tR tF
48 odc Output Duty Cycle CL = 10pF/30pF All parameters measured at 200MHz in, 100MHz out on HOST_XX and 50MHz out on MREF. Current adjust set for VOH = 0.7V. Measurements refer to MREF outputs only.
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87158AG
REV. B JULY 8, 2004
Integrated Circuit Systems, Inc.
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS /1, /2, /4 CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
3.3V5%
3.3V5%
VDD, V DD_X
SCOPE
Qx
VDD, V DD_X
SCOPE
450
HCSL
GND
LVCMOS
10pF/30pF
GND
0V
0V
3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
VDD
HOST_Nx
HOST_Px
nPCLK
V
PP
Cross Points
V
HOST_Ny HOST_Py
CMR
PCLK
tsk(o)
GND
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
80% Clock Outputs
80% VSW I N G
2.4V
20%
2.4V 0.4V
20%
tR
tF
Clock Outputs
0.4V
tR
tF
HCSL OUTPUT RISE/FALL TIME
87158AG
LVCMOS OUTPUT RISE/FALL TIME
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6
REV. B JULY 8, 2004
Integrated Circuit Systems, Inc.
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS /1, /2, /4 CLOCK GENERATOR
HOST_Nx HOST_Px
Pulse Width t
PERIOD
V MREF, nMREF Pulse Width t
DDO
2
PERIOD
odc =
t PW t PERIOD
odc =
t PW t PERIOD
HCSL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nPCLK PCLK HOST_Nx HOST_Px
tPD
PROPAGATION DELAY
87158AG
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7
REV. B JULY 8, 2004
Integrated Circuit Systems, Inc.
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS /1, /2, /4 CLOCK GENERATOR APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
87158AG
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8
REV. B JULY 8, 2004
Integrated Circuit Systems, Inc.
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS /1, /2, /4 CLOCK GENERATOR
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V SWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V
3.3V
3.3V
R1 50
R2 50
PCLK
3.3V Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
nPCLK
HiPerClockS PCLK/nPCLK
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R3 125
R4 125
PCLK
Zo = 50 Ohm
Zo = 50 Ohm
nPCLK
LVPECL
R1 84
R2 84
HiPerClockS Input
R5 100 - 200 R6 100 - 200 R1 125 R2 125
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V 3.3V 2.5V R3 120 SSTL Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK HiPerClockS PCLK/nPCLK
Zo = 50 Ohm
3.3V
3.3V 3.3V
Zo = 50 Ohm
R4 120
LVDS
C1
R3 1K
R4 1K
PCLK
R5 100
C2
nPCLK
HiPerClockS PCL K/n PC LK
R1 120
R2 120
R1 1K
R2 1K
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
FIGURE 2F.
HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
87158AG
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9
REV. B JULY 8, 2004
Integrated Circuit Systems, Inc.
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS /1, /2, /4 CLOCK GENERATOR
SCHEMATIC EXAMPLE
Figure 3 shows an example of the ICS87158 LVPECL to HCSL Clock Generator schematic.
In this example, the ICS87158 is configured as follows: PWR_DWN# = 1 Mult_[1:0] = 10, Rref = 475, IREF = 2.32mA, IOH = 6*IREF SEL_[A,B,U] = 000, MREF = PECL / 4, all HOST output = PECL / 2 SEL_T = 0, Output Enable
VDD=3.3V VDD=3.3V U1
Zo = 50
200MHz, 3.3V LVPECL
Zo = 50
3.3V LVPECL
R1 50
R2 50
ICS8431-01 ICS8431-11
R3 50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
GND VDD VDD_R PECL nPECL GND_R VDD_M MREF nMREF GND_M VDD GND VDD_L VDD GND_L SEL_T MULT_0 MULT_1 VDD_L GND_L SEL_A SEL_B SEL_U PWR_DWN# 85158
VDD GND_H VDD_H HOST_P1 HOST_N1 GND_H HOST_P2 HOST_N2 VDD_H HOST_P3 HOST_N3 GND_H HOST_P4 HOST_N4 VDD_H HOST_P5 HOST_N5 GND_H HOST_P6 HOST_N6 VDD_H IREF GND_I VDD_I
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Rref 475
100MHz, HCSL
Zo = 50 R6 33 Zo = 50 R7 33 R4 50 R5 50 +
R8 28
R9 28
Zo = 50
50MHz, LVCMOS/LVTTL
ICS9222-01_REFCLK
Zo = 50
ICS9222-01_REFCLK
(U1-2)
(U1-11)
C3 0.1uF C4 0.1uF
(U1-14)
C5 0.1uF
(U1-48)
C5 0.1uF
VDD=3.3V (U1-13)
(U1-19)
C7 0.1uF
(U1-7)
C8 0.1uF
(U1-28)
C9 0.1uF
(U1-34)
C10 0.1uF
(U1-40)
C9 0.1uF
(U1-46)
C10 0.1uF
(U1-25)
C10 0.1uF
(U1-23)
C10 0.1uF
C6 0.1uF
FIGURE 3. ICS87158 SCHEMATIC LAYOUT
87158AG
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10
REV. B JULY 8, 2004
Integrated Circuit Systems, Inc.
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS /1, /2, /4 CLOCK GENERATOR
pin as possible. It is preferable to locate the bypass capacitor on the same side as the IC. Figure 4 shows suggested capacitor placement. Placing the bypass capacitor on the same side as IC allows the capacitor to have direct contact with the IC power pin. This can avoid any vias between the bypass capacitor and the IC power pins. The vias should be place at the Power/Ground pads. There should be minimum one via per pin. Increase the number of vias from the Power/Ground pads to Power/Ground planes can improve the conductivity.
Power and Ground
This section provides a layout guide related to power, ground and placement of bypass capacitors for a high-speed digital IC. This layout guide is a general recommendation. The actual board design will depend on the component types being used, the board density and cost constraints. The description assumes that the board has clean power and ground planes. The principal is to minimize the ESR between the clean power/ground plane and the IC power/ground pin. A low ESR bypass capacitor should be used on each power pin. The value of bypass capacitors ranges from 0.01uF to 0.1uF. The bypass capacitors should be located as close to the power
Power Pin
IC
POWER Pads C GND Pads GND Pin VIA
FIGURE 4. RECOMMENDED LAYOUT
OF
BYPASS CAPACITOR PLACEMENT
87158AG
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11
REV. B JULY 8, 2004
Integrated Circuit Systems, Inc.
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS /1, /2, /4 CLOCK GENERATOR
To set logic high, the input pin connected directly to VDD. To set logic low, the control input connect directly to ground. For control signal source from the driver that has different power supply, a series current resistor of greater than 100 Ohm is required for random power on sequence.
LOGIC CONTROL INPUT
The logic input control signals are 3.3V LVCMOS compatible. The logic control input contains ESD diodes and either pull-up or pull-down resistor as shown in Figure 5. The data sheet provides pull-up or pull-down information for each input pin. Leaving the input floating will set the control logic to default setting.
VDD
VDD
D1 RU 51K INPUT_PU INPUT_DOWN
D1
D2 RD 51K
D2
A) Input with internal pull up resistor
B) Input with internal pull down resistor
FIGURE 5. LOGIC INPUT CONTROLS
HCSL DRIVER TERMINATION
The HCSL is a differential constant current source driver. The output current is set by control pins MULT_[1:0] and the value of resistor Rref. In the characteristic impedance of 50 Ohm environment, the match load 50 Ohm resistors R4 and R5 are terminated at the receiving end of the transmission line. The 33 Ohm series resistor R6 and R7 should be located as close to the driver pins as possible. For the clock traces that required very low skew should have equal length. Other general rules of high-speed digital design also should be followed. Some check points are listed as follows: Avoid sharp angles on the clock trace. Sharp angle turn causes the characteristic impedance change on the transmission lines. Keep the clock trace on same layer. Whenever possible, avoid any vias on the middle clock traces. Any via on middle the trace can affect the trace characteristic impedance and hence degrade signal quality. There should be sufficient space between the clock traces that have different frequencies to avoid cross talk. No other signal trace is routed between the clock trace pair. Transmission line should not be routed across the split plane on the adjacent layer.
-
-
87158AG
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REV. B JULY 8, 2004
Integrated Circuit Systems, Inc.
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS /1, /2, /4 CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 6A.
JAVS. AIR FLOW TABLE FOR 48 LEAD TSSOP PACKAGE
JA by Velocity (Linear Feet per Minute)
0 200
70.3C/W 52.3C/W
500
63.7C/W 49.9C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
82.6C/W 58.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6B.
JAVS. AIR FLOW TABLE FOR 48 LEAD SSOP PACKAGE
JA by Velocity (Linear Feet per Minute)
0 200
46.0C/W
500
42.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
52.9C/W
TRANSISTOR COUNT
The transistor count for ICS87158 is: 2631
87158AG
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REV. B JULY 8, 2004
Integrated Circuit Systems, Inc.
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS /1, /2, /4 CLOCK GENERATOR
48 LEAD TSSOP PACKAGE OUTLINE - F SUFFIX
FOR
PACKAGE OUTLINE - G SUFFIX
FOR
48 LEAD SSOP
TABLE 6A. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -6.00 0.50 BASIC 0.75 8 0.10 -0.05 0.80 0.17 0.09 12.40 8.10 BASIC 6.20 Millimeters Minimum 48 1.20 0.15 1.05 0.27 0.20 12.60 Maximum
TABLE 6B. PACKAGE DIMENSIONS
SYMBOL N A A1 b c D E E1 e h L 0.38 0.50 0 2.41 0.20 0.20 0.13 15.75 10.03 7.40 0.635 BASIC 0.64 1.02 8 Millimeters Minimum 48 2.80 0.40 0.34 0.25 16.00 10.68 7.60 Maximum
Reference Document: JEDEC Publication 95, MO-118
Reference Document: JEDEC Publication 95, MO-153
87158AG
www.icst.com/products/hiperclocks.html
14
REV. B JULY 8, 2004
Integrated Circuit Systems, Inc.
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS /1, /2, /4 CLOCK GENERATOR
Package 48 Lead TSSOP 48 Lead TSSOP on Tape and Reel 48 Lead SSOP 48 Lead SSOP on Tape and Reel 48 Lead "Lead-Free" SSOP 48 Lead "Lead-Free" SSOP on Tape and Reel Count 48 per Tube 2500 30 per Tube 1000 30 per Tube 1000 Temperature 0C to 85C 0C to 85C 0C to 85C 0C to 85C 0C to 85C 0C to 85C
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS87158AG ICS87158AGT ICS87158AF ICS87158AFT ICS87158AFLF ICS87158AFLFT Marking ICS87158AG ICS87158AG ICS87158AF ICS87158AF ICS87158AFLF ICS87158AFLF
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87158AG
www.icst.com/products/hiperclocks.html
15
REV. B JULY 8, 2004
Integrated Circuit Systems, Inc.
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS /1, /2, /4 CLOCK GENERATOR
REVISION HISTORY SHEET Description of Change Pin Assignment - corrected typo error for Pin 4 and 5. Corrected 3.3V LVCMOS Output Load Test Circuit Diagram. Updated Single Ended Signal Driving Differential Input Diagram. Updated format. Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Power Supply Table - changed IDD 48mA typical to 65mA max. Updated LVPECL Clock Input Interface section. Added Lead-Free bullet to Features section. Added Lead-Free par t number to Ordering Information table. Date
Rev
Table
Page 1 6 8
A
1/15/03
B B
T2 T4A
T7
3 4 9 1 15
6/24/04 7/8/04
87158AG
www.icst.com/products/hiperclocks.html
16
REV. B JULY 8, 2004

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