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Gigabit SERDES Transceiver
IDT77V7101TM
x x x
x x x x x x x x x x x
The IDT77V7101 is a monolithic 1.25 Gigabits per second (Gbps) Ethernet Serializer/Deserializer (SERDES) Transceiver. It is designed to provide the Physical Medium Attachment (PMA) portion of the IEEE 802.3z PHY layer.
PCS CHIP TXER TXEN TXD[7:0] GTX_CLK COL TRANSMIT BLOCK
TXCG[9:0] TCLK TRANSMIT SECTION
GMII Interface
RPT LEDs RESET CRS MDIO MDC RXER RXDV RXD[7:0] RXCLK
CONTROL
EWRAP SDT RECEIVE SECTION RXP RXN TERMINATION NETWORK
LINK CONFIG
RECEIVE BLOCK
COMDET ENCDET RCLK[1:0] RXCG[9:0]
7101 drw 01
The IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
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2000 Integrated Device Technology, Inc.
November 13, 2000
DSC-7101-1
MEDIUM
QRLWSLUFVH'
IEEE 802.3z Gigabit Ethernet compatible ANSI X3T11 Fibre Channel compatible 1.25 Gbps full duplex transmission and reception in a single IC Optical interface through fiber module 10-bit parallel TX and RX interfaces based on EIA/TIA X3T11 Signal Detect, internal or external Code Group Realignment with Disable Internal Loopback mode 62.5MHz recovered clock Low power 3.3V CMOS Few external components required 64-pin 10mm and 14mm packages Pin-outs are compatible with industry standard devices Industrial Temperature (-40C to +85C) is available.
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IEEE 802.3z Gigabit media interfaces: - 1000BASE-LX Optical - 1000BASE-SX Optical x Provides the PMA function of the PHY x High speed custom serial interface x Backplane serial link x Bus extension
IDT77V7101 IDT77V7101/7111 PMA CHIP
TXP TXN
TERMINATION NETWORK
IDT77V7101TM
Figure 1 shows a block diagram of a typical application. The parallel interface connects to a Physical Coding Sublayer (PCS) chip. The serial inputs and outputs connect directly to a fiber optic module for optical transmission. Figure 2 shows an internal block diagram of the IDT77V7101. The TXCG[9:0] inputs receive parallel 10-bit transmit code groups, already encoded in 8B/10B format by the PCS chip. The code groups are latched on the rising edges of the incoming 125MHz reference clock (TCLK). Then they are serialized, and the bit stream is retimed by an internal PLL that multiplies TCLK up to 1250MHz. This data stream is transmitted through PECL drivers into the cable or fiber optic module. The 77V7101 receives serial data from the fiber optic module. It deserializes the data into 10-bit receive code groups, and recovers a receive clock (RCLK) from the data stream. RCLK is used to clock-out the receive code groups to the PCS chip. RCLK is output at 62.5MHz in two complementary phases as RCLK[0] and RCLK[1]. RCLK[0] and RCLK[1] are used to clock out alternating code groups. A Signal Detect I/O pin has been provided. For fiber optic media, it can be configured as an input, allowing the fiber module to perform signal detection.
The user-supplied 125MHz transmit reference clock (TCLK) is used for several functions. As the transmit code group clock, its rising edges directly strobe the 10-bit input data latch to sample the transmit code group bus, TXCG[9:0]. Therefore, its edges must be properly aligned to the incoming parallel transmit data. TCLK also serves as the frequency reference for the Transmit PLL Clock Multiplier, which uses it to synthesize the internal clock signals necessary for 1.25 Gbps signaling.
It is assumed that the original 8-bit user data to be transmitted has already been 8B/10B-encoded into 10-bit transmit code groups by external PCS logic before being sent to the IDT77V7101 for transmission. The incoming code groups are received on the Transmit Code Group bus, TXCG[9:0], and are sampled on the rising edges of TCLK by the input data latch. Figure 6 shows the timing relationship between the clock and the parallel data, and the "AC Electrical Characteristics" section shows the timing requirements for these signals. The parallel transmit data is sent to the parallel-to-serial converter. This uses the internal clock signals synthesized by the transmit PLL to convert the 10-bit transmit data from parallel to serial format, and to retime each bit at 1250MHz. The least significant bit TXCG[0] is transmitted first.
PARALLEL TO SERIAL
INPUT DATA LATCHES
TXCG [9:0]
TX SERI AL DATA
DR IVE R
TCLK PLLCAP1 PLLCAP2 SDTSE L SDT
125M Hz
TX CLOCK 1,250MH z CLO CK M ULTIPLIE R PLL
SIG NAL DETEC T
ENA BLE OUTPUT DATA LATCHES & DRIVERS EQ USE L SERIAL TO PARALLEL RE-TIM ED R X SE RIAL DATA RX CLOCK & DATA REC OVE RY
1 0
RXC G[9:0]
1,250MH z
125M Hz RCLK [1] RCLK [0] 62.5M Hz (V 7101) 125M Hz (V 7111) RX CLOCK DIV IDER
CO M DET END ET
CO M M A DETEC T
RE-S YNC
Figure 1 IDT77V7101 Internal Block Diagram 2 of 13 November 13, 2000
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RX S E RIAL DATA REC OVE RED RX CLOC K
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TXP TXN
ENABLEO P
EW RAP
RX EQ UALIZE R
RXP RXN
IDT77V7101TM
The Line Driver is a source-follower that provides a voltage-mode differential PECL-level-compatible output. It has a differential source impedance of approximately 30W. ENABLEOP must be held to a logic high level for normal operation. When ENABLEOP is held low, the Line Driver output is set to a high impedance state. Refer to the "Medium Attachment" section below for more information on connecting the line driver to various media.
A code group alignment function detects the presence of comma+ characters (0011111xxx) in the receive data stream. If ENDET=1, each occurrence of a comma+ causes realignment of the bit positions of the received comma+ code group to match the standard 8B/10B format. Realignment may be achieved by dropping bits from the data stream when necessary. Comma+ characters are always clocked out by the rising edge of RCLK[1]. In the case of the 77V7101 this may entail stretching RCLK[1:0] half a cycle (nominally 8ns). Subsequent code groups retain this bit and clock alignment unless shifted by errors. If ENDET=0, realignment and clock stretching are disabled. The COMDET output is an indicator for the detection of comma+ characters. When ENDET is high and a comma+ character is detected, COMDET will go high for half an RCLK period, following the rising edge of RCLK[0]. Otherwise, it will remain low. Proper operation of COMDET, RCLK[1:0], and the code group alignment function requires that comma+ characters not be received back-toback, as per standard 8B/10B encoding.
The 77V7101 has an equalization circuit at the receiver input to compensate the signal distortion caused by unequalized cable. For operation over short cables or long internally equalized cables, the equalizer can be either enabled or disabled. Users may wish to disable it in cases where crosstalk or reflections rather than electrical line length are the major causes of signal impairment, such as when the serial link runs through a crowded backplane or poorly matched connector rather than a long unequalized cable. Doing so can improve the tolerance of these impairments. The equalizer can also be disabled for the same reason when interfacing to fiber optic transceivers or to short or internally-equalized cables.
Following equalization and buffering, the receive serial data stream is retimed by the recovered bit-clock, then converted from serial to parallel form using both bit- and code-group-clocks. Parallel receive data is clocked into the output data latch by the internal 125MHz code-groupclock, and output at the Receive Code Group bus, RXCG[9:0]. RCLK[1:0] are used to clock out the data from RXCG[9:0] as described in "Clock Recovery" above.
Loopback mode permits testing most of the internal circuitry without using an external medium, and is enabled by holding EWRAP high. Transmit code groups sent to the TXCG[9:0] inputs are processed normally by the transmit circuitry, then looped back through the receive circuitry to the RXCG[9:0] outputs as if they were incoming serial data. At the loopback point, transmit serial data is diverted from before the Line Driver, and replaces the equalizer output as the input to the clock and data recovery circuits. Nearly all the internal circuits except for the Line Driver and Receive Equalizer are exercised, with all internal Serializer, Deserializer, and clock functions occurring at their normal rates. Loopback mode holds the Line Driver output at PECL logic 1. For normal operation, EWRAP must be held low.
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After the serial input signal has passed through the front end's equalizing amplifier, a receive clock must be recovered with which to sample the incoming data stream. Clock recovery is automatic, with no user intervention such as PLL training necessary. The internal Receive PLL locks the phase of its VCO to that of the incoming data to produce a bitclock. This bit-clock is then divided down to become the internal 125MHz code-group clock (ICLK). Finally, the recovered receive clock is output as complementary signals (180o out of phase with each other) at RCLK[0] and RCLK[1] at 62.5MHz in the 77V7101. In the 77V7101, the 62.5MHz RCLK[0] and RCLK[1] signals are used to clock out alternating 125MHz code groups.
The Signal Detect pin SDT is a bi-directional pin controlled by SDTSEL. When STDSEL is high, SDT is an output that remains high when the receive signal amplitude exceeds the Signal Detect threshold VSD, and receive data will be output normally at RXCG[9:0]. (Note that this does not indicate that a compliant 1000BASE-X signal is being received.) A receive signal amplitude below the threshold causes the SDT output to remain low, and the RXCG[9:0] outputs to all be forced to logic 1. This helps prevent the generation of random data at the receiver outputs in the absence of valid incoming data. When SDTSEL is low, SDT becomes a PECL input to allow external devices such as fiber optic modules to perform the Signal Detect function. Signal detection should cause the external device to drive SDT to PECL logic 1, while insufficient signal amplitude should drive SDT to PECL logic 0. As before, a logic 0 at SDT will cause RXCG[9:0] outputs to all be forced to logic 1.
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The Transmit Line Driver transmits the serial data in differential form onto the transmit half of the chosen medium. The Line Driver can connect directly to copper media such as 150W twinax cable (through DC-blocking capacitors), or through a fiber optic transceiver module to fiber optic cable.
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November 13, 2000
IDT77V7101TM
Figure 3 shows a typical method of connecting either fiber optic links. In this case 150 bias resistors are connected from TXP and TXN to ground. AC-coupling of transmitter output to cable is used, as required by IEEE 802.3z. The optional series resistors RSER may be added to help absorb reflections due to mismatched loads. Typical values range from 0-50. The amount of output attenuation desired should also be considered when setting these values. Load terminations, transmission lines (including traces) and connectors should be selected or designed to have matching impedances.
The 77V7101 consumes less than 625 mW at peak power. The device is guaranteed in an ambient temperature range of 0 to +70 C for commercial temperature devices; -40 to +85 for industrial temperature devices.
October 6, 1999: Revised Figure 2. Changed figure numbers. Added "Recommended Operating Conditions." October 21, 1999: Revised "Receive Equalization" session. Changed tJTT from "200 ps pk-pk" to "40 ps RMS." Changed cable length from 30m to 25m. April 21, 2000: Removed references to 77V7114, 1000BASE-CX, and TwinAx cable. Deleted the figure "Typical 1000BASE-CX Medium Attachment." September 15, 2000: Changed 100 to 115 on page 5. November 13, 2000: Added Thermal Considerations section. Added Industrial Temperature information to Features and Ordering Information sections.
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HFDIUHWQ, ODLUH6 HFDIUHWQ, ODLUH6 HFDIUHWQ, ODLUH6 HFDIUHWQ, ODLUH6 WQHPKFDWW$ PXLGH0 WQHPKFDWW$ PXLGH0 WQHPKFDWW$ PXLGH0 WQHPKFDWW$ PXLGH0
July 1, 1999: Initial publication.
\ URWVL+ QRLVLYH5 \ URWVL+ QRLVLYH5 \ URWVL+ QRLVLYH5 \ URWVL+ QRLVLYH5
September 14, 1999: Deleted drawing on page 3.
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November 13, 2000
IDT77V7101TM
VCC (5V) 0.1uF
68.1 0.01uF
68.1
FIBER OPTIC LINK
0.01uF
TXP
0.01uF
TD+
RD+
115 100
RXP
TXN
150 150 191 191
TD-
RD0.01uF 270 270
RXN
100 OHM DIFFERENTIAL TRACE PAIRS
7101 drw 05
Figure 2 Typical 1000BASE-LX/SX Medium Attachment (Fiber Optic Half Link Shown)
Notes: x The optional series RSER resistors may be added to help absorb reflections due to mismatched loads. Typical values range from 0-50, depending on the characteristic impedance of the transmission lines and the amount of acceptable attenuation. x Termination circuits at the fiber optic module are typical values for a module running on a 5V supply, with 115 differential impedance at each load end. Modules with other supply voltages may require adjustment of these circuit values to achieve the recommended input voltages. Follow fiber optic module manufacturer's recommendations for setting input voltages, receiver bias resistors, and termination impedance.
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November 13, 2000
IDT77V7101TM
ENABLEOP
GND
GND
VDD
VDD
VDD
RXN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GND TXCG0 TXCG1 TXCG2 VDD TXCG3 TXCG4 TXCG5 TXCG6 VDD TXCG7 TXCG8 TXCG9 GND GND PLLCAP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
7101 drw 06
Pin 1 Index
VDD
RXP
EQ U SEL
GND
GND
VDD
TXP
VDD
TXN
ENCDET
PLLCAP2
SDT
RCLK1
UNUSED
UNUSED
RCLK0
VDD
TCLK
VDD
GND
GND
VDD
EWRAP
Figure 3 Pin Assignments
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GND
VDD
o
48 47 46 45 44 43 42
SDTSEL COMDET GND RXCG0 RXCG1 RXCG2 VDD RXCG3 RXCG4 RXCG5 RXCG6 VDD RXCG7 RXCG8 RXCG9 GND
IDT77V7101 IDT77V71x1
41 40 39 38 37 36 35 34 33
November 13, 2000
IDT77V7101TM
22
TCLK
TTL Input
The transmit code group clock, 1/10 the serial baud rate, whose rising edges are used to sample the incoming transmit code groups (TXCG[9:0]). TCLK is also the reference clock used by the transmit PLL to synthesize the high-speed serial data clock. The PMA chip's transmit code group input port, accepting 10-bit parallel transmit data already encoded in 8B/10B format. This bus is clocked into the chip on the rising edge of TCLK. TXCG[0] is the least significant bit and the first to be transmitted. The high-speed + and - serial data differential outputs to the cable or fiber optic transmitter. For output = "1", TXP > TXN. Table 1 Transmit-Side Signals
13,12,11,9,8,7, TXCG[9:0] 6,4,3,2 62,61 TXP,TXN
TTL Inputs
HS Output
54, 52 34,35,36,38, 39,40,41,43, 44,45 30, 31
RXP, RXN RXCG[9:0]
HS Input TTL Output
The high-speed serial data differential inputs from the twisted-pair cable or fiber optic receiver. For input = "1", RXP > RXN. The PMA chip's receive code group output port, presenting 10-bit receive data on alternate rising edges of RCLK[0] and RCLK[1] for the V7101. If ENCDET = 1, comma + code groups are realigned and forced to be clocked by RCLK[1]. RXCG[9:0] are forced high when SDT = 0. RXCG[0] is the least significant bit and the first to be received. The complementary receive clock outputs, recovered from the received serial data. The V7101 RCLK[1:0] outputs are 1/20 the serial baud rate, and clock-out alternate receive code groups from RXCG[9:0] on their rising edges. If ENCDET = 1. RCLK[1] clocks all comma + characters. Table 2 Receive-Side Signals
RCLK1 RCKL0
TTL Output
47
COMDET
TTL Output
When ENCDET=1 and a comma+ character is detected in the receive bit stream, COMDET will go high for half an RCLK period in the V7101, or one clock period in the V7111, following the rising edge of RCLK[0]. A high level on this pin is required to activate the Line Driver, which otherwise remains in a high impedance state. An internal 50k pull-up resistor prevents "floating". Hold ENABLEOP high for normal operation. A logic 1 input enables code group realignment on comma+ reception. A logic 0 input keeps current word alignment and disables COMDET. An internal 50k pull-up resistor prevents "floating". Mode Select input for Equalizer. If EQUSEL=0, equalization is on. If EQUSEL=1, equalization is off. Equalization may be turned on for all cable lengths. An internal 50k pull-down resistor prevents "floating". Hold EQUSEL low for normal operation. Table 3 Control Signals (Part 1 of 2)
59
ENABLEOP
TTL Input
24 49
ENCDET
EQUSEL
TTL Input TTL Input
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emaN emaN emaN
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November 13, 2000
IDT77V7101TM
19
EWRAP
TTL Input
"Enable Wrap," this signal must be at a logic low level for normal operation. A high logic level forces the transmit data to be looped back from TXCG[9:0] to RXCG[9:0], exercising most of the internal circuitry. An internal 50k pull-down resistor prevents "floating". Hold EWRAP low for normal operation. A .001F capacitor is connected between these pins to set the loop filter characteristics of the transmit PLL. Signal Detect, with direction controlled by SDTBYPASS. If SDTBYPASS is high, SDT is a TTL output, where a logic 1 indicates that the receiver input level is above the internal "signal detect" threshold. If SDTBYPASS is low, SDT becomes a PECL input, enabling signal detection by external devices such as fiber optic transceivers. In any case, a logic 0 at SDT forces all RXCG[9:0] signals high, while a logic 1 allows normal operation. Signal Detect direction control. If SDTBYPASS=0, SDT is a PECL level input. If SDTBYPASS=1, SDT is a TTL output. (See SDT description above.) An internal 50k pull-up resistor prevents "floating". Hold SDTBYPASS high for normal operation. This pin must be connected to VCC. This pin should be left unconnected. Table 3 Control Signals (Part 2 of 2)
16 17 26
PLLCAP1 PLLCAP2 SDT
Analog Bi-directional PECL Input TTL Output
48
SDTBYPASS
TTL Input
23 27
UNUSED UNUSED
TTL Input Output
5,10,18,20, 28,29,37,42,50,53,55,57,60,63 1,14,15,21, 25,32,33,46,51,56,58,64
VDD GND Table 4 Power Supply Pins
Power Power
Positive supply pins. Ground supply pins.
DC Supply Voltage (VDD) Terminal Voltage with respect to GND Terminal Voltage with respect to VDD Storage Temperature Range
1. Stresses
-0.5 -0.5
+5 +5 +0.5
V V V Celsius
-40 Table 5 Absolute Maximum Ratings1
+150
greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress ratng only and i functional operation of the device at these or any other conditions above those indicated in the operations sections of this spe cification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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November 13, 2000
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IDT77V7101TM
VDD TA
DC supply voltage Ambient Temperature
3.15 -40 Table 6 Recommended Operating Conditions
3.3
3.45 +85
V C
VIL, TTL 2 VIL, TTL 2
TTL Input High Voltage TTL Input Low Voltage PECL Input High Voltage PECL Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage Input Capacitance Transceiver VDD Supply Current DC supply voltage Power dissipation TA = 25 SDTSEL is low SDTSEL is low VDD = 3.45V, VIN = 2.4V VDD = 3.5V, VIN = 0.4V VDD = 3.15V, IOUT = -400A VDD = 3.15V, IOUT = 1mA
2.0 -0.3 VDD - 1.165 -0.3
VDD + 0.5 0.80 VDD + 0.5 VDD - 1.475 40
V V V V A A
VIL, PECL 3 VIL, PECL 3 IIH IIL VOH VOL CIH IDD VDD PD
1. Test conditions
-600 2.2 0 VDD 0.5 4 180 3.15 3.3 570 3.45 890
V V pF mA V mW
Table 7 DC Electrical Characteristics (Includes all I/O pins except TXP, TXN, RXP, RXN)
are Recommended Operating Conditions unless otherwise noted.
2. Not
for SDT. only, when SDTSEL is logic low.
3. For SDT
fBD2
Serial Baud Rate TCLK Reference Frequency TCLK Frequency Tolerance TCLK Duty Cycle TCLK Jitter TCLK Rise Time TCLK Fall Time RCLK Frequency (77V7101) RCLK Rise Time 0.8V to 2.0V, CL = 10pF 0.8V to 2.0V 2.0V to 0.8V
1000
1250 fBD/10
1360
MBaud MHz
fREF fTOL tDC, TC tJTT tR, TC tF, TC fRCLK tR, RC
-100 40
+100 60 40
ppm % ps RMS ns ns MHz
0.7 0.7 fBD/20 0.7
2.4 2.4
2.4
ns
Table 8 AC Electrical Characteristics (Part 1 of 2)
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November 13, 2000
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IDT77V7101TM
tF, RC tDC, RC tA-B tR, RX 3 tF, RX3
RCLK Fall Time RCLK Duty Cycle RCLK0 to RCLK1 rising edge skew (77V7101) RXCG Rise Time RXCG Fall Time RXCG Setup Time to rising RCLK RXCG Hold Time from rising RCLK TXCG Rise Time TXCG Fall Time TXCG Setup Time to rising TCLK TXCG Hold Time to rising TCLK Transmit Latency Receiver Latency Signal Detect Threshold HS Input Differential Voltage HS Output Differential Voltage HS Output Differential Off Voltage HS Output Differential Rise Time HS Output Differential Fall Time Total Transmit Jitter
0.8V to 2.0V, CL = 10pF 1.4V to 1.4V, CL = 10pF 1.4V to 1.4V, CL = 10pF 0.8V to 2.0V, CL = 10pF 0.8V to 2.0V, CL = 10pF {0.8,2.0}V to 1.4V, CL = 10pF 1.4V to {0.8,2.0}V, CL = 10pF 0.8V to 2.0V 0.8V to 2.0V {0.8,2.0}V to 1.4V 1.4V to {0.8,2.0}V
0.7 40 7.5 0.7 0.7 2.5 1.5 0.7 0.7 2.0 1.0 1 1
2.4 60 8.5
ns % ns ns ns ns ns ns ns ns ns
tSU, RX tHO, RX tR, TX3 tF, TX3
tSU, TX tHO, TX tLAT, TX4 tLAT, RX 5 VSD VIHS VOHS VOHS, OFF tR, HS tF, HS JTOTAL6
1. Test
16 34 200 200 1100 100 2000 2000 170 85 85 327 327 192 Table 8 AC Electrical Characteristics (Part 2 of 2)
ns ns mV pk-pk mV pk-pk mV pk-pk mV pk-pk ps ps ps pk-pk
conditions are Recommended Operating Conditions unless otherwise noted. 100ppm is the rate specified by IEEE 802.3z. not specify code group maximum rise and fall times, but TXCG and RXCG inputs and outputs must meet the required setup and hold times.
2. 1250 Mbaud 3. IEEE does
4. Transmitter latency is 5. Receiver
the time from the positive edge of TCLK that clocks in a particular transmit code group to the differenti al first edge of the first bit of that code group to be transmitted at TXP/N. Reference levels are 1.4V for TCLK, and zero-crossing for AC-coupled TXP-TXN.
latency is the time from the differential first edge of the first bit of a particular code group received at RXP/N to the positive edge of the RCLK output (RCLK 0 or RCLK1) that clocks out that code group. Reference levels are 1.4V for RCLK and zero-crossing for AC-coupled RXP-RXN.
6. Total jitter at this component level is specified by IEEE 802.3z at TP1, as they define test points. See subclauses 38.5, 38.6.8 -9, and 39.3.3 for system level specifications and measurement methods.
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November 13, 2000
WLQ8
[D0
S\7
QL0
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UHWHPD UD3
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IDT77V7101TM
VPDUJDL' JQLPL7 VPDUJDL' JQLPL7 VPDUJDL' JQLPL7 VPDUJDL' JQLPL7
TCLK TXCG[9:0]
0.8V 1.4V tSU, TX 2.0V
VALID DATA VALID DATA
tHO, TX
7101 drw 07
Figure 4 Transmit Parallel Interface Timing Diagram
RCLK[1] RXCG[9:0]
1.4V t SU, RX 2.0V 0.8V 2.0V tHO, RX
COMMA+ CODE GROUP
COMDET
0.8V t SU, RX
RCLK[0]
1.4V t A-B
7101 drw 08
Figure 5 Receive Parallel Interface Timing Diagram
RCLK[1] RXCG[9:0] COMDET
1.4V 2.0V 0.8V 2.0V 0.8V t SU, RX
COMMA+ CODE GROUP
t HO, RX
RCLK[0]
1.4V
7101 drw 09
Figure 6 Receive Parallel Interface Timing Diagram
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November 13, 2000
IDT77V7101TM
SYMBOL A A1 A2 D D1 E E1 L e b
MIN. -- 0.05 1.35 -- -- -- -- 0.45 -- 0.17
NOM. -- 0.10 1.40 12.00 10.00 12.00 10.00 -- 0.50 0.22
MAX. 1.60 0.15 1.45 -- -- -- -- 0.75 -- 0.27
MIN. -- 0.05 1.35 -- -- -- -- 0.45 -- 0.30
Note: Dimensions are in millimeters.
1. A more comprehensive package outline drawing is
available from the IDT website.
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13
33
VQRLVQHPL' HJDNFD3 VQRLVQHPL' HJDNFD3 VQRLVQHPL' HJDNFD3 VQRLVQHPL' HJDNFD3
Draft Angle = 11 -13 64 A2 1 A1 64-Pin TQFP PP64 or PN64 e 0.20 Rad Typ.
4.3514 ' .
E1
5.4035 '
E
0.20 Rad Typ. 4 4
2.4792 '
4.3021 '
D1 D
A
5.3521 ' 7101 drw 10
L
b
NOM. -- 0.10 1.40 16.00 14.00 16.00 14.00 -- 0.80 0.37
MAX. 1.60 0.15 1.45 -- -- -- -- 0.75 -- 0.45
November 13, 2000
IDT77V7101TM
QRLWDP URIQ, JQLUHGU2 QRLWDP URIQ, JQLUHGU2 QRLWDP URIQ, JQLUHGU2 QRLWDP URIQ, JQLUHGU2
797', 797', 797', 797',
77 V Device Type Supply Voltage 7 Network Type 1 Speed 0 Option 1 Ports T Package Temp Range/ Process Blank = Commercial Temperature (0 C to +70 C Ambient) I = Industrial Temperature (-40 C to +85 C Ambient) TF = 10x10mm TQFP PP64 PF = 14x14mm TQFP PN64 1 = 1-port device 0 = Standard 62.5 MHz RCLK 1 = 1.25 Gbits/s 7 = Ethernet V = 3.3V supply 77 = Network Product
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com
for Tech Support: email: atmhelp@idt.com phone: 408-492-8208
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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November 13, 2000

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