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| Z8 Encore!(R) Motor Control Series Z8 Encore!(R) Z8FMC16 MCU Programming Specification PRS000502-1005 PRELIMINARY ZiLOG Worldwide Headquarters 532 Race Street San Jose, CA 95126-3432 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters 532 Race Street San Jose, CA 95126-3432 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. Document Disclaimer (c)2005 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN TH IS DOCUM EN T. Zi LO G A LSO DO ES NO T ASSU ME LI ABILITY FO R I NTELLECTU AL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights. PRS000502-1005 PRELIMINARY Z8FMC16 MCU Programming Specification 1 Flash Memory Programming Overview The Z8 Encore!(R) Z8FMC16 Motor Control features a Flash program memory selections of 8KB or 16KB. By using Flash memory, you have the ability to easily update the code. The Z8 Encore!(R) features an on-chip Flash controller that typically manages the timing of Flash control signals for programming, page erase, and mass erase operations. The Flash controller can also be bypassed to allow direct control of Flash signals via the general purpose input/output (GPIO) pins. Flash memory can be programmed faster by controlling the Flash memory signals directly. Bypassing the Flash controller is beneficial when programming a large number of devices, and is most likely to be used by third party vendors who are developing the multi-site gang programmers. Bypassing the Flash Controller Flash controller bypass mode is enabled by writing the following three bytes of instruction to the on-chip debugger (OCD) via the DBG interface: 1. 80H - This instruction initiates auto-baud calculation of the DBG interface data and clock rate. 2. F0H - OCD writes testmode register command. 3. 04H - Data to be written to the testmode register. This data enables the Flash controller bypass mode. Flash Memory Control Signals Depending on the size (number of bytes) available in the Flash memory, the Flash memory uses fourty two signals for its direct interfacing. 16 signals for the address lines. 8 signals for data input. 8 signals for data output. 10 signals for control operations. The Flash memory control signals are listed and described in Table 1 PRS000502-1005 PRELIMINARY Flash Memory Programming Overview Z8FMC16 MCU Programming Specification 2 . Table 1. Flash Memory Control Signals Signal Direction I Description XADDR[9:0] X address input selects a row. XADDR[9:0] corresponds to the upper 10 bits of the program memory address space (PROGMEM[15:6]). For Z8 Encore!(R) devices with less than 64KB of program memory, the unused upper address bits must be set to 0. Y address input selects one byte within a row. YADDR[5:0] corresponds to the lower 6 bits of the program memory address space (PROGMEM[5:0]). Data input. Data output. X address enable. Y address enable. Sense amplifier enable. Output enable. Erase enable. This signal is used to select erase operations. Mass erase select. This signal is used to distinguish between page erase and mass erase operations. Program enable. This signal is used to select a program operation. Non-volatile store enable. This signal is used during page erase, mass erase, and programming operations. This signal should be set to 1 during all operations. Information area select. YADDR[5:0] I DIN[7:0] DOUT[7:0] XE YE SE OE ERASE MAS1 PROG NVSTR TMR IFREN I O I I I I I I I I I I Flash Memory Operations When bypassing the Flash controller, all Flash memory operations (read, program, page erase, and mass erase) are available. The mode of operation is set by the Flash memory control signals as described in Table 2. The selection of the Flash main memory or the Flash information area depends on the IFREN signal as described in Table 3. PRS000502-1005 PRELIMINARY Flash Memory Programming Overview Z8FMC16 MCU Programming Specification 3 Table 2. Flash Mode Truth Table Mode XE YE SE OE PROG ERASE MAS1 NVSTR TMR IFREN Read Program Page Erase Mass Erase H H H H H H L L H L L L H L L L L H L L L L H H L L L H L H H H H H H H L/H1 L/H1 L/H1 L/H1 See Table 3 for IFREN signal operation information. Table 3. IFREN Signal Truth Table Mode IFREN = 1 IFREN = 0 Read Program Page Erase Mass Erase Read Information Area Page Erase Information Area Mass Erase Information Area Read Main Memory Page Erase Main Memory Mass Erase Main Memory Program Information Area Program Main Memory Flash Bypass Mode Register Structure For using Flash controller bypass mode for all package sizes, the signals must be registered internally. This allows all data access to occur through pin PWM2L and Port A [6:0]. Three other pins (PWM2H, PWM1L, and PWM1H), selects one of the input data registers or the data output register as shown in Table 4. PRS000502-1005 PRELIMINARY Flash Memory Programming Overview Z8FMC16 MCU Programming Specification 4 Table 4. Control Registers in Flash Bypass Mode Register Select [PWM2H, PWM1L, PWM1H] 000 Input/Output Input 001 Input 010 Input 011 Input 100 Input 101 Output 110-111 Input PWM2L Port A6 Port A5 Port A4 Port A3 Port A2 Port A1 Port A0 XADDR[9] XADDR[1] DIN[7] XADDR[8] XADDR[0] DIN[6] XADDR[7] YADDR[5] DIN[5] XADDR[6] YADDR[4] DIN[4] XADDR[5] YADDR[3] DIN[3] XADDR[4] YADDR[2] DIN[2] XADDR[3] YADDR[1] DIN[1] XADDR[2] YADDR[0] DIN[0] XE YE SE OE ERASE PROG MAS1 NVSTR TMR IFREN NOP NOP NOP NOP NOP NOP DOUT[7] DOUT[6] DOUT[5] DOUT[4] DOUT[3] DOUT[2] DOUT[1] DOUT[0] NOP NOP NOP NOP NOP NOP NOP NOP PRS000502-1005 PRELIMINARY Flash Memory Programming Overview Z8FMC16 MCU Programming Specification 5 Flash Bypass Mode Register Structure Figure 1 illustrates the multiplexed register structure that allows access to all Flash memory signals through GPIO ports. Flash Registers XADDR[9:0] YADDR[5:0] Data Input/Output PortA0 PortA1 PortA2 PortA3 PortA4 PortA5 PortA6 PWM2L DIN[7:0] DOUT[7:0] XE YE OE SE ERASE PROG MAS1 NVSTR TMR IFREN Register Select PWM2H PWM1L PWM1H Figure 1. Flash Bypass Mode Register Structure Bypass Mode Register Read Timing Figure 2 illustrates the timing of a read operation using the Flash controller bypass mode registers. While reading data, output data is latched into the output register on the first PRS000502-1005 PRELIMINARY Flash Memory Programming Overview Z8FMC16 MCU Programming Specification 6 clock edge. The data is read during the next clock period. Mode selector comprises of the following pins: PWM2H, PWM1L, and PWM1H. XIN Mode Selector Port driven by Chip XX 101 XX XX Data Data Latched in Output Register Figure 2. Bypass Mode Register Read Timing Bypass Mode Register Write Timing Figure 3 illustrates the timing of a write operation using the Flash controller bypass mode registers. When writing data into the registers, the data is latched on the rising edge of XIN. XIN Mode Selector Port driven externally Data latched in selected register on rising edge of Xin Figure 3. Bypass Mode Register Write Timing Flash Row Programming The Flash memory can be programmed either as a single byte at a time or as a row of bytes at a time. Multi-byte row programming allows programming of a full row of Flash memory without incurring all of the programming setup and recovery time for each byte. During row programming, the Flash memorys PROG and NVSTR signals are PRS000502-1005 PRELIMINARY Flash Memory Programming Overview Z8FMC16 MCU Programming Specification 7 continuously asserted until all bytes in a row are programmed. This allows the row to be programmed faster than if these signals are deasserted after programming each byte. During row programming, you must ensure that the cumulative programming high voltage period does not exceed the specification limits for a row. Flash Memory Timing Table 5 and Figures 4 through Figure 7 provides the detailed timing information on accessing the Flash memory in Flash controller bypass mode. Table 5. Flash Memory Timing Parameters Parameter Symbol Min. Max. Unit X address access time Y address access time OE access time PROG/ERASE to NVSTR setup time NVSTR hold time NVSTR hold time (Mass Erase) NVSTR to program setup time Program hold time Byte program time Address / Data setup time Address / Data hold time Recovery time Cumulative program high Erase time Mass Erase time 1 Txa Tya Toa Tnvs Tnvh Tnvh1 Tpgs Tpgh Tprog Tads Tadh Trcv voltage period1 Thv Terase Tme 5 5 100 10 20 30 20 20 1 10 200 40 40 4 60 12 - ns ns ns s s s s ns s ns ns s ms ms ms Thv is the cumulative high voltage programming time for a single row before the next erase. Caution: The same address (byte) cannot be programmed more than twice before the next erase. PRS000502-1005 PRELIMINARY Flash Memory Programming Overview Z8FMC16 MCU Programming Specification 8 Flash Read Timing Figure 4 illustrates the timing of a read operation from the Flash memory. IFREN XADDR XE YADDR YE SE OE Txa DOUT Toa Tya ERASE = 0, MAS1 = 0, NVSTR = 0, TMR = 1 Figure 4. Flash Read Timing PRS000502-1005 PRELIMINARY Flash Memory Programming Overview Z8FMC16 MCU Programming Specification 9 Flash Program Timing Figure 5 illustrates the Flash programming operation for three bytes on a single row. The XADDR is unchanged while PROG and NVSTR are high, but the YADDR changes three times to identify three different bytes in a single row. IFREN XADDR XE YADDR YE DIN PROG Tadh Tnvs Tprog Tads Tpgh NVSTR Tpgs Thv Tnvh Trcv SE = 0, OE = 0, ERASE = 0, MAS1 = 0, TMR = 1 Figure 5. Flash Byte Program Timing PRS000502-1005 PRELIMINARY Flash Memory Programming Overview Z8FMC16 MCU Programming Specification 10 Flash Page Erase Timing Figure 6 illustrates the timing of a Flash page erase operation. IFREN XADDR XE ERASE Tnvs NVSTR Tnvh Terase Trcv YE = 0, SE = 0, OE = 0, PROG = 0, MAS1 = 0, TMR = 1 Figure 6. Flash Page Erase Timing PRS000502-1005 PRELIMINARY Flash Memory Programming Overview Z8FMC16 MCU Programming Specification 11 Flash Mass Erase Timing Figure 7 illustrates the timing of a Flash mass erase operation.With IFREN driven high (1), the mass erase operation will erase both the main memory and the information area. With IFREN driven low (0), the mass erase operation will erase only the main memory. IFREN XADDR XE MAS1 ERASE Tnvs NVSTR Tnvh1 Tme Trcv YE = 0, SE = 0, OE = 0, PROG = 0, TMR = 1 Figure 7. Flash Mass Erase Timing PRS000502-1005 PRELIMINARY Flash Memory Programming Overview Z8FMC16 MCU Programming Specification 12 Z8FMC16100 Flash Programming Flowchart Figure 8 illustrates an example flowchart for read and write operations. Z8FMC16100 Flash Programming Flowchart START RESET& DBG Low 5ms Release RESET 20us Release DBG OSCCT L E2 OSCCT L 18 OSCCT L E7 Autobaud Wait f or break Autobaud XIN is Sy sClk WriteOCD 0x08, 0x0F, 0x86, 0x01, 0xE2 4 E FFREQL* 2 0 Write OCD 0x08, 0x0F, 0x86, 0x01, 0x18 FCT L 7 3 Unlockstep1 Write OCD 0x08, 0x0F, 0x86, 0x01, 0xE7 FCT L 8C Unlockstep2 WriteOCD 0x80 WriteOCD 0x80 FFREQH* FCT L 6 3 Iss ues Mass erase Mass Erase Flash? N o WrT estmode Register WriteOCD 0x08, 0x0F, 0xFA, 0x01, 0x4E WriteOCD 0x08, 0x0F, 0xFB, 0x01, 0x20 Autobaud Write OCD 0x08, 0x0F, 0xF8, 0x01, 0x73 Write OCD 0x08, 0x0F, 0xF8, 0x01, 0x8C WriteOCD 0x08, 0x0F, 0xF8, 0x01, 0x63 WriteOCD 0xF0 WriteOCD 0x04 Flash Controller By passed Set T MR & TEST 1 Val ueforWr T es tmode Register WriteOCD 0x80 250 ms * The Values f or FFREQH and FFREQL are based on a 20MHz clock source. This v alue is set by the f ollowing equation {FFREQH[7:0], FFREQL[7:0]}=(Clock Frequency )/ 1000 0x4e20= (20 MHz)/1000 Do not use less then a 32kHz clock source. As sert XE& PROG SEL = PWM2H,PWM1L,PWM1H DIO = PWM2L,PORT[A6:A0] SEL = 0x04 DIN =0x80 Set ADDRH SetADDRL As sertNVST R Wr/Rd Memory ? Write SEL = 0x00 DIN =addr[15:8] SEL = 0x01 DIN=addr[7:0] As sert YE SEL = 0x03 DIN =0x84 SetDAT A Read SEL= 0x03 DIN=0xF0 5us SetADDRL SEL=0x03 DIN =0x85 DeassertYE SEL=0x03 DIN =0x85 Wr Done 30 us SEL = 0x03 DIN=0xC5 SEL = 0x02 DIN=data[7:0] SEL = 0x01 DIN=addr[7:0] 10 us No, increm ent YADDR DeassertPROG DeassertXE& NVST R Yes 20ns Set ADDRH SetADDRL SEL=0x03 DIN =0x81 5us SEL=0x03 DIN =0x00 STOP 1us SEL = 0x00 DIN =addr[15:8] SEL = 0x01 DIN=addr[7:0] No, increm ent YADDR 45 ns SEL = 0x05 DOUT =data[7:0] Address Val idto DataVal id Rd Loop Done Yes Figure 8. Z8FMC16100 Flash Gang Programming Flow PRS000502-1005 PRELIMINARY Flash Memory Programming Overview |
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