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74ACTQ843 Quiet SeriesTM 9-Bit Transparent Latch with 3-STATE Outputs
March 1990 Revised December 1998
74ACTQ843 Quiet SeriesTM 9-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACTQ843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths. The ACTQ843 utilizes Fairchild FACT Quiet SeriesTM technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTOTM output control and undershoot corrector in addition to a split ground bus for superior performance.
Features
s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Inputs and outputs on opposite sides of package for easy interface with microprocessors s Improved latch-up immunity s Outputs source/sink 24 mA s ACTQ843 has TTL-compatible inputs s Functionally and pin-compatible to AMD's AM29843 s 3-STATE outputs for bus interfacing
Ordering Code:
Order Number 74ACTQ843SC 74ACTQ843SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for DIP and SOIC
Pin Descriptions
Pin Names D0-D8 O0-O8 OE LE CLR PRE
FACTTM, Quiet SeriesTM, FACT Quiet SeriesTM and GTOTM are trademarks of Fairchild Semiconductor Corporation.
Description Data Inputs Data Outputs Output Enable Latch Enable Clear Preset
(c) 1999 Fairchild Semiconductor Corporation
DS010689.prf
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74ACTQ843
Functional Description
The ACTQ843 consists of nine D-type latches with 3STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. In addition to the LE and OE pins, the ACTQ843 has a Clear (CLR) pin and a Preset (PRE) pin. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. When PRE is LOW, the outputs are HIGH if OE is LOW. Preset overrides CLR.
Function Table
Inputs CLR PRE H H H H H H H L L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change
Internal LE H H L H H L X X X L L D L H X L H X X X X X X Q L H NC L H NC H L H L H
Outputs O Z Z Z L H NC H L H Z Z
Function
OE H H H L L L L L L H H
H H H H H H L H L H L
High Z High Z Latched Transparent Transparent Latched Preset Clear Preset Clear/High Z Preset/High Z
Logic Diagram
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74ACTQ843
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (I OK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current 300 mA 50 mA -65C to +150C 50 mA -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V -0.5V to +7.0V
Junction Temperature (TJ) PDIP 140C
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate V/t VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTTM circuits outside databook specifications.
4.5V to 5.5V 0V to VCC 0V to VCC -40C to +85C 125 mV/ns
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC VOLP VOLV VIHD VILD Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 5.0 1.2 0.8 V (Note 4)(Note 6) 5.0 1.9 2.0 V 5.0 -0.6 -1.2 V 5.0 1.1 1.5 V 5.5 5.5 5.5 5.5 8.0 0.6 1.5 75 -75 80.0 mA mA mA A 5.5 0.5 5.0 A VI = VIL, VIH VO = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND Figure 1, Figure 2 (Note 4)(Note 5) Figure 1, Figure 2 (Note 4)(Note 5) (Note 4)(Note 6) 5.5 0.001 0.001 TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 VIN = VIL or VIH 3.76 4.76 0.1 0.1 VIN = VIL or VIH 0.44 0.44 1.0 A V IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND V V IOH = 24 mA I OH = 24 mA (Note 2) IOUT = 50 A V V Units V Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A
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74ACTQ843
DC Electrical Characteristics
Note 4: DIP package.
(Continued)
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. Note 6: Max number of data inputs (n) switching. (n - 1) inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.
AC Electrical Characteristics
VCC Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPHL tPLH tOSLH tOSHL Parameter Propagation Delay Dn to On Propagation Delay Dn to On Propagation Delay LE to On Propagation Delay LE to On Propagation Delay PRE to On Propagation Delay CLR to On Output Enable Time OE to On Output Enable Time OE to On Output Disable Time OE to On Output Disable Time OE to On Propagation Delay PRE to On Propagation Delay CLR to On Output to Output Skew (Note 8) Dn to On 5.0 0.5 1.5 1.5 ns 5.0 2.5 7.3 11.0 2.0 12.0 ns 5.0 2.5 6.7 10.0 2.0 11.0 ns 5.0 1.5 5.1 8.0 1.0 8.5 ns 5.0 1.5 5.0 8.0 1.0 8.5 ns 5.0 2.5 7.5 9.5 2.0 10.5 ns 5.0 2.5 7.2 9.5 2.0 10.5 ns 5.0 2.5 7.2 11.0 2.0 12.0 ns 5.0 2.5 7.3 10.0 2.0 11.0 ns 5.0 2.5 6.9 9.0 2.0 10.0 ns 5.0 2.5 7.1 9.0 2.0 10.0 ns 5.0 2.5 6.7 9.5 2.0 10.0 ns (V) (Note 7) 5.0 Min 2.5 TA = +25C CL = 50 pF Typ 6.2 Max 9.5 TA = -40C to +85C CL = 50 pF Min 2.0 Max 10.0 ns Units
Note 7: Voltage Range 5.0 is 5.0V 0.5V. Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. Not tested.
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74ACTQ843
AC Operating Requirements
VCC Symbol Parameter (V) (Note 9) tS Setup Time, HIGH or LOW Dn to LE tH Hold Time, HIGH or LOW Dn to LE tW tW tW trec trec LE Pulse Width, HIGH PRE Pulse Width, LOW CLR Pulse Width, LOW PRE Recovery Time CLR Recovery Time 5.0 5.0 5.0 5.0 5.0 4.0 4.0 4.0 2.0 2.0 4.0 4.0 4.0 2.0 2.0 ns ns ns ns ns 5.0 1.5 1.5 ns 5.0 TA = +25C CL = 50 pF Typ 3.0 TA = -40C to +85C CL = 50 pF Guaranteed Minimum 3.0 ns Units
Note 9: Voltage Range 5.0 is 5.0V 0.5V.
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 52 Units pF pF V CC = OPEN V CC = 5.0V Conditions
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74ACTQ843
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. VOLP/VOLV and VOHP/V OHV: * Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50 coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: * Monitor one of the switching outputs using a 50 coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. * Next decrease the input HIGH voltage level on the, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as V IHD. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note 10: VOHV and VOLP are measured with respect to ground reference. Note 11: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps.
FIGURE 2. Simultaneous Switching Test Circuit
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74ACTQ843
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body Package Number M24B
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74ACTQ843 Quiet SeriesTM 9-Bit Transparent Latch with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300" Wide Package Number N24C
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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