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Datasheet File OCR Text:

CX25870/871
Video Encoder with Adaptive Flicker Filtering and HDTV Output
Conexant's CX25870/871 is specifically designed to meet TV out system requirements for the next-generation desktop PCs, notebook PCs, game consoles and set-top boxes. With pin and software-forward compatibility to the Bt868/869, manufacturers can quickly bring to market new solutions that support adaptive flicker filtering, ATSC High-Definition Television (HDTV) output, and resolutions from 320 x 200 (minimum) to 1024 x 768 (maximum). Adaptive flicker filtering is a Conexant technology in which the encoder looks at the characteristics of the video content on a pixel-by-pixel basis and automatically determines the optimal amount of flicker filtering required. If an end-user wants to work on a spreadsheet while watching a DVD movie in a window, both the text-intensive application requiring a lot of flicker filtering and the DVD movie requiring very little flicker filtering can look their best. The amount of flicker filtering and overscan compensation is entirely flexible. The CX25870/871 also provides a 3-wire analog RGB or YPRPB HDTV output. While the encoder is in HDTV output mode, the device will automatically insert horizontal tri-level synchronization pulses and vertical synchronization broad pulses. The CX25870/871 is compliant with the EIA770-3, SMPTE 274M/293M/296M standards and supports ATSC HDTV resolutions including 480p, 720p, and 1080i. All worldwide standard definition outputs are supported, including NTSC-M (N. America, Taiwan), NTSC-J (Japan), PAL-B,D,G,H,I (Europe, Asia), PAL-M (Brazil), PAL-N (Uruguay, Paraguay), PAL-Nc (Argentina), PAL-60 (China) and SECAM. The CX25870 and CX25871 are functionally identical, except the CX25871 can output standard definition video with Macrovision Level 7.1.L1 copy protection capability.
Distinguishing Features
* HDTV Output Mode (patents pending) - Compliant with EIA770-3 and SMPTE274M/293M/296M standards - Automatic tri-level sync generation - Component (YPRPB) or RGB HDTV outputs - Direct YPRPB or RGB output from progressive RGB graphics video in 1080i, 720p, 480p ATSC resolutions Software and register forward-compatibility with the Bt868/869 Ability to accept many different input data formats: - 15/16/24-bit RGB multiplexed or nonmultiplexed - 16-bit 4:2:2 and 24-bit 4:4:4 YCrCb multiplexed or nonmultiplexed - Flexible pixel ordering with various alternate formats Worldwide video output support: NTSC-M, J, 4.43, PAL-B, D, G, H, I, M, N, Nc, 60, and SECAM Interlaced and noninterlaced outputs S-Video output (simultaneous with composite NTSC, PAL, or SECAM) SCART RGB or Y/C output for Europe - 4th DAC is composite video - EN50-049 and IEC 933-1 compliant 5-Line vertical filtering scaling for overscan compensation and flicker reduction Adaptive Flicker Filtering for enhanced image and peaking filters for text sharpness (patents pending) CCIR601/ITU-RBT.601 (i.e., 480i) and CCIR656 compatible input modes Luma and chroma comb filtering 4 x 10-bit DACs Programmable power management Master, pseudo-master or slave timing operation Auto detection of TV 44 autoconfiguration modes Wide-Screen Signaling (WSS) support for variable clock rates - Adheres to EIAJ CPR-1024 and ITU-R TST.1119-1 standards Full register set readback capability 3.3 V operation with scalable low voltage graphic controller interface from 1.8 V to 1.1 V Buffered crystal clock output pin Component YUV analog output Colorstream TM (EIA 770.2) and Super Colorstream TM component video outputs Macrovision 7.1.L1 copy protection (CX25871) Compact 80-pin PQFP package
* *
* * * * * *
Functional Block Diagram
Color Space Conversion #1
24 P[23:0]
Input DEMUX
Flicker Filter/ Scaler
FIFO
*
FSADJUST
HSYNC* VSYNC* BLANK* FIELD SIC SID ALTADDR
Timing Internal Reference Serial Interface Video Encoder Color Space Conversion #2 To Internal Clocks DAC MUX 10-Bit 10-Bit 10-Bit 10-Bit COMP VREF DACA DACB DACC DACD VBIAS Clock Generation BIAS GEN CLKO CLKI
* * * * * * *
RESET* SLEEP SLAVE PAL
* * * * * *
XTALIN XTALOUT XTAL OSC PLL
XTL_BFO
*
Data Sheet
100381B September 2001
100381B
Conexant
Ordering Information
Model Number CX25870 CX25871(1)
NOTE(S):
Package 80-pin PQFP 80-pin PQFP
Ambient Temperature Range 0 C - 70 C 0 C - 70 C
1. Macrovision 7.1.L1 compliant (customer must possess Macrovision license to purchase CX25871).
(c) 2001, Conexant Systems, Inc. All Rights Reserved.
Information in this document is provided in connection with Conexant Systems, Inc. ("Conexant") products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no responsibility for errors or omissions in these materials. Conexant may make changes to specifications and product descriptions at any time, without notice. Conexant makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Conexant's Terms and Conditions of Sale for such products, Conexant assumes no liability whatsoever. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF CONEXANT PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. CONEXANT FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. CONEXANT SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS. Conexant products are not intended for use in medical, lifesaving or life sustaining applications. Conexant customers using or selling Conexant products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages resulting from such improper use or sale. The following are trademarks of Conexant Systems, Inc.: ConexantTM, the Conexant C symbol, and "What's Next in Communications Technologies"TM. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners. For additional disclaimer information, please consult Conexant's Legal Information posted at www.conexant.com, which is incorporated by reference. Reader Response: Conexant strives to produce quality documentation and welcomes your feedback. Please send comments and suggestions to tech.pubs@conexant.com. For technical questions, contact your local Conexant sales office or field applications engineer.
100381B
Conexant
100381B
Conexant
Table of Contents
List of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi 1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 1.2 1.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 GUI Controller Programmability and Frequency Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Low Voltage Graphics Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Clocking and Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.3.6.1 3:2 Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Master, Pseudo-Master, and Slave Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.3.7.1 Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.3.7.2 Reason for BLANK* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.3.7.3 Pseudo-Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.3.7.4 Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.3.7.5 Slave Interface Without a Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Autoconfiguration and Interface Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 Adaptations for Clock-Limited Master Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 Input Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 YCrCb Inputs (For Standard TV Outputs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 RGB Inputs (For Standard TV Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 Input Pixel Horizontal Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 Input Pixel Vertical Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Input Pixel Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Overscan Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 Standard Flicker Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35 Adaptive Flicker Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36 VGA Registers Involved in the TV Out Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40
1.3.8 1.3.9 1.3.10 1.3.11 1.3.12 1.3.13 1.3.14 1.3.15 1.3.16 1.3.17 1.3.18 1.3.19 1.3.20 1.3.21
100381B
Conexant
v
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology 1.3.22 1.3.23 1.3.24 1.3.25 1.3.26 1.3.27 1.3.28 1.3.29 1.3.30 1.3.31 1.3.32 1.3.33 1.3.34 1.3.35 1.3.36 1.3.37 1.3.38 1.3.39 Analog Horizontal Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40 Analog Vertical Sync. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 Analog Video Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 Video Output Standards Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 Subcarrier Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51 Subcarrier Phase Reset/Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51 Burst Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 Video Amplitude Scaling and SINX/X Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 Chrominance Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 FIELD Pin Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-53 Buffered Crystal Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 Noninterlaced Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 Closed Captioning (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-56 Wide Screen Signaling (WSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57 Chrominance and Luminance Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-58 Color Bar and Blue Field Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-61 CCIR656 Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-63 CCIR601 Mode Operation for DVD Playback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-65 1.3.39.1 CCIR601 Data In/NTSC Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-65 1.3.39.2 CCIR601 Data In/PAL Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-66 1.3.39.3 VGA- Compatible RGB Data In/NTSC Out . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-66 SECAM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-68 Macrovision Copy Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-74 HDTV Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-75 SCART Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-75 Interlaced Standard Definition Analog Component Video TV Outputs . . . . . . . . . . . . . . . 1-79 VGA(RGB)--DAC Output Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-84 TV Auto-Detection Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-87 Sleep/Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-89
1.3.40 1.3.41 1.3.42 1.3.43 1.3.44 1.3.45 1.3.46 1.3.47
2.0
Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 2.2 2.3 2.4 Essential Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Writing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Reading Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
3.0
PC Board Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 3.2 3.3 3.4 Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Power and Ground Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Recommended Schematics and Layout for CX25870/871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.1 3.4.2 3.4.3 Device Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Power Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 COMP Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
vi
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology 3.4.4 3.4.5 3.5 3.5.1 3.5.2 3.6 3.6.1 VREF Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 VBIAS Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Changes Required to Accommodate CX25870/871 in Bt868/869-Designs . . . . . . . . . . . 3-11 3.6.1.1 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.6.1.2 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Programmable Video Adjustment Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.6.2.1 Contrast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.6.2.2 Saturation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.6.2.3 Brightness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.6.2.4 Hue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.6.2.5 Sharpness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.6.2.6 Dot Crawl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.6.2.7 Standard and Adaptive Flicker Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.6.2.8 Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.6.2.9 Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 System Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 Electrostatic Discharge and Latchup Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 Clock and Subcarrier Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 Filtering Radio Frequency Modulator Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.6.2
3.6.3 3.6.4 3.6.5 3.6.6 3.7 3.8
CX870EVK Evaluation Kit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 3.8.1 Data Transfer on the Serial Interface Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
4.0
Parametric Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 4.2 4.3 DC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Mechanical Drawing for 80-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Appendix A. Scaling and I/0 Timing Register Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Appendix B. Approved Crystal Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Appendix C. Autoconfiguration Mode Register Values and Details . . . . . . . . . . . . . . . . . . . . . . . . C-1 Appendix D. Closed Caption Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 Appendix E. CX25870/871 HDTV Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
E.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 E.1.1 E.1.2 Allowable Interfaces for HDTV Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 Interface Bit Functionality in HDTV Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3
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Flicker-Free Video Encoder with Ultrascale Technology E.1.3 E.1.4 E.1.5 E.1.6 E.1.7 E.1.8 E.1.9 E.1.10 Interface Timing Between the HDTV Source Device (Master) and CX25870/ CX25871 (Timing Slave) E-3 Automatic Trilevel Sync Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5 Allowable Resolutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-7 720p Support with Character Clock Based Data Masters . . . . . . . . . . . . . . . . . . . . . . . . . E-8 Automatic Insertion of Broad Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9 HDTV Output Mode Register and Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9 Color Space Conversion Functionality to Support Analog RGB or YPBPR Component Video Outputs E-11 Timing Diagrams for HDTV Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-11
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List of Figures
List of Figures
Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 1-6. Figure 1-7. Figure 1-8. Figure 1-9. Figure 1-10. Figure 1-11. Figure 1-12. Figure 1-13. Figure 1-14. Figure 1-15. Figure 1-16. Figure 1-17. Figure 1-18. Figure 1-19. Figure 1-20. Figure 1-21. Figure 1-22. Figure 1-23. Figure 1-24. Figure 1-25. Figure 1-26. Figure 1-27. Figure 1-28. Figure 1-29. Figure 1-30. Figure 1-31. Figure 1-32. Figure 1-33. Figure 1-34. Figure 1-35. Figure 1-36. Pinout Diagram for CX25870/871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Flicker Filter Control Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 CX25870/871 Encoder Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Allowable Overscan Compensation Ratios for Dual Display, 800x600 Input/NTSC Output 1-15 Operating the CX25870/871 in Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Operating the CX25870/871 in Pseudo-Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Operating the CX25870/871 in Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 Decimation Filter at Fs=27 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 Windows Desktop Image From Encoder Without Overscan Compensation. . . . . . . . . . . . 1-33 Windows Desktop Image From CX25870 With Overscan Compensation . . . . . . . . . . . . . 1-34 Interlaced 525-Line (NTSC) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43 Interlaced 525-Line (PAL-M) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44 Interlaced 625-Line (PAL-B, D, G, H, I, Nc) Video Timing (Fields 1-4) . . . . . . . . . . . . . . . 1-45 Interlaced 625-Line (PAL-B, D, G, H, I, Nc) Video Timing (Fields 5-8) . . . . . . . . . . . . . . . 1-46 Interlaced 625-Line (PAL-N) Video Timing (Fields 1-4) . . . . . . . . . . . . . . . . . . . . . . . . . . 1-47 Interlaced 625-Line (PAL-N) Video Timing (Fields 5-8) . . . . . . . . . . . . . . . . . . . . . . . . . . 1-48 Noninterlaced 262-Line (NTSC) Video Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-49 Noninterlaced 262-Line (PAL-M) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-49 Noninterlaced 312-Line (PAL-B, D, G, H, I, N, Nc) Video Timing. . . . . . . . . . . . . . . . . . . . 1-49 Interlaced 625-Line (SECAM-B, D, G, K, K1, L, M) Video Timing (Fields 1-4) . . . . . . . . . . 1-50 FIELD Pin Output Timing Diagram (NTSC-M, J, 4.43). . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-53 FIELD Pin Output Timing Diagram (PAL-B, D, G, H, I, Nc) . . . . . . . . . . . . . . . . . . . . . . . . 1-54 Typical WSS Analog Waveform (NTSC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57 Luminance Upsampling Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-59 Text Sharpness (Luminance Upsampling) Filter with Peaking Options . . . . . . . . . . . . . . . 1-59 Close-Up of Text Sharpness (Luminance Upsampling )Filter with Peaking and Reduction Options 1-59 Text Sharpness (Luminance Peaking) Filter Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-60 Chrominance Filter (CHROMA_BW = 0) - default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-60 Chrominance Wide Bandwidth Filter (CHROMA_BW = 1) . . . . . . . . . . . . . . . . . . . . . . . . . 1-60 SECAM High Frequency Pre-emphasis Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-61 Composite and S-Video Format (Internal Colorbars). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-62 CX25870/871 Connection to CCIR656-Compatible Master Device . . . . . . . . . . . . . . . . . . 1-63 DVD Playback Utilizing Graphics Controller for Color-Space and Progressive Scan Conversion 1-67 CX25870 Driving a Type I SCART Connector (EN 50-049 and IEC 933-1 Compliant) . . . . 1-78 CX25870 Driving a Type II SCART Connector (Y/C and BBC SCART Compliant). . . . . . . . 1-79 YPR PB Component Video Signals using 100/0/100/0 Color Bars as the Digital Input Signal (Courtesy- EIA-770.2-A standard, page 8 and EIA-770.1 standard) 1-81
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-37. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10. Figure 3-11. Figure 3-12. Figure 3-13. Figure 3-14. Figure 3-15. Figure 3-16. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 4-8. Figure 4-9. Figure 4-10. Figure 4-11. Figure A-1. Figure A-2. Figure A-3. Figure A-4.
Filterless DAC Outputs for VGA (RGB)--DAC Output Operation . . . . . . . . . . . . . . . . . . . . 1-86 Power Plane Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Connection Diagram for Output Filters and Other Key Passive Components/Standard Definition TV Out Only 3-3 Connection Diagram for Output Filters and Other Key Passive Components/Standard and HDTV Out 3-4 CX25870/871 3.3 V Recommended Layout for Connection with 3.3 V Master Device Standard Definition TV Out Only 3-6 CX25870/871 3.3 V/1.8 V Recommended Layout for Connection with 1.8 V Master Device Standard Definition TV Out Only 3-7 Conexant Recommended GUI for CX25870/871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 CX25870/871 Autoconfiguration Modes for 640x480 RGB in, NTSC Out Desktop Resolutions 3-22 CX25870/871 Autoconfiguration Modes for 40x480 RGB In, PAL-BDGHI Out Desktop Resolutions 3-22 CX25870/871 Autoconfiguration Modes for 800 x 600 RGB In, NTSC Out Desktop Resolutions 3-23 CX25870/871 Autoconfiguration Modes for 800 x 600 RGB In, PAL-BDGHI Out Desktop Resolutions 3-23 CX25870/871 Autoconfiguration Modes for 1024 x 768 RGB In, NTSC Out Desktop Resolutions 3-24 CX25870/871 Autoconfiguration Modes for 1024 x 768 RGB In, PAL-BDGHI Out Desktop Resolutions 3-24 Direction-less Size Control Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 System Block Diagram for Desktop/Portable PC with TV Out . . . . . . . . . . . . . . . . . . . . . . 3-26 System Block Diagram for Graphics Card with TV Out . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 SID/SIC Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 Timing Details for All Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Master Interface Timing Relationship/Noninterlaced RGB/YCrCb Input . . . . . . . . . . . . . . . 4-8 Pseudo-Master Interface Timing Relationship - Active Line/Noninterlaced RGB Input . . . . 4-9 Pseudo-Master Timing Relationship Blank Line/Noninterlaced RGB/YCrCb Input. . . . . . . 4-10 Slave Interface Timing Relationship/Noninterlaced RGB/YCrCb Input . . . . . . . . . . . . . . . . 4-11 Slave Interface Timing Relationship/Interlaced Nonmultiplexed RGB Input (FLD_MODE = 10 - Default) 4-12 Slave Interface Timing Relationship/Interlaced Nonmultiplexed YCrCb Input (FLD_MODE = 01) 4-13 Slave Interface Timing Relationship/Interlaced Nonmultiplexed YCrCb Input (FLD_MODE = 00) 4-14 HDTV Output Horizontal Timing Details: 1080i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 HDTV Output Horizontal Timing Details: 720p. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 80-Pin PQFP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 Allowable Overscan Compensation Ratios for Dual Display, 640x480 Input, NTSC Output with 20 Clock HBlank Period A-4 Allowable Overscan Compensation Ratios for Dual Display, 640x480 Input, PAL-BDGHI Output with 20 Clock HBlank Period A-5 Allowable Overscan Compensation Ratios for Dual Display, 800x600 Input, NTSC Output . A-6 Allowable Overscan Compensation Ratios for Dual Display, 800x600 Input, PAL-BDGHI Output, Standard Clocking Mode A-7
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Flicker-Free Video Encoder with Ultrascale Technology Figure A-5. Figure A-6. Figure A-7. Figure A-8. Figure E-1. Figure E-2. Figure E-3. Figure E-4.
List of Figures
Figure E-5.
Figure E-6. Figure E-7. Figure E-8.
Allowable Overscan Compensation Ratios for Dual Display, 800x600 Input, NTSC Output in 3:2 Clocking Mode A-8 Allowable Overscan Compensation Ratios for Dual Display, 800x600 Input, PAL-BDGHI Output in 3:2 Clocking Mode A-9 Allowable Overscan Compensation Ratios for Dual Display, 1024x768 Input, NTSC Output . . . A-10 Allowable Overscan Compensation Ratios for Dual Display, 1024x768 Input, PAL-BDGHI Output A-11 CX25870/871's Pseudo-Master Interface with a Graphics Controller as the Timing Master E-2 CX25870/871's Slave Interface with a Graphics Controller as the Timing Master . . . . . . . . E-2 Typical Trilevel Sync Provided by CX25870/871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-7 Proper Interface Timing Between the HDTV Source Device (Master) and CX25870/871 (Timing Slave): Active Line in 1080i and 720p ATSC Format (RASTER_SEL[1:0] = 11 or 10), for R, G, B, and Y Analog Outputs E-12 Proper Interface Timing Between the HDTV Source Device (Master) and CX25870/871 (Timing Slave): Active Line in 1080i and 720p ATSC Format (RASTER_SEL[1:0] = 11 or 10) for P8 and PR Analog Outputs E-13 Proper Interface Timing Between the HDTV Source Device (Master) and CX25870/871 (Timing Slave): Broad Pulse Line in 1080i ATSC Format (RASTER_SEL[1:0] = 11) - Odd Field E-14 Proper Interface Timing Between the HDTV Source Device (Master) and CX25870/871 (Timing Slave): Two Successive Active Fields in 1080i ATSC Format (RASTER_SEL[1:0] = 11) E-15 Proper Interface Timing Between the HDTV Source Device (Master) and CX25870/871 (Timing Slave): Broad Pulse Line in 720p ATSC Format (RASTER_SEL[1:0] = 10) E-16
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Flicker-Free Video Encoder with Ultrascale Technology
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List of Tables
List of Tables
Table 1-1. Table 1-2. Table 1-3. Table 1-4. Table 1-5. Table 1-6. Table 1-7. Table 1-8. Table 1-9. Table 1-10. Table 1-11. Table 1-12. Table 1-13. Table 1-14. Table 1-15. Table 1-16. Table 1-17. Table 1-18. Table 1-19. Table 1-20. Table 1-21. Table 1-22. Table 1-23. Table 1-24. Table 1-25. Table 1-26. Table 1-27. Table 1-28. Table 1-29. Table 1-30. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 3-1. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Data Pin Assignments for Multiplexed Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Data Pin Assignments for Nonmultiplexed Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Maximum Programmability and Frequency Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Autoconfiguration Solutions that Utilize 3:2 Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Master Interface without a BLANK* Signal (Default Immediately after any Autoconfiguration Command) 1-21 Master Interface with a BLANK* Input to the CX25870/871 . . . . . . . . . . . . . . . . . . . . . . . . 1-22 Pseudo-Master Interface without a BLANK* Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 Pseudo-Master Interface with a BLANK* Input to the CX25870/871. . . . . . . . . . . . . . . . . . 1-23 Slave Interface without a BLANK* Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 Slave Interface with a BLANK* Input to the CX25870/871 . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 Adjustment to the CX25870/871 MSC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 Adjustment to the PLL_INT and PLL_FRACT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 Summary of Allowable BLANK* Signal Directions by Interface. . . . . . . . . . . . . . . . . . . . . . 1-31 Optimal Adaptive and Standard Flicker Filter Settings for Common PC Applications. . . . . . 1-38 VGA/CRTC Registers Involved in TV Out Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39 Important Bit Settings for Various Video Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-42 Composite and Luminance Amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-62 Composite and Chrominance Magnitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-63 Register Values for 640x480 / 800x600 / 1024x768 RGB In, SECAM-L Out . . . . . . . . . . . . 1-69 Vital SECAM Bitsettings-Register 0xA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-72 SECAM Specific Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-74 Serial Writes Required to Switch CX25870/871 into SCART Output Operation . . . . . . . . . . 1-76 Default SCART Outgoing Signal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-77 CX25870 SCART Outputs for Different SCART Standards. . . . . . . . . . . . . . . . . . . . . . . . . . 1-78 Common Registers Required to Switch CX25870/25871 into EIA-770.2-A- or EIA-770.1-Compliant Component Video Outputs 1-82 Unique Registers Required to Switch CX25870/25871 into EIA-770.2-A- Compliant Component Video Outputs 1-82 Serial Writes Required to Switch CX25870/871 into VGA/DAC Output Operation . . . . . . . . 1-84 Serial Writes Required to Remove Bilevel Syncs from all VGA/DAC Outputs . . . . . . . . . . . 1-85 ESTATUS[1:0] Read-back Bit Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-88 Register Bit Map (* Indicates Read-Only Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Serial Address Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Bit Map for Read-Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Data Details Defined for Read-Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Programming Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Typical Parts List for Key Passive Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
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Flicker-Free Video Encoder with Ultrascale Technology
Table 3-2. Table 3-3. Table 3-4. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table A-1. Table A-2. Table A-3. Table A-4. Table A-5. Table A-6. Table A-7. Table A-8. Table A-9. Table A-10. Table A-11. Table A-12. Table A-13. Table A-14. Table A-15. Table A-16. Table A-17. Table A-18. Table A-19. Table A-20. Table A-21. Table A-22. Table A-23.
Relative Register Map for CX25870/871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Hardware Modifications to Bt868/869-based PCB Required to Accommodate the CX25870/871 3-12 CX25870 Optimal Adaptive Flicker Filter Bit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 Recommended Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 DC Characteristics for CX25870/871. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 AC Characteristics for CX25870/871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Target Video Parameters for Standard Definition TV Output Formats . . . . . . . . . . . . . . . . . . A-2 Key Parameters for Supported Standard Definition Video Output Formats . . . . . . . . . . . . . . A-3 Constant Values Dependent on Encoding Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Overscan Values, 640 x 480 NTSC, Pixel-Based Controller, 1-Pixel Resolution, 2.5 s HBlank. . A-12 Overscan Values, 640 x 480 NTSC, Character Clock-Based Controller, 8-Pixel Resolution, 2.5 s HBlank A-14 Overscan Values, 640 x 480 NTSC, Character Clock-Based Controller, 9-Pixel Resolution, 2.5 s HBlank A-15 Overscan Values, 640 x 480 PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, 2.5 s HBlank A-16 Overscan Values, 640 x 480 PAL-BDGHI, Character Clock-Based Controller, 8-Pixel Resolution, 2.5 s HBlank A-19 Overscan Values, 640 x 480 PAL-BDGHI, Character Clock-Based Controller, 9-Pixel Resolution, 2.5 s HBlank A-20 Overscan Values, 800 x 600 NTSC, Pixel-Based Controller, 1-Pixel Resolution. . . . . . . . . . A-21 Overscan Values, 800 x 600 NTSC, Character Clock-Based Controller, 8-Pixel Resolution, 0-1.5 s HBlank A-25 Overscan Values, 800 x 600 NTSC, Character Clock-Based Controller, 9-Pixel Resolution, 0-3.0 s HBlank A-26 Overscan Values 800 x 600 NTSC, Pixel-Based Controller, 1-Pixel Resolution, 3:2 Clocking Mode A-27 Overscan Values 800 x 600 NTSC, Character Clocked-Based Controller, 8-Pixel Resolution, 3:2 Clocking Mode A-31 Overscan Values 800 x 600 NTSC, Character Clocked-Based Controller, 9-Pixel Resolution, 3:2 Clocking Mode A-32 Overscan Values, 800 x 600 PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, >2.5 s HBlank A-34 Overscan Values, 800 x 600 PAL-BDGHI, Character Clock-Based Controller, 8-Pixel Resolution A-36 Overscan Values, 800 x 600 PAL-BDGHI, Character Clock-Based Controller, 9-Pixel Resolution A-37 Overscan Values 800 x 600 PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, 3:2 Clocking Mode A-38 Overscan Values 800 x 600 PAL-BDGHI, Character Clock-Based Controller, 8-Pixel Resolution, 3:2 Clocking Mode A-41 Overscan Values 800 x 600 PAL-BDGHI, Character Clock-Based Controller, 9-Pixel Resolution, 3:2 Clocking Mode A-41 Overscan Values 1024 x 768 NTSC, Pixel-Based Controller, 1-Pixel Resolution, >1.50 ms. Hblank A-42 Overscan Values 1024 x 768 NTSC, Character Clock-Based Controller, 8Pixel Resolution, >1.50
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Flicker-Free Video Encoder with Ultrascale Technology
List of Tables
Table A-24. Table A-25. Table A-26. Table A-27. Table C-1. Table C-2. Table C-3. Table C-4. Table C-5. Table C-6. Table C-7. Table C-8. Table C-9. Table E-1. Table E-2. Table E-3. Table E-4. Table E-5. Table E-6.
s HBlank A-46 Overscan Values 1024 x 768 NTSC, Character Clock-Based Controller, 9-Pixel Resolution A-47 Overscan Values 1024 x 768 PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, >3 ms. Hblank A-49 1024 x 768 PAL-BDGHI, Character Clock-Based Controller, 8-Pixel Resolution , >4 ms. Hblank A-52 Overscan Values 1024 x 768 PAL-BDGHI, Character Clock-Based Controller, 9-Pixel Resolution A-52 CX25870/871 Register Values for Autoconfiguration Modes 0-4 . . . . . . . . . . . . . . . . . . . . . C-1 CX25870/871 Register Values for Autoconfiguration Modes 5-10 . . . . . . . . . . . . . . . . . . . . C-4 CX25870/871 Register Values for Autoconfiguration Modes 11-15 . . . . . . . . . . . . . . . . . . . C-6 CX25870/871 Register Values for Autoconfiguration Modes 16-21 . . . . . . . . . . . . . . . . . . . C-8 CX25870/871 Register Values for Autoconfiguration Modes 22-26 . . . . . . . . . . . . . . . . . . C-10 CX25870/871 Register Values for Autoconfiguration Modes 27-30 . . . . . . . . . . . . . . . . . . C-12 CX25870/871 Register Values for Autoconfiguration Modes 31-36 . . . . . . . . . . . . . . . . . . C-14 CX25870/871 Register Values for Autoconfiguration Modes 37-42 . . . . . . . . . . . . . . . . . . C-16 CX25870/871 Register Values for Autoconfiguration Modes 43-47 . . . . . . . . . . . . . . . . . . C-18 CX25870 Register Settings for 24-Bit RGB Multiplexed In, Y/PR/PB HDTV Out. . . . . . . . . . . E-4 Default State of CX25870/871 Immediately After Switch into HDTV Output Mode . . . . . . . . E-5 CX25870/871 RASTER_SEL[1:0] bit functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-6 CX25870/871 HDTV Supported Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-7 Register Bit Map for HDTV-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9 CX25870/871 Registers 0x2E & 0x32 - HDTV Output Mode Bit Descriptions . . . . . . . . . . E-10
100381B
Conexant
xv
List of Tables
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
xvi
Conexant
100381B
1
1.0 Functional Description
1.1 Pin Descriptions
The pinout diagram is illustrated in Figure 1-1. Pin names, input/output assignments, numbers, and descriptions are listed in Tables 1-1, 1-2, and 1-3.
Figure 1-1. Pinout Diagram for CX25870/871
VAA_X XTALOUT XTALIN VSS_X AGND_DAC DACD VAA_DACD DACA VAA_DACA DACB VAA_DACB DACC VAA_DACC AGND_DAC COMP VREF VBIAS FSADJUST AGND VAA_VREF
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
VDD VAA_PLL AGND_PLL VDD_CO CLKO VSS_CO CLKI RESET* SLEEP SLAVE PAL VDD_VREF ALTADDR VDD_SI VDD_SO SIC SID VSS_SO VSS_SI VSS
CX25870/871 80-pin PQFP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDDL VSS/TEST BLANK* FIELD VSYNC* HSYNC* P[23] P[22] P[21] VSS VDD P[20] P[19] P[18] P[17] P[16] P[15] P[14] VSS VSS
VDD VDD XTL_BFO VSS P[0] P[1] P[2] P[3] P[4] P[5] P[6] P[7] P[8] P[9] P[10] P[11] P[12] P[13] VDD VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
100381_002
100381B
Conexant
1-1
1.0 Functional Description
1.1 Pin Descriptions
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Aside from pins 2, 3, 65, 66, and 67, which are no connects within the Bt868/869, the CX25870/871 is completely pin-to-pin compatible with Conexant's first generation VGA encoder.
Table 1-1. Pin Assignments (1 of 3) Pin Name
VAA_VREF AGND FSADJUST VBIAS I O
I/O
-- --
Pin #
80 79 78 77
Description
Analog power. All VAA and VDD pins must be connected together on the same PCB plane to prevent latchup. Analog ground. All AGND and VSS pins must be connected together on the same PCB plane to prevent latchup. Full-scale adjust control pin. A resistor (RSET) connected between this pin and GND controls the full-scale output current on the analog outputs. DAC bias voltage. A 0.1 F ceramic capacitor must be used to bypass this pin to GND. The capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Voltage reference pin. A 1.0 F ceramic capacitor must be used to decouple this pin to GND. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Compensation pin. A 0.1 F ceramic capacitor must be used to bypass this pin to VAA. The capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. DACC Analog power. All VAA and VDD pins must be connected together on the same PCB plane to prevent latchup. DACC Analog output. DACB Analog power. All VAA and VDD pins must be connected together on the same PCB plane to prevent latchup. DACB Analog output. DACA Analog power. All VAA and VDD pins must be connected together on the same PCB plane to prevent latchup. DACA Analog output. DACD analog power. All VAA and VDD pins must be connected together on the same PCB plane to prevent latchup. DACD analog output. If unused, DACD should be left as a no connect. Common DAC Analog ground return. All AGND and VSS pins must be connected together on the same PCB plane to prevent latchup. Crystal oscillator ground pin. This pin should be tied to the ground plane. A crystal can be connected to these pins. The pixel clock output (CLKO) is derived from these pins with a PLL. XTALIN can be driven as a CMOS input pin. Internally, this is a CMOS inverter tying XTALOUT to XTALIN. If XTALOUT is unused, it should be left as a no connect. Crystal oscillator supply pin. This pin should be tied to the power supply. Analog power for PLL. All VAA and VDD pins must be connected together on the same PCB plane to prevent latchup. Analog ground for PLL. All AGND and VSS pins must be connected together on the same PCB plane to prevent latchup.
VREF
O
76
COMP
O
75
VAA_DACC DACC VAA_DACB DACB VAA_DACA DACA VAA_DACD DACD AGND_DAC VSS_X XTALIN XTALOUT I O O O O
--
73 72
--
71 70
--
69 68 67 66
-- O -- --
65, 74 64 63 62
VDD_X VAA_PLL AGND_PLL
-- -- --
61 59 58
1-2
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-1. Pin Assignments (2 of 3) Pin Name
VDD_CO CLKO VSS_CO CLKI I O --
1.0 Functional Description
1.1 Pin Descriptions
I/O
--
Pin #
57 56 55 54
Description
Clock output supply pin. This pin should be tied to the power supply. For low voltage infacing this pin should be tied to the low voltage supply. Pixel clock output (TTL compatible). This pin is three-state if the CLKI pin provides the encoder clock. Clock output ground pin. This pin should be tied to the ground plane. Pixel clock input (TTL compatible). This may be used as either the encoder clock or a delayed version of the CLKO pin synchronized with the pixel data input. Reset control input (TTL compatible). A logical 0 applied for a minimum of 20 CLKI clock cycles resets and disables video timing (horizontal, vertical, subcarrier counters) to the start of VSYNC of the first field and resets the serial interface registers. RESET* must be a logical 1(3.3 V) for normal operation. Power-down control input (TTL compatible). A logical 1 configures the device for power-down mode. A logical 0 configures the device for normal operation. Slave/master mode select input (TTL compatible). A logical 1 configures the device for slave video timing operation. A logical 0 configures the device for master video timing operation. PAL/NTSC mode select input (TTL compatible). A logical 1 configures the device for PAL video format and Autoconfiguration Mode 1. A logical 0 configures the device for NTSC video format and Autoconfiguration Mode 0. Input threshold adjustment. This pin should be tied to VDD for 3.3 V input swings or VDDL/2 for low voltage input swings. Alternate slave address input (TTL compatible). A logical 0 configures the device to respond to a serial write address of 0x88. A logical 1 configures the device to respond to a serial write address of 0x8A. In addition, serial reads to address 0x89 (ALTADDR = 0) or 0x8B (ALTADDR = 1) are possible with this pin. Serial interface input supply pin. This pin should be tied to VDD (3.3 V). Serial interface output supply pin. This pin should be tied to VDD (3.3 V). Serial interface clock input (TTL compatible). Serial interface data input/output (TTL compatible). Data is written to and read from the device via this serial bus. Serial interface input ground pin. This pin should be tied to the ground plane. Serial interface input ground pin. This pin should be tied to the ground plane. Digital power for low voltage interface. All VAA and VDD pins must be connected together on the same PCB plane to prevent latchup. For a low voltage interface, this pin should be tied to the low voltage supply. Test pin. Should be tied to VSS for normal operation. Composite blanking control (TTL compatible). This can be generated by the encoder or supplied from the graphics controller. If internal blanking is used, this pin can be used to indicate the control character clock edge. If unused, BLANK* should be tied high through a 10 k pullup resistor.
RESET*
I
53
SLEEP SLAVE
I I
52 51
PAL
I
50
VDD_VREF ALTADDR
I I
49 48
VDD_SI VDD_SO SIC SID VSS_SO VSS_SI VDDL I
-- --
47 46 45 44 43 42 40
I/O -- -- --
VSS/TEST BLANK*
I I/O
39 38
100381B
Conexant
1-3
1.0 Functional Description
1.1 Pin Descriptions
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-1. Pin Assignments (3 of 3) Pin Name
FIELD
I/O
O
Pin #
37
Description
Field control output (TTL compatible). FIELD transitions after the rising edge of CLK, two clock cycles following falling HSYNC*. It is a logical 0 during odd fields and is a logical 1 during even fields. If unused, FIELD should be left as a no connect. Vertical sync input/output (TTL compatible). As an output (timing master operation), VSYNC* is output following the rising edge of CLK. As an input (timing slave operation), VSYNC* is clocked on the rising edge of CLK. Horizontal sync input/output (TTL compatible). As an output (timing master operation), HSYNC* is output following the rising edge of CLK. As an input (timing slave operation), HSYNC* is clocked on the rising edge of CLK. Pixel inputs. See Table 1-2. The input data is sampled on both the rising and falling edge of CLK for multiplexed modes, and on the rising edge of CLK in nonmultiplexed modes. A higher bit index corresponds to a greater bit significance. Digital ground for core logic. All AGND and VSS pins must be connected together on the same PCB plane to prevent latchup. Buffered crystal clock output. On power-up, the encoder will transmit a 0 to 3.3 V signal at a frequency equal to the frequency of the crystal found between the XTALIN/XTALOUT ports. Normally the XTL_BFO output is at a rate of 13.500 MHz. If unused, XTL_BFO should be left as a no connect. Digital power for core logic. All VAA and VDD pins must be connected together on the same PCB plane to prevent latchup.
VSYNC*
I/O
36
HSYNC*
I/O
35
P[23:21] P[20:14] P[13:0] VSS XTL_BFO
I I I -- O
34-32 29-23 18-5 4, 21, 22, 31, 41 3
VDD
--
1, 2, 19, 20, 30, 60
1-4
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-2. Data Pin Assignments for Multiplexed Input Formats Falling Edge of CLKI IN_MODE[3:0] 0000 0010/0001 0101 16-bit YCrCb Mode
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 -- -- -- --
1.0 Functional Description
1.1 Pin Descriptions
0100 24-bit YCrCb Mode
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb3 Cb2 Cb1 Cb0
1000 Alternate 24-bit RGB Mode
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4
0110 Alternate 16-bit YCrCb Mode
-- -- -- -- Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
1100 Alternate 24-bit YCrCb Mode
Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 Y7 Y6 Y5 Y4
Pin
24-bit RGB Mode
R7 R6 R5 R4 R3 G7 G6 G5 R2 R1 R0 G1
15/16-bit RGB Mode
R4 R3 R2 R1 R0 G5(1) G4 G3 -- -- -- --
P[11] P[10] P[9] P[8] P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0]
Rising Edge of CLKI
P[11] P[10] P[9] P[8] P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0]
NOTE(S):
(1)
G4 G3 G2 B7 B6 B5 B4 B3 G0 B2 B1 B0
G2 G1 G0 B4 B3 B2 B1 B0 -- -- -- --
Cr/Cb7 Cr/Cb6 Cr/Cb5 Cr/Cb4 Cr/Cb3 Cr/Cb2 Cr/Cb1 Cr/Cb0 -- -- -- --
Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 Cb7 Cb6 Cb5 Cb4
G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
-- -- -- -- Cr/Cb7 Cr/Cb6 Cr/Cb5 Cr/Cb4 Cr/Cb3 Cr/Cb2 Cr/Cb1 Cr/Cb0
Y3 Y2 Y1 Y0 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0
G5 is ignored in 15-bit RGB Multiplexed Input Mode.
100381B
Conexant
1-5
1.0 Functional Description
1.1 Pin Descriptions
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-3. Data Pin Assignments for Nonmultiplexed Input Formats IN_MODE[3:0] 1010 1110 16-bit nonmux YCrCb
-- -- -- -- Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cr/Cb7 Cr/Cb6 Cr/Cb5 Cr/Cb4 Cr/Cb3 Cr/Cb2 Cr/Cb1 Cr/Cb0 -- -- -- --
0011
0111 24-bit nonmux YCrCb
Cb7 Cb6 Cb5 Cb4 Cb2 Cb2 Cb1 Cb0 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
1011 Alternate 16-bit nonmux RGB
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
1111 Alternate 24-bit nonmux YCrCb
Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0
Pin
16-bit nonmux RGB
-- -- -- -- R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 -- -- -- --
24-bit nonmux RGB
B7 B6 B5 B4 B3 B2 B1 B0 G7 G6 G5 G4 G3 G2 G1 G0 R7 R6 R5 R4 R3 R2 R1 R0
P[23] P[22] P[21] P[20] P[19] P[18] P[17] P[16] P[15] P[14] P[13] P[12] P[11] P[10] P[9] P[8] P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0]
1-6
Conexant
100381B
CX25870/871
1.0 Functional Description
Flicker-Free Video Encoder with Ultrascale Technology 1.2 GUI Controller Programmability and Frequency Requirement
1.2 GUI Controller Programmability and Frequency Requirement
Programmability and frequency requirements for the Graphics Controller/Data Master device are defined in Table 1-4 for the most common input resolutions.
Table 1-4. Maximum Programmability and Frequency Requirements Maximum Total Desktop Input Mode Pixels/HTOTAL
640 x 480 800 x 600 800 x 600 (3:2 CLK mode) 1024 x 768 (3:2 CLK mode) 1075 1075 1625 1625
Maximum End of Active to Vsync Lines
76 91 92 122
Maximum Frequencies
Lines/VTOTAL
665 835 834 1068
Line (kHz)
39.860 49.450 49.630 63.776
Pixel (MHz)
31.563 39.997 59.063 75.750
Table 1-4 contains maximum values for the dual display solutions that provide 8 percent to 32 percent horizontal and vertical overscan compensation. For larger overscan compensation percentages, the values would be larger. The maximum pixel frequency supported is 53.333 MHz for standard clocking mode and 80.000 MHz for 3:2 clocking mode.
100381B
Conexant
1-7
Figure 1-2. Flicker Filter Control Diagram
1-8
Color Space Converter Flicker Filter/Scaler FIFO
ADPT_FF = 0; F_SELY[2:0] DIS_GMSHY DIS_GMUSHY DIS_YFLPF YCORING[2:0] 000 = Bypass 000 = 1.0 Gain 001 = 15/16 Gain 010 = 7/8 Gain 011 = 3/4 Gain 100 = 1/2 Gain 101 = 1/4 Gain 110 = 1/8 Gain 111 = 0.0 Gain YLPF[1:0] YATTENUATE[2:0] 000 = 5 Line 001 = 2 Line 010 = 3 Line 011 = 4 Line 100 = Alt. 5 Line 1 101 = Alt. 5 Line 2 110 = Alt. 5 Line 3 111 = Alt. 5 Line 4 ADPT_FF = 0; F_SELC[2:0] 000 = 5 Line CLPF[1:0] 00 = Bypass 01 = Reserved 001 = 2 Line 010 = 3 Line 011 = 4 Line 100 = Alt. 5 Line 1 101 = Alt. 5 Line 2 110 = Alt. 5 Line 3 111 = Alt. 5 Line 4 000 = 1.0 Gain 001 = 15/16 Gain 010 = 7/8 Gain 011 = 3/4 Gain 100 = 1/2 Gain 101 = 1/4 Gain 110 = 1/8 Gain 111 = 0.0 Gain CATTENUATE[2:0] 11 = Luma, Horizontal LPF3 0 = Enable Chroma Psuedo Gamma Removal 0 = Enable Chroma Anti-Psuedo Gamma Removal DIS_GMSHC DIS_GMUSHC 0 = Enable Luma Psuedo Gamma Removal 0 = Enable Luma Anti-Pseudo Gamma Removal 0 = Enable Initial Luma Horizontal Low Pass Filter 00 = Bypass 01 = Luma, Horizontal LPF1 10 = Luma, Horizontal LPF2 001 = 1/128 of Range 010 = 1/64 of Range 011 = 1/32 of Range 100 = 1/16 of Range 101 = 1/8 of Range 110 = 1/4 of Range 111 = Reserved CCORING[2:0] ADPT_FF = 1; Y_ATLFF[1:0] 00 = 5 Line 01 = 2 Line 10 = 3 Line 11 = 4 Line ADPT_FF = 1; C_ATLFF[1:0] 00 = 5 Line 01 = 2 Line 10 = 3 Line 11 = 4 Line 10 = Chroma, Horizontal LPF2 11 = Chroma, Horizontal LPF3 000 = Bypass 001 = +/-1/256 of Range 010 = +/- 1/128 of Range 011 = +/- 1/64 of Range 100 = +/- 1/32 of Range 101 = +/- 1/16 of Range 110 = +/- 1/8 of Range 111 = Reserved
Input
IN_MODE[3:0]
1.0 Functional Description
0000 = 24-bit RGB Mux
0001 = 16-bit RGB Mux
0010 = 15-bit RGB Mux
0011 = 24-bit RGB Non-Mux
0100 = 24-bit YCrCb Mux
0101 = 16-bit YCrCb Mux
0110 = Alternate 16-bit YCrCb Mux
1.2 GUI Controller Programmability and Frequency Requirement Flicker-Free Video Encoder with Ultrascale Technology
Conexant
0111 = 24-bit YCrCb Non-Mux
1000 = Alternate 24-bit RGB Mux
1001 = Reserved
1010 = 16-bit RGB Non-Mux
1011 = Alternate 24-bit RGB Non-Mux
1100 = Alternate 24-bit YCrCb Mux
1101 = Reserved
1110 = 16-bit YCrCb Non-Mux
CX25870/871
1111 = Alternate 24-bit RGB Non-Mux
100381_003
100381B
100381B
SIC SID FSADJUST
VREF SYNC_AMP
CX25870/871
RESET*
Video Timing Control, SID Registers
Sync Processor Y
Internal Voltage Reference
COMP
MY
Y[9:0]
X
VBIAS
+
Closed Captioning, Macrovision
CGMS
Luma Delay
Figure 1-3. CX25870/871 Encoder Core Block Diagram
10
+
U/V RGB CVBS DLY
CVBS
Out Mode Out Mux
DAC 10 10 DAC DAC
DACA DACB DACC
Flicker-Free Video Encoder with Ultrascale Technology 1.2 GUI Controller Programmability and Frequency Requirement
Conexant
MCR MCB Luminance 2x Upsample and Cross Color Peaking Filt.
Color Space Convert
+
CRCB[9:0]
X 9 1.3 MHz LPF and 2X Upsample/ Matrix Multiplication
Modulator, 10 Mixer and SECAM Filt.
10
C
DAC
DACD
Burst Processor
HUE_OFF
BST_AMP
RGB/ YCRCB/ YPRPB 24
HSYNC* VSYNC*
HDTV Sync Gen.
1.0 Functional Description
100381_004
1-9
1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3 Device Description
1.3.1 Overview
The CX25870/871 is a video encoder designed for TV output of interlaced and noninterlaced graphics data. Common applications requiring flicker-filtered TV output include: * * * * * * desktop/portable PCs with TV Out high definition TVs DVD players and set top boxes graphic cards with TV Out game consoles set-top boxes
It incorporates normal and adaptive filtering technology for flicker removal and flexible amounts of overscan compensation for high-quality display of noninterlaced images on an interlaced TV The CX25870/871 accomplishes this . by minimizing the flicker and controlling the amount of overscan so that the entire image is viewable. The CX25870/871 consists of a Color Space Converter/Flicker Filter engine followed by a digital video encoder. The Color Space Converter/Flicker Filter contains: * * * A timing converter Various horizontal video processing functions Flicker filter and vertical scaler for overscan compensation
The output of this engine feeds into a FIFO for synchronization with the digital video encoder. The CX25870/871 provides Composite, S-Video, or 3-signal analog RGB or YPBPR HDTV output. While the encoder is in HDTV output mode, the device will automatically insert trilevel synchronization pulses (when necessary) and vertical synchronizing "broad pulses." The CX25870/871 is compliant with EIA770-3, SMPTE 274M/293M/296M and supports ATSC HDTV resolutions including 480p, 720p, and 1080i.
1.3.2 Serial Interface
The device includes a 2-wire read and write serial interface for programming the registers in the device. The interface is designed to operate with 3.3 V levels. To ensure that valid serial data is received and transmitted, make sure the VDD_SI pin is connected to a stable 3.3 V supply. Review Chapter 2.2, Chapter 2.3 and Chapter 2.4 for more details of the encoder's serial interface.
1-10
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
1.3.3 Low Voltage Graphics Interface
The CX25870/871 can receive or transmit signals from/to a graphics controller at any of five different voltage levels. The allowable voltage levels are 3.3 V 1.8 V , , 1.5 V, 1.3 V and 1.1 V. Default input/output voltage amplitude for the interface , signals (defined as P[23:0], HSYNC*, VSYNC*, CLKI, CLKO, BLANK*, and FIELD) is 3.3 V and matches the Bt868/869 to ensure backwards compatibility. For a 3.3 V digital interface, no special configuration steps are necessary. Simply follow "Recommended Layout for Connection with a 3.3 V Master Device" in Chapter 3.3 and on power-up, the encoder will automatically expect 3.3 V signal transitions. For a 1.8 V or lower digital interface, several special configuration steps are necessary. First, the layout must adhere to Chapter 3.3's "3.3 V/1.8 V . Recommended Layout for Connection with a 1.8 V Master Device." Second, program the DRVS[1:0] field (bits[6:5] of register (0x32)) to 01(or an alternate value for 1.5 V, 1.3 V or 1.1 V interface). This forces the encoder to increase its drive strength on each interface signal used as an output in the interface. Third, connect the VDDL (pin 40) and VDD_CO (pin 57) power supply pins to the correct lower supply voltage (1.8 V or other). Fourth, using a voltage divider circuit or some other method, tie the CX25870/871's VDD_VREF input (pin 49) to a level equal to (VDDL/ 2 ). Make sure this voltage source is stable since the VDDL pin controls the output signal levels. The VDD_VREF pin dictates the encoder threshold voltage received for the appropriate input signals. The third and fourth steps are illustrated in Figure 3-5. Make sure the graphics controller is configured to send and accept signals at the lower supply voltage. Adjusting VDD_CO, VDDL and VDD_VREF appropriately controls the input voltage levels for the digital input pins P[23:0], CLKI, and HSYNC*/VSYNC*/BLANK* (in slave interface; EN_BLANKO = 0). Using the DRVS[1:0] bits control the output voltage levels for the digital output pins CLKO, FIELD, and HSYNC*/VSYNC*/BLANK* (in master or pseudo-master interface; EN_BLANKO = 1). In this way, the digital input pins can operate at different input voltage levels than the digital output voltage levels.
100381B
Conexant
1-11
1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-5. Digital Pins that Comprise the Low Voltage Graphics Interface Pin #
5 6 7 8 9 10 11 12 13 14 15 16 17 18 23 24 25 26 27 28 29 32 33 34 35 36 37 38 54 56
Pin Name
Pixel[0] Pixel[1] Pixel[2] Pixel[3] Pixel[4] Pixel[5] Pixel[6] Pixel[7] Pixel[8] Pixel[9] Pixel[10] Pixel[11] Pixel[12] Pixel[13] Pixel[14] Pixel[15] Pixel[16] Pixel[17] Pixel[18] Pixel[19] Pixel[20] Pixel[21] Pixel[22] Pixel[23] HSYNC* VSYNC* FIELD BLANK* CLKI CLKO Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input
Direction of Pin
Input or Output Input or Output Output Input or Output Input Output
1-12
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
1.3.4 Reset
If the RESET* pin is held low (between 0.8 V and GND -0.5 V) for a minimum of 20 clock cycles, a timing reset and a software reset is performed and the serial interface is held in the reset condition. A timing reset, which can be generated by setting the TIMING_RST register bit, will set the subcarrier phase to zero, and configure the horizontal and vertical counters to the beginning of VSYNC* of Field 1 (both counters equal to zero). If the CX25870/871 is in the master interface (i.e., CX25870 sends the syncs to the data master) then after a power-on or pin reset the encoder and the flicker filter starts a line 1, pixel 1 of their respective timing generation. For the encoder this means the odd field is always the first field after a power-on reset, pin reset, or timing reset. In timing the slave interface (CX25870 is either pseudo-master or pure slave), even though the input is receiving progressive frames that have no field associated with it, the input timing generator keeps track of the frames received. As a result, after every second frame received, a frame sync is sent to the encoder section so that the input and encoder remain synchronized. The frame sync forces the encoder to the beginning of the odd field. Conexant recommends that after every overscan compensation or video output type change, the TIMING_RST bit be enabled. The setting of the TIMING_RST bit should occur after waiting a minimum of 1 ms between the last CX25870 register write for the new overscan compensation ratio. The TIMING_RST register bit clears itself and reinitializes the internal timing generators. A software reset, which can be generated by setting the SRESET register bit, initializes all the serial interface registers to their default state. As a result, all digital output control pins are three-stated. Registers 0x38 and 0x76 to 0xB4 inclusive are then initialized to auto-configuration mode 0 (see the Auto Configuration section values) or mode 1 depending on the state of the PAL pin. The EN_OUT bit must be set to enable the digital outputs. A power-on reset, pin reset, or timing reset (register 0x6C, bit 7) causes the input timing generator to send the encoder a frame synchronization pulse setting the encoder to the beginning of the odd field. The first HSYNC*/VSYNC* combination then corresponds to the encoder even field and then the second HSYNC*/VSYNC* combination again causes a frame synchronization pulse and the encoder will start the odd field, and so on and so forth. A power-on reset is generated on power-up. The power-on reset generates the same type of reset as the RESET* pin. A time delay circuit triggered after the supply voltage reaches a value sufficiently high enough for the circuit to operate and then generate the power-on reset. As such, the device may not initialize to the default state unless the power supply ramp rate is sufficiently fast enough. A hardware/pin reset is recommended if the default state is required.
1.3.5 Device Initialization
After a reset condition, the device must be programmed through the serial interface to activate a video output and enable the CLKO, HSYNC*, VSYNC*, and FIELD outputs. The easiest method for accomplishing the initialization phase is to use one of the auto configuration modes in Appendix C, and program the interface bits appropriately. (Refer to Section 1.3.8.)
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.6 Clocking and Timing Generation
Two timing generators control the operation of the encoder. The output encoder timing block generates the signals for the proper encoding of the video into NTSC, PAL, or SECAM and extracts the processed input pixels from the internal FIFO. The encoding timing generator can receive its clock from either an external crystal oscillator and internal PLL (master and pseudo-master interface), or from the CLKI pin (slave interface). Conexant recommends that the encoding clock be generated by the PLL. Register bit EX_XCLK selects the clock source. If EN_XCLK is set to a logical 0, the internal clock source is selected via the crystal attached to XTALIN/XTALOUT. When the EN_XCLK bit is set, the clock source received at the CLKI pin is utilized as the main pixel/encoder clock. Conexant recommends that the encoding clock be generated by the PLL. A crystal must be present between XTALIN and XTALOUT pins if the internal clock source is selected. In this case, the CX25870/871's CLK frequency is synthesized by its PLL such that the pixel clock frequency equals For PLL DIV10=0: Fclk = Fxtal * {PLL_INT(5:0) + [PLL_FRACT(15:0)/216]}/6 For PLL DIV10=1: Fclk = Fxtal * {PLL INT(5:0) + [PLL FRACT(15:0)/216]}/10 where: Fclk = CLKO Output Frequency = CLKI Input Frequency
NOTE:
In some special modes, CLKO = Fclk / 2.
The crystal must be chosen so that the precise line rate for the video standards required can be achieved. This is done to maintain the subcarrier relationship to the line rate and thereby achieve the precise subcarrier frequency required. The crystal oscillator is designed to oscillate from 5 MHz through 25 MHz. A 13.5000 MHz crystal meets the requirements for NTSC, PAL, and SECAM video standards. The crystal must be within 50 ppm of the maximum desired clock rate for NTSC operation, and 25 ppm for PAL or SECAM operation, across the temperature range (0 to 70 C). If the CX25870/871 is to provide all video outputs selectable through software, the customer must use a crystal with a maximum tolerance across the temperature range of 25 ppm. Appendix B contains a list of previously tested and recommended crystal vendors. The crystal oscillator is disabled by the XTAL _PAD_DIS register bit. Sufficient time (20 s) must be allowed after coming out of sleep mode to allow the oscillator to stabilize. The PLL_LOCK bit is set when the PLL is stable. In addition, if the PLL_INPUT register bit is set to a logical 1, CLKI is selected as the reference for PLL. In this special mode (slave interface with the PLL_32CLK high), the above Fclk formulas replace Fxtal with FCLKI/2 (i.e., input clock frequency is divided by 2). If the external clock source is selected (EN_XCLK=1), a clock signal of the desired pixel clock rate must be present at the CLKI pin. The CLKO pin is three-stated, and the crystal oscillator disabled. The clock must meet the same requirements as above. It is highly recommended that the internal clock be used in order to ensure the output video remains within the specifications defined by the relevant video standard. Any aberration in the source clock is reflected in the color subcarrier frequency of the output video and detracts from the quality of the image on the television.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
The BY_PLL bit bypasses the PLL, and the encoder clock will be at the crystal frequency. This bit takes precedence over the EN_XCLK bit. The second timing generator controls the generation of the HSYNC*, VSYNC*, and BLANK* signals, and pixel input clocking. This is normally the same clock as the encoding clock. The EN_ASYNC register bit, if set, allows this clock to be driven directly by the CLKI pin. If the DIV2 register bit is set, this internal clock is divided by two before driving the second timing generator. This is required for interlaced input to interlaced output mode (i.e., CCIR601/DVD and CCIR656 applications). The CLKI pin is the clock used for synchronizing pixel inputs (P[23:0]) with the timing input signals (HSYNC*, VSYNC*, and BLANK*) and normally is a delayed version of the CLKO pin. It can be directly connected to CLKO if desired. Data is registered with this input and re-synchronized to the internal clock. In a multiplexed input mode, both edges of the CLKI input are used. If the MODE2X register bit is set, the internal clock is divided by two, allowing a 2x external clock, and data to be provided on the rising edge only. 1.3.6.1 3:2 Clocking Mode All graphics controllers require some finite time for resetting their internal counters to zero, clearing register flags, and any other event that needs to be performed on a line-by-line basis. The sum of time these incidents take are the graphics controller's Horizontal Blanking Time. The amount of Horizontal Blanking time varies from one master device to another but it can never be less than 0 s and usually does not exceed 4 s per digital line.
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Conexant
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-4 illustrates higher resolutions (i.e., 800x600 or greater), for some data master devices that require more Horizontal Blanking Time than the CX25870/871 provides in standard clocking mode, for dual display of certain overscan compensation percentage pairs. For example, a graphics controller may require a minimum total of 1.25 s of Horizontal Blanking time per line while clocking a frame with an active resolution of 800x600 to the encoder. If this were the case, the entire set of overscan compensation solutions charted at the 1 s diagonal plot line (denoted with a dot-dash-dot) and below are made unavailable to the designer. The result is a more limited set of overscan pairs to choose from, and correspondingly less size control for the picture when displayed on a television.
Figure 1-4. Allowable Overscan Compensation Ratios for Dual Display, 800x600 Input/NTSC Output
Overscan Compensation Percentage Pairs for 800x600 NTSC 24
22
3 s
Horizontal Overscan Compensation Percentage
20
18
2 s
16
1 s
14
.75 s
12 0 s Horizontal Blanking 10
8
8
10
12
14
16
18
20
22
Legend: = Pixel Clock Solution = 8-Cycle Character Clock Solution = 9-Cycle Character Clock Solution
Vertical Overscan Compensation Percentage
NOTE(S): Use this chart for PAL M and PAL 60 allowable overscan ratios
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
Since the CX25870/871 contains this new 3:2 Clocking Mode, the designer does not face this constraint any longer. By choosing an appropriate autoconfiguration mode, setting the PLL_32CLK bit to 1, and altering the values for various timing registers within the controller and encoder (e.g., H_CLKI = HTOTAL, VLINES_I = VTOTAL, H_BLANKI, V_BLANKI, etc.), the encoder switches into the 3:2 Clock mode. While in this operational state, additional solutions in the overscan-compensation-pairs domain for higher resolutions now exist. In addition, the encoder now allows the data master (e.g., graphics controller) to send digital data to it at a faster rate than is clocked out of the encoder. Specifically, the CX25870/871 begins to transfer pixels out at a rate of [2/3] that of the CLKI input frequency. In other words, the pixel input frequency clocks in data at a ratio of [3:2] or 11/2 times faster than the CX25870/871 outputs the analog pixel data. In this mode, the encoder's expansive on-chip FIFO bridges the frequency difference that now exists between the digital-timing input and mixed-signal encoder output blocks of the CX25870/871. The result is a much closer match in the available overscan percentages in the horizontal and vertical direction for the higher resolutions. This ensures the TV Out picture appears more orthogonal where the amount of blanking is nearly equal on all sides of the image. Since the Horizontal Blanking Time only becomes a critical issue at higher resolutions, the user should use a 3:2 Clocking Mode only when necessary at 800x600, and always at 1024x768. For software programming ease, some of the autoconfiguration modes for 800x600 and all for the 1024x768 resolution are 3:2 solutions already. The specific modes that use the 3:2 clock feature are contained in Appendix C and summarized in Table 1-6 below.
Table 1-6. Autoconfiguration Solutions that Utilize 3:2 Clocking Mode Autoconfiguration Mode #
10 11 14 15 18 22 26 30 34 40 42 43
Active Resolution
1024x768 1024x768 1024x768 1024x768 800x600 800x600 1024x768 1024x768 800x600 800x600 1024x768 1024x768
Type of Digital Input
RGB RGB YCrCb YCrCb RGB YCrCb RGB YCrCb RGB RGB RGB RGB
Overscan Ratio
Standard Standard Standard Standard Lower Lower Lower Lower Higher Alternate Higher Higher
Video Output Type
NTSC PAL-BDGHI NTSC PAL-BDGHI NTSC NTSC NTSC NTSC NTSC NTSC NTSC PAL-BDGHI
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
If the desired overscan ratio is not available via a particular autoconfiguration mode, you should derive another 3:2 Solution via Super Cockpit (i.e., CX25870 register programming tool), or contact your local FAE directly. If done correctly, this CX25870/871 register set will have PLL_32CLK (bit 5 of register 0x38) set and adjust the timing registers appropriately.
1.3.7 Master, Pseudo-Master, and Slave Interfaces
Like its predecessor, the Bt868/869, the CX25870/871 encoder can be operated in three possible interfaces. These connection types are named master, pseudo-master, and slave. The clocking ability of the master device and direction of the timing signals dictate what particular interface is used between the Conexant encoder and graphics controller/data master device. 1.3.7.1 Master Interface In master interface, CLKO, HSYNC*, VSYNC*, and BLANK*, are generated by the encoder as outputs. These signals' leading edges denote when a new clock period, new line, and new frame starts respectively. Because the encoder transmits the clock and timing signals, this interface is also referred to as clocking master/timing master. An illustration of the master interface is shown below using the graphics controller as the master device and S-Video and two Composite ports as the video outputs.
Figure 1-5. Operating the CX25870/871 in Master Interface
Clock
Clock Delay Graphics Controller RGB or YCrCb HSYNC* VSYNC* BLANK*
CLKI
CLKO
Composite #1 Luma Chroma Composite #2 S-Video
CX25870/ CX25871
100381_054
A minimum of 9 inputs (CLKI and 8 lines for pixel data- P[7:0]) and 3 outputs (HSYNC*, VSYNC*, and CLKO) are required for this configuration. The amount of inputs could grow as high as 25 if 24-bit RGB nonmultiplexed mode is chosen as the Input Pixel Mode (i.e., IN_MODE[3:0] = 0011) by the designer. Master interface can only exist if the graphics controller can accept the encoder's reference clock and send back a version of that clock at the same frequency with the pixel data transitions synchronized to CLKI's rising and falling edges. This is accomplished via the VGA encoder's clock output (CLKO) and clock input (CLKI) ports.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
1.3.7.2 Reason for BLANK*
If the graphics controller possesses pixel-based resolution (i.e., pixels are only a single pixel clock wide) then the encoder does not have to transmit or receive the BLANK* signal. However, for graphics controllers that are character clock based, a BLANK* signal is necessary. The BLANK line is necessary because a character clock is actually 8 or 9 pixel clocks in duration. This causes several pixel clocks to elapse, resulting in an erroneous delay prior to the next HSYNC* being observed by the encoder and the next line starting. The only method of compensating for this delay is for character clock based controllers to use the BLANK* signal. This signal is required in the physical interface to indicate the exact location of the first active pixel on each line. In pseudo-master interface, the CX25870/871 generates clock reference signal, CLKO as an output. This signal's purpose is to inform the graphics controller the exact frequency at which the data must be sent to the encoder. Timing signals, HSYNC*, VSYNC*, and BLANK*, are received by the encoder as inputs. The leading edges of these signals denote when a new clock period, new line, and new frame starts, respectively. Because this connection scheme shares mastering responsibilities, the interface is also named clocking master/timing slave. An illustration of the pseudo-master interface is illustrated below using the graphics controller as the timing master device.
1.3.7.3 Pseudo-Master Interface
Figure 1-6. Operating the CX25870/871 in Pseudo-Master Interface
Clock
Clock Delay Graphics Controller RGB or YCrCb HSYNC* VSYNC* BLANK*
CLKI
CLKO
Composite #1 Luma Chroma Composite #2
CX25870/ CX25871
100381_055
A minimum of 11 inputs (CLKI, HSYNC*, VSYNC*, and 8 lines for pixel data- P[7:0]) and 1 output (CLKO) are required for this configuration. The amount of inputs could grow as high as 28 if 24-bit RGB nonmultiplexed mode is chosen as the Input Pixel Mode (i.e., IN_MODE[3:0] = 0111) by the designer. Pseudo-Master interface can only exist if the graphics controller can accept the encoder's reference clock and send back a version of that clock at the same frequency with the pixel data transitions synchronized to CLKI's rising and falling edges. This is accomplished via the VGA encoder's clock output (CLKO) and clock input (CLKI) ports.
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1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.7.4 Slave Interface
In slave interface, no output signals are generated by the encoder. The CX25870/871 relies strictly on the graphics controller to send clock and timing signals to trigger when a new clock period, new line, and new frame starts. Because no frequency reference signal is used (CLKO), the master device must pre-program the encoder with an appropriate register set so the CX25870/871 expects data at the specific digital pixel rate prior to actually receiving the data. In addition, the timing signals must be shaped so they adhere to the appropriate slave interface timing diagrams illustrated in Chapter 4.0. Due to the added complexity of this interface, Conexant recommends its use only as a final option. The slave interface is illustrated in Figure 1-7 below using the graphics controller as the master device and S-Video and 2 Composite ports as the video outputs.
Figure 1-7. Operating the CX25870/871 in Slave Interface
Clock RGB or Graphics Controller YCrCb HSYNC* VSYNC* BLANK*
CLKI CX25870/ CX25871
Composite #1 Luma Chroma Composite #2
100381_056
A minimum of 11 inputs (CLKI, HSYNC*, VSYNC*, and P[7:0]) are required for this configuration. The amount of inputs will increase to 15 (without BLANK*) or 16 (with BLANK*) if 24-bit multiplexed RGB mode is chosen as the Input Pixel Mode (i.e., IN_MODE[3:0] = 0000) by the designer. It is highly recommended that the device operate in master or pseudo-master interface to ensure that the input and output video streams remain synchronized. If either the master device, supplying the HSYNC* and VSYNC* inputs, or the encoder, which receives the data, is not correctly programmed, the output image will lose lock with the input. By running the CX25870/871 in either clock master interface, any timing errors that occur can be absorbed to some extent by the expansive on-board FIFO.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
1.3.7.5 Slave Interface Without a Crystal
For price-sensitive applications, it is possible to remove the crystal found between the XTALIN and XTALOUT ports and strictly utilize the incoming CLKI signal as both the data transfer mechanism and internal main clock source for the encoder. To complete this architecture, the data master must also program the CX25870's EN_XCLK bit to 1. This will trigger CLKI to be used for all operations requiring a clock source and force the encoder to ignore any oscillations received via its XTALIN and XTALOUT pins. The flicker filter and timing blocks will utilize this asynchronous clock on the input side for data processing, and the encoder will combine its internal PLL and CLKI in conjunction with the DACs to transmit video from the device. Since CLKI will be the only incoming frequency reference, the encoder uses this signal to run its internal PLL for derivation of the video color subcarrier (Fsc). Since PAL and SECAM televisions are not lenient in accepting color subcarrier frequencies with more than 25 ppm error (i.e., Fsc 330 Hz), it is critical the data master maintain a very high level of accuracy for the incoming clock. In numerical terms, this means that the incoming clock should always remain within a window of {ideal CLKI} 25 ppm. As an example, for autoconfiguration mode #1, CLKI would have to reside in the range [29.499270 MHz < ideal CLKI = 29.500008 MHz < 29.500746 MHz.] Tight control of the incoming digital clock ensures that the CX25870 generates an analog Fsc of 4.433618 MHz 338 Hz for PAL-BGHI or 4.250000 / 4.406250 MHz 338 Hz for SECAM. Actual testing has found that excursions outside this range result in loss of color for PAL and SECAM televisions and sometimes affect NTSC sets in the same manner. When the CX25870 is receiving an external clock, its serial bus is also dependent on this incoming signal. As a result, the data master should never disable the input clock. If this happens, even momentarily, the only way the encoder can recover is for the data master to pin RESET* the CX25870. The encoder will then be re-enabled as a timing master and respond again to serial commands transmitted by the data master. Several other registers must be reprogrammed to make this special type of interface work properly. Consult your local Conexant representative for technical assistance.
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.8 Autoconfiguration and Interface Bits
The default operation of the CX25870/871 is tied into its 44 autoconfiguration modes. Autoconfiguring the device occurs when bits CONFIG[5:3] and CONFIG[2:0] in register 0xB8 are programmed to any state from 000000 to 101111. At the conclusion of this serial write, default values are copied from the CX25870/871's internal ROM into the most important timing registers that have the indices 0x38 and 0x76 to 0xB4, inclusive. All other registers are not changed at the conclusion of an autoconfiguration mode. After an autoconfiguration command, the CX25870/871 device remains in the same interface it was in before the command execution. Depending on which autoconfiguration mode# was initiated, the CX25870/871 will expect to receive either a 320x200, 320x240, 640x400, 640x480, 720x400, 720x480, 720x576, 800x600, or 1024x768 active digital input frame and output a NTSC or a PAL composite and/or S-video signal. See Table 2-5 of this data sheet for a description of CONFIG[5:0] and Appendix C for more detail on each autoconfiguration mode. Using an autoconfiguration mode is the easiest method for bringing up the most popular desktop, game/Direct X, DOS boot-up screen, and DVD resolutions with the encoder as both the timing and clock master. This is true even if the graphics controller cannot utilize the CX25870/871 in master mode but must use pseudo-master mode. To turn the direction of the SYNCs around so they are transmitted by the graphics controller and received by the CX25870/871 simply requires reprogramming the encoder via several serial writes. The Interface bits that need to be changed are SLAVER, EN_BLANKO, EN_DOT, and EN_OUT. Since the abilities of graphics controllers vary greatly, Tables 1-7 through 1-12 have been compiled below to explain the relationship between the Interface bits and the actual interface itself. Even more permutations of the following interfaces below are possible but Tables 1-7 to 1-12 capture the six most popular architectures.
Table 1-7. Master Interface without a BLANK* Signal (Default Immediately after any Autoconfiguration Command) Interfaced Used
MASTER (default) BLANK* is an output from the CX25870/871 or BLANK* s NOT included as part of the interface.
SLAVER (Bit 5 of 0xBA) ORed with Slave Pin
0
EN_BLANKO (MSb of Register 0xC6)
1
EN_DOT (Bit 6 of Register 0xC6)
0
EN_OUT (LSb of Register 0xC4)
1
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
*
* * *
If the SLAVE pin is tied to GND, the state of the SLAVER bit dictates whether the CX25870/871 is the timing master or timing slave by controlling the direction of the HSYNC* and VSYNC* ports. In other words, SLAVER will determine whether the overall interface is master or pseudo-master. The SLAVER bit allows the graphics controller vendor to switch between master video timing and slave video timing through software so long as the SLAVE pin (#51) is low. EN_BLANKO is high (=1), signifying the CX25870/871's BLANK* port is an output or that NO BLANK* signal is used as part of the system. EN_DOT = 0 telling the CX25870/871 to use its internal counters to determine the active versus the blanking regions. EN_OUT = 1 ensures there is a clock output (CLKO) from the CX25870/871 and also enables HSYNC* and VSYNC* outputs.
Table 1-8. Master Interface with a BLANK* Input to the CX25870/871 Interfaced Used
MASTER BLANK* SIGNAL transmitted to the CX25870/871 and received as an input.
SLAVER (Bit 5 of 0xBA) ORed with Slave Pin
0
EN_BLANKO (MSb of Register 0xC6)
0
EN_DOT (Bit 6 of Register 0xC6)
1
EN_OUT (LSb of Register 0xC4)
1
*
* *
*
If the SLAVE pin is tied to GND, the state of the SLAVER bit dictates whether the CX25870/871 is the timing master or timing slave by controlling the direction of the HSYNC* and VSYNC* ports. In other words, SLAVER determines whether the overall interface is master or pseudo-master. The SLAVER bit allows the graphics controller vendor to switch between master video timing and slave video timing through software so long as SLAVE pin (#51) is low. EN_BLANKO is low (= 0), signifying the CX25870/871's BLANK* port is an input. EN_DOT = 1 telling the CX25870/871 to use the BLANK* signal it is receiving to determine where active video starts (rising edge of BLANK*) and uses HACTIVE register to determine the start of the blanking region. EN_OUT = 1 ensures there is a clock output (CLKO) from the CX25870/871 and also enables HSYNC* and VSYNC* outputs.
Table 1-9. Pseudo-Master Interface without a BLANK* Signal Interfaced Used
PSEUDO MASTER BLANK* is NOT included as part of the interface.
SLAVER (Bit 5 of 0xBA) ORed with Slave Pin
1
EN_BLANKO (MSb of Register 0xC6)
1
EN_DOT (Bit 6 of Register 0xC6)
0
EN_OUT (LSb of Register 0xC4)
1
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
* * * *
SLAVER bit = 1 so the CX25870/871 is the video timing slave. It expects to receive the syncs from the graphics controller. EN_BLANKO is high(=1), signifying the CX25870/871's BLANK* port is an output or that NO BLANK* signal is used as part of the system. EN_DOT = 0 telling the CX25870/871 to use its internal counters to determine the active versus the blanking regions. EN_OUT = 1 ensures there is a clock output (CLKO) from the CX25870/871.
Table 1-10. Pseudo-Master Interface with a BLANK* Input to the CX25870/871 Interfaced Used
PSEUDO MASTER BLANK* SIGNAL transmitted to the CX25870/871 and received as an input.
SLAVER (Bit 5 of 0xBA) ORed with Slave Pin
1
EN_BLANKO (MSb of Register 0xC6)
0
EN_DOT (Bit 6 of Register 0xC6)
1
EN_OUT (LSb of Register 0xC4)
1
* * *
*
SLAVER bit = 1 so the CX25870/871 is the video timing slave. It expects to receive the syncs from the graphics controller. EN_BLANKO is low (= 0), signifying the CX25870/871's BLANK* port is an input. EN_DOT = 1 telling the CX25870/871 to use the BLANK* signal it is receiving to determine where active video starts (rising edge of BLANK*) and where the blanking region starts (falling edge). EN_OUT = 1 ensures there is a clock output (CLKO) from the CX25870/871.
Table 1-11. Slave Interface without a BLANK* Signal Interfaced Used
SLAVE BLANK* is NOT included as part of the interface.
SLAVER (Bit 5 of 0xBA) ORed with Slave Pin
1
EN_BLANKO (MSb of Register 0xC6)
1
EN_DOT (Bit 6 of Register 0xC6)
0
EN_OUT (LSb of Register 0xC4)
0
EN_XCLK (MSb of Register 0xA0)
1
*
*
After an autoconfiguration command, the CX25870/871 expects active low VSYNC* and HSYNC* signals from the controller. The format of pixels at input of encoder needs to be 24-bit RGB multiplexed unless modifications are made to the IN_MODE[3:0] 4-bit sequence. In addition to Table 1-11, another bit must be programmed manually with this interface. The most significant bit of CX25870/871 register 0xA0 must be set. This guarantees that EN_XCLK is high (=1) which will allow the CX25870/871 to accept CLKI as the pixel clock source.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
*
* * *
SLAVER bit = 1 the CX25870/871 is the video timing slave. It expects to receive the syncs from the graphics controller. Since the CX25870 is in slave mode, the HSYNC* and VSYNC* outputs will be three-stated and the CX25870/871 will be set up to receive these timing signals from the graphics controller. EN_BLANKO is high (=1), signifying the CX25870/871's BLANK* port is an output or that NO BLANK* signal is used as part of the system. EN_DOT = 0 telling the CX25870/871 to use its internal counters to determine the active versus the blanking regions. EN_OUT = 0: This ensures the clock output port (CLKO) is three-stated from the encoder.
Table 1-12. Slave Interface with a BLANK* Input to the CX25870/871 Interfaced Used
SLAVE BLANK* SIGNAL transmitted to the CX25870/871 and received as an input.
SLAVER (Bit 5 of 0xBA) ORed with Slave Pin
1
EN_BLANKO (MSb of Register 0xC6)
0
EN_DOT (Bit 6 of Register 0xC6)
1
EN_OUT (LSb of Register 0xC4)
0
EN_XCLK (MSb of Register 0xA0)
1
*
*
*
* *
*
NOTE:
After an autoconfiguration command, the CX25870/871 expects active low VSYNC* and HSYNC* signals from the controller. The format of pixels at input of encoder needs to be 24-bit RGB multiplexed unless modifications are made to the IN_MODE[3:0] 4-bit sequence. In addition to Table 1-11, another bit must be programmed manually with this interface. The most significant bit of CX25870/871 register 0xA0 must be set. This guarantees that EN_XCLK will be high (=1) which will allow the CX25870/871 to accept CLKI as the pixel clock source. SLAVER bit = 1 so the CX25870/871 is the video timing slave. It will expect to receive the syncs from the graphics controller. Since the CX25870 is in slave mode, then the HSYNC* and VSYNC* outputs will be three-stated and the CX25870/871 will be set up to receive these timing signals from the graphics controller. EN_BLANKO is low (= 0), signifying the CX25870/871's BLANK* port is an input. EN_DOT = 1, telling the CX25870/871 to use the BLANK* signal it is receiving to determine where active video starts (rising edge of BLANK*) and the HACTIVE register to denote where the blanking region starts. EN_OUT = 0: This will ensure the clock output port (CLKO) is three-stated from the encoder. Autoconfiguration Mode #28 and #29 for NTSC and PAL DVD Playback place the encoder into slave interface where it expects a BLANK* input (Table 1-11).
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Flicker-Free Video Encoder with Ultrascale Technology
1.3.9 Adaptations for Clock-Limited Master Devices
Ideally, the graphics controller or proprietary ASIC, in combination with the CX25870/871, operates in either master or pseudo-master interface. Occasionally, using either of the clock master configurations is not possible because the master device does not have the capabilities of receiving a clock from the encoder nor can it synchronize the digital data with this clock on its return. If either limitation exists, only slave interface can be used for the system configuration. Often, within the slave interface, the data master can only generate certain discrete clock frequencies. This means the encoder has to make extra accommodations for normal TV Out to occur. Fortunately, the encoder does have the flexibility to adapt to almost any incoming clock frequency in the range from 20 MHz to 80 MHz. All that is required is to follow the procedure in Table 1-13 which forces the encoder to accept a frequency through CLKI that does not match any CX25870/871 autoconfiguration frequency. Once the CX25870/871's 4-byte wide MSC register is reprogrammed accordingly, the result is the generation of the correct color subcarrier frequency for NTSC or PAL and corresponding proper S-Video or Composite TV output. Table 1-13 and Table 1-14 contain the procedures required for the encoder to accept a frequency through CLKI that is not equal but is close to the chosen CX25870/871 autoconfiguration mode clock frequency. Completion of the steps contained in the two tables will modify the MSC register and PLL_INT and PLL_FRACT registers correctly and thus produce an accurate NTSC or PAL analog output.
Table 1-13. Adjustment to the CX25870/871 MSC Registers
What is input frequency to CX25870/871's CLKI input from data master? Depending on answer to step 1, find an autoconfiguration mode that has a frequency close to the incoming input frequency (within 1 MHz is preferred). 3. Look up the clock frequency for the chosen autoconfiguration mode in Appendix C of the CX25870/871 data sheet. 4. Determine the scaling factor `x' where x= input frequency to CLKI input (usually from data master) autoconfiguration mode frequency as specified in Appendix C
1. 2. 5.
6. 7. 8.
9.
Determine the autoconfiguration mode's MSC[31:0] value in hex by reading back the CX25870/871's registers; 0xB4(=MSB), 0xB2, 0xB0, 0xAE(=LSB). These register values can also be found by looking them up in Register C. The values determined will have to be cascaded together. Convert the MSC[31:0] 4-byte hexadecimal value to decimal. Divide the total found from step 6 by the scaling factor `x' found from step 4. Convert the answer from step 7 to the hexadecimal format. This value should be comprised of a total of 4 bytes. The most significant byte will likely not change from the previous value in register MSC[31:24]. Other MSC values may not change either but the least significant bytes should have definitely been modified. Program the bytes determined from step 8 into the CX25870/871's MSC[31:0] registers. Write these bytes in order to registers 0xB4 (most significant byte = MSC[31:24]), 0xB2, 0xB0, and 0xAE (least significant byte = MSC[7:0]).
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Table 1-14. Adjustment to the PLL_INT and PLL_FRACT Registers
1.0 Functional Description
1.3 Device Description
What is input frequency to CX25870/871's CLKI input from data master? Depending on answer to step 1, find an autoconfiguration mode that has a clock frequency close to the incoming CLKI frequency (within 1 MHz is preferred). 3. Look up the desired clock frequency for the chosen autoconfiguration mode in Appendix C of the CX25870/871 data sheet. 4. Determine the scaling factor `x' where:
1. 2.
x=
5. 6. 7. 8.
input frequency to CLKI input (usually from data master) autoconfiguration mode frequency as specified in Appendix C
9. 10. 11. 12. 13.
Determine the PLL_INT value in hex by reading back the CX25870/871's register 0xA0 for that autoconfiguration mode. This register value can also be found by looking it up in Appendix C. Convert the PLL_INT register value to decimal. Multiply the answer found in step 6 by 216 = 65536. Determine the PLL_FRACT value in hex by reading back the CX25870/871's register 0x9E and 0x9C. These two registers cascade to form the PLL_FRACT[15:0] 2-byte value. These register values can also be found by looking them up in Appendix C. Convert the 2-byte PLL_FRACT register value to decimal. From steps 7 and 9, add the PLL_INT and PLL_FRACT decimal values. Multiply the total found from step 10 by the scaling factor `x' found from step 4. Convert the answer from step 11 to the hexadecimal format. The value should be comprised of a total of three bytes. The most significant byte will likely be the original PLL_INT[7:0] byte from step 2. Program the bytes determined from step 12 into the CX25870/871's PLL_INT[7:0] and PLL_FRACT[15:0] registers. The most significant byte from step 12 is the new PLL_INT value. Write this to register 0xA0. The 2 least significant bytes from step 12 is the new PLL_FRACT value. Write these bytes in order to registers 0xBE and 0xBC respectively.
1.3.10 Input Formats
The device can convert a wide range of input formats to analog standard or HDTV television video formats. The input can be either noninterlaced or interlaced digital data from 320 x 200 to a maximum of 1024 x 768 pixels per frame for standard TV outputs. While generating HDTV outputs the device can accept greater than 1024 x 768 input frames. Many other nonstandard input formats can be encoded as well. For detailed information on the CCIR601 mode, please refer to the DVD Movie Playback Architecture and Solutions Application Note. This application note can be obtained from your local Conexant Systems sales office. For instructions on how to display nonstandard resolutions on the TV, request the "Supporting TV Out with Non-Standard Graphics Input Resolutions" Application Note from your local Conexant Systems sales office.
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Flicker-Free Video Encoder with Ultrascale Technology
1.3.11 Input Pixel Timing
The device can accept the input data in either RGB or YCrCb color spaces. Data can be input either a full pixel at a time clocked in on the rising edge of CLKI only, or in various multiplexed modes, using both edges of CLKI. In YCrCb format, either 24-bit 4:4:4 data or 16-bit 4:2:2 data can be input. In RGB format, either 15-bit 5:5:5, 16 bit 5:6:5, or 24-bit RGB can be input. In 16-bit 4:2:2 YCrCb input format, multiplexed Y, Cr, and Cb data is input through the P[11:4] or P[7:0]input pins. The Y data is input on the falling edge of CLKI. The Cr/Cb data is input on the rising edge of CLKI. The Cb/Y/Cr/Y sequence begins at the first active pixel. An additional 4:2:2 YCrCb input format maps Y to P[19:12] and Cr/Cb multiplexed on P[11:4]. In 24-bit 4:4:4 YCrCb input format, multiplexed Y, Cr, and Cb data is input through the P[11:0] inputs. Both the rising and falling edge of CLKI sample the input data. In RGB input format, input data is sampled as 12 bits at a time in 24-bit RGB format or 8 bits at a time in 15/16 bit RGB format on both the rising and falling edge of CLKI. Table 1-2 shows the data pin assignments for all available multiplexed input formats. In addition, all 24-bit formats, a 16-bit RGB format, and a 16-bit YCrCb format can utilize the nonmultiplexed clocking method. See Table 1-3 for these pin-to-bit assignments.
1.3.12 YCrCb Inputs (For Standard TV Outputs)
Y has a nominal range of 16-235; Cr and Cb have a nominal range of 16-240, with 128 (80 hex) equal to zero. Values of 0 and 255 are interpreted as 1 and 254, respectively. Y values of 1-15 and 236-254, and CrCb values of 1-15 and 241-254, are interpreted as valid linear values.
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Figure 1-8 illustrates the frequency response of the sub-sampling process. If 4:4:4 data is input, it is subsampled to 4:2:2 prior to overscan compensation and flicker filtering.
Figure 1-8. Decimation Filter at Fs=27 MHz
Chroma Decimation Filter 0
5
10
15
Decibels (dB)
20
25
30
35
40
45
0
1
2
3
4
5
6
Frequency (Fs = 27 MHz)
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The resulting 4:2:2 output must then be converted to YUV values and then scaled for the output range of the DACs. The MY, MCR, and MCB registers must be programmed to perform this conversion. The scaling equations are as follows: MY = (int) [V100/(219.0 * VFS) * 26 + 0.5] MCR = (int)[(128.0/127.0) * V100 * 0.877/(224.0 * VFS * 0.713 * sinx) * 26 + 0.5] MCB = (int)[(128.0/127.0)* V100 * 0.493/(224.0 * VFS * 0.564 * sinx) * 26 + 0.5] where:V100 = 100% white voltage (0.661 V for NTSC, 0.7 V for PAL/SECAM) VFS = Full scale output voltage (1.28 V) Fsc = color subcarrier frequency (see Table A-2) Fclk = Analog pixel rate Sinx = Sin ( *FSC/FCLK)/( *FSC/FCLK)
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Flicker-Free Video Encoder with Ultrascale Technology
1.3.13 RGB Inputs (For Standard TV Outputs)
With IN_MODE[3:0] set to a RGB mode, the encoder must receive digital gamma-corrected RGB data as an input. If this occurs, the RGB data will be converted to Y/R-Y/B-Y as follows: Y[9:0] = [INT(0.299 * 210) * R[7:0]} + INT(0.587 * 210 * G[7:0] + INT(0.114 * 210) * B[7:0] + 27] * 2-8 0 Y[9:0] 1024 For 15 and 16 bit RGB input formats, individual R, G, and B values are left justified to eight bit numbers. After the initial conversion, the Y/R-Y/B-Y values are sub-sampled to 4:2:2 data prior to overscan compensation and flicker filtering. The resulting 4:2:2 output must then be converted to YUV values and then scaled for the output range of the DACs. The MY, MCR, and MCB registers must be programmed to perform this conversion. The scaling equations are: MY = (int)[V100/(255 * VFS)*26 + 0.5] MCR = (int)[(128.0/127.0) * V100 * 0.877/(127 * VFS * sinx) * 25 + 0.5] MCB = (int)[(128.0/127.0) * V100 * 0.493/(127 * VFS * sinx) * 25 + 0.5] where:V100 = 100% white voltage (0.661 V for NTSC, 0.7 V for PAL) VFS = Full scale output voltage (1.28 V) Fsc = color subcarrier frequency (see Table A-2) Fclk = CLKI input frequency Sinx = Sin [(2 FSC/FCLK)/(2 FSC/FCLK)] For SECAM formulas see the SECAM section.
1.3.14 Input Pixel Horizontal Sync
The HSYNC* pin provides line synchronization for the pixel input data. It is an output in master interface and an input in slave and pseudo-master interface. In the master interface, it is a pulse two CLKI cycles in duration whose leading edge indicates the beginning of a new line of pixel data. The period between two consecutive HSYNC* pulses is H_CLKI CLK cycles. The first active pixel should be presented to the device H_BLANKI minus the internal pipelined clock (5 CLK cycles) after the leading edge of HSYNC*. The next H_ACTIVE pixels are accepted as active pixels and used in the construction of the output video. In the slave interface the exact number of clocks per line (H_CLKI) must be provided as calculated for the desired overscan ratio. Only the leading edge of HSYNC* is used, low times must be at least two CLKI cycles in duration. HSYNC* is clocked into the encoder by the rising edge of CLKI. The polarity of the HSYNC* signal is changed by the HSYNCI register bit. The default convention is active low.
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1.3.15 Input Pixel Vertical Sync
The VSYNC* pin provides field synchronization for the pixel input data. It is an output in master interface, and an input in the slave and the pseudo-master interface. For noninterlaced input timing in master interface, VSYNC* is a pulse one horizontal line time in duration whose leading edge indicates the beginning of a frame of input pixel data. The leading edge coincides with the leading edge of HSYNC*. The period of the pulses is V_LINESI horizontal lines. The first line of active data should be presented to the device V_BLANKI lines after the leading edge of VSYNC*. The next V_ACTIVEI lines are accepted as active lines and used in the construction of the output video. The CX25870/871 disregards lines after the leading edge of VSYNC* but before VSYNC* + V_BLANKI lines by not encoding them. In slave interface, the period must be exactly the frame rate of the desired video format. Only the leading edge is used, and the high and low duration must be at least two CLKI cycles. The beginning of the frame of data is indicated by the next leading edge of HSYNC* coincident with or after the leading edge of VSYNC*. For interlaced input timing, only the slave interface is supported. The period must be exactly the frame rate of the desired video format. If the leading edge of HSYNC* and VSYNC* are coincident, that indicates the input is in odd field, the internal line counter is reset to line 1 at the leading edge of VSYNC*. If the leading edges of HSYNC* and VSYNC* are not coincident, and separated by a minimum of two CLKI cycles, this indicates the input is an even field. In this case, the internal line counter is reset to line 2 at the beginning of the next line. Only the leading edge of VSYNC* is used, and the high and low VSYNC* width must be at least two CLKI cycles. VSYNC* is clocked in by the rising edge of CLKI. The polarity of the VSYNC* input and output can be programmed by the VSYNCI register bit. The default convention is active low. The FLD_MODE bits allow further flexibility in HSYNC* and VSYNC* timing relationship.
1.3.16 Input Pixel Blanking
Input pixel blanking can be controlled by either the BLANK* pin or by the internal registers. Blanking can be programmed independently of master or slave interface using the EN_BLANKO register bit. As an output (EN_BLANKO = 1), pixel blanking is generated based on the active area defined by H_BLANKI, H_ACTIVE, V_BLANKI, and V_ACTIVEI registers. With EN_BLANKO = 1, the BLANK* pin is output in the proper relationship to the syncs to indicate the location of active pixels. As an input (EN_BLANKO = 0), when the BLANK* pin goes high, it indicates the start of active pixels at the pixel input pins. In addition, the H_BLANKI register must be programmed properly. The duration of active data is still determined by the H_ACTIVE register. BLANK* is clocked by the rising edge of CLKI. An additional function for the BLANK* pin is used if the EN_DOT register bit is set. If EN_DOT = 1, the BLANK* pin becomes an input whose rising edge defines the graphics controller character clock boundary. This is used internally by the encoder to keep track of the exact pixel count for controllers that cannot operate at pixel clock rates but instead operate at VGA character clock rates. The polarity of the BLANK* input/output can be programmed by the BLANKI register bit. The default convention is active low.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-15 summarizes the direction of the BLANK* encoder in each interface. For more information refer to Section 1.3.8.
Table 1-15. Summary of Allowable BLANK* Signal Directions by Interface Interface
Master Pseudo-master Slave
Allowable Direction of BLANK*
Input or Output Input Input
1.3.17 Overscan Compensation
Overscan compensation is the process by which the encoder converts the digital input lines to the appropriate number of output lines for producing a full-screen image on the television receiver. This conversion is done in accordance with the Vertical Scaling Ratio (VSR). VSR is the ratio of the number of input lines received to number of output lines generated by the CX25870 (i.e., 262.5 lines/field for NTSC and 312.5 lines/field for PAL-BDGHI and SECAM). Using the correct amount of compensation in both the horizontal and vertical dimensions (at least 10 percent) will ensure that the entire digital image normally seen on the PC monitor is satisfactorily mapped to the analog television without any pixels or lines hidden in unviewable areas. Increasing the Horizontal Overscan Compensation (HOC) percentage while keeping the Vertical Overscan Compensation (VOC) percentage the same will have several effects on the VGA Encoder. First, the number of output clocks per line (H_CLKO) will increase. Correspondingly, the clock frequencies shared between the data master and CX25870 (i.e., CLKO = CLKI) will increase. Therefore, the original number of active pixels will be squeezed into a smaller analog video display region because the frequency at which input data is clocked into the CX25870 has increased. Since the CX25870 now processes active data at a faster rate than CCIR601-only compatible encoders, the graphics controller will need to transmit more blank pixels per line (i.e., HTOTAL must increase to match CX25870's H_CLKI) to make up the difference. Increasing the (VOC) percentage while keeping the Horizontal Overscan Compensation percentage the same will have several different effects on the VGA Encoder. First, the H_CLKO total will stay the same as will the pixel rate (i.e., CLKI = CLKO). These parameters are dictated by the HOC value only. Second, the number of total vertical input lines (V_LINESI = data master's VTOTAL) will increase, which will increase the internal VSR. The net result is that more active pixels and more active lines will be used to generate each output line. The only way for the graphics controller to transmit these additional input lines with the same clock frequency as before is to decrease the amount of blanked pixels per line.
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To support a custom overscan ratio, an entire set of overscan compensation calculations is required. This results in as many as 25 new register values for the CX25870. For ease of use, these equations are embedded into Conexant's programming application called Super Cockpit. Each computation is somewhat interdependent on the others but the basic overscan equations are as follows: (*) VSR = (V_LINESI) / (# of total output lines per field) and (**) # Blanked Pixels = {[H_CLKO / VSR] - H_ACTIVE} For illustrative purposes, the calculations used to generate the 13.785 percent HOC percentage for Autoconfiguration Mode 0-640x480 RGB in, H_CLKO = 1792, NTSC output, are shown below: From Appendix C (CX25870/871 Data Sheet): Number of clocks necessary to latch in the V .S.R. # of input lines for every 1 analog output line = 1792 CLKs [i.e., H_CLKO] CX25870 must ensure input is 2X upsampled. Therefore: # active CLKs per analog line = 2*(H_ACTIVE) # active CLKs per analog line = 1280 active CLKs per analog line percent of input used to create active video area = {1280 active CLKs / 1792 total CLKs} = 71.4286 percent Therefore: (x) = active region percent of analog output line = 71.4286 percent (y) = active region percent of typical analog video for NTSC = 52.65556 s / 63.55556 s = (y) = 82.4945 percent of line is active Ratio of [x/y] = {71.4286 percent / 82.4945 percent} = 0.862147 HOC percentage = 1-{Ratio of [x/y]} HOC percent = 1-0.862147 = 13.785 percent = HOC percentage for Autoconfiguration Mode 0 As a result, 13.785 percent of the horizontal active region within each line of an NTSC signal will be forcibly blanked by the CX25870. For most TVs, this will resize the upsampled digital image properly so all of the pixels fit horizontally within the bezeled area of North American or Japanese TVs. The 13.785 percent overscan percentage is equally distributed on either side of the horizontal active region (i.e., 13.785 percent / 2 = 6.89 percent extra blanking for the beginning and end of the line). The original 640 active pixels (i.e., H_ACTIVE) will then be `squeezed' into the remaining analog active region due to the faster pixel rate. The explanation of the vertical overscan percentage value is similar. For autoconfiguration mode #0, V_ACTIVEO is 212, which means there are 210 full active lines per field. The first and last lines are filtered lines that assist in smoothing the transitions into and out of the active region to avoid flickering and are not counted. Any NTSC standard calls for 243 active lines per field, so 210/243 = 0.864198 of the vertical active region is used. This calculation yields a vertical overscan compensation percentage of 100-86.4198 = 13.5802 percent.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Flicker filtering and vertical and horizontal overscan compensation are NOT SUPPORTED in any interlaced RGB or YCrCb input format sent to the CX25870. Interlaced input data is commonly used for DVD Out from a MPEG2 Decoder chip. Because of the data and image content types, flicker filtering and overscan compensation are not necessary in this case. Illustrations showing the before and after effects of overscan compensation can be found in Figures 1-9 and 1-10.
Figure 1-9. Windows Desktop Image From Encoder Without Overscan Compensation
Active Viewable Area with no Vertical Overscan Compensation * a number of active lines are hidden behind TV's bezel
Active Viewable Area with no Horizontal Overscan Compensation * a number of active pixels are hidden behind TV's bezel
NOTE(S): Overscan percentages taken from CX25870's Autoconfiguration Mode 0.
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Figure 1-10. Windows Desktop Image From CX25870 With Overscan Compensation
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13.58 % / 2 = 6.79 % Blanking on Each Side of TV
13.78 % / 2 = 6.89 % Blanking on Each Side of TV
NOTE(S): Overscan percentages taken from CX25870's Autoconfiguration Mode 0.
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In Figure 1-10, the CX25870 overscan compensated the 640 horizontal active pixels of data to fit within the viewable video region. With 13.78 percent HOC, the active data is contained within a 45.397 s. portion of time within each active line while the remaining 7.26 s (52.65556 s.-45.397 s.) part of the active region is blanked by the encoder. The net result of overscan compensation will be an interlaced NTSC, PAL, or SECAM video image that fits within the bezel area of a TV Monitor. Correct choice of the HOC and Vertical Overscan Compensation (VOC) percentages is important so that no regions of the active input image will be hidden behind the plastic of the TV unit. Various TVs require different HOC and VOC values to fully utilize the entire viewable area of the TV For the user's convenience, . Conexant has generated Appendix A in the CX25870/871 datasheet which lists many of the possible overscan ratios for the 3 major desktop resolutions (640x480, 800x600, and 1024x768) and the 2 most popular video outputs (NTSC and PAL-BDGHI). Varying amounts of blanking would be required depending on the HOC and VOC percentages and active input resolutions. Ultimately, the blanked regions would be dictated by the BLANK* signal itself and/or the internal pixel counter for the CX25870/871. Actual transmission of null or blanked pixels is not necessary since the encoder ignores any data sent to it via the pixel input port within the blanked regions. Only the active pixels need to be sent to the encoder from the controller during the digital active period.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figures A-1 through A-8 illustrate many of the allowable overscan compensation percentage pairs for the major desktop resolutions and the most popular video outputs. These figures illustrate the minimum horizontal blanking times the data master must possess along with overscan compensation plots for pixel based data masters as well as 8-and 9-cycle character clock based graphics controllers.
1.3.18 Standard Flicker Filtering
To understand what flicker filtering is, one must understand two of the primary differences between the analog video standards used by TVs and the technology used in today's computer monitors. First of all, computer monitors receive their video signal in a more basic, pristine form than TVs do. As discussed earlier, the video signal sent by a computer to its monitor is broken into multiple electrical components (red, green, blue and sync) while a TV signal has all necessary information combined into a single composite signal or separate Luma and Chroma analog channels (S-Video). In order to process this composite signal, a TV must break it up into its original components, inevitably degrading the picture quality and creating distortions. A second factor contributing to the decreased quality of images displayed on TV monitors is interlacing, a technique by which a complete TV picture is drawn in two passes from top to bottom on the picture tube. In interlacing, the first pass paints all the "odd" lines and the second pass paints the "even" lines. Noticeable flicker occurs when the images in the odd lines are very different from the images in the even lines. As the odd and even lines are alternately displayed, the eye perceives the quick appearing and disappearing of visual information. This results the in the irritation called flicker. Flicker is especially noticeable when viewing thin horizontal lines that only take up a single row within the odd or even field. If, for example, the line happens to be on an odd row, it totally disappears every time the even rows are displayed resulting in that item appearing and disappearing at the field rate on the TV . Unlike TV monitors, computer monitors paint an entire image in one pass from top to bottom, in a display format called noninterlaced or progressive. Images displayed in a noninterlaced format do not suffer from the same flicker problems. For improved image quality and reduced flickering, the CX25870 contains a 5-tap or 5-line flicker filter for both the Luma (F_SELY[2:0]) channel and Chroma (F_SELC[2:0]) channel. The Conexant standard flicker-filter works by applying a mathematically weighted averaging algorithm to the incoming pixels of data from different lines. This slightly alters the digital information that is processed and eventually converted to the odd and even lines of a TV picture so that the alternating lines are more similar to each other. This way, when they appear and disappear in the interlacing process, the flicker is less noticeable. The more similar the lines are made to appear, the less flicker is visible.
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However, the trade-off is that as flicker is reduced, more and more information is being altered by the encoder and potentially lost from the original picture. Vertical resolution is therefore sacrificed and text clarity suffers especially for small fonts below 10 points in size. For this reason, the amount of flicker filtering is programmable and should be controllable by the end user. Finding an optimal standard flicker filter setting for Luma and Chroma is somewhat subjective in nature and ensures that a pleasing image is seen on the television. Unlike other encoders, the CX25870 integrates both a standard flicker filter and additional adaptive flicker filter. This implementation allows for the preservation of small font text clarity and other challenging video images lost with only one filtering step. The adaptive feature eliminates more flicker with less loss of resolution because it is able to selectively apply more aggressive flicker reduction only to those portions of an image where the effect will be beneficial. Encoders lacking this adaptive filter apply the standard flicker filtering process to the entire screen. Small text and icons often become unreadable and thin, horizontal lines may completely disappear. The CX25870's adaptive flicker filter prevents this from happening and is described in its own section within this document. So long as progressive RGB or YCrCb data is received, the CX25870's flicker filter is effective with any active resolution from 320x200 to a maximum of 1024 x 768. The flicker reduction is present on any interlaced video output such as NTSC, PAL, or SECAM. The DIS_FFILT register bit turns off the standard flicker filter. The vertical scaling can be disabled by setting the internal V_SCALE register to 4096 for a noninterlaced input. Finally, the CX25870 supports up to 24-bit color processing, meaning that the converted image will feature the same depth of color as the original computer picture.
1.3.19 Adaptive Flicker Filter
Adaptive Flicker Filtering is a new feature included with the CX25870/871. It allows the encoder to automatically alter the amount of flicker filtering based on the image being processed. The result is a high-quality optimized image because the perfect balance between vertical resolution and flicker reduction has been achieved. The adaptive flicker filter is enabled via the ADPT_FF bit. There are four possible settings ranging from 2-line (most observable flicker, greatest vertical resolution) to 5-line (minimal observable flicker, moderate vertical resolution). The luminance and chrominance outputs are independent in terms of the level of adaptive flicker filtering. When the adaptive flicker filter is on, the manual flicker filter is off and vice versa. Vertical filtering in the CX25870/871 serves three purposes: * Vertical polyphase interpolation filtering to upsample the image data vertically. This increases the resolution and accuracy of the subsequent vertical downsampling required to fit the entire image into the visible region of the television. Anti-alias filtering to reduce aliasing artifacts when downsampling vertically. Flicker filtering to reduce the flicker produced when vertical high frequency content is displayed on an interlaced device.
* *
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
The vertical interpolation filtering and vertical anti-alias filtering requirements are driven by the amount of vertical down scaling required, and do not vary substantially with image content. The flicker filtering requirement, however, is dependent upon the image content. Regions of the image with vertical high frequency content will flicker in proportion to the amplitude of that high frequency content. Regions with high amplitude vertical high frequency content require substantial flicker filtering, but regions with low amplitude or no vertical high frequency content require little or no flicker filtering. For this reason, the CX25870/871 provides adaptive flicker filtering. It analyzes the image content to detect areas that require strong flicker filtering, and adjusts its vertical filtering to apply stronger flicker filtering to those regions. This analysis and adjustment occurs on a pixel by pixel basis, so each pixel in the output line has the optimal amount of flicker filtering applied to it. The Adaptive_FF1 and Adaptive_FF2 registers (0x34 and 0x36) configure the adaptive algorithm. The Y_ALTFF[1:0] and C_ALTFF[1:0] fields allow the selection of the alternative (i.e., stronger) flicker filter to combine with the standard flicker filter selected by fields F_SELY[1:0] and F_SELC[1:0] (register 0xC8). This creates an array of flicker filters for the Y channel and C channel respectively. The actual flicker filter applied for a given pixel output depends on the detection and location of any high amplitude vertical high frequency content within the input samples that creates that output pixel. The amplitude of the high frequency content that triggers an adaptation of the flicker filter can be adjusted via the Y_THRESH[2:0] and C_THRESH[2:0] bit fields. The FFRTN bit offers two ways to combine the standard and alternate flicker filters to generate an array of flicker filters. The YSELECT bit allows the Chroma channel flicker filter to be adapted based on the Chroma channel or the Y (i.e., Luminance) channel content.
NOTE:
Neither standard nor adaptive flicker filtering is supported by the CX25870/871 in noninterlaced video output formats (VGA style RGB, HDTV 480p, 720p).
Table 1-16 summarizes recommended configurations of the adaptive flicker filter for various types of image content and resolutions.
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Table 1-16. Optimal Adaptive and Standard Flicker Filter Settings for Common PC Applications and Resolutions CX25870 Adaptive FF settings
ADPT_FF On=Checked On=Checked On=Checked On=Checked On=Checked On=Checked ADPT_FF On=Checked On=Checked On=Checked ADPT_FF Y_ALTFF C_ALTFF Y_THRESH C_THRESH 5-line 5-line 110 110 On Y_SELECT 5-line 5-line 010 010 Off 4-line 4-line 100 100 Off Off Off Off FFRTN Y_ALTFF C_ALTFF Y_THRESH C_THRESH Y_SELECT FFRTN 5-line 5-line 110 110 On Off 1 BYYCR 1 1 1 BYYCR 5-line 5-line 110 110 On Off 1 0 0 CHROMA_BW 0 0 0 CHROMA_BW 5-line 5-line 010 010 On On 1 0 5-line 5-line 010 010 Off On 1 0 80 80 80 80 Final Hex Value 9B 80 80 Final Hex Value Off 100 On On Off 1 1 0 0 9B 80 4-line 4-line 100 100 On On 1 0 9B 4-line 4-line 000 000 On On 1 0 9B Y_ALTFF C_ALTFF Y_THRESH C_THRESH Y_SELECT FFRTN BYYCR CHROMA_BW Final Hex Value
100381B Register 0x34 Register 0x36
Final Hex Value C0 E4 92 D2 F6 F6 Final Hex Value 24 12 F6 Final Hex Value 92 64 On=Checked On=Checked 5-line 5-line 100 4-line 4-line 010 010
Standard FF settings
CX25870/871
Desktop Resolution/ Video Output Type
FSEL_Y
FSEL_C
640x480 in, NTSC out
3-line
3-line
640x480 in, PAL-BDGHI out
3-line
3-line
800x600 in, NTSC out
4-line
4-line
800x600 in, PAL-BDGHI out
4-line
4-line
1024x768 in, NTSC out
5-line
5-line
1024x768 in, PAL-BDGHI out
5-line
5-line
Flicker-Free Video Encoder with Ultrascale Technology
Web Page Resolution/ Video Output Type
FSEL_Y
FSEL_C
Conexant
640x480 in, NTSC out
4-line
3-line
800x600 in, NTSC out
4-line
4-line
1024x768 in, NTSC out
5-line
5-line
Word Processing Resolution/Video Output Type
FSEL_Y
FSEL_C
640x480 in, NTSC out
3-line
3-line
800x600 in, NTSC out
4-line
4-line
NOTE(S): Off means a '0' bit setting while On denotes a '1' bit setting.
1.0 Functional Description
1.3 Device Description
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.20 VGA Registers Involved in the TV Out Process
Timing constraints for the CX25870/871 are driven by the timing requirements of the analog video output (NTSC, PAL, or SECAM) together with the active resolution and overscan compensation ratio (i.e., amount of blanking in the active region) of the television image. To explain what specific CRTC or VGA registers within the graphics controller need to be involved in displaying a nonstandard or desktop format on both a TV and CRT, one can work backwards from those output signal timing requirements to determine the input timing requirements. Each output field has a vertical blanking region and an active region. These regions are defined relative to the vertical sync pulse, horizontal sync pulse, given format (i.e., number of lines per field), and a given pixel clock frequency (i.e., number of pixel clocks per line). Within each line of the active region there is a horizontal blanking period (that includes a horizontal sync pulse) and an active period (where the image data is located). Given those parameters, at least six registers within every generic graphics controller need to be changed for each active/total resolution. Table 1-17 lists VGA/CRTC Registers Involved in TV Out Process.
Table 1-17. VGA/CRTC Registers Involved in TV Out Process Register Name
Start VBLANK/VSYNC* and End VBLANK/VSYNC* VACTIVE VTOTAL HBLANK/HSYNC* Start and HBLANK/HSYNC* End HACTIVE HTOTAL
Description
These VGA registers work in combination with each other to control the scan line at which the vertical blanking period begins and the point at which it ends. Dictates the specific number of active lines for the present digital frame. Specifies the number of scan lines from one VSYNC* active to the next VSYNC* active pulse. The difference between Vtotal and Vactive is the amount of blanked lines. This VGA register set works in combination with each other to control the value of the pixel or character clock counter where the HSYNC* signal becomes active and the position at which HSYNC* becomes inactive. Dictates the specific number of active pixels per line. Specifies the number of pixel clocks or character clocks from one HSYNC* active to the next HSYNC* active pulse. In other words, this is the total time required for both the displayed and nondisplayed portions of a single scan line. The difference between Htotal and Hactive is the amount of blanked pixels per line.
To achieve VGA compatibility, the controller must manipulate some of its own VGA register settings in order to produce a hi-quality dual display on both the computer monitor and TV It should be noted that the encoder has no way of . knowing that a different VGA mode has been selected. As a result, it relies on the I2C(R)-compatible master device to reconfigure it via an autoconfiguration mode or complete register rewrite to make adjustments in its timing. When the two devices are programmed correctly, regardless of the interface, the required input HSYNC*/VSYNC* to first input active pixel or line spacing "matches" the output HSYNC*/VSYNC* to first output active pixel or line spacing. When this occurs, the graphics controller always transmits active data at the time the CX25870/871 expects to receive it. Superior TV Out quality is achieved only when this type of timing symmetry exists.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
1.3.21 Output Modes
The encoder can generate output video as Composite/Y-C(S-Video), YUV , component, VGA-style RGB, SCART, Component (YPRPB) for HDTV or RGB for HDTV. These outputs are selected by the OUT_MODE[1:0] register bits in combination with the HDTV_EN and EN_SCART bits. While the encoder is in VGA style RGB, no color space conversion is possible from input to output. Analog RGB is transmitted from a digital RGB input and analog YCrCb is output from a digital YCrCb input. When outputting RGB with HDTV_EN = 0, the device outputs VGA/SVGA analog RGB with a bilevel sync. In this mode, the R, G, and B input data is fed to the DACs after the addition of the horizontal sync and, if the SETUP bit is one, the setup pedestal is added. The output currents are scaled so that the DACs output the proper 1 V full-scale (sync tip to peak white) levels for driving a CRT monitor. The graphics controller must provide all the timing control (HSYNC and VSYNC signals) for the monitor, which results in the encoder operating as a slave in this case. Only the P[23:0], BLANK*, HSYNC*, and VSYNC* input pins and the RGB analog output pins are active. The BLANK*, HSYNC*, and VSYNC* pins are automatically enabled as inputs in this mode. Each of the four video signals generated by the OUT_MODE[1:0] field can be multiplexed to any DAC using the OUT_MUXA[1:0], OUT_MUXB[1:0], OUT_MUXC[1:0], and OUT_MUXD[1:0] register bits. To do this, program the 2-bit value representing the desired type of output into the appropriate OUT_MUXx[1:0] register. As an example, suppose a system requires composite video (i.e., 00) to be output from DAC_A, chroma (10) on DAC_B, luma (01) on DAC_C, and composite video (00) on DAC_D. This scheme could be accomplished by programming register 0xC6 with 0001 1000 binary or 18 hex. The LUMADLY[1:0] register bits control the amount of delay for the Y_DLY analog output. The allowable delay ranges from 0 (no delay) to 3 pixel clocks. All digital-to-analog converters are designed to drive standard video levels into a combined RLOAD of 37.5 (doubly-terminated 75 loads). Unused outputs should be disabled by setting the corresponding DACDISx bit to minimize the supply current or left as a no connect. Disabling unused DAC outputs reduces cross chroma distortion and improves picture quality.
1.3.22 Analog Horizontal Sync
The HSYNC_WIDTH[7:0] register determines the duration of the horizontal sync pulse. The beginning of the horizontal sync pulse corresponds to the reset of the internal horizontal pixel counter. The horizontal line rate is determined by H_CLKO[11:0]. The internal horizontal counter is reset to 1 at the beginning of the horizontal sync and counts up to H_CLKO. The sync rise and fall times are automatically controlled. The sync amplitude is programmable over a range of values by SYNC_AMP[7:0]. Incrementing the sync amp by 1 increases the sync amplitude of the analog sync pulse by 30 millivolts.
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.23 Analog Vertical Sync
The analog vertical sync duration is selectable as either 2.5 or 3 lines by register bit VSYNC_DUR. If VSYNC_DUR = 1, 3 lines are selected; if VSYNC_DUR = 0, 2.5 lines are selected. The device automatically blanks the video from the start of the horizontal sync interval through the end of the burst, as well as the vertical sync to prevent erroneous video timing generation.
1.3.24 Analog Video Blanking
Analog video blanking is controlled by the H_BLANKO, V_BLANKO, and V_ACTIVEO registers. Together they define an active region where pixels are displayed. V_BLANKO defines the number of lines from the leading edge of the analog vertical sync to the first active output line per field. V_ACTIVEO defines the number of active output lines. H_BLANKO defines the number of output pixels from the leading edge of horizontal sync to the first active output pixel. H_ACTIVE defines the number of active output pixels. The device automatically blanks video from the start of the horizontal sync interval through the end of the burst, as well as the vertical sync interval to prevent erroneous video timing generation.
1.3.25 Video Output Standards Supported
There are several bits (625LINE, SETUP, VSYNC_DUR, PAL_MD, FM, DIS_SCRST), a PAL pin, and various autoconfiguration modes, that control the generation of various video standards. (These are summarized in Table 1-18.) They allow the generation of all the different NTSC, PAL, and SECAM video standards. The aforementioned bits control the specific encoding process parameters. It is likely other registers may need to be modified to meet all the video parameters of the particular video standard. Video timing diagrams are illustrated in Figures 1-11 through 1-22. These show typical events that occur for each type of video format.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
Table 1-18. Important Bit Settings for Various Video Outputs
Video Output Bit NTSC-M NTSCJapan PALBDGHI PAL-N PAL-Nc PAL-M PAL-60 SECAMSECAMSECAM-L(1) B, G, H(3) D, K, K1(2)
VSYNC_DUR 625LINE SETUP PAL_MD DIS_SCRST FM
NOTE(S):
(1) (2)
1 0 1 0 0 0
1 0 0 0 0 0
0 1 0 1 0 0
1 1 1 1 0 0
0 1 0 1 0 0
1 0 1 1 0 0
1 0 0 1 0 0
0 1 0 0 1 1
0 1 0 0 1 1
0 1 0 0 1 1
SECAM-L used primarily in France. SECAM-D, K, K1 used primarily in Russia and Eastern European nations. (3) SECAM-B, G, M used primarily in the Middle East. (4) Other CX25870 registers and bits must be reprogrammed to generate different video outputs. The bits in Table 1-18 are the most important settings.
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-11. Interlaced 525-Line (NTSC) Video Timing
RESET* Start of VSYNC
Analog FIELD 1
523
524
525
1
2
3
4
5
6
7
8
9
10
22
BURST PHASE Analog FIELD 2
261
262
263
264
265
266
267
268
269
270
271
272
285
Analog FIELD 3
523
524
525
1
2
3
4
5
6
7
8
9
10
22
BURST PHASE Analog FIELD 4
261
262
263
264
265
266
267
268
269
270
271
272
285
Burst Begins with Positive Half-Cycle Burst Phase = Reference Phase = 180 Relative to B-Y Burst Begins with Negative Half-Cycle Burst Phase = Reference Phase = 180 Relative to B-Y
Note(s): SMPTE line numbering convention is used rather than CCIR624.
100381_006
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100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-12. Interlaced 525-Line (PAL-M) Video Timing
1.0 Functional Description
1.3 Device Description
RESET* Start of VSYNC*
Analog FIELD 1
523
524
525
1
2
3
4
5
6
7
8
9
10
11
12
22
Burst Phase Analog FIELD 2
261
262
263
264
265
266
267
268
269
270
271
272
273
274
285
Analog FIELD 3
523
524
525
1
2
3
4
5
6
7
8
9
10
11
12
22
Burst Phase Analog FIELD 4
261
262
263
264
265
266
267
268
269
270
271
272
273
274
285
Burst Phase = Reference Phase = 135 Relative to U PAL Switch = 0, +V Component Burst Phase = Reference Phase + 90 = 225 Relative to U PAL Switch = 1, -V Component
100381_007
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Conexant
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-13. Interlaced 625-Line (PAL-B, D, G, H, I, Nc) Video Timing (Fields 1-4)
RESET*
Start of VSYNC Analog FIELD 1
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
- U PHASE Analog FIELD 2
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog FIELD 3
620
621
622
623
624
625
1
2 Analog FIELD 4
3
4
5
6
7
23
24
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
FIELD One Burst Blanking Intervals FIELD Two FIELD Three FIELD Four
Burst Phase = Reference Phase = 135 Relative to U PAL Switch = 0, +V Component Burst Phase = Reference Phase + 90 = 225 Relative to U PAL Switch = 1, -V Component
100381_008
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-14. Interlaced 625-Line (PAL-B, D, G, H, I, Nc) Video Timing (Fields 5-8)
RESET* Start of VSYNC Analog FIELD 5
1.0 Functional Description
1.3 Device Description
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
- U PHASE Analog FIELD 6
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog FIELD 7
620
621
622
623
624
625
1
2 Analog FIELD 8
3
4
5
6
7
23
24
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
FIELD Five Burst Blanking Intervals FIELD Six FIELD Seven FIELD Eight
Burst Phase = Reference Phase = 135 Relative to U PAL Switch = 0, +V Component Burst Phase = Reference Phase + 90 = 225 Relative to U PAL Switch = 1, -V Component
100381_009
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Conexant
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-15. Interlaced 625-Line (PAL-N) Video Timing (Fields 1-4)
VSYNC*
Analog FIELD 1 RESET*
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
- U PHASE Analog FIELD 2
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog FIELD 3
620
621
622
623
624
625
1
2 Analog FIELD 4
3
4
5
6
7
23
24
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
FIELD One Burst Blanking Intervals FIELD Two FIELD Three FIELD Four
Burst Phase = Reference Phase = 135 Relative to U PAL Switch = 0, +V Component Burst Phase = Reference Phase + 90 = 225 Relative to U PAL Switch = 1, -V Component
1000381_010
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-16. Interlaced 625-Line (PAL-N) Video Timing (Fields 5-8)
1.0 Functional Description
1.3 Device Description
VSYNC* Analog FIELD 5
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
- U PHASE Analog FIELD 6
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog FIELD 7
620
621
622
623
624
625
1
2 Analog FIELD 8
3
4
5
6
7
23
24
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
FIELD Five Burst Blanking Intervals FIELD Six FIELD Seven FIELD Eight
Burst Phase = Reference Phase = 135 Relative to U PAL Switch = 0, +V Component Burst Phase = Reference Phase + 90 = 225 Relative to U PAL Switch = 1, -V Component
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-17. Noninterlaced 262-Line (NTSC) Video Timing
START of VSYNC
261
262
1
2
3
4
5 FIELD 1
6
7
8
9
10
21
Burst Begins with Positive Half-Cycle Burst Phase = Reference Phase = 180 Relative to B-Y Burst Begins with Negative Half-Cycle Burst Phase = Reference Phase = 180 Relative to B-Y
100381_012
Figure 1-18. Noninterlaced 262-Line (PAL-M) Video Timing
START of VSYNC
261
262
1
2
3
4
5 FIELD 1
6
7
8
9
10
11
12
21
Burst Begins with Positive Half-Cycle Burst Phase = Reference Phase = 180 Relative to B-Y Burst Begins with Negative Half-Cycle Burst Phase = Reference Phase = 180 Relative to B-Y
100381_013
Figure 1-19. Noninterlaced 312-Line (PAL-B, D, G, H, I, N, Nc) Video Timing
RESET* Start of VSYNC
308
309
310
311
312
1
2
3
4
5
6
7
23
24
Burst Phase = Reference Phase = 135 Relative to U PAL Switch = 0, +V Component Burst Phase = Reference Phase + 90 = 225 Relative to U PAL Switch = 1, -V Component
100381_014
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-20. Interlaced 625-Line (SECAM-B, D, G, K, K1, L, M) Video Timing (Fields 1-4)
1.0 Functional Description
1.3 Device Description
RESET* Start of VSYNC End of the preceding 4-field sequence
621 622 623 624 625 1
Analog FIELD 1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Analog FIELD 2
DRDB
DR
309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336
DRDB
Analog FIELD 3
1 2 3 4 5 6 7
DBDR
DB
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
621 622 623 624 625
8
DBDR
Analog FIELD 4
DR
DB
309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336
DR
DRDB
DR
NOTE(S): 1. DR and DB color subcarrier signal sequences over four consecutive fields shown above. 2. DR color subcarrier frequency is 4.406250 MHz. 3. DB color subcarrier frequency is 4.250000 MHz.
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.26 Subcarrier Generation
The device uses a 32-bit-word to synthesize the subcarrier. The value of the subcarrier increment required to generate the desired subcarrier frequency is found with the following equations: NTSC: MSC[31:0] = int((455/(2*H_CLKO)) *232 + 0.5) PAL: MSC[31:0] = int((1135+1/625)/H_CLKO)*232 + 0.5 SECAM: MSC_DB[31:0] = int((272/(2*H_CLKO)*232 + 0.5) MSC_DR[31:0] = int((272/(2*H_CLKO)*232 + 0.5) where:H_CLKO is the number of output clocks/line (this is register 0x76 and the low nibble of 0x86). This allows the generation of any desired subcarrier for any desired video standard. The 32-bit subcarrier increment must be loaded by the serial interface before the subcarrier is enabled. The device is reset to disable chroma until the last byte of the 32-bit increment loads, at which time the chroma is enabled, unless the DCHROMA bit is set. In order to prevent any residual errors from accumulating, the subcarrier DTO (Discrete Time Oscillator) is reset every four fields for NTSC formats and every eight fields for PAL formats. For best quality in SECAM, the DIS_SCRST bit should be set preventing a subcarrier phase reset at the beginning of each color field sequence. Furthermore, the SECAM subcarrier is generated on lines 23-310 and 336-623 automatically unless disabled by the PROG_SC bit.
1.3.27 Subcarrier Phase Reset/Offset
In order to maintain correct SC-H phasing, the subcarrier phase is set to 0 degrees on the leading edge of the analog vertical sync every four (NTSC) or eight (PAL) fields, unless the DIS_SCRST (bit four of register 0xA2) is set to a logical 1. This is true for both interlaced and noninterlaced outputs. The subcarrier phase can be adjusted from the nominal 0 degrees phase by the PHASE_OFF[7:0] register, where each LSB change corresponds to a 360/256 = 1.406 degrees change in the phase. Setting DIS_SCRST to 1 may be useful in situations where the ratio of CLK/2 to HSYNC* edges in a color frame is noninteger, which could produce a significant phase impulse by resetting to 0.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
1.3.28 Burst Generation
The subcarrier burst generation is a function of the video standard (e.g., NTSC, PAL, or SECAM), the subcarrier frequency increment (MSC[31:0]), and the burst horizontal begin and end register settings (HBURST_BEGIN[7:0] and HBURST_END[7:0]). To calculate the value of HBURST_END[7:0] subtract 128 from the desired location in clock cycles. The burst will automatically be blanked during the horizontal sync preventing invalid sync pulses from being generated. Burst blanking is automatically controlled by the selected video format. Burst rise and fall times are automatically generated by the device. The burst amplitude is programmed by the BST_AMP[5:0] field.
1.3.29 Video Amplitude Scaling and SINX/X Compensation
Both the luminance and chrominance video amplitudes can be scaled by the MCR, MCB, and MY registers. This allows various colormetry standards to be achieved, and can also be used to boost the chroma to compensate for the sin x/x loss of the DACs. Appendix A show the range of values achievable and values for various video formats. The DAC output response is a typical sinx/x response. For the composite video output, this results in a slightly lower than desired burst and chroma amplitude value. This is compensated for, to some extent, by choosing an output filter that boosts the frequency response slightly. Another method which can be used effectively, and is used by default in the auto configuration modes, is to boost the burst and chroma gain as programmed by the BST_AMP and MCR/MCB register values by a factor of(x/sinx). The amount of sinx/x amplitude reduction is calculated by: sinx/x = sin ( * Fsc/Fclk) / ( * Fsc/Fclk) Fsc = desired subcarrier burst frequency Fclk = present input clock frequency
1.3.30 Chrominance Disable
The chrominance subcarrier can be turned off by setting the DCHROMA bit to a logical 1. This disables the subcarrier burst as well, providing luminance-only signals on the CVBS output and a static blank level on the chrominance output.
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.31 FIELD Pin Output
Like its predecessor, the Bt868/869, the CX25870/871 includes a FIELD pin output. This signal is output only and is accessed through pin #37. The frequency of the FIELD pin is 30 Hz during an NTSC video output, and 25 Hz throughout a PAL or SECAM video output. The only programming step required to obtain the FIELD output is to serially write the EN_OUT bit to 1. The purpose of this signal is to provide a digital TTL compatible output which tracks the analog interlaced field presently being transmitted by the CX25870/871 DACs. The peak-to-peak amplitude of this output will be from 0 V to the level present on the VDD_CO and VDDL pins. If these pins are tied to 3.3 V then the , FIELD high state is transmitted at a 3.3 V level. If these pins are tied to 1.8 V or lower voltage, then the FIELD high state is transmitted at a 1.8 V or lower level. The logical 0 level from FIELD will always be GND/VSS regardless of the logical 1 voltage. The FIELD output transitions after the rising edge of CLKI, two clock cycles following the leading edge of the digital HSYNC* input or output. Figure 1-21 shows the relationship between the FIELD and Composite (CVBS) outputs and VSYNC* input for NTSC. Figure 1-22 illustrates this same relationship for PAL.
Figure 1-21. FIELD Pin Output Timing Diagram (NTSC-M, J, 4.43)
RESET* Start of Analog FIELD 1 = ODD VSYNC*
Composite Output
523 524 525 1 2 3 4 5 6 7 8 9 10 22
FIELD Pin Output
Analog FIELD 2 = EVEN
Composite Output
261 262 263 264 265 266 267 268 269 270 271 272 285
FIELD Pin Output *FIELDI Bit = 0
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
Figure 1-22. FIELD Pin Output Timing Diagram (PAL-B, D, G, H, I, N, Nc)
RESET*
Start of VSYNC* Analog FIELD 1
Composite Output
620 621 622 623 624 625 1 2 3 4 5 6 7 23 24
FIELD Pin Output
Analog FIELD 2
Composite Output
308 309 310 311 312 313 314 315 316 317 318 319 320 336 337
FIELD Pin Output *FIELDI Bit = 0
100381_095
By default, the internal FIELDI bit will be 0 which forces the CX25870 to transmit a logical 1 during transmission of an EVEN field and logical 0 for the period of an ODD field. To change the FIELD polarity, reprogram the FIELDI bit. If the CX25870/871 is the timing master and sends out HSYNC* and VSYNC*, then after a power-on, pin, or timing reset (setting of bit 7, register 0x6C), the encoder and the flicker filter portions of the device start at line 1, pixel 1 of their respective timing generation. For the CX25870/871, this means the ODD field is always the first field conveyed after a power-on reset, pin reset, or timing reset. When the CX25870 receives an interlaced data format, its FIELD pin represents only the output field presently being generated by the on-chip DACs. When the CX25870 receives progressive (i.e., noninterlaced) frames which have no field associated with it, the CX25870's input timing generator still keeps track of frames received. As a result, after the entire second frame has been received, the input and encoder sections become resynchronized. This re-synchronization is done through an internal frame sync signal. This action, in turn, forces the CX25870 to the beginning of the odd field and changes the FIELD pin back to its odd state. If the CX25870/871 is the timing slave (i.e., it accepts HSYNC* and VSYNC*) receiving a power-on reset, pin reset, or timing reset (register 0x6C, bit 7) causes the input timing generator to send the encoder the aforementioned frame sync. This sets the encoder to the beginning of the odd field which is denoted through the FIELD pin. The first digital HSYNC* and VSYNC* combination then corresponds to the encoder's EVEN output field. The second digital HSYNC* and VSYNC* combination will again cause a frame sync and the encoder will start sending the ODD field both from its DACs and FIELD pin. This ODD-EVEN-ODD-EVEN ... field sequence continues indefinitely.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.32 Buffered Crystal Clock Output
The buffered crystal clock output (XTL_BFO) pin provides a buffered output (0 V to 3.3 V peak-peak) of whatever frequency is found between the CX25870's XTALIN and XTALOUT pins. This signal can then be used as a much more accurate input clock to the graphics controller because controllers typically utilize clock sources with errors between 75-150 ppm. This implementation ultimately results in better VGA picture quality because the clock driving the data master is within the same tolerance (i.e., 25 ppm) as the TV Out encoder. This can also lead to a considerable savings in cost, component count, and PC board space because the crystal attached to the data master has been completely eliminated. On power-up, the encoder will transmit a 0 to 3.3 V signal at a frequency equal to the frequency of the crystal found between the XTALIN and XTALOUT ports. The tolerance of the XTL_BFO signal will match the tolerance found within the encoder's crystal. The CX25870 was designed to expect a 13.500 MHz 25 ppm crystal. As a result, all the PLL_INT and PLL_FRACT register values found within each CX25870 autoconfiguration mode possess this set of default values. The CX25870 does have the flexibility to support an alternate 14.31818 MHz crystal with a tolerance of 25 ppm. To switch the encoder to operate with this crystal frequency, install an appropriate crystal and crystal circuit between the XTALIN and XTALOUT ports and set the 14318_XTAL bit to 1. Enabling this bit translates the 13.500 MHz-dependent auto configuration registers to their new 14.31818 MHz settings. For CX25870 designs, a small (e.g., 33 ) series resistor should be added to XTL_BFO, as close as possible to the signal source device. This reduces overshoot and undershoot on this signal as it changes states. The buffered crystal clock output pin should be floated if not used. Disabling the XTL_BFO pin is possible through the XTL_BFO_DIS bit.
1.3.33 Noninterlaced Output
When the CX25870/871 is programmed for noninterlaced video out via the NI_OUT bit, it always transmits the odd field. The FIELD pin will continue to change state on the leading edge of the analog vertical sync. A 30 Hz offset should be subtracted from the color subcarrier frequency while in NTSC mode so that the color subcarrier phase is inverted from field to field. The transition from interlaced to noninterlaced in master interface occurs during odd fields to prevent synchronization disturbance.
NOTE:
Consumer VCRs can record noninterlaced video with minor noise artifacts, but special effects (e.g., scan >2x) may not function properly.
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Flicker-Free Video Encoder with Ultrascale Technology
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1.3 Device Description
1.3.34 Closed Captioning (CC)
The CX25870/871 encodes NTSC/PAL-M closed captioning on scan line 21, and NTSC/PAL-M extended data services on scan line 284. Four 8-bit registers (CCF1B1, CCF1B2, CCF2B1, and CCF2B2) provide the data while bits ECCF1 and ECCF2 enable display of the data. A logical 0 corresponds to the blanking level of 0 IRE, while a logical 1 corresponds to 50 IRE above the blanking level. Closed captioning for PAL-B, D, G, H, I, N, Nc is similar to that for NTSC. Closed-caption (CC) encoding is performed for 625-line systems according to the system proposed by the National Captioning Institute; clock and data timing is identical to that of NTSC system, except that encoding is provided on lines 22 and 335, for closed captioning and extended data services, respectively. The CX25870/871 generates the clock run-in and appropriate timing automatically. Pixel inputs are ignored during CC encoding. See FCC Code of Federal Regulations (CFR) 47 Section 15.119 (10/91 edition or later) for programming information. The EIA608 standard describes ancillary data applications for Field 2 Line 21 (line 284). When CCF1B2 is written, CCSTAT_O is set; when CCF2B2 is written, CCSTAT_E is set. After the CC bytes for the odd field are encoded, CCSTAT_O is cleared; after the CC bytes for the even field are encoded, CCSTAT_E is cleared. If the ECCGATE bit is set, no further encoding is performed until the appropriate registers are written again; a null is transmitted on the appropriate CC line in that case. If the ECCGATE bit is not set, the user must rewrite the CC registers prior to reaching the CC line; otherwise the last bytes are re-encoded. The CC data bytes are double-buffered to prevent loss of data during the encoding process. Pseudo-code that can be used to create a software function for Closed Caption Encoding is included as Appendix D.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.35 Wide Screen Signaling (WSS)
The CX25870/871 supports the WSS methods outlined in the EIAJ CPR-1204 and ITU-R BT.1119 standards. Three serial interface registers control WSS data insertion. For 525 line NTSC systems, two bits enable the insertion of the WSS bit data on lines 20 and 283. The EWSSF1 register bit controls line 20 and EWSSF2 controls line 283. Twenty bits are used to insert the 14 bits of payload, plus six bits of CRC data. CRC data is not computed and must be inserted by the user. For 625 line PAL and SECAM systems, WSS data insertion is only specified for line 23. In this case, the EWSSF1 register enables WSS data insertion on line 23 and EWSSF2 is ignored. Only 14 bits of payload are specified for 625 line PAL and SECAM systems. No CRC is generated, therefore bits WSSDAT[20:15] are ignored in these systems. WSSINC[19:0] specifies the incremental value of the PQ ratio counter to generate the desired WSS waveform. The increment value is found by: 525 line: WSSINC[19:0] = 220 / (2.234*10-6*Fclk) 625 line: WSSINC[19:0] = 220 / (200*10-9*Fclk) where:Fclk = CLKI frequency = CLKO frequency. Figure 1-23 illustrates a typical WSS signal, where WSSDAT[14:1] = 0x00.
NOTE:
WSS uses biphase coding of its data bits. The amplitude of the WSS pulses is 500 mV above black when high and black when low. For further WSS details, see specification ETS 300294 or ITU-R BT.1119.
Figure 1-23. Typical WSS Analog Waveform (NTSC)
0.5 V
0.0 V
Run-In 5.86 s (NTSC)
Start Code
Bit 14 14 Data Bits
Bit 1
NTSC: Field 1, Line 20 Field 2, Line 20 PAL: Field 1, Line 23
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Flicker-Free Video Encoder with Ultrascale Technology
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1.3 Device Description
The CX25870 does not support the CGMS/A standard for analog PAL or analog NTSC video systems. CGMS stands for Copy Generation Management System whereby scan line 23 of PAL Field 1 or lines 20 and 283 of NTSC video outputs contains a data burst which details the signal format. The burst also specifies the aspect ratio, type of enhanced services, and subtitle location for the TV to use during the broadcasted show. In addition to the details about the signal format, the CGMS bits can indicate whether a recording device can make no copies, one copy, or unlimited copies. If no copies are allowed, the recording device will not make a copy. If a single copy is allowed, the recording device will make one copy and change the CGMS data to indicate that no future copies can be made from the native content. The major reasons the CX25870 does not support the analog method of CGMS/A are as follows: * No movie studio even considers the notion of allowing the user to make a single copy. All DVDs released from the movie industry now enable the Macrovision copy protection system so it is impossible to make any copies of DVDs in the analog domain. There are no plans for DVD content providers to allow users to make limited copies of their intellectually copyrighted material. Some aspects of the CGMS/A system are not pirate-proof and can be disabled remotely. The CGMS/A standard appears to be a vendor rather than a DVD consortium mandate. Only a few DVD players have this feature now, and it is expected that they will abandon this as newer versions of the Macrovision standard are released or a tamper-proof version of CGMS exists.
* * *
1.3.36 Chrominance and Luminance Processing
Once the input data is converted to internal YUV format, the Y and UV components are filtered and upsampled to the system clock frequency. The luminance signal is always low-pass filtered using the upsampling filter response illustrated in Figure 1-24. Additional peaking or reduction filters can be enabled (see Figures 1-25, 1-26, and 1-27), using the PKFIL_SEL[1:0] register field. The peaking filters are optimized for high bandwidth frequency response, and optimal picture quality. The default chrominance filter response is illustrated in Figure 1-28, but an alternate wide bandwidth response can be selected using register bit CHROMA_BW, as illustrated in Figure 1-29. Figure 1-30 illustrates the SECAM pre-emphasis filter response for the modulated chrominance signal.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-24. Luminance Upsampling Filter
0 -10 -20 Amplitude in dB -30 -40 -50 -60 -70 -80
0
2
4
6 8 Frequency in MHz
10
12
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Figure 1-25. Text Sharpness (Luminance Upsampling) Filter with Peaking Options
0
PKFIL_SEL=11
-10
Amplitude in dB
PKFIL_SEL=00
-20
-30
-40
-50 -60
0
2
4
6 8 Frequency in MHz
10
12
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Figure 1-26. Close-Up of Text Sharpness (Luminance Upsampling )Filter with Peaking and Reduction Options
0
Amplitude in dB
-5
-10
-15
-20
0
1
2
3 4 5 Frequency in MHz
6
7
8
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
Figure 1-27. Zoom-In of Text Sharpness (Luminance Peaking) Filter Options
4 3.5 3 Amplitude in dB 2.5 2 1.5 1 0.5 0
0
1
2
3 4 Frequency in MHz
5
6
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Figure 1-28. Chrominance Filter (CHROMA_BW = 0) - default
0
-10
-20 Amplitude in dB
-30
-40
-50
-60 0 0.5 1 1.5 2 2.5 Frequency in MHz 3 3.5 4
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Figure 1-29. Chrominance Wide Bandwidth Filter (CHROMA_BW = 1)
0
-10
Amplitude in dB
-20
-30
-40
-50
-60 0 1 2 3 4 Frequency in MHz 5 6
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-30. SECAM High Frequency Pre-emphasis Filter
16 14 12
Amplitude in dB
10 8 6 4 2 0 3.5 4 4.5 Frequency in MHz 5
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1.3.37 Color Bar and Blue Field Generation
The CX25870/871 has two internal color bar generators. Preflicker filter color bars are enabled by setting the FFCBAR bit to a logical 1. Postflicker filter color bars are enabled by setting the ECBAR bit to a logical 1.
NOTE:
FFCBAR color bars are optimized for RGB input mode and ECBAR color bars are optimized for YCrCb input mode.
The device uses the H_BLANKO register value to determine the starting point of the color bars, and the H_ACTIVE register value to determine the width. Eight bars are displayed, with the colors and amplitudes being generated internally. The pixel inputs (P23-P0) are ignored in color bar mode. The CX25870/871 must be programmed with the appropriate MY, MCR, and MCB register values for the desired input format, RGB or YCrCb. The CX25870/871 also produces a blue field by setting register bit EBLUE to 1. Pixel inputs are ignored while any of the color generation wave forms are being produced.
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Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
Figure 1-31 and Tables 1-19 and 1-20 illustrate the voltage amplitudes for the different color bar outputs.
Figure 1-31. Composite and S-Video Format (Internal Colorbars)
Magenta
Yellow
Green
White
Myel Mcyn
Awht Mb Async Ayel Acyn
Mgrn Mmgt Mred
Agrn
Amgt
Mblu
Ablk
Composite
Ared Ablu
Awht Ayel Async Acyn Agrn Amgt Ared Ablu Ablk
Y
S Video
Mb Mwht Mblk Myel Mcyn Mgrn Mmgt Mred Mblu Blank Level
C
NOTE(S):
1. Ax is the DC (luminance) amplitude referenced to black, except for Ablk and Async, which are referenced to blank. 2. Mx numbers are the peak-to-peak amplitudes of the subcarrier waveform.
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Table 1-19. Composite and Luminance Amplitude Y and Composite Amplitudes
NTSC-M (volts) NTSC-J (volts) PAL-B (volts)
Async
-0.286 -0.286 -0.300
Awht
0.661 0.714 0.700
Ayel
0.441 0.477 0.465
Acyn
0.347 0.375 0.368
Agrn
0.292 0.316 0.308
Amgt
0.203 0.220 0.217
Ared
0.149 0.161 0.157
Black
Cyan
Blue
Red
Ablu
0.054 0.059 0.060
Ablk
0.0536 0 0
NOTE(S): Ax is the DC (luminance) amplitude referenced to black, except for Ablk and Async, which are referenced to blank.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-20. Composite and Chrominance Magnitude C and Composite Magnitudes
NTSC-M (volts) NTSC-J (volts) PAL-B (volts)
Mb
0.286 0.286 0.300
Mwht
0 0 0
Myel
0.444 0.480 0.470
Mcyn
0.630 0.681 0.663
Mgrn
0.589 0.636 0.620
Mmgt
0.589 0.636 0.620
Mred
0.629 0.681 0.664
Mblu
0.444 0.480 0.470
Mblk
0 0 0
NOTE(S): Mx numbers are the peak-to-peak amplitudes of the subcarrier waveform.
1.3.38 CCIR656 Mode Operation
Data transmitted from MPEG-2 video decoders or various Multimedia Processors is often done in a format called CCIR656. This format is similar to the CCIR601 in many ways but is unique in that the video sync information is embedded as codes in the data stream. As a result, no digital HSYNC or VSYNC signals are required as part of the physical interface between the timing master and slave devices. Applications for CCIR656 typically include consumer appliances such as Video CD players, DVD players, set-top boxes, and MPEG add-in cards where pin counts are limited. The actual digital CCIR656 input data delivered to the CX25870/871 is interlaced 4:2:2 YCrCb over eight physical lines. In addition, there are two timing reference codes, one at the beginning of each video data block (Start of Active Video, SAV) and one at the end of each video data block (End of Active Video, EAV). These timing reference values are digital words consisting of a unique 4-word sequence that conveys when the active video starts and ends. The CCIR656 compliant master device embeds both SAV and EAV codes into the stream where appropriate. While in CCIR656 Mode, the CX25870/871 acts as the Slave device (both clocking and timing). An illustration of this correct connection scheme is shown in Figure 1-32.
Figure 1-32. CX25870/871 Connection to CCIR656-Compatible Master Device
CX25870/CX871 27 MHz Clock MPEG2 Decoder CLKI
Composite #1 Luma
8 4:2:2 YCrCb
P[7:0]
Chroma Composite #2
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Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
While in CCIR656 Mode, the encoder adheres to all input guidelines specified in the ITU-R BT.656-3 standard. This specification was developed for the transmission of color video signals in YCrCb format at a pixel rate of 27.000 MHz without the use of dedicated timing reference signals. To display a DVD movie on a TV and computer monitor simultaneously with high-quality MPEG2 image format, the CX25870/871 must be integrated into the hardware design. Next, actual CCIR656 data must be sent from a MPEG2 decoding master device directly to the CX25870/871 encoder. Finally, various software steps are necessary so the encoder switches to its Slave interface and is set up to accept the interlaced YCrCb data and video timing reference codes. The first programming step is to configure the CX25870/871 to accept interlaced 4:2:2 YCrCb data with an active resolution of 720x480 and output a standard NTSC video output. The pertinent set of conditions for this option are:
* Type of Digital Video Input: * Active Resolution (HorizontalxVertical): * Overscan Compensation: * Interface: * Pixel Rate * Type of Analog Video Output: Interlaced 4:2:2 YCrCb 720 pixels x 480 lines None. Horizontal = 0%; Vertical = 0% CX25870/871 is clock and timing slave 27.000 MHz Standard NTSC[NTSC-M]
Given this set of conditions, autoconfiguration mode 28 is a perfect fit. As a result, simply use the MPEG2 decoders serial bus mastering ability to program the CX25870/871s CONFIG[5:0] field with a binary value of 011100. This translates into writing a hexadecimal number of 0x34 to register 0xB8. Once the encoder acknowledges this write to its autoconfiguration register, it automatically loads the appropriate values for this type of DVD configuration into its register indices from 0x76 to 0xB4, including register 0x38. The exact data transferred into these registers is contained in Appendix C. After completion of the autoconfiguration command, the encoder expects to receive interlaced 4:2:2 YCrCb data from the clock and timing master device at a rate of 27.000 MHz with blanking regions being defined by HSYNC* and VSYNC*. Since these external signals, by definition, do not exist in CCIR656 mode, a second and final programming step is required. After enabling autoconfiguration mode 28, the programmer must make sure to set (=1) the E656 bit. This is bit 6 of register 0xD6 and enables a CCIR656 input to be received via the CX25870/871s P[7:0] port. Once this is done, the encoder deciphers digital blanking through the SAV and EAV codes and disregards the synchronization signals. Only after the completion of these steps will a DVD stream be properly encoded and rendered onto the television by the VGA Encoder. For CCIR Mode operation with a PAL Composite or S-Video output, use Autoconfiguration Mode 29 instead of autoconfiguration mode 28 and program the master device to send a digital frame with an active resolution of 720x576.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.39 CCIR601 Mode Operation for DVD Playback
Data coming from a DVD is decoded by a MPEG2 decoder or graphics controller into a format called CCIR601. CCIR601 is the more common name for 4:2:2 YCrCb data at a 27 MHz pixel rate, as specified in the ITU-R BT.601 standard. This specification was developed specifically for the digitalization of color video signals. To play a DVD movie on a television in addition to a CRT monitor, the CX25870/871, a CCIR601 compatible encoder, must be integrated into the hardware design. Actual CCIR601 data must be sent from a MPEG2 decoding master device directly to the CX25870/871 encoder. This can be either a dedicated MPEG2 decoder chip or a graphics controller with this functionality. Various software steps are necessary so the encoder enters slave or master interface and is set up to accept the interlaced YCrCb data or noninterlaced RGB digital format. After all of these steps have been executed properly, a DVD movie stream is properly encoded and rendered onto the television by the VGA encoder. There are different capabilities among graphics controllers, MPEG2 decoders, and proprietary ASICs that impact the particular DVD implementation. This section seeks to cover all the possible hardware/software configurations and the trade-offs associated with each. If the reader has an interface idea about the routing of data from the CCIR601 source to encoder that is not discussed here, please contact your local Conexant Field Applications Engineer for further technical support. 1.3.39.1 CCIR601 Data In/NTSC Out The first option to playing a DVD movie via the CX25870/871 is to send the digital video CCIR601 data directly to the encoder from the MPEG2 decoder. In this case, the graphics controller does not have any effect on the CCIR601 digital stream arriving at the input of the encoder because it bypassed the data or the data was routed around the controller. In either case, the CX25870/871 must be configured to accept interlaced 4:2:2 YCrCb data with an active resolution of 720x480 and output a standard NTSC video output. The pertinent set of conditions for this option are:
* Type of Digital Video Input: * Active Resolution (HorizontalxVertical): * Overscan Compensation: * Interface: * Pixel Rate * Type of Analog Video Output: Interlaced 4:2:2 YCrCb 720 pixels x 480 lines None. Horizontal = 0%; Vertical = 0% CX25870/871 is clock and timing slave 27.000 MHz Standard NTSC[NTSC-M]
Given this set of conditions, autoconfiguration mode 28 is a perfect fit for this architectural option. As a result, simply use the MPEG2 decoders serial bus mastering ability to program the CX25870/871s CONFIG[5:0] field with a binary value of 011100. This translates into writing a hexadecimal number of 0x34 to register 0xB8. Once the encoder acknowledges this write to its autoconfiguration register, it automatically loads the appropriate value for this type of DVD configuration into its register indices from 0x76 to 0xB4 including 0x38. The exact data transferred into these registers is contained in Appendix C.
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Flicker-Free Video Encoder with Ultrascale Technology
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1.3 Device Description
After completion of the autoconfiguration command, the encoder expects to receive interlaced CCIR601 data from the clock and timing master device at a rate of 27.000 MHz. If this occurs, approximately 40 clocks later (i.e., pipeline delay), the encoder begins transmitting a NTSC-compatible S-Video or Composite Video signal containing the DVD movie. 1.3.39.2 CCIR601 Data In/PAL Out The second option is very similar to the first. In this scenario, the interlaced CCIR601 video data is transmitted directly to the encoder from the MPEG2 decoder. However, instead of generating a NTSC signal, the encoder produces a PAL-BDGHI compatible DVD movie output. The active resolution changes as well for this alternative by increasing to 720x576. To enable DVD playback in this scenario, the CX25870/871 must be configured to accept interlaced 4:2:2 YCrCb data with an active resolution of 720x576 and output a standard PAL video output. The pertinent set of conditions for this option are:
* Type of Digital Video Input: * Active Resolution (HorizontalxVertical): * Overscan Compensation: * Interface: * Pixel Rate * Type of Analog Video Output: Interlaced, 4:2:2 YCrCb 720 pixels x 576 lines None. Horizontal = 0%; Vertical = 0% CX25870/871 is clock and timing slave 27.000 MHz Standard PAL[PAL-BDGHI]
Given this set of conditions, autoconfiguration mode 29 is a perfect fit for this architectural option. As a result, simply use the MPEG2 decoder's serial bus mastering ability to program the CX25870/871s CONFIG[5:0] field with a binary value of 011101. This translates into writing a hexadecimal number of 0x35 to register 0xB8. Once the encoder acknowledges this write to its autoconfiguration register, it automatically loads the appropriate value for this type of DVD configuration into its register indices from 0x76 to 0xB4 including 0x38. The exact data transferred into these registers is contained in Appendix C. After completion of the autoconfiguration command, the encoder expects to receive interlaced CCIR601 data from the clock and timing master device at a rate of 27.000 MHz. If this occurs, approximately 40 clocks later (i.e., pipeline delay), the encoder will begin transmitting a PAL-compliant S-Video or Composite video signal containing the DVD Movie. 1.3.39.3 VGACompatible RGB Data In/NTSC Out The third option for DVD playback is unlike the previous two methods. In this case, the MPEG2 decoder's 4:2:2 YCrCb interlaced data is sent as an input to the graphics controller. In turn, the controller deinterlaces and color space converts the CCIR601 data into a noninterlaced RGB format. The encoder finally ends up receiving this standard VGA digital data from the graphics controllers digital output port for generation into an analog TV signal.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
This design is illustrated in Figure 1-33.
Figure 1-33. DVD Playback Utilizing Graphics Controller for Color-Space and Progressive Scan Conversion
CRT Monitor 100 kbit/s Subpicture Decoder Graphics 20 Accelerator Mbit/s
10 DVD-ROM Mbit/s Drive
Host Adapter
15 Stream Mbit/s Parsing
MPEG-2 Decoder
CX25870/ CX25871 NTSC or PAL Television
450 kbit/s
AC-3 Decoder
Sound Card Speakers
100381_061
To enable DVD playback with this architecture, the graphics controller must be able to deinterlace and color space convert the CCIR601 input data from the MPEG2 decoding source. Furthermore, since the pixel clock frequency is not 27.000 MHz any longer, the graphics controller must have the ability to synchronize the pixel data to the clock rate dictated by the CX25870/871s CLKO signal. Finally, the controller must be able to function as the clocking master and timing slave as described in Section 1.3.7 of this data sheet. The recommended interface for the CX25870/871 for this option is Master and the encoder must be programmed to accept noninterlaced RGB data and output a standard NTSC video output. The pertinent factors for this option are:
* Type of Digital Video Input: * Active Resolution (HorizontalxVertical): * Overscan Compensation Ratio: * Interface: * Pixel Rate * Type of Analog Video Output: Progressive Scan/Noninterlaced; 24-bit RGB per pixel Multiplexed Input Format 720x480 Minimal; Horizontal = 1.24%; Vertical = 1.23% CX25870/871 is clock and timing master 27.6923 MHz Standard NTSC[NTSC-M]
Given this set of conditions, autoconfiguration mode 44 is a perfect fit for this architectural option. As a result, simply use the graphics accelerator's serial bus mastering ability to program the CX25870/871s CONFIG[5:0] field with a binary value of 101100. This translates into writing a hexadecimal number of 0x54 to register 0xB8. Once the encoder acknowledges this write to its autoconfiguration register, it automatically loads the appropriate values for this type of DVD configuration into its register indices from 0x76 to 0xB4 including 0x38. The exact data transferred into these registers is contained in Appendix C.
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Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
After completion of the autoconfiguration command, the encoder enters Master interface. In addition, the CX25870/871 will expect to receive digital frames with an active resolution of 720x480 comprised of noninterlaced RGB data at a pixel rate of 27.6923 MHz. If these events occur, approximately 40 clocks later (i.e., pipeline delay), the encoder will begin transmitting a NTSC-compliant S-Video or Composite video signal containing the DVD movie.
1.3.40 SECAM Output
Unlike its predecessor, the Bt868/869, the CX25870/871 now includes an encoder block for conversion of digital video data into a SECAM Composite (CVBS) and/or a SECAM S-Video signal. Like other video outputs, any active resolution from 320x200 to 1024x768 can be supported with the SECAM encoder block. The circuit accepts RGB or YCrCb data in a variety of multiplexed or nonmultiplexed input formats, reformats the digital data, and finally routes the stream through the four on-chip Digital-to-Analog Converters (DACs). The encoder supports all variations of the SECAM analog video standard including those commonly used in France (SECAM-L), Eastern Europe/Russia (D, K, K1), and Greece/Middle East (B, G, H). The SECAM specific processing is achieved in this block by a pre-emphasis of the color difference signals. Once data is received, it is converted to an internal YUV format. Next, the Y component is filtered and then upsampled to the system clock frequency while the UV components are used to frequency modulate the two subcarrier frequencies appropriately. The luminance signal is always low-pass filtered using the upsampling filter response illustrated in Figure 1-24. Additional peaking or reduction filters can be enabled (see Figures 1-25 through 1-27), using the PKFIL_SEL[1:0] bit field. The peaking filters are optimized for a high bandwidth frequency response and optimal picture quality. The default chrominance filter response is illustrated in Figure 1-28, but an alternate wide bandwidth response can be selected by setting register bit CHROMA_BW, as illustrated in Figure 1-29. The color subcarrier frequencies, 4.25000 MHz for Db and 4.40625 MHz for Dr, are controlled by a number of registers, chiefly MSC_DB[31:0] for Db and MSC[31:0] for Dr. Figure 1-30 illustrates the SECAM pre-emphasis filter response at higher (>3 MHz) frequencies within the standard definition television passband. Table 1-21 lists three complete register sets for the most common desktop input resolutions with the SECAM output. This output adheres to the SECAM target video parameters included in Table A-1. This occurs only if the Conexant encoder is programmed correctly with the register values listed in Table 1-21, the master device provides the RGB data at the listed clock frequency (CLKI/CLKO), and the interface bits are modified to match the desired connection type.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-21. Register Values for 640x480 / 800x600 / 1024x768 RGB In, SECAM-L Out (1 of 4) 640x480 RGB in, SECAM-L out HOC = 16.55%, VOC = 16.66%
CLKI/CLKO Frequency State of PLL_32CLK bit Internal Pixel Clock Frequency 29.500007 MHz 0 29.500007 MHz
800x600 RGB in, SECAM-L out HOC = 14.52% VOC=13.19%
36.000000 MHz 0 36.000000 MHz
1024x768 RGB in, SECAM-L out HOC = 12.72% VOC = 12.15%
67.687489 MHz 1 45.124993 MHz
Register Address
0x00 0x02 0x04 0x06 0x2E 0x30 0x32 0x34 0x36 0x38 0x3A 0x3C 0x3E 0x40 0x42(5) 0x44(5) 0x46(5) 0x48(5) 0x4A(5) 0x4C(5) 0x4E(5) 0x50(5) 0x52(5) 0x54(5)
CX25870 Register Values
00 00 00 00 00 00 00 00 00 00 00 80 80 80 8B A0 E1 24 28 3B 25 28 3B 25
CX25870 Register Values
00 00 00 00 00 00 00 00 00 00 00 80 80 80 8E E3 38 1E 3A 77 1C 3A 77 1C
CX25870 Register Values
00 00 00 00 00 00 00 00 00 20 00 80 80 80 9B 5D 1C 18 5F C4 13 5F C4 13
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Flicker-Free Video Encoder with Ultrascale Technology
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1.3 Device Description
Table 1-21. Register Values for 640x480 / 800x600 / 1024x768 RGB In, SECAM-L Out (2 of 4) 640x480 RGB in, SECAM-L out HOC = 16.55%, VOC = 16.66% Register Address
0x56(5) 0x58(5) 0x5A 0x5C 0x5E 0x60 0x62 0x64 0x66 0x68 0x6A 0x6C(1) 0x6E 0x70 0x72 0x74 0x76 0x78 0x7A 0x7C 0x7E 0x80 0x82 0x84 0x86 0x88 0x8A 0x8C 0x8E 0x90
800x600 RGB in, SECAM-L out HOC = 14.52% VOC=13.19%
1024x768 RGB in, SECAM-L out HOC = 12.72% VOC = 12.15% CX25870 Register Values
7A 31 00 00 00 00 00 00 D9 00 00 46 00 0F 00 01 48 00 D4 FC E2 79 28 FE 4B 00 91 5E 0D B6
CX25870 Register Values
AC 20 00 00 00 00 00 00 3C 00 00 46 00 0F 00 01 60 80 8A A6 68 C1 2E F2 27 00 B0 0A 0B 71
CX25870 Register Values
18 27 00 00 00 00 00 00 E3 00 00 46 00 0F 00 01 00 20 AA CA 9A 0D 29 FC 39 00 C0 8C 03 EE
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-21. Register Values for 640x480 / 800x600 / 1024x768 RGB In, SECAM-L Out (3 of 4) 640x480 RGB in, SECAM-L out HOC = 16.55%, VOC = 16.66% Register Address
0x92 0x94 0x96 0x98 0x9A 0x9C 0x9E 0xA0 0xA2 0xA4 0xA6 0xA8(5) 0xAA(5) 0xAC 0xAE(5) 0xB0(5) 0xB2(5) 0xB4(5) 0xB6 0xB8 0xBA 0xBC 0xBE 0xC0 0xC2 0xC4(2) 0xC6(3) 0xC8
800x600 RGB in, SECAM-L out HOC = 14.52% VOC=13.19%
1024x768 RGB in, SECAM-L out HOC = 12.72% VOC = 12.15% CX25870 Register Values
76 00 3F A4 A0 55 15 1E 24 F0 56 4B 31 8C 76 4A FF 18 0 33 0 0 0 0 0 1 3 1B
CX25870 Register Values
5A E0 06 00 50 72 1C 0D 8C F0 58 76 4D 8C EA BE 3C 26 00 01 00 00 00 00 00 01 03 1B
CX25870 Register Values
5F 58 0A 66 96 0 0 10 8C F0 57 5F 3E 8C 55 55 55 1F 0 3 0 0 0 0 0 1 3 1B
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Flicker-Free Video Encoder with Ultrascale Technology
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1.3 Device Description
Table 1-21. Register Values for 640x480 / 800x600 / 1024x768 RGB In, SECAM-L Out (4 of 4) 640x480 RGB in, SECAM-L out HOC = 16.55%, VOC = 16.66% Register Address
0xCA 0xCC 0xCE(4) 0xD0 0xD2 0xD4 0xD6 0xD8
NOTE(S):
800x600 RGB in, SECAM-L out HOC = 14.52% VOC=13.19%
1024x768 RGB in, SECAM-L out HOC = 12.72% VOC = 12.15% CX25870 Register Values
C0 C0 24 0 0 0 0 40
CX25870 Register Values
C0 C0 24 00 00 00 00 40
CX25870 Register Values
C0 C0 24 0 0 0 0 40
1. Register 0x6C contains the TIMING_RESET bit. Set this bit as your last programming step and the CX25870 will clear it automatically later. 2. Register 0xC4 contains the EN_OUT bit. Adjust according to your design's interface as necessary. 3. Register 0xC6 contains the EN_BLANKO, EN_DOT, and IN_MODE[2:0] bits. Adjust according to your design's interface as necessary. 4. Register 0xCE contains the OUT_MUXD[1:0], OUTMUXC[1:0], OUTMUXB[1:0], and OUTMUXA[1:0] bit fields for output routing. Adjust according to your design's interface as necessary. 5. This is a SECAM specific register.
The procedure required to obtain a SECAM output with an overscan compensation percentage that differs from those solutions in Table 1-21 is fairly simple. First, configure the encoder so it generates a standard PAL-B output with the desired overscan compensation percentage. This can be done through the use of an autoconfiguration mode, a hand-generated, or a predefined register set. Second, perform a full register read-back from the CX25870. Carefully note the value for register 0xA2. Third, program only the bits found in Table 1-22 to their new state within the CX25870.
Table 1-22. Vital SECAM Bit Settings-Register 0xA2 Bit Name
FM PAL_MD VSYNC_DUR
Location
Bit 7 of register 0xA2 Bit 5 of register 0xA2 Bit 3 of register 0xA2 0 1 0
State for PAL-BDGHI
1 0 0
State for SECAM
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology Finally, calculate the values for the MSC_DB[31:0], MCR[7:0], MCB[7:0], FILFSCONV[5:0], FIL4286INCR[7:0], and MSC[31:0] registers for the particular SECAM overscan solution. To accomplish this task, read back both values that comprise the HCLKO[11:0] register, convert it to decimal (base 10), and use it in the equations below. After solving each SECAM register equation, perform a conversion back to a hexadecimal number and program the appropriate registers with their new SECAM specific values.
The equations for generation of a SECAM output based on a RGB input only are: MSC_DB[31:0] = int ((272 / H_CLKO[11:0]) * 232 + 0.5) DR_LIMITP[10:0] = ((4.756 MHz/ Internal Pixel Clock Frequency)*2^13) DR_LIMITN[10:0] = ((3.9 MHz/ Internal Pixel Clock Frequency)*2^13) DB_LIMITP[10:0] = ((4.756 MHz/ Internal Pixel Clock Frequency)*2^13) DB_LIMITN[10:0] = ((3.9 MHz/ Internal Pixel Clock Frequency)*2^13) *If PLL_CLK32 is 0, then Internal Pixel Clock Frequency = CLKI = CLKO. *If PLL_CLK32 is 1(for some overscan ratios in 800x600 and all 1024x768 resolutions), then Internal Pixel Clock Frequency = (2/3) * CLKI FIL4286INCR[7:0]: Six equations required to find hex value SCINCR_OFF = int(8192 * 4.286 * 1728 / (27 * H_CLKO[11:0]) + 0.5) SCINCR_OFFh = dec2hex(SCINCR_OFF) SCINCR_OFFb = hex2bin(SCINCR_OFFh) SCINCR_INTb = SCINCR_OFFb &(bitwise AND operator) with 111111111(binary) SCINCR_INTnot = NOT[SCINCR_INTb] FIL4286INCR[7:0] = [BIN2DEC{SCINCR_INTnot}] 2 FILFSCONV[5:0] = int((27 * H_CLKO[11:0] * 1.087) / 1728 + 0.5) For RGB input only: MCR[7:0] = int ((920.26) / (288036.0 * H_CLKO[11:0] * SINX) * 226 + 0.5) where SINX = [sin (p * Fsc / CLKI)] / (p * Fsc / CLKI) MCB[7:0] = int ((598.15) / (288036.0 * H_CLKO[11:0] * SINX) * 226 + 0.5) where SINX = [sin (p * Fsc / CLKI)] / (p * Fsc / CLKI) MSC[31:0] = int ((282 / H_CLKO[11:0]) * 232 + 0.5) MY = same as PAL, no change required for SECAM For YCrCb input only: MCR[7:0] = int (1.902/(224*0.713)*(0.28/Fclk)/(84*SINX)*227+0.5) MCB[7:0] = int (1.505/(224*0.564)*(0.28/Fclk)/(84*SINX)*227+0.5) MY = same as PAL, no change required for SECAM
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Table 1-23. SECAM Specific Registers Register Address
0x42 0x44 0x46 0x48 0x4A 0x4C 0x4E 0x50 0x52 0x54 0x56 0x58 0xA8 0xAA 0xAE 0xB0 0xB2 0xB4
1.0 Functional Description
1.3 Device Description
Description
MSC_DB[7:0] MSC_DB[15:8] MSC_DB[23:16] MSC_DB[31:24] DR_LIMITP[7:0] DR_LIMITN[7:0] DR_LIMITN[10:8] & DR_LIMITP[10:8] DB_LIMITP[7:0] DB_LIMITN[7:0] DB_LIMITN[10:8] & DB_LIMITP[10:8] FIL4286INCR[7:0] Bits 5-0 are FILFSCONV[5:0] MCR[7:0] MCB[7:0] MSC[7:0] MSC[15:8] MSC[23:16] MSC[31:24]
Value for PAL-BDGHI
Not Used for PAL-BDGHI Not Used for PAL-BDGHI Not Used for PAL-BDGHI Not Used for PAL-BDGHI Not Used for PAL-BDGHI Not Used for PAL-BDGHI Not Used for PAL-BDGHI Not Used for PAL-BDGHI Not Used for PAL-BDGHI Not Used for PAL-BDGHI Not Used for PAL-BDGHI Not Used for PAL-BDGHI Overscan Ratio Dependent Overscan Ratio Dependent Overscan Ratio Dependent Overscan Ratio Dependent Overscan Ratio Dependent Overscan Ratio Dependent
Value for SECAM
Use MSC_DB[31:0] equation Use MSC_DB[31:0] equation Use MSC_DB[31:0] equation Use MSC_DB[31:0] equation Use DR_LIMITP[10:0] equation Use DR_LIMITN[10:0] equation Use DR_LIMITN[10:0] equation Use DR_LIMITP[10:0] equation Use DB_LIMITP[10:0] equation Use DB_LIMITN[10:0] equation Use DB_LIMITN[10:0] equation Use DB_LIMITP[10:0] equation Use FIL4286INCR[7:0] equation Use FILFSCONV[5:0] equation Use MCR[7:0] equation Use MCB[7:0] equation Use MSC[31:0] equation Use MSC[31:0] equation Use MSC[31:0] equation Use MSC[31:0] equation
1.3.41 Macrovision Copy Protection
The CX25871 device supports Version 7.1.L1 of the Macrovision specification for copy protection for all NTSC, PAL, and SECAM video outputs. The CX25870 does not support the Macrovision feature whatsoever.
NOTE:
The CX25871 will power-up with Macrovision copy protection enabled as required by Macrovision Version 7.1.L1.
For detailed instructions and lists of default register values for the CX25871 obtain a Macrovision license and then ask for the Macrovision Process Supplement application note from your local Conexant salesperson or field application engineer.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.42 HDTV Output Mode
The CX25870/871 includes an HDTV Output Mode that generates the analog RGB or analog YPBPR component video outputs necessary for driving an HDTV's HD input port. While generating HDTV outputs, the device accepts RGB or YPRPB digital data in a 480p, 720p, or 1080i ATSC resolution. After a pipeline delay, it outputs either analog RGB or analog YPBPR signals and automatically inserts trilevel synchronization pulses (when necessary) and vertical synchronizing `broad pulses'. The output waveforms, input data requirements and all configuration details are explained in Appendix E. The device complies with all major SMPTE and EIA standards governing the HDTV resolutions.
1.3.43 SCART Output
In this mode of operation, the CX25870/871 can be used successfully to provide one full Red/Green/Blue/Composite (or optionally, a 2-signal Luminance and Chrominance) SCART/Peritel output to drive SCART-compatible televisions or VCRs. Many PAL/European TVs being manufactured now have SCART compatible sockets, that allows the television and the set top box, graphics card, or game console driving it to work in RGB color instead of the standard composite. The picture quality for full SCART is significantly better due to the individual RGB Composite signals being sent directly to the TV color guns. This is opposed to the TV having to modulate and decode the RGB signals from another color format. This ultimately yields a crisper picture. On power-up, the CX25870/871 will output NTSC or PAL standard-definition television outputs depending on the state of the PAL pin. To switch the device into SCART Output Mode with three sync-less Red/Green/Blue (RGB) analog outputs and a single Composite (CVBS) PAL video output from the fourth DAC, program the encoder into a satisfactory PAL output mode and then perform the sequence of serial writes found in Table 1-24.
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Flicker-Free Video Encoder with Ultrascale Technology
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1.3 Device Description
Table 1-24. Serial Writes Required to Switch CX25870/871 into SCART Output Operation Bit Name
EN_SCART
Location
Bit 3-Register 0x6C
Value
1
Comment
Enables SCART Output mode. DACs will transmit Video[0-3] as SCART compatible RGB/CVBS outputs. By default, in SCART Output mode, the CX25870 will transmit: DAC_A = Video[0] = Red DAC_B = Video[1] = Green DAC_C = Video[2] = Blue DAC_D = Video[3] = PAL Composite (CVBS)
OUT_MUXD[1:0] OUT_MUXC[1:0] OUT_MUXB[1:0] OUT_MUXA[1:0]
Bits 7:0-Register CE
E4
By configuring the DAC routing register, the CX25870 will now transmit: DAC_A = Video[0] = 00 = Red DAC_B = Video[1] = 01 = Green DAC_C = Video[2] = 10 = Blue DAC_D = Video[3] = 11 = PAL Composite (CVBS) Forces CX25870 to generate SCART output mode.
OUT_MODE[1:0]
Bits 3:2-Register D6
11
NOTE:
No change to the incoming or outgoing HSYNC* and VSYNC* signal frequencies are necessary for SCART generation. The sync rates should continue to match those found with PAL-BDGHI transmission.
While the CX25870/871 is in SCART outmode, the composite video output (Video[3]) contains a standard bilevel analog sync along with all other components that comprise a standard PAL-BDGHI video signal. The sync pulse has an amplitude of 0 mV to 300 mV peak-to-peak and a duration of 4.70 s by default. The amplitude can only be adjusted through the use of external passives, but its width can be adjusted through serial writing of the CX25870 HSYNC_WIDTH register. The CX25870's Composite should be used by the subsystem to provide the positive-going Video output/sync output expected by SCART-compliant display devices. In other words, the PAL Composite output should be fed into the Video Input (Contact #20-CEI IEC 933-1) on the SCART connector. CVBS will possess the same bandwidth and time delays as the CX25870 RGB primary color signals. The inclusion of a full composite video signal as the 4th output exceeds the SCART capabilities of some non-Conexant Flicker Filter encoders which choose to output only Composite Sync as the 4th output. This implementation benefits the customer because some European Set-Top Boxes connect to TVs solely through the SCART connector. If the TV only receives Composite video via the SCART connector, and the Set Top Box is set to RGB output with sync for blanking (not CVBS) on pin 20, a picture will not be present at all on the TV. However, with the CX25870, if the TV only receives CVBS (not RGB) and the Set Top Box is set to RGB output with CVBS on pin 20 the customer will get a colorful picture on his TV .
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
The RGB primary color signals generated in SCART mode will not contain any embedded syncs. For each output, the difference between the peak value (pure white) and blanking level is 0.7 V ( 3 dB). Therefore, the blanking level will reside at GND (0 mV) and the maximum level is 700 mV for RGB. The HSYNC* and VSYNC* digital inputs received by the CX25870/871 continue to act as a trigger to start a new line and new frame respectively as is the case with Composite and SVHS outputs. The RGB signals are blanked in accordance with the values contained in the H_BLANKO and V_BLANKO registers, with H_CLKO and H_ACTIVE playing a lesser role. The primary color signals expect a 75 load from the display device. Correct RGB amplitudes are generated when the CX25870's SCART outputs each `see' an equivalent impedance of 37.5 between the source and destination. By default, the RGB positive-going signals are transmitted from the CX25870 in the following manner:
Table 1-25. Default SCART Outgoing Signal Assignments Pin # on CX25870/871
68 = DACA 70 = DACB 72 = DACC 66 = DACD
SCART Output
Video[0] = Red Primary Color Video[1] = Green Primary Color Video[2] = Blue Primary Color Video[3] = PAL-BDGHI Composite
NOTE:
Video[0-3] can be routed out of any of the 4 on-chip DACs by adjusting the appropriate OUT_MUXA/B/C/D[1:0] bits.
Other major characteristics of the CX25870/871 SCART Output Mode are: * * * * * * * * Acceptable digital RGB inputs include 24/16/or 15 bits per pixel multiplexed or nonmultiplexed, noninterlaced RGB. Acceptable digital YCrCb inputs include 24/16 bits per pixel multiplexed or nonmultiplexed, noninterlaced YCrCb. CX25870 can operate in master, pseudo-master, or slave interface. Pixel sampling rate in this mode is determined based on the incoming and outgoing clock frequencies (CLKI and CLKO). DAC resolution for all DACs = 10-bits. Red/Green/Blue/Composite SCART Output from CX25870/871 limited to a max active resolution of 800 x 600. Y/C SCART output OK to a maximum active resolution of 1024 x 768. Compliance with the European EN50-049 SCART connector standard. Blue should be received as Pin #7, Green as Pin #11, Red as Pin #15, and CVBS Out from the CX25870 as Composite Out at Pin #19 (Display Side of Connector). Compliance with the CEI IEC Publication 933-1 standard. Blue should be received as Pin #7, Green as Pin #11, Red as Pin #15, and CVBS Out from the CX25870 as Composite Out at Pin #19 (Display Side of Connector).
*
The CX25870 is compliant with the major standards and technical reports governing the SCART interface. Table 1-26 summarizes the pins to be used for transmission of SCART RGB/CVBS video with this Conexant device.
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Table 1-26. CX25870 SCART Outputs for Different SCART Standards RGB Standard
European EN50-049 SCART (1) connector CEI IEC 933-1 : (1) BBC SCART Arrangement #1
1.0 Functional Description
1.3 Device Description
Red
Pin 15 Pin 15
Green
Pin 11 Pin 11
Blue
Pin 7 Pin 7
Composite/Blanking
Pin 19 -Composite Out (To Display) Pin 19 - Composite Out (To Display)
Y- C Standard
Luminance - Chrominance (2) SCART: BBC SCART Arrangement #2
NOTE(S):
(1) (2)
Chroma
Pin 15
x c
Luma
Pin 20
x --
Red/Green/Blue signals levels are from 0 V + 0.7 V peak-to-peak with 75 load impedance. The Luminance - Chrominance Outputs for SCART are equivalent to PAL-BDGHI S-Video. Therefore, OUTMODE[1:0] should be programmed to 00, the EN_SCART bit should be reset to 0, and the OUTMUXA/B/C/D[1:0] bits adjusted according to which DACs must transmit Luminance(Video[1]) and Chrominance(Video[2]).
A specialized cable and connector are required to connect the CX25870's RGB/CVBS or Y/C outputs to the TV's SCART input. This cable can be procured from various European electronic stores and comes in at least two different arrangements. Consult the CEI IEC 933-1 specification (Audio, Video, and Audiovisual systems-Interconnections and Matching Values) for a precise illustration of their 21-contact SCART connector, video signal peak-peak values, and cordset types. The most common types of SCART connectors are the so-called Type I and Type II variety. Figures 1-34 and 1-35 illustrate the recommended Type I and Type II SCART connector pinout arrangements.
Figure 1-34. CX25870 Driving a Type I SCART Connector (EN 50-049 and IEC 933-1 Compliant)
3.3 V
CVBS as Sync 75 1% CX25870/871 Y/R C/G CVBS/B Std Def LPF Std Def LPF Std Def LPF
3.3 V
Std Def LPF
21 19 17 15 3.3 V 13 11 3.3 V 9 7 5 3
20 18 16 14 12 10 8 6 4 2
+3.3 V
75 1%
75 1%
75 1%
1
SCART Connector
100381_092
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-35. CX25870 Driving a Type II SCART Connector (Y/C and BBC SCART Compliant)
21 19 3.3 V 17 3.3 V
20 18 16 14 12 10 8 6 4 2
+3.3 V
CX25870/871 Y/R C/G CVBS/B
Std Def LPF Std Def LPF
15 13 11 9 7 5
75 1%
75 1%
3 1
SCART Connector
100381_093
Conexant recommends that any designer utilizing the CX25870 with either type of SCART output utilize the same DAC low-pass filters used for standard definition TV outputs listed in Chapter 3.0 of this data sheet.
1.3.44 Interlaced Standard Definition Analog Component Video TV Outputs
In this mode of operation, the CX25870/25871 provides a set of Component Video Y, PB (B-Y), PR (R-Y) outputs based on a 480 line interlaced RGB or YCrCb digital input format. Some DVD Players, such as those made by Toshiba and Panasonic, call the Component Video Output format by their branded name, "ColorStream." Others refer to the two EIA standards governing this video format-EIA-770.1 and EIA-770.2-A, and state this video type as Interlaced Component Video, 480i Component Video, or Component YUV. Regardless of the different names, the video format remains the same. For instructions on how to configure the CX25870/871 to generate progressive 480p Component Video (or ColorStream Pro), refer to that particular section in this data sheet. The designer can enable ColorStream by using three of the CX25870's DACs to generate two color difference signals (PR and PB sometimes referred to as CR and CB) and a single luminance signal (Y). These three channels allow the video generating device to bypass the TV's internal Y/C separator and color decoder circuits. The analog information therefore gets routed directly into the TV's matrix decoder. By sending the pure component video signal directly to a Component Video or ColorStream input-equipped display media, the input signal forgoes the extra processing that normally would degrade the analog image.
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1.0 Functional Description
1.3 Device Description
The advantage of this type of video is increased image quality combined with more lifelike colors and crisper detail. Because the video information is transferred over three separate connecting cables instead of two (for S-Video) or one (for Coaxial or RCA/Composite), 480i Component Video yields the best standard definition TV quality available. However, because we are still dealing with standard 480 line interlaced resolutions, this format remains inferior to High-Definition TV . Output devices used for generating this format include, but are not limited to, Digital TV set top boxes, Satellite DBS Receiver Decoders, and DVD players. Input media capable of decoding ColorStream include television receivers and/or monitors. While in the Component Video mode, all 10-bits of the CX25870's D/A converters are available for encoding. This results in a D/A conversion more accurate than conventional 8-bit, 13.500 MHz systems. The end result is a more artifact-free and clear image. Some major characteristics governing the interlaced standard definition television analog component video interface are as follows:
Output Scanning Format
Interlaced
Pixels per Active Line
720
Active Lines per Frame
480
Frame Rate (Hz)
30 / 1.001
Total Samples per Line
858
Total Liens per Frame
525
*
*
*
The digital input stream can be received in a progressive (i.e., noninterlaced) format or interlaced format. Interlaced data must be transmitted as ODD-EVEN-ODD ... fields. The fields carry every other scan line in succession with succeeding fields carrying the lines not scanned by the previous field. Each field will be divided into an active picture area and a vertical blanking interval (VBI). Similarly, each line will be divided into an active pixel area and a horizontal blanking interval. The 480i video output will be capable of either a 4:3 or 16:9 aspect ratio through embedding of Wide Screen Signaling (WSS) bits into the appropriate lines in the VBI. Review the section 1.3.35 in the data sheet for more details.
If configured properly, the CX25870's EIA 770.2-A compliant Component Video luminance signal has a peak amplitude of 700 mV from the blanking level, with zero setup. A negative-going bilevel sync pulse of 300 mV conforming to , the timing requirements in Figure 1.3-a, is added to the Luma signal as the only timing reference for the complete Y PR PB set of signals. Neither PR nor PB will contain an embedded sync pulse. Both will have a maximum peak amplitude of 350 mV. The DC level of PR and PB during the horizontal line shown in Figure 1-36 below will be at reference black with a voltage of 0 V It will be generated in conformance with the EIA 770.2-A and . EIA770.1 standards. The only differences between these standards are the presence of the 7.5 IRE setup pedestal and slightly different luminance levels. Check Tables 1-27 and 1-28 for complete programming instructions for either standard.
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Conexant
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
The three component video signals Y, PB, and PR will be coincident with respect to each other within 5.0 ns. Any filtering that introduces group delay exceeding 5.0 ns should be redesigned.
Figure 1-36. YPR PB Component Video Signals using 100/0/100/0 Color Bars as the Digital Input Signal (Courtesy- EIA-770.2-A standard, page 8 and EIA-770.1 standard)
EIA770.1
EIA770.2-A WHT YEL CYN GRN MGT RED BLU BLK
+714
+700
0 -286 EIA770.1 +350 0 -350 EIA770.1 +350 0 -350
0
Y
-300 EIA770.2-A +350 0 -350 EIA770.2-A +350 0 -350
PB
PR
CLAMP PERIOD SYNC PERIOD
100381_098
To switch the device into 480i Component Video Output Mode with bilevel syncs embedded into each of the three YPRPB analog outputs, first, program up the CX25870/871 into a fully functional NTSC over-scan solution where Composite and/or S-Video is being generated out of at least three of the encoder's outputs. Next, change the registers found in Table 1-27 to the indicated values.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
Table 1-27. Common Registers Required to Switch CX25870/25871 into EIA-770.2-A- or EIA-770.1-Compliant Component Video Outputs Register/Bit Name
MCOMPY[7:0] MCOMPU[7:0] MCOMPV[7:0] SETUP
Location
Bits 7:0 - Register 3C Bits 7:0 - Register 3E Bits 7:0 - Register 40 Bit 1 - Register A2
Value
80 (hex) 90 (hex) 66 (hex) 1 (binary)
Comment
Gain multiplication factor for Y analog output. Gain multiplication factor for PB analog output. Gain multiplication factor for PR analog output. Required for EIA770.1 compliance. Enables 7.5 IRE pedestal normally present within NTSC-M active video lines. Enables Component Video output mode. CX25870 DACs will transmit Video[0-3] as EIA-770.2-A or 770.1 compliant PR / Y / PB / Y_DELAY outputs. By default, in Component Video output mode, the CX25870 will transmit: DAC_A = Video[0] = PR = V DAC_B = Video[1] = Y DAC_C = Video[2] = PB = U DAC_D = Video[3] = Y_DELAY
OUT_MODE[1:0]
Bits 3:2 - Register D6
10 (binary)
OUT_MUXA[1:0] OUT_MUXB[1:0] OUT_MUXC[1:0] OUT_MUXD[1:0]
Bits 1:0 - Register CE Bits 3:2 - Register CE Bits 5:4 - Register CE Bits 7:6 - Register CE
00 (binary) 01 (binary) 10 (binary) 11 (binary)
For EIA-770.1 compliant Component Video out, no other programming steps are required for the CX25870/871 beyond Table 1-27. For the more common EIA-770.2-A compliant Component Video out, a few additional programming steps are required. These are listed in Table 1-28 below:
Table 1-28. Unique Registers Required to Switch CX25870/25871 into EIA-770.2-A- Compliant Component Video Outputs Register/Bit Name
SETUP
Location
Bit 1-Register A2
Value
0 (binary)
Comment
Required for EIA770.2-A compliance. Removes 7.5 IRE pedestal normally present within NTSC-M active video lines. Multiplication factor for adjusting the analog sync amplitude tip to -300 mV for EIA-770.2-A. Additional gain multiplication factor for Y EIA-770.2-A analog output. This register needs to be increased by 6 percent of its nominal value. For a NTSC output based on a RGB digital input, this register would be increased 6 percent to 8C (hex) from a nominal value of 85 (hex).
SYNC_AMP[7:0] MY[7:0]
Bits 7:0-Register A4 Bits 7:0-Register AC
F0 (hex) 85 (hex)
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
The analog Y, PB, and PR - Video[0-3] outputs can be routed out of any of the four on-chip DACs by adjusting the appropriate OUT_MUXA/B/C/D[1:0] bits. All of the OUT_MUX bits are contained in register 0xCE. Because the CX25870 device has four DACs and only three are needed for Component Video, the designer can choose to use the 4th output, usually from DAC_D, for any purpose deemed necessary. This output can be configured to either the PR, Y, PB, or Y_DELAY output via OUT_MUXD. If the output is not going to be used whatsoever, Conexant recommends DAC_D be disabled by setting DACDISD (bit 3, Register BA). This will save on power dissipation. The Component Video output signals expect a 75 load to ground from the display medium. Correct Y, PR, PB amplitudes will be generated only when each CX25870 output sees an equivalent impedance of 37.5 between the source and destination. The CX25870 is compliant with the major standards and technical reports governing the Standard Definition TV Analog Component Video interface. The name of these standards are as follows: * * * EIA 770.2-A-Standard Definition TV Analog Component Video Interface EIA 770.1-Standard Definition TV Analog Component Video Interface ANSI/SMPTE Standard 170M (1994) (M/NTSC) for Television-Composite Analog Video Signal-NTSC for Studio Applications
To obtain any of these specifications, visit Global Engineering Documents at: http://global.ihs.com/ Conexant recommends that any designer utilizing the CX25870 with a Component Video output utilize the same DAC low-pass filters used for standard definition TV outputs listed in Figure 3-2 of this data sheet.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
1.3.45 VGA(RGB)--DAC Output Operation
In this mode of operation, the CX25870/871 acts as a general-purpose triple high-speed D/A converter used to drive video receivers, such as PC monitors. The encoder accomplishes this by bypassing most of the encoder blocks utilized for television outputs, such as the Flicker Filter and FIFO and routing the RGB or YCrCb digital data straight through to the on-chip 10-bit DACs. Once the data arrives at the DACs, it is quickly converted to a set of 700 mV peak-to-peak analog outputs, streamed through the respective DAC_X output pins, and routed onto the rest of the graphics system according to the PCB layout. Optimal performance is achieved when the CX25870/871's current controlled DACs are terminated into appropriate resistive loads to produce voltage outputs. The chip's DAC outputs are specifically designed to produce video output levels with a total peak-peak active-region amplitude of 700 mV when directly connected to a single-ended, doubly terminated (Req = 37.5 ) load. With the recommended loading of two 75 1 percent resistors (one each for the transmitting and receiving side), the full-scale video amplitude is from 286 mV (blanking) to 986 mV (maximum luminance) and synchronization pulses from 0 mV (negative sync tip) to 286 mV (blanking) respectively. The analog synchronization pulse is generated by the CX25870/871 every time it receives a falling edge on either the HSYNC* or the VSYNC* input by default. These sync pulses can be disabled for the RGB outputs by following the steps found in Table 1-30. On power-up, the CX25870/871 will output NTSC or PAL standard-definition television outputs depending on the state of the PAL pin. To switch the device into VGA-DAC Output Mode with bilevel syncs embedded on every Red/Green/Blue (RGB) analog output, perform the sequence of serial writes found in Table 1-29 only.
Table 1-29. Serial Writes Required to Switch CX25870/871 into VGA/DAC Output Operation Bit Name
SLAVER EN_XCLK SETUP OUT_MODE[1:0]
Location
Bit 5-Register 0xBA Bit 7-Register 0xA0 Bit 1-Register 0xA2 Bits 3:2-Register D6
Value 1 1 0 11
Comment
Ensures CX25871 in slave or pseudo-master interface CLKI used as pixel clock source. Setup off. The +56 mV pedestal setup is disabled for active video lines. Video [0-3] = 11 = VGA Output Mode: DAC_A = Video[0] = Red DAC_B = Video[1] = Green DAC_C = Video[2] = Blue Disables DACD output. Current is set to 0 mA. Output voltage goes to 0 V.
DAC_DISD
Bit 3-Register 0xBA
1
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Of course, the master device's timing signals (HSYNC*, VSYNC*, CLKI) and the digital data sent to the CX25870/871 must also be adjusted to ensure the proper operation of this mode. Some applications, such as VESA compliant PC Monitors, dictate that the embedded bilevel syncs be completely absent from the RGB analog outputs. Fortunately, the CX25870/871 can provide VESA's `syncless' outputs so long as the additional set of bits found in Table 1-30 are programmed as shown: Complete all steps in Tables 1-29 plus 1-30.
Table 1-30. Serial Writes Required to Remove Bilevel Syncs from all VGA/DAC Outputs Bit Name
HDTV_EN RASTER_SEL[1:0] RGB2PRPB BPB_SYNC_DIS GY_SYNC_DIS RPR_SYNC_DIS
Location
Bit 7--Register 0x28 Bits[1:0]--Register 0x28 Bit 6--Register 0x28 Bit 3--Register 0x28 Bit 4--Register 0x28 Bit 5--Register 0x28
Value 1 00 0 1 1 1
Comment
DACs output HDTV compatible RGB Default state. No need to reprogram. Default state. No need to reprogram. Disables sync on Blue output Disables sync on Green output Disables sync on Red output
NOTE(S): When all bits in Tables 1-29 and 1-30 are programmed correctly, the active video level range will be from +286 mV to +986 mV.
The outputs generated from the combined steps listed in Table 1-29 and Table 1-30 will not contain any embedded syncs, but will contain a positive 286 mV DC offset because the encoder cannot generate negative voltage levels. Therefore, the blanking level will reside at 286 mV and the maximum luminance level is 986 mV for the 3 different outputs. The HSYNC* and VSYNC* digital inputs received by the CX25870/871 will continue to cause blanking, but this is irrelevant since the data itself is blanked at these times. To reiterate, the VESA Video Signal Standard specification requires that the DAC analog output stay between 0.0 Vdc and 0.700 Vdc +.07 V (or -.03 V) with no excursions at all times. Clearly, the blank and maximum luminance levels for the CX25870/871 are in violation of this specification. To compensate for the DC offset, the CX25870/871 is reliant on the VGA Monitor's decode capabilities to remove this DC deviation. Through testing, Conexant has determined that most, if not all, present-day monitors have this function to filter out minor DC offsets. Other major characteristics of the CX25870/871 VGA--DAC Output Mode are: * * * * * Acceptable digital RGB inputs include 24/16/or 15 bits per pixel multiplexed or nonmultiplexed RGB Acceptable digital YCrCb inputs include 24/16 bits per pixel multiplexed or nonmultiplexed YCrCb CX25870 can only be a slave to the data master in this type of operation Sampling rate in this mode is determined based on the incoming clock frequency (CLKI) DAC resolution for all DACs = 10-bits
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100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
Finally, Conexant recommends that any designer utilizing the CX25870 in this mode circumvent the three capacitors and one inductor found in the DAC low-pass filters used for standard definition TV outputs. Figure 1-37 illustrates one method of bypassing the capacitors and inductor. Note that an additional RCA (or other type) of connector is recommended in this case for the Red. Green, and Blue VGA Outputs.
Figure 1-37. Filterless DAC Outputs for VGA (RGB)--DAC Output Operation
DAC A
2
VGA R Output
D6 BAT54S SOT-23 5443R10-0041 VAA 3.3 V
C8 22 pF 0805 5% AOUT R1 75.0 0805 5% L1 1.8 H 1210 C9 270 pF 5% 0805 5%
1
3 2
C10 330 pF 0805 5%
CVBS = Composite
1 2 VGA G Output 1 3 2 3 3
100381_083
2
1
3
DACA
68
DAC B C12 22 pF 0805 5% BOUT R2 75.0 0805 5% L3 1.8 H 1210 C13 270 pF 5% 0805 5%
CX25870/871
In VGA Output Mode
DAC B
D6 BAT54S SOT-23 5443R10-0041 VAA 3.3 V
3
Y = Luma
C14 330 pF 0805 5% 2 1 VGA B Output 1 3 2 1 3
70
DACB
2
1
DAC B C15 22 pF 0805 5% COUT R7 75.0 0805 5% L2 1.8 H 1210 C16 270 pF 5% 0805 5%
72
DAC C
D6 BAT54S SOT-23 5443R10-0041 VAA 3.3 V
DACC
3
C = Chroma
C17 330 pF 0805 5%
NOTE(S): Make sure to have only one of the paired outputs plugged in simultaneously.
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1
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.46 TV Auto-Detection Procedures
The device can determine whether or not the DAC output is connected to a monitor by verifying that the output is doubly-terminated. The MONSTATx bit for the corresponding DAC is set to a 1 if the device senses a doubly-terminated load on a reset condition or if the CHECK_STAT register bit is set. While CHECK_STAT is set, the output is forced to 2/3 of VREF when terminated and 4/3 of VREF if unterminated. The MONSTATx bit reflects the condition when the DAC output is less than or equal to VREF. The CHECK_STAT bit is automatically cleared after two clock cycles. The CX25870/871 can be read from using 2 different methods. The first method is called Standard serial read-back. To perform a read, simply have the master device issue the CX25870/871's serial device address (0x89 or 0x8B depending on the state of the encoders ALTADDR pin), transmit the particular subaddress (encoder register index) to read from, and then wait for the CX25870/871 to transmit the appropriate 8-bits of data. Of course, START and STOP conditions and ACKs must exist at the pertinent times as well, but this summarizes the basic procedure. The second method that can be used to read back from the encoder is called the Legacy method. This is because the procedure that follows was the only manner in which Conexant's first generation encoder (i.e., Bt868/869) could be read from. For compatibility purposes, this method was carried forward and exists in this second generation encoder. The Legacy procedure to follow for serial read-back and TV detection purposes is: Write 01 to the ESTATUS[1:0]{bits D7=msb and D6 of register 0xC4}bit field. This sets up the encoder to read the MONSTAT data and check if the DACs have a TV connected. 2. Write the CHECK_STAT register bit to a one (bit D6 of register BA). This will latch the MONSTAT data internally and then clear itself. 3. Wait 600 s to allow the analog nodes to reach their operating point. 4. Read the MONSTAT data by issuing 0x89 or 0x8B for the CX25870/871's device address. This ensures the least significant bit of the device write portion of the transaction is 1, which indicates to the encoder that it must send a byte of data on the next serial transaction. Do not write a subaddress to the encoder (this is not necessary since the first generation encoder only had one read register) and then read the next byte after the ACK. The 8-bit read in Step 1 contains either the CX25870's ID&VERSION (if ESTATUS was written to 00) or the CX25870's Monitor Detection for DACs C, B, and A + Closed Caption Status info and the FIELD # (if ESTATUS = 01). If ESTATUS was written to 10 in Step 1, the read byte will contain the PLL_LOCK, FIFO status bits, PAL bit, and BUSY bit.
1.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.0 Functional Description
1.3 Device Description
Table 1-31 summarizes the meaning of the read-back bits when the agency procedure is used and ESTATUS[1:0] = 10, 01, or 00.
Table 1-31. ESTATUS[1:0] Read-back Bit Map ESTATUS [1:0]
00 01 10 MONSTAT_A Reserved
7
6
ID[2:0] MONSTAT_B SECAM
5
4
3
2
VERSION[4:0]
1
0
MONSTAT_C PLL_RESET_O UT
CCSTAT_E PLL_LOCK
CCSTAT_O FIFO_OVER FIFO_ UNDER
FIELD[2:0] PAL RESERVED
NOTE(S): Descriptions of these bits are found in Table 2-4.
If ESTATUS = 01, the serial master should receive one byte of information telling it the following information in this order: a. Monitor Connection Status for DACA output (MONSTAT_A = most significant bit). b. Monitor Connection Status for DACB output (MONSTAT_B). c. Monitor Connection Status for DACC output (MONSTAT_C). d. CCSTAT_E, CCSTAT_O. e. FIELD2, FIELD1, FIELD0 (least significant bit). The FIELD[2:0] bits indicate the field number that was last encoded. 000 indicates the 1st field. 6. The serial master must issue a STOP condition to finish the Read transaction. An ACK is not necessary before closing the transaction because the CX25870 just ignores the ACK anyway. In reality, the CX25870/871 does not really care about ending a transaction properly as long as a proper START condition is used to start the next transaction. In the read mode when the CX25870 is driving the SDA port, ending the transaction cannot take place until the encoder releases control of the SID line. This happens during the transition from when the last bit of the register is output to the receiving of the ACK. 7. The graphics controller, acting as the serial master, should clear the CHECK_STAT register bit back to 0 (bit D6 of register BA) by writing zero to the CHECK_STAT register bit (bit D6 of register BA) to display standard video again from the CX25870/871 VGA encoder.
5.
To reiterate, a START condition needs to be issued by the serial master to start the next transaction. In the read mode, when the CX25870/871 is driving the SID port, an end to the transaction cannot take place until the encoder releases control of the SID line. This event happens during the transition from when the last bit of the register is output to the receiving of the ACK.
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Conexant
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1.0 Functional Description
1.3 Device Description
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.47 Sleep/Power Management
There are a number of sleep/power down options for the CX25870/871. These options can be grouped into three different categories. The first category pertains to power management during normal operation. * DIS_PLL bit: In nonsleep mode, when an external clock is being used, and the PLL is not needed, this bit will disable the PLL function. XTAL_PAD_DIS bit: Setting this bit forces the crystal oscillator circuit to completely shut down. This requires the CX25870/871 to switch over to an external clock or the RESET* pin needs to be pulsed low to recover. XTL_BFO_DIS bit: This disables the crystal buffer when it is not needed. DIS_CLKO bit: This will disable the CLKO output pin when not needed, i.e., an external clock is used in slave interface or to reduce sleep current. DACDISx/DACOFF bits: Each individual DAC can be powered down by setting its corresponding DACDISx bit. This is useful only if some of the DACs are not being utilized by the graphics system. The entire analog subsection of the device can be powered-down with the DACOFF bit, allowing digital operations to continue while reducing the power in the analog circuitry. This will achieve a significant reduction in power while maintaining all digital functionality.
*
* *
*
The second category pertains to software enabled sleep operation. * SLEEP_EN bit: Shuts down all internal clocks except the serial port interface clock. Disables all digital I/O pins except these: SLEEP, ALTADDR, CLKI, CLKO, and XTAL_OUT. Disables the PLL. Turns off all DACs and VREF; SLEEP and RESET* are never disabled. PLL_KEEP_ALIVE bit: When the PLL is used to provide a system clock, this bit keeps it functioning if the rest of the chip is slept through either the sleep pin or sleep bit. This bit has no affect if DIS_PLL is set. DIS_CLKI bit: The disable for the CLKI is separate from the sleep bit and sleep pin to accommodate using an external clock as the clock source for the CX25870/871 or as the PLL input. SLEEP pin: In addition to what the SLEEP_EN bit does, the sleep pin shuts down the serial port interface and disables the ALTADDR pin. If the SLEEP pin = 1, the only way the encoder can return to normal operation is by resetting the SLEEP pin in 0.
*
*
The third category relates to the pin driven sleep operation. *
To achieve additional power savings, all the power management options available in normal operation are also available in software or pin driven sleep operation. For the lowest possible power consumption, set the XTL_BFO_DIS, DIS_CLKO, DIS_CLKI, and XTAL_PAD_DIS bits in order, then pull the SLEEP pin (#52) high.
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2
2.0 Internal Registers
A complete register bit map CX25870/871 is displayed in Table 2-1. All registers are read/write unless denoted otherwise. For bit descriptions and detailed programming information, follow the register bit map below. All registers are set to their default state following a software reset. A software reset is always performed at power-up. After power-up, a reset can be triggered by to writing the SRESET register bit.
Table 2-1. Register Bit Map (* Indicates Read-Only Register) (1 of 4) 8-Bit Address
*00 *02 *04 *06 28 2E 30 32 34 36 38(1) 3A 3C 3E 40 42 44 46 48 MSC_DB[23:16] MSC_DB[31:24] HDTV_EN SLEEP_EN AUTO_CHK ADPT_FF FFRTN Reserved Reserved Reserved YSELECT PIX_DOUBLE Reserved PLL_32CLK Reserved RGB2PRPB XTAL_PAD_ DIS
D7
D6
ID[2:0]
D5
D4
D3
D2
VERSION[4:0]
D1
D0
MONSTAT_A MONSTAT_B Reserved SECAM
MONSTAT_C PLL_RESET_ OUT MONSTAT_C
CCSTAT_E PLL_LOCK MONSTAT_D
CCSTAT_0 FIFO_OVER
FIELD_CNT[2:0] FIFO_UNDER PAL Reserved
MONSTAT_A MONSTAT_B
FIELD_CNT[3:0]
SERIALTEST[7:0] RPR_SYNC_D GY_SYNC_DIS IS XTL_BFO_ DIS PLL_KEEP_ ALIVE BPB_SYNC_D HD_SYNC_ IS EDGE DIS_CLKI DIS_PLL RASTER_SEL[1:0] DIS_CLKO OFFSET_ RGB Y_ALTFF[1:0] Y_THRESH[2:0] HBURST_ END[8] HALF_CLKO HBURST_ BEGINS[8] PLL_DIV10 V_LINESI [10] H_BLANKI [9] Reserved CSC_SEL
DRVS[1:0] Reserved
SETUP_HOLD_A IN_MODE[3] DATDLY_RE DJ C_ALTFF[1:0] C_THRESH[2:0] DIV2 14318_XTAL Reserved
PLL_INPUT DIV2_ LATCH
MCOMPY[7:0] MCOMPU[7:0] MCOMPV[7:0] MSC_DB[7:0] MSC_DB[15:8]
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2.0 Internal Registers
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-1. Register Bit Map (* Indicates Read-Only Register) (2 of 4) 8-Bit Address
4A 4C 4E 50 52 54 56 58 5A 5C 5E 60 62 64 66 68 6A 6C 6E 70 72 74 76(1) 78(1) 7A(1) 7C(1) 7E(1) 80(1) 82(1) 84(1) 86(1) V_ACTIVEO[ 8] H_ACTIVE[10:8] Reserved TIMING_ RST Reserved EN_REG_RD Reserved FFCBAR
D7
DR_LIMITP[7:0] DR_LIMITN[7:0] Reserved
D6
D5
D4
D3
D2
D1
D0
Reserved
DR_LIMITN[10:8]
DR_LIMITP[10:8]
DB_LIMITP[7:0] DB_LIMITN[7:0] Reserved Reserved DB_LIMITN[10:8] DB_LIMITP[10:8]
FIL4286INCR[7:0] Reserved Y_OFF[7:0] HUE_ADJ[7:0] XDSSEL[3:0] EWSSF2 EWSSF1 Reserved Reserved WSDAT[12:5] WSDAT[20:13] WSSINC[7:0] WSSINC[15:8] Reserved BLNK_IGNORE EN_SCART WSSINC[19:16] EACTIVE FLD_MODE[1:0] CCSEL[3:0] WSDAT[4:1] Reserved FILFSCONV[5:0]
HSYNOFFSET[7:0] HSYNOFFSET[9:8] Reserved DATDLY DATSWP Reserved H_CLKO[7:0] H_ACTIVE[7:0] HSYNC_WIDTH[7:0] HBURST_BEGIN[7:0] HBURST_END[7:0] H_BLANKO[7:0] V_BLANKO[7:0] V_ACTIVEO[7:0] H_CLKO[11:8] VSYNWIDTH[2:0] HSYNWIDTH[5:0]
2-2
Conexant
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-1. Register Bit Map (* Indicates Read-Only Register) (3 of 4) 8-Bit Address
88(1) 8A(1) 8C(1) 8E(1) 90(1) 92(1) 94(1) 96(1) 98(1) 9A(1) 9C(1) 9E(1) A0(1) A2(1) A4(1) A6(1) A8(1) AA(1) AC(1) AE(1) B0(1) B2(1) B4(1) B6 B8(2) BA BC BE C0 C2 Reserved SRESET CHECK_STAT CONFIG[5:3] SLAVER DACOFF EN_XCLK FM BY_PLL ECLIP PAL_MD DIS_SCRST H_BLANKO[9:8] CLPF[1:0] YLPF[1:0] V_SCALE[7:0] V_SCALE[13:8] PLL_FRACT[7:0] PLL_FRACT[15:8]
PLL_INT[5:0]
2.0 Internal Registers
D7
D6
D5
D4
H_FRACT[7:0] H_CLKI[7:0] H_BLANKI[7:0]
D3
D2
D1
D0
Reserved
Reserved
Reserved
VBLANKDLY
H_BLANKI[8]
H_CLKI[10:8]
V_LINESI[7:0] V_BLANKI[7:0] V_ACTIVEI[7:0] V_ACTIVEI[9:8] V_LINESI[9:8]
VSYNC_DUR 625LINE
SETUP
NI_OUT
SYNC_AMP[7:0] BST_AMP[7:0] MCR[7:0] MCB[7:0] MY[7:0] MSC[7:0] MSC[15:8] MSC[23:16] MSC[31:24] PHASE_OFF[7:0] Reserved DACDISD CCF2B1[7:0] CCF2B2[7:0] CCF1B1[7:0] CCF1B2[7:0] DACDISC CONFIG[2:0] DACDISB DACDISA
100381B
Conexant
2-3
2.0 Internal Registers
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-1. Register Bit Map (* Indicates Read-Only Register) (4 of 4) 8-Bit Address
C4 C6 C8 CA CC CE D0 D2 D4 D6 D8
NOTE(S):
(1) (2)
D7
D6
D5
D4
D3
ECCGATE HSYNCI
D2
ECBAR
D1
DCHROMA IN_MODE[2:0] F_SELY[2:0] YATTENUATE[2:0] CATTENUATE[2:0]
D0
EN_OUT
ESTATUS[1:0] EN_BLANKO EN_DOT DIS_YLPF DIS_FFILT
ECCF2(EXDS) ECCF1(ECC) FIELDI VSYNCI F_SELC[2:0] YCORING[2:0] CCORING[2:0] OUT_MUXC[1:0]
DIS_GMUSHY DIS_GMSHY DIS_GMUSHC DIS_GMSHC OUT_MUXD[1:0]
OUT_MUXB[1:0]
OUT_MUXA[1:0]
CCR_START[7:0] CC_ADD[7:0] MODE2X CCR_ START[9] CHROMA_ BW DIV2 E656 BY_YCCR EN_ASYNC BLANKI CCR_START[8] EBLUE PKFIL_SEL[1:0] CC_ADD[11:8] OUT_MODE[1:0] FIELD_ID CVBSD_INV LUMADLY[1:0] SC_ PATTERN PROG_SC
Denotes a register that is reprogrammed by the autoconfiguration process. When sequentially writing a new register set to the CX25870/871, make sure to skip register 0xB8. This is the autoconfiguration register and writing to it will overwrite registers 0x76 through 0xB4 and 0x38 with autoconfiguration values.
2-4
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
2.0 Internal Registers
2.1 Essential Registers
2.1 Essential Registers
The power-up state will be either autoconfiguration mode 0 (640 x 480 RGB in NTSC out) or autoconfiguration mode 1 (640 x 480 RGB in, PAL_BDGHI out) depending on the state of the PAL pin. By default, the CX25870/871 will be in master interface. To enable active video, the EACTIVE register bit must be set.
2.2 Device Address
The serial device address for the CX25870/871 is configurable by the state of the ALTADDR pin at reset. Table 2-2 lists how the ALTADDR pin switches the devices serial address. The ALTADDR pins state should only be changed during power-up.
Table 2-2. Serial Address Configuration ALTADDR State
0 1
Device Address for Writing
0x88 0x8A
Device Address for Reading
0x89 0x8B
2.3 Writing Registers
Following a start condition, writing 0x88 as the device ID initiates write access to the CX25870/871 registers when the ALTADDR pin is low. Alternative device ID 0x8A initiates write access when the ALTADDR pin is high. If the data is written sequentially in subaddress order, only the first subaddress needs to be written; the internal address counter will automatically increment after each write to the next register. When writing an entirely new register set to the CX25870/871, make sure to skip register 0xB8. This is the autoconfiguration register, and writing any value to it after having loaded values into other registers will replace desired data with unwanted data.
100381B
Conexant
2-5
2.0 Internal Registers
2.4 Reading Registers
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
2.4 Reading Registers
Following a start condition, writing 0x89 and then the desired subaddress initiates the read-back sequence. The next eight bits of information, returned by the CX25870/871, can be read from the SID pin, most significant bit first. Alternative address 0x8B is required if the ALTADDR pin is high. Registers 0x00 through 0x06 are read only. All other registers can be read from or written to. The ID[2:0] bits of register 0x00 indicate the part type (CX25870/871 or Bt868/869). The lower five bits (VERSION[4:0]) indicate the version number of that particular encoder. For software detection of a connected TV monitor on each DAC output, the MONSTAT_x bits (found in 0x06 and 0x02 for legacy purposes) should be read accordingly after writing to CHECK_STAT. For a description of this process follow the guidelines contained in the Section 1.3.46. To check the status of the monitor connections at the DAC output automatically once per frame during the vertical blanking interval, set the AUTO_CHK bit. The following pseudocode sample should be used for properly reading registers within the CX25870/871. First, there are some basic action assignments: S_ACK M_ACK NACK START STOP D_ADDR The slave device generates the acknowledge (i.e., the CX25870/871) The serial master generates the acknowledge. No acknowledge is generated by either device. Serial start condition; falling edge of SID occurs when SIC is high. Serial stop condition; rising edge of SID occurs when SIC is high. The device address is 88 hex with ALTADDR = 0, 8A when it is a 1.
* Next, load 46 hex into register 6C. This will write the EN_REG_RD bit to 1. This enables the serial master to read back all encoder registers. Perform the following transaction with the serial master: - START/D_ADDR/S_ACK/6C/S_ACK/46/S_ACK/STOP * Next, use the serial master to write the register address from which read-back will occur: - START/D_ADDR/S_ACK//S_ACK/STOP Finally, read the data starting at the read_address previously issued: - START/D_ADDR+1/S_ACK//M_ACK//M_ ACK/ /M_ACK/.../...//M_ACK// NACK/STOP where: readdata(0) is the data from CX25870/871 register readdata(1) is the data from CX25870/871 register +1 readdata(2) is the data from CX25870/871 register +2 As long as the CX25870/871 detects an acknowledge from the serial master (M_ACK) after providing the readdata, it will expect the read transaction to continue. When no acknowledge is received, the encoder will end the read operation. Using this approach, consecutive register reads can be provided with less software overhead. To read just one register location, every programming step remains the same up to the point where the read data transaction occurs.
2-6
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
2.0 Internal Registers
2.4 Reading Registers
In this case, the master should simply substitute a STOP in place of the M_ACK. The final step of the transaction will therefore be: * START/8B/S_ACK//NACK/STOP . Table 2-3 contains the bitmap for the encoder's read-only registers. Table 2-4 contains the data details for these registers. As mentioned previously, to enable full register read back, the EN_REG_RD bit must be set to 1.
Table 2-3. Bit Map for Read-Only Registers Register Address
00 02 04 06
7
6
ID[2:0]
5
4
3
2
VERSION[4:0]
1
0
MONSTAT_A MONSTAT_B MONSTAT_C Reserved SECAM PLL_RESET_ OUT
CCSTAT_E PLL_LOCK
CCSTAT_O FIFO_OVER FIFO_ UNDER
FIELD_CNT[2:0] PAL Reserved
MONSTAT_A MONSTAT_B MONSTAT_C MONSTAT_D
FIELD_CNT[3:0]
100381B
Conexant
2-7
2.0 Internal Registers
2.4 Reading Registers
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-4. Data Details Defined for Read-Only Registers Bit Names
ID[2:0] VERSION[4:0]
Data Definition
Indicates the part number of the Conexant VGA Encoder: 000 is returned from the Bt868, 001 is returned from the Bt869, 010 is returned from the CX25870, and 011 is returned from the CX25871. Version number; for Revision A of the CX25870/871, these bits are all 00000. Revision C (25870/871-13) is denoted by 00001 of the CX25870/871. Revision D (25870/871-14) is denoted by 00010 of the CX25870/871. Revision E (25870/871-15) is denoted by 00011 of the CX25870/871. Monitor connection status for DACA output, 1 denotes monitor connected to DACA. Monitor connection status for DACB output, 1 denotes monitor connected to DACB. Monitor connection status for DACC output, 1 denotes monitor connected to DACC. Monitor connection status for DACD output, 1 denotes monitor connected to DACD. High if closed-caption data has been written for the even field; it is low immediately after the clock run-in on the extended service line for the even field. High if closed-caption data has been written for the odd field; it is low immediately after the clock run-in on the closed caption line for the odd field. Field number, where 0000 indicates the first field, 1111 indicates the 15th field. An extra bit was added to accommodate the SECAM standard. Indicates status of SECAM mode. If the encoder is outputting SECAM, this bit will be set to 1. PLL reset state. High when PLL is locked. Will be low if PLL loses lock. Set to one if FIFO overflows. Reset on read. Set to one if FIFO underflows. Reset on read. Indicates status of PAL mode. If the encoder is outputting PAL, this bit will be set to 1. If the encoder is transmitting NTSC, this bit is set to 0.
MONSTAT_A MONSTAT_B MONSTAT_C MONSTAT_D CCSTAT_E CCSTAT_O FIELD_CNT[3:0] SECAM PLL_RESET_OUT PLL_LOCK FIFO_OVER FIFO_UNDER PAL
2-8
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
2.0 Internal Registers
2.4 Reading Registers
Table 2-5 contains the data details for the CX25870/871 read/write registers.
Table 2-5. Programming Detail For All Read/Write Registers (1 of 16) Bit/Register Names
14318_XTAL
Bit Location
Bit 4-3A
Bit/Register Definition
0 = 13.500 crystal operation. (DEFAULT) 1 = 14.318 MHz crystal operation. Adjusts autoconfiguration register values for the alternative crystal frequency. The default state of this bit will be 1 if the PAL pin is 1. 0 = 525-line format (NTSC-M, NTSC-J, PAL-M). 1 = 625-line format (PAL-BDGHI, PAL-N, PAL-Nc, SECAM). 0 = Disable adaptive flicker filter. (DEFAULT) 1 = Enable adaptive flicker filter. 0 = Normal operation. (DEFAULT) 1 = The status of the monitor connections will be automatically checked once per frame during the VBI (vertical blanking interval). 0 = Active low BLANK* pin. (DEFAULT) 1 = Active high BLANK* pin. 0 = Use BLANK* pin to indicate the active pixel region in CCIR 656 mode. (DEFAULT) 1 = Use registers H_BLANKI & V_BLANKI to determine the active pixel region in CCIR 656 mode. This bit is only effective when OUT_MODE[1:0] = 11, HDTV_EN = 1, and RASTER_SEL is nonzero. 0 = Enables trilevel sync on HDTV Blue or PB output. (DEFAULT) 1 = Disables trilevel sync on HDTV Blue or PB output. This bit will have to be set manually for EIA-770.3 compliance. Color burst amplitude factor. Each bit adjustment represents 1.25 mV of burst amplitude. 0 = Use on chip PLL (DEFAULT) 1 = Bypass PLL (encoder clock is crystal frequency). 0 = Normal operation (DEFAULT) 1 = Bypass luma cross color reduction filter. Optimal standard definition quality most often realized with this setting. Chroma alternate flicker filter selection. This bit will only have an effect when ADPT_FF is set. C_ALTFF should always be programmed to a value greater than or equal to F_SELC. 00 = 5 line (DEFAULT) 01 = 2 line 10 = 3 line 11 = 4 line Controls the sensitivity or limit of turning on the alternate flicker filter for chroma in adaptive mode. (DEFAULT = 000)
625LINE
Bit 2-A2
ADPT_FF AUTO_CHK
Bit 7-34 Bit 7-32
BLANKI BLNK_IGNORE
Bit 5-D6 Bit 4-6C
BPB_SYNC_DIS
Bit 3-2E
BST_AMP[7:0] BY_PLL BY_YCCR
Bits[7:0]-A6 Bit 6-A0 Bit 6-D8
C_ALTFF[1:0]
Bits [4:3]-34
C_THRESH[2:0]
Bits [5:3]-36
100381B
Conexant
2-9
2.0 Internal Registers
2.4 Reading Registers
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (2 of 16) Bit/Register Names
CATTENUATE[2:0]
Bit Location
Bits [2:0]-CC
Bit/Register Definition
Chroma Attenuation. Used for saturation control. 000 = 1.0 gain No Attenuation (DEFAULT) 001 = 15/16 gain 010 = 7/8 gain 011 = 3/4 gain 100 = 1/2 gain 101 = 1/4 gain 110 = 1/8 gain 111 = 0 gain (Force Chroma to 0) Closed-captioning DTO increment. This is the first byte of closed-caption information for the odd field, line 21 for NTSC or line 22 for PAL. Data is encoded LSB first. This is the second byte of closed-caption information for the odd field, line 21 for NTSC or line 22 for PAL. Data is encoded LSB first. This is the first byte of closed-caption information for the even field, line 284 for NTSC or line 335 for PAL. Data is encoded LSB first. This is the second byte of closed-caption information for the even field, line 284 for NTSC or line 335 for PAL. Data is encoded LSB first. Chroma Coring. Values below the CCORING[2:0] limit are automatically clamped to a saturation value of 0. 000 = Bypass (DEFAULT) 001 = 1/128 of range ( 1/256 of range) 010 = 1/64 of range ( 1/128 of range) 011 = 1/32 of range ( 1/64 of range) 100 = 1/16 of range ( 1/32 of range) 101 = 1/8 of range ( 1/16 of range) 110 = 1/4 of range ( 1/8 of range) 111 = Reserved
CC_ADD[11:0] CCF1B1[7:0] CCF1B2[7:0] CCF2B1[7:0] CCF2B2[7:0] CCORING[2:0]
Bits [3:0]-D4 and bits [7:0]-D2 Bits [7:0]-C0 Bits [7:0]-C2 Bits [7:0]-BC Bits [7:0]-BE Bits [5:3]-CC
CCR_START[9] CCR_START[8] CCR_START[7:0] CCSEL[3:0]
Bit 7 of D6, bit 4 of D4, and bits [7:0] of D0 Bits [3:0]-5E
Closed-captioning clock run-in start in clock cycles from leading edge of HSYNC*.
Line position of Closed Captioning (CC) Content. Controls which line Closed Captioning (CC) data is encoded. Each line enable is independent. 0001 = Closed Captioning (CC) on line 19 (525-line) and line 21 (625-line) 0010 = Closed Captioning (CC) on line 20 (525-line) and line 22 (625-line) 0100 = Closed Captioning (CC) on line 21 (525-line) and line 23 (625-line) (DEFAULT) 1000 = Closed Captioning (CC) on line 22 (525-line) and line 24 (625-line)
CHECK_STAT
Bit 6-BA
Writing a 1 to this bit checks the status of the monitor connections at the DAC output. This is also automatically performed on any reset condition, including a software reset. This bit must be cleared by the serial interface master. 0 = Normal chroma bandwidth. See Figure 1-28 (DEFAULT). 1 = Wide chroma bandwidth. See Figure 1-29.
CHROMA_BW
Bit7-D8
2-10
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (3 of 16) Bit/Register Names
CLPF[1:0]
2.0 Internal Registers
2.4 Reading Registers
Bit Location
Bits [7:6]-96
Bit/Register Definition
Chroma Post-Flicker Filter/Scaler Horizontal Low Pass Filter: 00 = Bypass (DEFAULT) 01 = Reserved 10 = Chroma Horizontal LPF2 setting 11 = Chroma Horizontal LPF3 setting
100381B
Conexant
2-11
2.0 Internal Registers
2.4 Reading Registers
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (4 of 16) Bit/Register Names
CONFIG[5:0]
Bit Location
Bits [6:4] and bits [2:0]-B8
Bit/Register Definition
The combination of CONFIG[5:3] and CONFIG[2:0] determines the autoconfiguration mode entered by the CX25870/871 immediately after register 0xB8 is written. Check Appendix C for a list of all register values by autoconfiguration mode.
CONFIG [5:0] 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000
Input Format
Active Resolution
Output NTSC PAL-BDGHI NTSC PAL-BDGHI NTSC PAL-BDGHI NTSC PAL-BDGHI NTSC PAL-BDGHI NTSC PAL-BDGHI NTSC PAL-BDGHI NTSC PAL-BDGHI
Output Ratio Overscan = Lower Overscan = Standard Overscan = Alternate Overscan = Lower Overscan = Lower Overscan = Standard Overscan = Alternate Overscan = Lower Overscan = Standard Overscan = Standard Overscan = Standard Overscan = Standard Pix Double Set = Standard Pix Double Set = Standard Overscan = Higher Overscan = Higher
Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Mode 8 Mode 9 Mode 10 Mode 11 Mode 12 Mode 13 Mode 14 Mode 15 Mode 16 Mode 17 Mode 18 Mode 19 Mode 20 Mode 21 Mode 22 Mode 23 Mode 24 Mode 25 Mode 26 Mode 27 Mode 28
Overscan = Lower Overscan = Lower Overscan = Standard 9-dot font for DOS Overscan =Standard 011001 = RGB 720x400 PAL-BDGHI 9-dot font for DOS Overscan =Standard 011010 = RGB 1024x768 NTSC Overscan = Lower 011011 = Reserved 011100 = YCrCb 720x480 NTSC Interlaced Input, Slave Interface Overscan = 0% DIV2 set
= RGB 640x480 = RGB 640x480 = RGB 800x600 = RGB 800x600 = YCrCb 640x480 = YCrCb 640x480 = YCrCb 800x600 = YCrCb 800x600 = RGB 640x400 = RGB 640x400 = RGB 1024x768 = RGB 1024x768 = RGB 320x240 = RGB 320x240 = YCrCb 1024x768 = YCrCb 1024x768 = Reserved = RGB 640x480 = RGB 800x600 = RGB 800x600 = Reserved = YCrCb 640x480 = YCrCb 800x600 = YCrCb 800x600 = RGB 720x400
PAL-BDGHI Overscan = Lower NTSC Overscan = Lower PAL-BDGHI Overscan = Standard PAL-BDGHI NTSC PAL-BDGHI NTSC
2-12
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (5 of 16) Bit/Register Names Bit Location Bit/Register Definition
2.0 Internal Registers
2.4 Reading Registers
011101 =YCrCb
011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111
PAL-BDGHI Interlaced Input, Slave Interface Overscan = 0% DIV2 set = YCrCb 1024x768 NTSC Overscan = Lower = Reserved = RGB 640x480 NTSC Overscan = Higher = RGB 640x480 PAL-BDGHI Overscan = Higher = RGB 800x600 NTSC Overscan = Higher = RGB 800x600 PAL-BDGHI Overscan = Higher = YCrCb 640x480 NTSC Overscan = Higher = YCrCb 640x480 PAL-BDGHI Overscan = Higher = YCrCb 800x600 NTSC Overscan = Higher = YCrCb 800x600 PAL-BDGHI Overscan = Higher = RGB 800x600 NTSC Overscan = Standard = RGB 320x200 PAL-BDGHI Pix Double Set Overscan = Standard = RGB 1024x768 NTSC Overscan = Higher = RGB 1024x768 PAL-BDGHI Overscan = Higher = RGB 720x480 NTSC Noninterlaced Input for DVD Overscan = Very Low = RGB 320x200 NTSC Pix Double Set Overscan = Standard = RGB 640x480 PAL-M Overscan = Standard (Brazil) = RGB 640x480 PAL-Nc Overscan = Standard (Argentina)
720x576
Mode 29
Mode 30 Mode 31 Mode 32 Mode 33 Mode 34 Mode 35 Mode 36 Mode 37 Mode 38 Mode 39 Mode 40 Mode 41 Mode 42 Mode 43 Mode 44 Mode 45 Mode 46 Mode 47
CSC_SEL
Bit 0-32
This bit is only effective when OUT_MODE[1:0] = 11, HDTV_EN = 1, and RASTER_SEL is nonzero. 0 = Standard color space conversion for RGB to Y (R-Y) (B-Y) based on Y =0 .299R +0 .587G +0 .114 B (DEFAULT) 1 = HDTV color space conversion for RGB to Y (R-Y) (B-Y) based on Y = 0.2126R + 0.7152G + 0.0722B 0 = Normal operation. (DEFAULT) 1 = Invert CVBS_DLY output. No more than 1 DAC should be disabled at any time. 0 = Normal operation. (DEFAULT) 1 = Disables DACA output. Current is set to 0 mA; output will go to 0 V. No more than 1 DAC should be disabled at any time. 0 = Normal operation. (DEFAULT) 1 = Disables DACB output. Current is set to 0 mA; output will go to 0 V.
CVBSD_INV DACDISA
Bit 2-D8 Bit 0-BA
DACDISB
Bit 1-BA
100381B
Conexant
2-13
2.0 Internal Registers
2.4 Reading Registers
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (6 of 16) Bit/Register Names
DACDISC
Bit Location
Bit 2-BA
Bit/Register Definition
No more than 1 DAC should be disabled at any time. 0 = Normal operation. (DEFAULT) 1 = Disables DACC output. Current is set to 0 mA; output will go to 0 V. No more than 1 DAC should be disabled at any time. 0 = Normal Operation. (DEFAULT) 1 = Disables DACD output. Current is set to 0 mA; output will go to 0 V. 0 = Normal operation. (DEFAULT) 1 = Disables DAC output current and internal voltage reference for all DACs. This will limit power consumption to just the internal digital circuitry. 0 = No delay in falling edge pixel data. (DEFAULT) 1 = Delays the falling edge pixel data by 1 full clock period. This bit is used to correct a multiplexed input data sequence that delivers a pixel on a falling edge and the following rising edge (rather than a rising edge and the following falling edge, as expected). 0 = No delay in rising edge pixel data. (DEFAULT) 1 = Delays the rising edge pixel data by 1 full clock period. This bit is used together with DATSWP to correct a multiplexed input data sequence that delivers a pixel on a falling edge and the following rising edge with the falling edge and rising edge data swapped. 0 = VGA Encoder expects an order of rising edge data/falling edge data coming from the graphics controller (DEFAULT). 1 = Swaps the falling edge pixel data with the rising edge pixel data at the input of the pixel port. Lower bound limit for DB frequency deviation in SECAM. Review SECAM Output Section. Upper bound limit for DB frequency deviation in SECAM. Review SECAM Output Section. 0 = Normal operation. (DEFAULT) 1 = Disable the chrominance portion of video output. Composite and S-Video outputs appear as gray scale. 0 = Normal operation. (DEFAULT) 1 = Disable CLKI input. Disabling the CLKI input is separate from the sleep bit and SLEEP pin. This forces the CX25870/871 to use an external clock as the clock source for the CX25870/871 or as the PLL input. 0 = Enable CLKO output. (DEFAULT) 1 = Three-state CLKO output. This will disable the CLKO output when not needed, i.e., an external clock is used (Slave Interface). Disabling CLKO is also effective in reducing the current draw in SLEEP mode. 0 = Enables Standard Flicker Filter. (DEFAULT) 1 = Disables Standard Flicker Filter. 0 = Enables Chroma Pseudo Gamma Removal. 1 = Disables Chroma Pseudo Gamma Removal. (DEFAULT) 0 = Enables Luma Pseudo Gamma Removal. 1 = Disables Luma Pseudo Gamma Removal. (DEFAULT) 0 = Enables Chroma Anti-Pseudo Gamma Removal. 1 = Disables Chroma Anti-Pseudo Gamma Removal. (DEFAULT)
DACDISD
Bit 3-BA
DACOFF
Bit 4-BA
DATDLY
Bit 7-74
DATDLY_RE
Bit 2-32
DATSWP
Bit 6-74
DB_LIMITN[10:8} DB_LIMITN[7:0] DB_LIMITP[10:8} DB_LIMITP[7:0] DCHROMA
Bits [5:3]-54 and bits [7:0]-52 Bits [2:0]-54 and bits [7:0]-50 Bit 1-C4
DIS_CLKI
Bit 3-30
DIS_CLKO
Bit 1-30
DIS_FFILT DIS_GMSHC DIS_GMSHY DIS_GMUSHC
Bit 6-C8 Bit 6-CC Bit 6-CA Bit 7-CC
2-14
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (7 of 16) Bit/Register Names
DIS_GMUSHY DIS_PLL
2.0 Internal Registers
2.4 Reading Registers
Bit Location
Bit 7-CA Bit 2-30
Bit/Register Definition
0 = Enables Luma Anti-Pseudo Gamma Removal. 1 = Disables Luma Anti-Pseudo Gamma Removal. (DEFAULT) 0 = PLL enable. (DEFAULT) 1 = PLL disable. In nonsleep mode, if an external clock is being used and the PLL is not needed, this bit will disable the PLL function. NOTE(S): Some of the special modes are not available when the PLL is disabled. 0 = Normal operation. The subcarrier phase is reset to 0 at the beginning of each color field sequence. (DEFAULT) 1 = Disables subcarrier reset event at beginning of field sequence. 0 = Enable Luma Initial Horizontal Low Pass filter. (DEFAULT) 1 = Disable Luma Initial Horizontal Low Pass filter. 0 = Normal operation. (DEFAULT) 1 = Divides input pixel rate by two (for CCIR601 interlaced timing input). Useful for DVD playback resolutions. The DIV2 bit in register D4 was kept for Bt868/869 compatibility purposes. The DIV2 bit in register 38 is autoconfigurable. These bit values always mirror each other. Changing the state of one DIV2 register field automatically updates the other DIV2 register field. This bit only has an effect when DIV2 = 1. 0 = Data is clocked at rising edge of CLKI while encoder is in DIV2 mode. (DEFAULT) 1 = Data is clocked at rising and falling edges of CLKI. Lower bound limit for DR frequency deviation in SECAM. Review SECAM Output Section. Upper bound limit for DR frequency deviation in SECAM. Review SECAM Output Section. Controls the low voltage pad drive strength. Review Low Voltage Graphics Interface section. 00 = 3.3 V peak-to-peak signal levels (DEFAULT) 01 = 1.8 V peak-to-peak signal levels 10 = 1.5 V and 1.3 V peak-to-peak signal levels 11 = 1.1 V peak-to-peak signal levels 0 = Input pixel format defined by IN_MODE[3:0] register. (DEFAULT) 1 = CCIR 656 input on P[7:0] port. 0 = Black burst. 1 = Enable normal video. (DEFAULT) 0 = Normal operation. (DEFAULT) 1 = Generate blue field. 0 = Normal operation. (DEFAULT) 1 = Enable standard color bars. 0 = Disables closed-caption encoding on field 1. (DEFAULT) 1 = Enables closed-caption encoding on field 1. 0 = Disables closed-caption encoding on field 2. (DEFAULT) 1 = Enables closed-caption encoding on field 2.
DIS_SCRST
Bit 4-A2
DIS_YLPF DIV2
Bit 7-C8 Bit 6-D4 and bit 4-38
DIV2_LATCH
Bit 0-3A
DR_LIMITN[10:8} DR_LIMITN[7:0] DR_LIMITP[10:8} DR_LIMITP[7:0] DRVS[1:0]
Bits [5:3]-4E and bits [7:0]-4C Bits [2:0]-4E and bits [7:0]-4A Bits [6:5]-32
E656 EACTIVE EBLUE ECBAR ECCF1(ECC) ECCF2(EXDS)
Bit 6-D6 Bit 2-6C Bit 4-D6 Bit 2-C4 Bit 4-C4 Bit 5-C4
100381B
Conexant
2-15
2.0 Internal Registers
2.4 Reading Registers
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (8 of 16) Bit/Register Names
ECCGATE
Bit Location
Bit 3-C4
Bit/Register Definition
0 = Normal closed-caption encoding. (DEFAULT) 1 = Enables closed-caption encoding constraints. After encoding, future encoding is disabled until a complete pair of new data bytes is received. This prevents encoding of redundant or incomplete data. 0 = Normal operation. (DEFAULT) 1 = Enable clipping; DAC values less than 31 hex are made 31 by the encoder. 0 = Normal operation. (DEFAULT) 1 = Enable asynchronous flicker filer and encoder block timing operation. Use CLKI for flicker filter and input blocks and PLL for encoder block. Allows for additional clock ratios between flicker filter and encoder blocks to provide more overscan solutions similar to the 3:2 clocking mode. Interface bit: Works in conjunction with EN_DOT, EN_OUT, and SLAVER. Controls direction of BLANK* signal. 0 = Enables BLANK* as an input. 1 = Enables BLANK* pin as an output, or no BLANK* signal is utilized in the system interface. (DEFAULT) Interface bit: Works in conjunction with EN_BLANKO, EN_OUT, and SLAVER. Controls blanking method. 0 = Encoder uses its internal counters to determine the active-versus-blanked regions of input data. (DEFAULT) 1 = Encoder uses the BLANK* signal being received to determine where active video starts (rising edge by default) and where blanking region starts (falling edge by default). Interface bit: Works in conjunction with EN_BLANKO, EN_DOT, and SLAVER. Turns timing outputs on or off. 0 = Three-state (CLKO, HSYNC*, VSYNC*, BLANK* and FIELD) timing outputs. (DEFAULT) 1 = Allows CLKO and other outputs to be enabled (depending upon EN_BLANKO register bit and the OR combination of the SLAVE pin and the SLAVER bit). 0 = Use ESTATUS[1:0] register to select read back status registers. Enable Bt869-like Legacy read-back method. (DEFAULT) 1 = Enable Standard serial register read back of all registers. Enables SCART video output for Europe. OUT_MODE[1:0] field must be set to 11 (VGA Mode) and HDTV_EN bit must be set to 0. 0 = Enables VGA mode. DACs will output analog RGB with standard bilevel (-40 IRE) analog syncs (DEFAULT). 1 = Enables SCART output mode. DAC will transmit SCART compatible RGB outputs and a composite video output which includes an analog sync. 0 = Encoder generates pixel clock. (DEFAULT) 1 = Use CLKI pin as pixel clock source. This bit must be set for slave interface. Bt868/869 Legacy serial read back status bit selection. Used in conjunction with EN_REG_RD, CHECK_STAT, and AUTO_CHK. Review Table 1-30. 0 = Disable field 1 WSS data. (DEFAULT) 1 = Enable field 1 WSS data. 0 = Disable field 2 WSS data. (DEFAULT) 1 = Enable field 2 WSS data (525 line only).
ECLIP EN_ASYNC
Bit 6-A2 Bit 5-D4
EN_BLANKO
Bit 7-C6
EN_DOT
Bit 6-C6
EN_OUT
Bit 0-C4
EN_REG_RD
Bit 6-6C
EN_SCART
Bit 3-6C
EN_XCLK ESTATUS[1:0] EWSSF1 EWSSF2
Bit 7-A0 Bits [7:6]-C4 Bit 6-60 Bit 7-60
2-16
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (9 of 16) Bit/Register Names
F_SELC[2:0]
2.0 Internal Registers
2.4 Reading Registers
Bit Location
Bits [5:3]-C8 Chroma Standard Flicker Filter: 000 = 5 Line (DEFAULT) 001 = 2 Line 010 = 3 Line 011 = 4 Line 100 = Alternate 5 Line 101 = Alternate 5 Line 110 = Alternate 5 Line 111 = Alternate 5 Line Luma Standard Flicker Filter: 000 = 5 Line (DEFAULT) 001 = 2 Line 010 = 3 Line 011 = 4 Line 100 = Alternate 5 Line 101 = Alternate 5 Line 110 = Alternate 5 Line 111 = Alternate 5 Line
Bit/Register Definition
F_SELY[2:0]
Bits [2:0]-C8
FFCBAR FFRTN
Bit 5-6C Bit 7-36
0 = Normal operation. (DEFAULT) 1 = Enable flicker filtered color bars. Alternate flicker filter detect and select. This bit is effective only when ADPT_FF = 1. 0 = Once the adaptive algorithm selects the alternate filter, use that filter's coefficients for the rest of the samples for that line. For example, the sequence could be STD/STD/ALT/ALT/ALT; (DEFAULT) 1 = Once the adaptive algorithm selects the alternate filter, use the filter's coefficients for that sample only. For example, the sequence with FFRTN=1 could be STD/STD/ALT/STD/STD. 0 = Suppress the SECAM field synchronization signal. (DEFAULT) 1 = Enable the SECAM field synchronization signal (bottle-neck pulses). 0 = Logical 1 from the FIELD pin indicates an even field. (DEFAULT) 1 = Logical 1 from the FIELD pin indicates an odd field. Adjust SECAM high frequency preemphasis filter according to the clock frequency. Review the SECAM Output section for the correct equations. Adds a phase offset to the UV digital components. Review the SECAM Output section for the correct equations. CX25870/871 uses this bit to interpret HSYNC* and VSYNC* edges and field detection in slave mode. 00 = A leading edge of VSYNC* that occurs within 1/4 of HCLKI from the leading edge of HSYNC* indicates the beginning of odd field. A leading edge of VSYNC* that occurs within 1/4 of HCLKI from the center of the line indicates the beginning of even field. 01 = A leading edge of VSYNC* occurs during HSYNC* active indicates the beginning of odd field. A leading edge of VSYNC* occurs during HSYNC* inactive indicates the beginning of even field. 10 = A leading edge of VSYNC* coincides with the leading edge of HSYNC* indicates the beginning of odd field. A leading edge of VSYNC* does not coincide with the leading edge of HSYNC* indicated the beginning of even field. (DEFAULT) 11 = Reserved.
FIELD_ID FIELDI FILFSCONV[5:0] FIL4286INCR[7:0] FLD_MODE[1:0]
Bit 3-D8 Bit 5-C6 Bits [5:0]-58 Bits [7:0]-56 Bits [1:0]-6C
100381B
Conexant
2-17
2.0 Internal Registers
2.4 Reading Registers
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (10 of 16) Bit/Register Names
FM
Bit Location
Bit 7-A2
Bit/Register Definition
This bit must be enabled for a valid SECAM video output. 0 = QAM color encoding (NTSC/PAL). (DEFAULT) 1 = FM color encoding (SECAM). This bit is only effective when OUT_MODE[1:0] = 11, HDTV_EN = 1, and RASTER_SEL is nonzero. 0 = Enables trilevel sync on HDTV Green or Y output. (DEFAULT) 1 = Disables trilevel sync on HDTV Green or Y output. Number of active input and output pixels. Number of CLKI clock cycles between the digital HSYNC* leading edge and first active pixel. Number of CLKO clock cycles between leading edge of analog horizontal sync and active video. Number of CLKI clock cycles between consecutive leading edges of the digital HSYNC* signal. Number of CLKO clock cycles per analog line. Fractional number of input clocks per line. No effect if 00. 0 = Normal operation. (DEFAULT) 1 = CLKO (clock output) frequency divided by 2 while being transmitted. This register contains the number of CLKO clock cycles between the analog horizontal sync falling edge and the 50% point of the first colorburst cycle. This register contains the number of CLKO clock cycles minus 128 between the analog horizontal sync falling edge and the 50% point of the last colorburst cycle. Make sure to subtract 128 CLKO clock cycles from the calculated 50% point of the last colorburst cycle value and load into this register. This bit is only effective when OUT_MODE[1:0] = 11, HDTV_EN = 1 and RASTER_SEL is nonzero. 0 = Trilevel sync edges transition time is equal to 4 input clocks. (DEFAULT) 1 = Trilevel sync edges transition time is equal to 2 input clocks. Enable HDTV output mode, OUT_MODE[1:0] register bits must be set to 11 (VGA mode) and EN_SCART must = 0. 0 = Enables VGA mode. DACs will output analog RGB with standard bilevel (-40 IRE) analog syncs. (DEFAULT) See Section 1.3.45 for details. 1 = Enables HDTV output mode. DACs will output HDTV compatible RGB or component video (Y/ PR/ PB) outputs. Trilevel syncs and vertical synchronizing/broad pulses will be inserted automatically if RASTER_SEL[1:0] = nonzero.
NOTE(S): The EN_SCART bit must be 0 for HDTV Output Mode to be functional.
GY_SYNC_DIS
Bit 4-2E
H_ACTIVE[10:8] H_ACTIVE[7:0] H_BLANKI[9] H_BLANKI[8] H_BLANKI[7:0] H_BLANKO[9:8] H_BLANKO[7:0] H_CLKI[10:8] H_CLKI[7:0] H_CLKO[11:8] H_CLKO[7:0] H_FRACT[7:0] HALF_CLKO HBURST_BEGIN[8] HBURST_BEGIN [7:0] HBURST_END[8] HBURST_END[7:0]
Bits [6:4]-86 and bits [7:0]-78 Bit 0-38, bit 3-8E, and bits[7:0]-8C Bits [7:6]-9A and bits [7:0]-80 Bits [2:0]-8E and bits [7:0]-8A Bits [3:0]-86 and bits [7:0]-76 Bits [7:0]-88 Bit 3-3A Bit2-38 and bits [7:0]-7C Bit 3-38 and bits [7:0]-7E
HD_SYNC_EDGE
Bit 2-2E
HDTV_EN
Bit 7-28
HSYNC_WIDTH [7:0]
Bits [7:0]-7A
Analog horizontal sync width in number of CLKO clock cycles.
2-18
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (11 of 16) Bit/Register Names
HSYNCI
2.0 Internal Registers
2.4 Reading Registers
Bit Location
Bit 3-C6
Bit/Register Definition
0 = Configures the encoder to send/receive an active low HSYNC* digital signal (DEFAULT) 1 = Configures the encoder to send/receive an active high HSYNC* digital signal. A 2s-complement number. The values range from -512 pixels to +511 pixels. This register manipulates the falling edge position of the digital HSYNC* output from the CX25870/871. The default value is 0 and denotes the standard position of the HSYNC* leading edge. This register is only effective in master interface. Controls the duration/width of the digital HSYNC output pulse. Value will be hexadecimal and its units are in terms of pixels. A value of 0 is a disallowed condition. The acceptable range is 0x02 pixels to 0x3F pixels (=63 decimal). The default value is 0x02. Never set to 0. This register is only effective in master interface. Adjust the color subcarrier phase during the video active region. Increasing this value by 1 unit has the effect of increasing the phase by (360/256) = 1.406 degrees. This bit is used in conjunction with IN_MODE[2:0] to configure the encoder to receive a desired input pixel format. Format of input pixels when IN_MODE[3] = 0 (MSb of this 4-bit sequence): 0000 = 24-bit RGB multiplexed 0001 = 16-bit RGB multiplexed 0010 = 15-bit RGB multiplexed 0011 = 24-bit RGB nonmultiplexed 0100 = 24-bit YCrCb multiplexed 0101 = 16-bit YCrCb multiplexed 0110 = Alternate 16-bit YCrCb multiplexed 0111 = 24-bit YCrCb nonmultiplexed Format of input pixels when IN_MODE[3] = 1(MSb of this 4-bit sequence): 1000 = Alternate 24-bit RGB multiplexed 1001 = Reserved 1010 = Alternate 16-bit RGB nonmultiplexed 1011 = Alternate 24-bit RGB nonmultiplexed 1100 = Alternate 24-bit YCrCb multiplexed 1101 = Reserved 1110 = Alternate 16-bit YCrCb nonmultiplexed 1111 = Alternate 24-bit YCrCb nonmultiplexed
HSYNOFFSET[9:8] HSYNOFFSET[7:0]
Bits [7:6]-70 and bits [7:0]-6E
HSYNWIDTH[5:0]
Bits [5:0]-70
HUE_ADJ[7:0] IN_MODE[3] and IN_MODE[2:0]
Bits [7:0]-5C Bit 3-32 and bits [2:0]-C6
LUMADLY[1:0]
Bits [1:0]-D6
Used to program the luminance delay in pixels for the CVBS_DLY and Y_DLY output modes. 00 = No delay (DEFAULT) 01 = 1 pixel 10 = 2 pixels 11 = 3 pixels Multiplication factor for Cb (or B-Y) component prior to subcarrier modulation. Multiplication factor for component video U output. Value 0x80 (DEFAULT) represents 1.0 scale factor. Multiplication factor for component video V output. Value 0x80 (DEFAULT) represents 1.0 scale factor. Multiplication factor for component video Y output. Value 0x80 (DEFAULT) represents 1.0. scale factor. Multiplication factor for Cr (or R-Y) component prior to subcarrier modulation.
MCB[7:0] MCOMPU[7:0] MCOMPV[7:0] MCOMPY[7:0] MCR[7:0]
Bits [7:0]-AA Bits [7:0]-3E Bits [7:0]-40 Bits [7:0]-3C Bits [7:0]-A8
100381B
Conexant
2-19
2.0 Internal Registers
2.4 Reading Registers
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (12 of 16) Bit/Register Names
MODE2X
Bit Location
Bit 7-D4
Bit/Register Definition
0 = Normal operation (DEFAULT). 1 = Divides selected input clock by two (allows for single edge rather than double-edge clock input for pixel latching). Subcarrier increment. Subcarrier increment for Db component of SECAM. MSC_DB = int ((272/H_CLKO) * 232 + 0.5) Multiplication factor for Luma component. Controls adjustment of contrast. 0 = Interlaced analog video output. (DEFAULT) 1 = Noninterlaced analog video output. This bit is only effective when OUT_MODE[1:0] = 11, HDTV_EN = 1, and RASTER_SEL is nonzero. 0 = Standard RGB digital input. Range is 0 - 255 decimal. (DEFAULT) 1 = HDTV OFFSET RGB digital input. Range is 16 - 235 decimal. 00 = Video[0] = Composite (CVBS), Video[1] = Luminance (Y), Video[2] = Chrominance (C), Video[3] = Luma_Delay (Y_DLY) (DEFAULT) 01 = Video[0-3] is CVBS_DLY/ Y/ C/ Y_DLY 10 = Video[0-3] is V/ Y/ U/ Y_DLY 11 = Video[0-3] is VGA (RGB/x), SCART, or HDTV output mode. See EN_SCART and HDTV_EN bit descriptions for more programming detail. 00 = Output Video[0] on DACA (DEFAULT = Composite (CVBS)) 01 = Output Video[1] on DACA 10 = Output Video[2] on DACA 11 = Output Video[3] on DACA 00 = Output Video[0] on DACB 01 = Output Video[1] on DACB (DEFAULT = Luminance (Y) 10 = Output Video[2] on DACB 11 = Output Video[3] on DACB 00 = Output Video[0] on DACC 01 = Output Video[1] on DACC 10 = Output Video[2] on DACC (DEFAULT = Chrominance) 11 = Output Video[3] on DACC 00 = Output Video[0] on DACD 01 = Output Video[1] on DACD 10 = Output Video[2] on DACD 11 = Output Video[3] on DACD (DEFAULT = Luma Delay (Y_DLY)) Video output switch bit after power-up. 0 = Disable phase alternation (NTSC and SECAM). (DEFAULT) 1 = Enable phase alternation (PAL).
NOTE(S): The PAL pin (#50) determines the power-up standard definition video output. This bit overrides the PAL pin after power-up.
MSC[31:0] MSC_DB[31:0]
Bits [7:0]-B4, B2, B0, AE Bits [7:0]-48, -46, -44, -42 Bits [7:0]-AC Bit 0-A2 Bit 1-32
MY[7:0] NI_OUT OFFSET_RGB
OUT_MODE[1:0]
Bits [3:2]-D6
OUT_MUXA[1:0]
Bits [1:0]-CE
OUT_MUXB[1:0]
Bits [3:2]-CE
OUT_MUXC[1:0]
Bits [5:4]-CE
OUT_MUXD[1:0]
Bits [7:6]-CE
PAL_MD
Bit 5-A2
PHASE_OFF[7:0]
Bits [7:0]-B6
Subcarrier phase offset. Default value is 00. SCH Phase increased by 1.406 degrees per bit increment.
2-20
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (13 of 16) Bit/Register Names
PIX_DOUBLE
2.0 Internal Registers
2.4 Reading Registers
Bit Location
Bit 6-38
Bit/Register Definition
Low resolution pixel doubling bit. 0 = Encoder accepts each pixel input individually and processes it. (DEFAULT) 1 = Encoder replicates/copies each input pixel received. This bit is automatically set for autoconfiguration modes #12, #13, and #41. Text sharpening filter. Also referred to as the luma peaking filter selection (Refer to Section 1.3.36 and Figure 1-27 for details). 00 = Bypass (DEFAULT) 01 = Filter 1 (1 dB gain) 10 = Filter 2 (2 dB gain) 11 = Filter 3 (3.5 dB gain) Use this bit primarily to support the 1024 x 768 resolution and additional 800 x 600 overscan options. For more details, review the 3:2 Clocking Mode section. 0 = Use PLL 3x pixel clock output. (DEFAULT) 1 = Use PLL generated 2x pixel clock to run the encoder and output timing section. Use PLL generated 3x pixel clock to run the flicker filter.
NOTE(S): The 3x pixel clock will be output from the CLKO pin during either state of this
PKFIL_SEL[1:0]
Bits [5:4]-D8
PLL_32CLK
Bit 5-38
bit. PLL_DIV10 Bit 2-3A Scales the CLKO frequency. (See Section 1.3.6 for details) 0 = PLL equation divided by 6. (DEFAULT) 1 = PLL equation divided by 10.
PLL_FRACT[15:0] PLL_INPUT
Bits [7:0]-9E, -9C Fractional portion of PLL multiplier. Bit 1-3A 0 = PLL uses the crystal between XTALIN and XTALOUT pins to generate the CLKO programmed frequency. (DEFAULT) 1 = PLL uses CLKI/2 as the reference for the PLL. Integer portion of PLL multiplier. 0 = Normal operation. (DEFAULT) 1 = Keeps PLL enabled during the sleep mode. This bit is overwritten by DIS_PLL. If the PLL is used to provide a system clock, this bit keeps it functioning if the rest of the chip is slept through either the sleep pin or sleep bit. This bit has no affect if DIS_PLL is set. SECAM subcarrier control bit. PROG_SC only has an effect when FM bit is set. 0 = SECAM subcarrier is generated on lines 23-310 and 336-623. (DEFAULT) 1 = SECAM subcarrier is generated on the active lines defined by V_BLANKO[7:0] and V_ACTIVEO[8:0]. This bit is only effective when HDTV_EN = 1, and OUT_MODE[1:0] = 11 00 = Device does not generate trilevel sync automatically in HDTV output mode. Trilevel sync periods dictated by active HSYNC* input signal (as HIGHSYNC) and active VSYNC* input signal (as LOWSYNC). (DEFAULT) 01 = Trilevel sync generation for 480P format. 10 = Trilevel sync generation for 720P format. 11 = Trilevel sync generation for 1080I format. Works in conjunction with FIL_4286INCR[7:0] to set gain on UV digital component. Review the SECAM output section for the correct equations. Reserved for future software compatibility; should be set to 0 for normal operation.
PLL_INT[5:0] PLL_KEEP_ALIVE
Bits [5:0]-A0 Bit 4-30
PROG_SC
Bit 0-D8
RASTER_SEL[1:0]
Bits [1:0]-28
REGFSCONV[5:0] Reserved
Bits [5:0]-58 Various
100381B
Conexant
2-21
2.0 Internal Registers
2.4 Reading Registers
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (14 of 16) Bit/Register Names
RGB2YPRPB
Bit Location
Bit 6-28
Bit/Register Definition
HDTV output switching bit. This bit is only effective when HDTV_EN = 1, OUT_MODE[1:0] = 11, RASTER_SEL[1:0] = nonzero, and IN_MODE[3:0] = a RGB input format. 0 = Digital RGB Input to HDTV RGB output. (DEFAULT) 1 = Digital RGB Input to HDTV YPRPB output. This bit is only effective when OUT_MODE[1:0] = 11, HDTV_EN = 1, and RASTER_SEL is nonzero. 0 = Enables trilevel sync on HDTV Red or PR output. (DEFAULT) 1 = Disables trilevel sync on HDTV Red or PR output. This bit will have to be set manually for EIA-770.3 compliance. SECAM phase sequence. SC_PATTERN only has an effect when FM bit is set. 0 = 0 0 180 0 0 180 SECAM subcarrier phase sequence. (DEFAULT) 1 = 0 0 0 180 180 180 SECAM subcarrier phase sequence. Use this register for testing the write and read ability of the serial master. A consecutive write and read sequence will return the original value. The default value is 0x00. 0 = Setup off. The 7.5 IRE pedestal setup is disabled for active video lines (NTSC-J, PAL, and SECAM). 1 = Setup on. The 7.5 IRE pedestal setup is enabled for active video lines (NTSC-M). (DEFAULT) 0 = Graphic port inputs must have minimum setup = 3 ns, hold = 0 ns (DEFAULT). This setting is compatible with Bt868/869. 1 = Graphics port inputs must have minimum setup = 1.25 ns, hold = 1.5 ns. This is a new option for interfacing the CX25870/871 to other data master devices. Interface bit: Works in conjunction with EN_BLANKO, EN_DOT, and EN_OUT Controls whether the interface will be timing Master or timing Slave. 0 = Configures encoder as the timing master. HSYNC* and VSYNC* will be transmitted as outputs when this bit or a combination of this bit and SLAVE pin is 0. (DEFAULT) 1 = Configures encoder as the timing slave (pseudo-master or slave interface). HSYNC* and VSYNC* will be received as inputs when this bit or a combination of this bit and SLAVE pin is 1. 0 = Normal operation. (DEFAULT) 1 = Enables sleep state. Shuts down all internal clocks except the serial port interface clock. Disables all digital I/O pins except: SLEEP, ALTADDR, CLKI, CLKO, and XTALOUT. Disables the PLL. Turns off all DACs and VREF. SLEEP and RESET* pins are never disabled. 0 = Normal Operation. (DEFAULT) 1 = Setting this bit performs a software reset. All registers are reset to their default state. This bit is automatically cleared. Multiplication factor for controlling the analog sync amplitude. SYNC_AMP + 1 LSb (least significant bit) = +1.25 mV increase in the analog sync amplitude. 0 = Normal Operation. (DEFAULT) 1 = Enable timing reset. Resets timing and pixel counters to 1 This bit is automatically cleared. The designer should wait a minimum of 1 ms, after the last register write before enabling TIMING_RST. Number of active input lines.
RPR_SYNC_DIS
Bit 5-28
SC_PATTERN
Bit 1-D8
SERIALTEST[7:0] SETUP
Bits [7:0]-28 Bit 1-A2
SETUP_HOLD_ADJ
Bit 4-32
SLAVER
Bit 5-BA
SLEEP_EN
Bit 7-30
SRESET
Bit 7-BA
SYNC_AMP[7:0]
Bits [7:0]-A4
TIMING_RST
Bit 7-6C
V_ACTIVEI[9:8] V_ACTIVEI[7:0]
Bits [3:2]-96 and Bits [7:0]-94
2-22
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (15 of 16) Bit/Register Names
V_ACTIVEO[8] V_ACTIVEO[7:0] V_BLANKI[7:0] V_BLANKO[7:0] V_LINESI[10] V_LINESI[9:8] V_LINESI[7:0] V_SCALE[13:8] V_SCALE[7:0]
2.0 Internal Registers
2.4 Reading Registers
Bit Location
Bit 7-86 and Bits [7:0]-84 Bits [7:0]-92 Bits [7:0]-82 Bit 1-38, Bits [1:0]-96, Bits [7:0]-90 Bits [5:0]-9A and Bits {7:0]-98
Bit/Register Definition
Number of active output lines/field. Number of input lines between VSYNC* leading edge and first active line. Line number of first active output line (number of blank lines + 1). Number of vertical input lines. This register value must match the graphic controller's VTOTAL register for a new overscan ratio. Vertical scaling coefficient. VSR = V_ACTIVEI / (ALO * (1 - VOC)) V_SCALE[13:0] = (int) ((VSR - 1) * 212) 0 = Normal operation. (DEFAULT) 1 = The effective vertical blanking value in the second field is V_BLANKI+1. Commonly used in CCIR601 input. No effect if 0. 0 = Generates 2.5 line VSYNC analog output (found in equalization and serration pulse region). Common for most PAL and SECAM formats. 1 = Generates 3 line VSYNC analog output (found in equalization and serration pulse region). Common for all NTSC, PAL-N, PAL-M, and PAL-60 formats. (DEFAULT) 0 = CX25870/871 transmits or receives active digital low VSYNC*. (DEFAULT) 1 = CX25870/871 transmits or receives active digital high VSYNC*. Controls the width of the VSYNC* output pulse. Denotes the number of lines the VSYNC* digital signal remains low on field transitions. Value will be hexadecimal and its units are in terms of lines. A value of 0 is a disallowed condition. The acceptable range is 1 line to (23 -1) lines. The default value is 1. Never set to 0. This register is only effective in master interface. Wide screen signaling (WSS) data bits. Review WSS section for more details.
VBLANKDLY
Bit 4-8E
VSYNC_DUR
Bit 3-A2
VSYNCI VSYNWIDTH[2:0]
Bit 4-C6 Bits [2:0]-74
WSSDAT[20:1]
Bits [7:0]-64, - 62, and bits [3:0]-60
WSSINC[19:0] XDSSEL[3:0]
Bits [3:0]-6A and WSS DTO increment bits. Review WSS section for more details. bits [7:0]-68, - 66 Bits [7:4]-5E Line position of Extended Data Services (XDS) Content. Controls which line contains Extended Data Services data. Each line enable is independent of the other. 0001 = Extended Data Services on line 282 (525-line) and line 333 (625-line). 0010 = Extended Data Services on line 283 (525-line) and line 334 (625-line). 0100 = Extended Data Services on line 284 (525-line) and line 335 (625-line). (DEFAULT) 1000 = Extended Data Services on line 285 (525-line) and line 336 (625-line).
XTL_BFO_DIS
Bit 5-30
On power-up, a 50% duty cycle buffered output will be transmitted at the frequency found between the XTALIN and XTALOUT ports from the XTL_BFO pin #3. 0 = Enable buffer crystal clock output. [DEFAULT] 1 = Disable buffer crystal clock output. 0 = Normal operation. (DEFAULT) 1 = Disable XTALIN and XTALOUT crystal pin. Encoder must receive main clock through CLKI pin.
XTAL_PAD_DIS
Bit 6-30
100381B
Conexant
2-23
2.0 Internal Registers
2.4 Reading Registers
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (16 of 16) Bit/Register Names
Y_ALTFF[1:0]
Bit Location
Bits [1:0]-34
Bit/Register Definition
Luma alternate flicker filter selection. This bit will only have an effect when ADPT_FF is set. Y_ALTFF should always be programmed to a value greater than or equal to F_SELY. 00 = 5 line (DEFAULT) 01 = 2 line 10 = 3 line 11 = 4 line Brightness control. This is the luminance level offset. Expressed as a 2's complement number. (DEFAULT = 0x00) The luminance level offset is referenced from black, and can be adjusted from -22.31 IRE (below black) to +22.14 IRE (above black). Active video will be added to the offset level. Y_OFF is a two's complement number, such that 0x00 = 0 IRE offset 0x7 is +22.14 IRE offset and 0x8 is -22.31 IRE offset. 1 lsb =1.25 mV or .175 IRE of adjustment. Controls the sensitivity or limit of turning on the alternate flicker filter for luma in adaptive flicker filter mode. (DEFAULT = 000) Works in conjunction with register MY for contrast control. This bit field is for Luma Attenuation in discrete steps. 000 = 1.0 gain (no attenuation) (DEFAULT) 001 = 15/16 gain 010 = 7/8 gain 011 = 3/4 gain 100 = 1/2 gain 101 = 1/4 gain 110 = 1/8 gain 111 = 0 gain (Force Luma to 0) Luma Coring. Values below the YCORING[2:0] limits that follow are automatically clamped to pure black by the encoder. 000 = Bypass (DEFAULT) 001 = 1/128 of range 010 = 1/64 of range 011 = 1/32 of range 100 = 1/16 of range 101 = 1/8 of range 110 = 1/4 of range 111 = Reserved Luma Post-Flicker Filter/Scaler Horizontal Low Pass Filter: 00 = Bypass (DEFAULT) 01 = Luma Horizontal LPF1 setting 10 = Luma Horizontal LPF2 setting 11 = Luma Horizontal LPF3 setting This bit will only have an effect when ADPT_FF is set. 0 = Use the C_THRESH value to determine the threshold for turning on the alternate flicker filter setting for chrominance. (DEFAULT) 1 = Use the Y_THRESH value to determine the threshold for turning on the alternate flicker filter setting for chrominance. Both chroma and luma digital data is automatically processed with their alternate flicker filter settings when the Y_THRESH limit is exceeded.
Y_OFF[7:0]
Bits [7:0]-5A
Y_THRESH[2:0] YATTENUATE[2:0]
Bits [2:0]-36 Bits {2:0]-CA
YCORING[2:0]
Bits [5:3]-CA
YLPF[1:0]
Bits [5:4]-96
YSELECT
Bit 6-36
2-24
Conexant
100381B
3
3.0 PC Board Considerations
For optimum performance of the CX25870/871, proper CMOS layout techniques should be studied before PC board layout is begun. The layout should be optimized for lowest noise on the power and ground planes by providing good decoupling. The trace length between groups of VAA (or VDD) and GND (or VSS) pins should be as short as possible to minimize inductive ringing. A well-designed power distribution network is critical to eliminating digital switching noise. The ground plane must provide a low-impedance return path for the digital circuits. A PC board with a minimum of four layers is recommended, with layers 1 (top) and 4 (bottom) for signals, and layers 2 and 3 for ground and power, respectively.
3.1 Component Placement
Components should be placed as close as possible to the associated pin in order for traces to be connected point to point. The optimum layout places the CX25870/871 as close as possible to the power supply connector and the video output connector, as illustrated in Figure 3-1. Some other PC board layout tips to follow are: * Include a silk screen layer of labels in your layout artwork showing each component and its reference designation. Label numbered test nodes and the correct polarity of diodes and electrolytic capacitors. Leave adequate space around components so ESD transients only have minimally adverse effects on ICs. Make sure signals that need access for troubleshooting or analysis are easy to find and probe.
* *
100381B
Conexant
3-1
3.0 PC Board Considerations
3.2 Power and Ground Planes
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
3.2 Power and Ground Planes
For optimum performance, a common digital and analog ground plane and a common digital and analog power plane are recommended. The power plane should provide power to all CX25870/871 power pins, reference voltage (VREF) circuitry, and COMP decoupling. The CX25870/871 power plane should be connected to the graphics system power plane (VCC) at a single point through a ferrite bead, as illustrated in Figures 3-1 and 3-2. This bead should be located within 3 inches of the CX25870/871. The bead provides resistance to switching currents by acting as a resistor at high frequencies. A low-resistance bead should be used, such as Ferroxcube 5659065-3B, Fair-Rite 2723021447, or TDK BF45-4001. See Table 3-1 for a typical parts list for key passive components.
Figure 3-1. Power Plane Illustration
Bracket Composite #1 Luma Chrome Composite #2 3.3 V CX25870 Ferrite Bead o VCC3.3
S-Video
3.3 VAA-CX870 Analog Oscillator
Conexant (Bt835) Video Decoder
o VCC3.3 Data
5V
Clocks
TOP 4 layer board plane order:
Signals GND PWR
PCI or AGP Connector
BOTTOM Signals
100381_017
3-2
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
3.0 PC Board Considerations
3.2 Power and Ground Planes
Figure 3-2. Connection Diagram for Output Filters and Other Key Passive Components/Standard Definition TV Out Only
+1.1 V to +1.8 V CX25870/871 Power Plane CX25870/871 VAA C7 VDDL(1) VDD_CO(1) COMP VBIAS VREF C8 10 K 1% GND 75 , 75 , 75 , 75 , 1% 1% 1% 1% C9 C2-C6 + C10 C1 Ground (Power Supply Connector) FB +3.3 V (VCC)
FSADJUST VDD_VREF(1) 10 K 1%
RSET =
75 ,1%
DACA DACB DACC P P P P P: VAA SD LPF Schottky Diodes To Filter Schottky Diodes GND 1.8 H, 5% 270 pF, 5% 330 pF, 5% 22 pF, 5%
SD LPF SD LPF SD LPF SD LPF To Video Connector
DACD XTALIN XTALOUT 13.500 MHz XTAL 27 pF(2), 5% 33 pF(2), 5% DAC Output
Note(s): (1) VDDL VDD_CO, VDD_VREF must be tied to 3.3 V CX25870/871 Power Plane unless interface to low power graphics controller is required. (2) Depending on the parasitic capacitance of your PCB and loading expectations of your crystals, these capacitor values may change slightly. Generally, the 27 pF and 33 pF combination matches a 20 pF internal XTAL load. (3) No RF Modulator has been included on any of the DAC outputs. Baseband video is always generated by the CX25870.
100381_018a
100381B
Conexant
3-3
3.0 PC Board Considerations
3.2 Power and Ground Planes
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 3-3. Connection Diagram for Output Filters and Other Key Passive Components/Standard and HDTV Out
HD Filter D9 BAT54S SOT-23 5443R10-004 VAA 3.3 V
C8 33 pF 0805 5%
DAC A
DOUT R11 75.0 0805 1% L1 0.27 H 1210 C9 62 pF 5% 0805 5% 3
2
CVBS = Composite #1 or HD PB
1 3
C10 75 pF 0805 5%
2
1
HD Filter D7 BAT54S SOT-23 5443R10-004 VAA 3.3 V
C8 33 pF 0805 5%
CX25870/871
DAC B
BOUT R2 75.0 0805 1% L1 0.27 H 1210 C9 62 pF 5% 0805 5% 3
2
Y = Luma or HD Y
1 3
C10 75 pF 0805 5%
2
1
HD Filter D8 BAT54S SOT-23 5443R10-004 VAA 3.3 V
C8 33 pF 0805 5%
DAC C
COUT R7 75.0 0805 1% L1 0.27 H 1210 C9 62 pF 5% 0805 5% 3
2
C = Chroma or HD PR
1 3
C10 75 pF 0805 5%
2
1
SD Filter D9 BAT54S SOT-23 5443R10-004 VAA 3.3 V
22 pF 0805 5%
DAC D
2 R11 75.0 0805 1% L1 1.8 H 1210 C21 270 pF 5% 0805 5%
CVBS = Composite #2
3
C22 330 pF 0805 5%
NOTE(S): 1. HD Filter imparts a passband of DC to 30 MHz. 2. SD Filter imparts a passband of DC to 8 MHz.
100381_084
2
1
3-4
Conexant
1
3
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 3-1. Typical Parts List for Key Passive Components Location
C1-C7, C9 C8 C10 FB RSET TRAP -- XTAL 0.1 F Ceramic Capacitor 1.0 F Ceramic Capacitor 47 F Capacitor Ferrite Bead-Surface Mount 75 , 1% Metal Film Resistor Ceramic Resonator Schottky Diodes 13.5000 MHz Fundamental, Parallel Resonant, 20 pF load, Crystal Oscillator with 25 ppm Total Tolerance over 0 C - 70 C range.
3.0 PC Board Considerations
3.2 Power and Ground Planes
Description
Vendor Part Number
Erie RPE112Z5U104M50V, or equivalent Erie RPE11224U104M5V, or equivalent Mallory CSR13F476KM, or equivalent Fair-Rite 2743021447 Dale CMF-55C, Many others Murata TPSx.xMJ or MB2 (where x.x = sound carrier frequency in MHz) BAT85 (BAT54F Dual) HP 5082-2305 (1N6263) Siemens BAT 64-04 (Dual) See Appendix B
NOTE(S): Vendor numbers are listed only as a guide. Substitution of devices with similar characteristics will not affect CX25870/871 performance.
100381B
Conexant
3-5
1
3
23 18 17 P[13] P[12] 1 2 46 47 60 VDD3
19 20 30
VAA_3.3V D1 DA204K SOT-23 270 pF 0805 5% 330 pF 0805 5% 75.0 OHM 0805 1% C9 C10
3
3
1
1 2 3
8 7 6
P[3] P[2]
1
2
P_IN3 P_IN2 P_IN1 P_IN0 D2
DACA 68 4 5
RN3A RN3B RN3C RN3D
1632 8 7 6 5 VAA_3.3V DA204K SOT-23 75.0 OHM 0805 1% R2 P3 P2 P1 P0
P[1] P[0]
**24bit RGB multiplexed
CX25870/871
FINAL PINOUT
DACB 70
270 pF 0805 5%
330 pF 0805 5%
interface shown in diagram
1/02/01
DACC 72
**The type and location of each Video Output is selectable
J3 RCA JACK2
2
HSYNC_BI VSYNC_BI CBLANK_BI
HSYNC VSYNC CBLANK
35 36 38 HSYNC* VSYNC* BLANK*
C15 22 pF 0805 5% DAC_C
*If BLANK* pin not used, tie to 3.3V thru 10kohm resistor
CX25870_3.3V R3
DACD
3
see chart
8 7 52 51 SLEEP SLAVE PAL VBIAS VREF 76 77 FSADJUST 50 48 78 1 6 5
10K 0805 VAA_3.3V
3
1
2
1 2
DA204K SOT-23
75.0 OHM 0805 1%
RSET RESISTOR
45 44 SID (SDA) VDD_VREF SIC (SCL) 49
1
3V_SCL 3V_SDA 0805 CLKIN
54 CLKI CLKO 56 FIELD 37
3
3V_SCL 3V_SDA
VAA_3.3V
3
1
2
62 XTALOUT VSS_CO AGND_PLL VSS_X AGND_DAC AGND_DAC RESET* AGND 58 64 65 74 79 55
**R14 MUST be placed as close
33 pF 5% CRYSTAL_OUTPUT
3 XTL_BFO
VSS_SI VSS_SO
41 42 43
Figure 3-4. CX25870/871 3.3 V Recommended Layout for Connection with 3.3 V Master Device Standard Definition TV Out Only
as possible to source=encoder
0805
**Float FIELD if not used
FIELD
XTAL_CLK_Output
80 PQFP
**Float XTL_BFO if not used
R14 33 OHM RESET
53
**Series termination MUST be placed as close as possible to source=encoder
CLKOUT 0805
870FIELD_OUT
RESET
Key Crystal(Y1) Specs: - Operating Temperature: - Mode of Operation: - Load Capacitance: - Frequency Tolerance: maximum for PAL/SECAM. This includes both the Frequency Tolerance at 25deg.C and Frequency Stability over Temperature(0 -70deg.C) 20pF(for the XTAL shown), Parallel Resonant 50 PPM total maximum for NTSC; 25 PPM total Fundamental 0-70 degrees C
870CLK_OUT R15 33 OHM
CX25870
STATE IF
STATE IF
PIN#: SLEEP
PIN#=0 NORMAL
PIN#=1 SLEEP
SLAVE
MASTER
SLAVE
PAL
NTSC
PAL
ALTADDR
ADDR x88
ADDR x8A
7 6 5
Conexant
R4 10K 0805 10K 0805 10K OHM 0805 R5 R6
66
3 4
SLEEP SLAVE_CTL PAL_CTL I2C_ADDR
R8
75 OHM, 1%
0805 1% C18 C20
270 pF 0805 5%
330 pF 0805 5%
ALTADDR
SW DIP-4
3
3-6
VCC_3.3V
FB1
CX25870_3.3V
3.3V ANALOG SUPPLY AND DECOUPLING
CX25870_3.3V CX25870_3.3V
FERRITE BEAD Fair-Rite 2743021447 + 10 uF 7343
VAA_PLL VAA_DACA P[23] P[22] P[21] VAA_VREF VDD 1 73 67 80 P[20] P[19] P[18] VAA_DACB VAA_DACC VAA_DACD
C1 0.01 uF 0805 0.1 uF 0805 0.1 uF 0805
C2
C3
C4
C5 0.1 uF 0805
C6 0.1 uF 0805
C7 1.0 uF 0805
40 57 VDDL VDD_CO
If VDD_VREF = 3.3V, then the following CX25870/871 inputs must
34
be received at 3.3V levels: CLKI, HSYNC*, VSYNC*, BLANK*, and
59 69 71
the pixel inputs- P[0] - P[11]
33 32 29 28
J1 RCA JACK2 AOUT
2
If VDD_CO & VDDL = 3.3V, then the following CX25870/871 outputs
27 26 25
C8 22 pF 0805 5% DAC_A
3.2 Power and Ground Planes
will be transmitted at 3.3V levels as well: CLKO, HSYNC*, VSYNC*, BLANK*,
24 P[15] P[14] VDD1 VDD2 P[17] P[16] 2
3.0 PC Board Considerations
and FIELD. All other signals will also be at 3.3V CMOS levels unless
R1 L1 1.8uH 1210 5%
denoted otherwise.
CVBS = Composite (SCART = R)
**Resistor packs MUST be placed as close
61
VDD4 VDD_SO
as possible to graphics controller=source
33 OHM
P[11] P[10] 1 2 3 16 15 14
VDD_SI VDD5 VDD_X
C11 0.1 uF 0805
75
P_IN11 P_IN10 P_IN9 P_IN8
4 13 12 P[7] P[6] P[5] P[4] COMP 11 10 9 P[9] P[8]
RN1A RN1B RN1C RN1D 33 OHM
1 2 3 4
1632 8 7 6 5 P11 P10 P9 P8 C12 22 pF 0805 5% DAC_B
J2 RCA JACK2 BOUT
2
P_IN7 P_IN6 P_IN5 P_IN4 33 OHM L2 1.8uH 1210 5% C13
RN2A RN2B RN2C RN2D
1632 8 7 6 5 P7 P6 P5 P4
Y = LUMA (SCART = G)
C14
C = CHROMA
COUT R7 D3 C16 L3 1.8uH 1210 5%
(SCART = B)
C17
CX25870_3.3V 1.0 uF
R10 10K OHM 0805 0805 10% 0.1 uF 0805
J4 RCA JACK2
C19 22 pF 0805 5% DAC_D DOUT
2
R9
10K OHM 0805
Y_DELAY
R11 D4 DA204K SOT-23 C21 75.0 OHM 0805 1% 270 pF 0805 5% L4 1.8uH 1210 5% C22 330 pF 0805 5%
CX25870_3.3V
(SCART=CVBS) S-Video Y/C Output
P1
1 2
870_CLKIN R12 33 OHM C23 27 pF 5% 0805 13.500 MHz HC49U
63 XTALIN VSS3 VSS4 22 31 39 VSS1 VSS2 4 21
**R12 MUST be placed as close as
Y1
possible to source=data master
COUT BOUT
3 4
4
3 2 1
C24 0805
VSS/TEST VSS5
Connector
Flicker-Free Video Encoder with Ultrascale Technology
CX25870/871
100381_096
100381B
3
1
3
1
34 P[23] 33 P[22] 32 P[21] 29 P[20] 28 P[19] 27 P[18] 26 P[17] 25 P[16] 24 P[15] 23 P[14] 18 P[13] 17 P[12] P[23] P[22] P[21] 67 80 1
P[12] 1 2 1 47 60 2 61
transmitted at 1.8V levels: CLKO, HSYNC*, VSYNC*, BLANK*,BLANK*, and All transmitted at 1.8V levels: CLKO, HSYNC*, VSYNC*, and FIELD. FIELD. All
VDD5 VDD_X
other signals will be atwill beCMOS levels unless denoted denoted otherwise. other signals 3.3V at 3.3V CMOS levels unless otherwise.
33 OHM 1632 33 OHM 1 RN1A 18 2 RN1B 27
16 15 16 P[11] 15 P[10]
VDD4 VDD_SO VDD_SI
VDD3 30 VDD4 46 VDD_SO 47 VDD_SI 60 VDD5 61 VDD_X
19 20 30 46
(SCART = R) = R) (SCART
330 pF 0805 5%
3
If VDD_CO & VDDL & 1.8V, then the then the following CX25870/871will be will be If VDD_CO = VDDL = 1.8V, following CX25870/871 outputs outputs
DA204K SOT-23 270 pF 0805 5% 330 pF 0805 5%
23 18 17 P[13] VDD3
VDD1 19 VDD2 20
VAA_3.3V VAA_3.3V D1 D1 75.0 OHM 75.0 OHM C12 DA204K0805 270 pF 0805 SOT-23 0805 1% 1% 5% C13 C13
3
3
P[3] P[2] DACA 1 2 1 2 P[1] P[0] 68 DACA 68
VAA_3.3V VAA_3.3V R2 D2 R2 D2 DA204K SOT-23
3
1
3
1
P_IN3 P_IN2 P_IN1 P_IN0
P_IN3 P_IN2 P_IN1 P_IN0
RN3A RN3B RN3C RN3D
33 OHM 1 RN3A 2 RN3B 3 RN3C 4 RN3D
1 2 3 4 8 7 6 5 8 P[3] 7 P[2] 6 P[1] 5 P[0]
1632 33 OHM 8 7 6 5 P3 P2 P1 P0 P3 P2 P1 P0
1632 8 7 6 5
**Resistor packs should beshould be placed as possible to graphics controller controller **Resistor packs placed as close as close as possible to graphics
**24bit RGB multiplexed interface shown in diagramdiagram **24bit RGB multiplexed interface shown in
FINAL PINOUT PINOUT FINAL
HSYNC VSYNC CBLANK
35 36 38 HSYNC* DACB 70 DACB 70
Flicker-Free Video Encoder with Ultrascale Technology
CX25870/871 CX25870/871
1/02/01 1/02/01
DACC 72 DACC 72
75.0 OHM 75.0 OHM C16 DA204K0805 270 pF 0805 SOT-23 0805 1% 1% 5%
270 pF 0805 5%
330 pF 0805 5%
330 pF 0805 5%
**The type and location location of each **The type and of each Video Output is selectable Video Output is selectable
C18 22 pF 0805 5% C18 22 pF 0805 5% COUT COUT
2
HSYNC_BI HSYNC_BI VSYNC_BI VSYNC_BI CBLANK_BI CBLANK_BI
VSYNC* BLANK*
HSYNC VSYNC CBLANK
35 HSYNC* 36 VSYNC* 38 BLANK*
J3
3
3
1
3
1
78 FSADJUST FSADJUST VBIAS VREF 76 VREF 76 77 VBIAS 77
78 1 2 1
1 2 3 5 SLEEP SLAVE PAL ALTADDR
1 2 3
8 7 6
8 7 6
4
4
5
52 SLEEP SLEEP SLAVE_CTL SLAVE_CTL 51 PAL_CTL PAL_CTL 50 I2C_ADDR I2C_ADDR 48 52 SLEEP 51 SLAVE 50 PAL 48 ALTADDR
R8
75 OHM,75 OHM, 1% 1%
0805 C21 0805 0.1 uF 0805
R8
2
DA204K SOT-23
75.0 OHM 75.0 OHM C19 DA204K0805 270 pF 0805 SOT-23 0805 1% 1% 5%
270 pF 0805 5%
330 pF 0805 5%
330 pF 0805 5%
SW DIP-4 SW DIP-4
CX25870_3.3V CX25870_3.3V 1.0 uF
C23
J4
3
RSET RESISTOR
RSET RESISTOR
3
1
3
1
3V_SCL 3V_SDA
49 VDD_VREFVDD_VREF FIELD CLKO 56 CLKO 56 37 FIELD 37 49
3V_SCL 3V_SDA 0805 CLKIN
54 CLKI 54 CLKI
45 SIC (SCL) SIC (SCL) 44 SID (SDA) SID (SDA)
3
3V_SCL 3V_SDA
45 44
3V_SCL 3V_SDA
10K OHM 10K OHM 0805 0805 1% 1%
VAA_3.3V VAA_3.3V
3
1
2
1
0805 CLKIN
2
7 6 5
62
**R16 MUST beMUST be placed as close **R16 placed as close
33 pF 0805
3
62 XTALOUT XTALOUT
43 55 58 64 65 74 79
33 pF
3 80 PQFP 80 XTL_BFO XTL_BFO
as possible to source=encoder as possible to source=encoder
5% 5% CRYSTAL_OUTPUT CRYSTAL_OUTPUT
0805
Figure 3-5. CX25870/871 3.3 V/1.8 V Recommended Layout for Connection with 1.8 V Master Device Standard Definition TV Out Only
XTAL_CLK_Output XTAL_CLK_Output
PQFP
VSS1 21 VSS2 22 VSS3 VSS3 31 VSS4 VSS4 39 VSS/TEST VSS/TEST 41 VSS5 VSS5 42 VSS_SI VSS_SI 43 VSS_SO VSS_SO 55 VSS_CO VSS_CO 58 AGND_PLL AGND_PLL 64 VSS_X VSS_X 21 22 31 39 41 42
**Float FIELD pin if not used not used **Float FIELD pin if
FIELD FIELD
**Float XTL_BFO if not used not used **Float XTL_BFO if
R16 33 OHM RESET
53 RESET* 53 RESET*
**Series termination MUST beMUST be placed **Series termination placed as close as possible to source=encoder as close as possible to source=encoder
CLKOUT CLKOUT 0805 0805
870FIELD_OUT 870FIELD_OUT
R16 33 OHM RESET
RESET
RESET
65 AGND_DAC AGND_DAC 74 AGND_DAC AGND_DAC 79 AGND AGND
Key Crystal(Y1) Specs: Specs: Key Crystal(Y1) - Operating Temperature: 0-70 degrees degrees C - Operating Temperature: 0-70 C - Mode of Mode of Operation: - Operation: Fundamental Fundamental - Load Capacitance: - Load Capacitance: 20pF(for 20pF(for the XTAL shown), Resonant the XTAL shown), Parallel Parallel Resonant - Frequency Tolerance: 50 PPM total maximum for NTSC; 25 PPM total - Frequency Tolerance: 50 PPM total maximum for NTSC; 25 PPM total maximum for PAL/SECAM. This includes includes both the maximum for PAL/SECAM. This both the Frequency Tolerance at 25deg.C 25deg.C and Frequency Frequency Tolerance at and Frequency Stability over Temperature(0 -70deg.C) Stability over Temperature(0 -70deg.C)
870CLK_OUT 870CLK_OUT R17 33 OHM R17 33 OHM
STATE IF CX25870 STATE IF CX25870 STATE IF STATE IF
PIN#: PIN#: PIN#=0 PIN#=0 PIN#=1 PIN#=1 SLEEP SLEEP NORMAL NORMAL SLEEP SLEEP
MASTER MASTER SLAVE SLAVE SLAVE SLAVE
Title
Title
PAL
PAL NTSC NTSC
PAL
PAL
CX25870/871 3.3V/1.8V Recommended Layout CX25870/871 3.3V/1.8V Recommended Layout
Size B Date: Size Document Number Number Document B Please contact your local Conexant FAE with questions. If that If that Please contact your local Conexant FAE with questions. fails, callfails, call 1-949-483-6996 for more information. 1-949-483-6996 for more information. Date: Monday,Monday,13, 200113, 2001 August August Sheet Sheet 1 1 of of1 Rev Rev
ALTADDR ALTADDR x88 ADDR x8A ADDR x8A ADDR ADDR x88
7 6 5
Conexant
DAC_C R3
DACD
see chart see chart
10K 0805
10K 10K 0805 0805
10K 10K 0805 0805
10K OHM 10K OHM 10K 0805 0805 0805
VAA_3.3V VAA_3.3V
3
100381B
VCC_3.3V VCC_3.3V
FB1 FB1
CX25870/871
3.3V ANALOG SUPPLY AND DECOUPLING 3.3V ANALOG SUPPLY AND DECOUPLING
CX25870_3.3V CX25870_3.3V
VCC_1.8V VCC_1.8V
+ 10 uF 0.01 uF 7343 0805 0.01 0.1 uF uF 08050805 0.1 uF uF 0.1 08050805 C1 C2 C2 C3 C3 C4 C4 C5 0.1 uF uF 0.1 08050805
40 57 VDD_CO 59 69 71 73 VDDL 40 VDDL 57 VDD_CO
FB2 10 uF 7343
FB2
1.8V ANALOG SUPPLY AND DECOUPLING 1.8V ANALOG SUPPLY AND DECOUPLING
CX25870_1.8V CX25870_1.8V
FERRITE BEAD FERRITE BEAD Fair-Rite Fair-Rite + 2743021447 2743021447 C1
CX25870_3.3V CX25870_3.3V
C5 C6 0.1 uF uF 0.1 08050805
C6 C7 0.1 uF uF 1.0 08050805
C7 1.0 uF 0805
C8 C9 0.1 uF 0805
32 29 1 VDD 34 33
C9 C10
C10
FERRITE BEAD FERRITE BEAD Fair-Rite Fair-Rite + + 2743021447 2743021447 C8 10 uF 7343
59 VAA_PLL VAA_PLL 69 VAA_DACAVAA_DACA 71 VAA_DACBVAA_DACB 73 VAA_DACCVAA_DACC 67 VAA_DACDVAA_DACD 80 VAA_VREF VAA_VREF
10 uF 0.01 uF 7343 0805
0.01 0.1 uF uF 08050805
J1
J1 RCA JACK2 RCA JACK2
C11 22 pF 0805 5% DAC_A DAC_A AOUT AOUT
2
C11 22 pF 0805 5%
2
If VDD_VREF = 1.8V / 2, 1.8V / 2, then the following CX25870/871 inputs must If VDD_VREF = then the following CX25870/871 inputs must
VDD 24 P[15] P[14] VDD1 VDD2 P[16] 2 2
be received receivedlevels: CLKI, HSYNC*, VSYNC*, BLANK*,BLANK*, and the be at 1.8V at 1.8V levels: CLKI, HSYNC*, VSYNC*, and the
28 27 26 25
P[20] P[19] P[18] P[17]
pixel inputs- P[0] - P[11] - P[11] pixel inputs- P[0]
R1 R1
L1 1.8uH 1210 5% C12
L1 1.8uH 1210 5%
CVBS = CVBS = Composite Composite
C14 0.1 uF 0805
75
C14 0.1 uF 0805 DAC_B DAC_B
P_IN11 P_IN10 P_IN9 P_IN8
3 RN1C 4 RN1D 14 13 12 11 10 9 COMP P[7] 11 P[6] 10 P[5] 9 P[4] 75 COMP P[7] P[6] P[5] P[4] 12 14 P[9] 13 P[8] 3 4 6 5
P_IN11 P_IN10 P_IN9 P_IN8 33 OHM 1632 33 OHM 1 RN2A 18
2 RN2B 3 RN2C 4 RN2D 2 3 4 7 6 5
RN1A RN1B RN1C RN1D
P[11] P[10] P[9] P[8]
1632 8 7 6 5 P11 P10 P9 P8 C15 22 pF 0805 5% P11 P10 P9 P8 C15 22 pF 0805 5%
J2
J2 RCA JACK2 RCA JACK2 BOUT BOUT
2 2
P_IN7 P_IN6 P_IN5 P_IN4
P_IN7 P_IN6 P_IN5 P_IN4
RN2A RN2B RN2C RN2D L2 1.8uH 1210 5% C16
1632 8 7 6 5 P7 P6 P5 P4 P7 P6 P5 P4
Y = LUMA Y = LUMA
L2 1.8uH 1210 5% C17 C17
(SCART = G) = G) (SCART
J3 RCA JACK2 RCA JACK2
2
*If BLANK* pin not used, not to VDDL thru 10kohm resistor resistor *If BLANK* pin tie used, tie to VDDL thru 10kohm
DAC_C
CX25870_3.3V CX25870_3.3V R3 R4 R4 R5 R5 R6 R6
66 DACD 66
C = CHROMA C = CHROMA
R7 D3 D3 R7 L3 1.8uH 1210 5% C19 L3 1.8uH 1210 5% C20 C20
(SCART = B) = B) (SCART
J4 RCA JACK2 RCA JACK2 DAC_D DAC_D DOUT DOUT
2 2
R9 R11 R11
R9
R10
R10
0805 10%
C21 C23 0.1 uF 0805 1.0 uF 0805 10%
CX870_1.8V CX870_1.8V
C22 22 pF 0805 5%
C22 22 pF 0805 5%
10K OHM 10K OHM OHM 10K OHM 10K 0805 0805 0805 0805
Y_DELAY Y_DELAY
R12 D4 DA204K SOT-23 D4 R12 75.0 OHM 75.0 OHM C24 DA204K0805 0805 270 pF SOT-23 1% 1% 0805 5% L4 1.8uH 1210 5% C24 270 pF 0805 5% L4 1.8uH 1210 5% C25 330 pF 0805 5% C25 330 pF 0805 5%
(SCART=CVBS) (SCART=CVBS) S-Video S-Video Y/C Output Y/C Output
P1
1 2 3
870_CLKIN870_CLKIN 33 OHM 5% 0805
4 4 63 XTALIN 63 XTALIN VSS1 VSS2
**R13 MUST beMUST be placed as close as R13 **R13 placed as close as
C26 27 pF C26 27 pF
R13 33 OHM
P1 4 R14 R14 10K OHM 10K OHM 0805 0805 1% 1% COUT BOUT COUT BOUT
4 1 2 3 4
possible to source=data master master possible to source=data
Y1 5% Y1 0805 13.500 MHz 13.500 MHz HC49U HC49U
4 3 2 2 1
3 1
C27 0805
C27 0805
Connector Connector
3.0 PC Board Considerations
3.2 Power and Ground Planes
100381_097
100381_097
3-7
1
3.0 PC Board Considerations
3.3 Recommended Schematics and Layout for CX25870/871
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
3.3 Recommended Schematics and Layout for CX25870/871
For the CX25870/871 to operate at an optimal technical level, it is imperative to adopt the passive components, values, tolerances, and guidelines contained in the following figures. Conexant has done extensive lab testing with these components, and found that they yield the best combination of performance and price. The complete schematic diagram for a 3.3 V only design is illustrated in Figure 3-4. The complete schematic diagram for a mixed 3.3 V and 1.8 V design environment is illustrated in Figure 3-5. For a complete schematic diagram for a mixed 3.3V and lower voltage (1.5 V or 1.1 V) design environment, request assistance from your local FAE. The finished schematic for the 3.3 V/1.5 V or 3.3 V/1.1 V case will look similar to Figure 3-5. Substitution of resistors, capacitors, inductors, and crystals with nonrecommended values or greater than recommended tolerances may degrade the video output quality of the CX25870/871 encoder.
3-8
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
3.0 PC Board Considerations
3.4 Decoupling
3.4 Decoupling
3.4.1 Device Decoupling
For optimum performance, all capacitors should be located as close as possible to the device, and the shortest possible leads (consistent with reliable operation) should be used to reduce the lead inductance. Chip capacitors are recommended for minimum lead inductance. Radial lead ceramic capacitors can be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. Values are chosen to have self-resonance above the pixel clock.
3.4.2 Power Supply Decoupling
The best power supply performance is obtained with a 0.1 F ceramic capacitor decoupling each group of VAA pins and each group of VDD pins to GND. The capacitors should be placed as close as possible to the device VAA/VDD pins and GND pins and connected with short, wide traces. The 47 F capacitor shown in Figure 3-2 is for low-frequency power supply ripple; the 0.1 F capacitors are for high-frequency power supply noise rejection. Inclusion of a 0.01 F and a 1.0 F capacitor between the group of VAA/VDD pins and GND/VSS pins will improve power supply decoupling at intermediate frequencies as well. When a linear regulator is used, the proper power-up sequence must be verified to prevent latchup. A linear regulator is recommended to filter the analog power supply if the power supply noise is greater than or equal to 200 mV. This is especially important when a switching power supply is used, or low voltage interface is implemented, and the switching frequency is close to the raster scan frequency. About 5 percent of the power supply hum and ripple noise less than 1 MHz will couple onto the analog outputs.
3.4.3 COMP Decoupling
The COMP pin must be decoupled to the closest VAA pin, typically with a 0.1 F ceramic capacitor. Low-frequency supply noise will require a larger value. The COMP capacitor must be as close as possible to the COMP and VAA pins. A surface-mount ceramic chip capacitor is preferred for minimal lead inductance. Lead inductance degrades the noise rejection of the circuit. Short, wide traces will also reduce lead inductance.
3.4.4 VREF Decoupling
A 1.0 F ceramic capacitor should be used to decouple this input to GND.
3.4.5 VBIAS Decoupling
A 0.1 F ceramic capacitor should be used to decouple this output to GND.
100381B
Conexant
3-9
3.0 PC Board Considerations
3.5 Signal Interconnect
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
3.5 Signal Interconnect
3.5.1 Digital Signal Interconnect
The digital inputs to the CX25870/871 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane or analog output signals. Most of the noise on the analog outputs will be caused by fast transitioning clock edges, data edges (less than 3 ns), and overshoot, undershoot, and ringing on the digital inputs. The digital edge rates should not be faster than necessary because feedthrough noise is proportional to the digital edge rates. Lower-speed applications will benefit from using lower-speed logic (3-5 ns edge rates) to reduce data-related noise on the analog outputs. Transmission lines will mismatch if the lines do not match the source and destination impedance. This will degrade signal fidelity if the line length reflection time is greater than one-fourth the signal edge time. Line termination or line-length reduction is the solution. For example, logic edge rates of 2 ns require line lengths of less than 4 inches without use of termination. Ringing can be reduced by damping the line with a series resistor (30-50 ). Radiation of digital signals can also be picked up by the analog circuitry. This is prevented by reducing the digital edge rates (rise/fall time), minimizing ringing with damping resistors, and minimizing coupling through PC board capacitance by routing the digital signals at a 90-degree angle to any analog signals. The clock driver and all other digital devices must be adequately decoupled to prevent noise generated by the digital devices from coupling into the analog circuitry.
3.5.2 Analog Signal Interconnect
The CX25870/871 analog output traces should be located as close as possible to the output connectors and be of equal length to minimize noise pickup and reflections caused by impedance mismatch. The analog outputs are susceptible to crosstalk from digital lines; therefore digital traces must not be routed under or adjacent to the analog output traces. To maximize the high-frequency power supply rejection, the video output signals should overlay the ground plane. For maximum performance, the analog video output impedance, cable impedance, and load impedance should be the same. The load resistor connection between the video outputs and GND should be as close as possible to the CX25870/871 to minimize reflections. Unused DAC analog outputs should be left floating.
3-10
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
3.0 PC Board Considerations
3.6 Applications Information
3.6 Applications Information
3.6.1 Changes Required to Accommodate CX25870/871 in Bt868/869-Designs
3.6.1.1 Software The CX25870/871 is software backward compatible with Conexant's first generation VGA Encoder, the Bt868/869. This means that all register indices for the Bt868/869 were carried forward to the exact same indices for the CX25870/871. For Conexant's second generation encoder, new registers were added, but the actual addresses used were outside of the 0x6C to 0xD6 range reserved for the Bt868/869 legacy functionality. Some reserved bits within the Bt868/869 did take on significance with the CX25870/871 where necessary.
Table 3-2. Relative Register Map for CX25870/871
Shared CX25870/871 & Bt868/869 registers Register Addresses 0x00 to 0x04 (Read Only) (Must be accessed through `Legacy' read procedure with ESTATUS[1:0] bits in Bt868/869) (`Standard' or `Legacy' read-back procedure ok for CX25870/871) CX25870/871 specific registers Register Address 0x06(Read Only) and Register Addresses 0x28E to 0x6A (Read/Write) Shared CX25870/871 & Bt868/869 registers Register Address 0x6C(Read/Write) to Register Address 0xD6(Read/Write) CX25870/871 specific register Register Address 0xD8(Read/Write)
The most significant difference in software between the two encoders is the fact that the CX25870/871 can be read from using the Standard serial method as well as the Legacy serial method. To use the Standard procedure, the master issues CX25870's device ID and subaddress in consecutive bytes, and the slave acknowledges with a pulse after each transaction. Upon completion of these 2 steps, the slave transmits the final byte which contains the 8 bits of data. The Bt868/869 cannot be read from in this manner and instead relies solely on the Legacy method. This process is explained step-by-step in the `TV Auto-Detection Procedures' section of this specification. Another difference in terms of software between the two encoders is the power-up video output routing. The CX25870 after power-up or a signal-driven reset transmits Video0 = composite on DAC_A, Video1 = Luma (Y) on DAC_B, Video2 = Chroma (C) on DAC_C, and Video3 = Luma Delay on DAC_D. The Bt868 was different in this respect. On power-up, it sent out Video0 = composite from DAC_A, DAC_B, and DAC_C. Reprogramming register 0xCE correctly ensures proper video output routing.
100381B
Conexant
3-11
3.0 PC Board Considerations
3.6 Applications Information
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Another difference between the two encoders is the default video output routing through the on-chip DACs. On power-up, the Bt868 transmitted Video[0] = Composite from all three of its DACs. Due to the popularity of S-Video out, the CX25871, on power-up, broadcasts Video[0] = Composite from DAC_A, Video[1] = Luminance from DAC_B, Video[2] = Chrominance from DAC_C, and Video[3] = Delayed Luminance from DAC_D. For Bt868 drivers that did not program register 0xCE, this step may be necessary to re-route the Video outputs with the CX25870. As a result of software register compatibility, no modifications to a customer's source code are required to enable the same features that exist within both Conexant VGA encoders. Of course, to exploit the new features within the CX25870/871, such as display of 1024x768 resolution on a TV HDTV output, , SECAM output, and others, some software changes and new register sets will be necessary. This usually equates to the release of a new driver and/or graphics BIOS for support of the CX25870. 3.6.1.2 Hardware Similarly, the Bt868/869 is pin-for-pin backward compatible with the newest Conexant encoder. Both devices are housed in exactly the same compact 80-pin, [14 mm x 14 mm x 2.4 mm] plastic PQFP package. Furthermore, aside from pins 2, 3, 65, 66, and 67, which were no connects within the Bt868/869, the CX25870/871 is identical in its pinout to the previous generation. Consequently, if the customer's Bt868-designed PCB actually has no connects for the pins listed as N/C on the Bt868/869, then no PC board changes are needed except for some passive component stuffing changes when upgrading to the CX25870/871. However, if the Bt868/869 N/C pins were actually grounded or utilization of the new external features within the CX25870/871 is desired, then a few changes to a customer's Bt868/869-based PC Board are definitely required to accommodate the new CX25870/871. Table 3-3 summarizes all the likely alterations that need to be performed to existing designs.
Table 3-3. Hardware Modifications to Bt868/869-based PCB Required to Accommodate the CX25870/871 (1 of 3) Pin #
1
Bt868/9 Pin Name
AGND
CX25870/1 Pin Name
VDD
Comment
This pin should be tied to VDD (3.3V) for both the CX25870/1 and Bt868/9, so the encoder's output video levels match the IRE levels that it was designed to transmit. Conexant has seen 2-3 IRE excursions away from the correct color bar and other test pattern IRE levels and have verified that either encoder's pin #1 being tied to GND to be the root cause. An output video difference of 2-3 IRE is a very small amplitude AND would only be noticeable if you used a VM700T from Tektronix or some other advanced piece of video measuring equipment. Visually, it is quite difficult to even detect a 2-3 IRE excursion. In conclusion, tie Pin #1 which was the Bt868/9's `AGND' to VDD/VAA = 3.3V for both the CX25870/1 and Bt868/9 for best operation. Rename this pin (#1) on any schematics so it says 'VDD.' The digital power pin needs to be tied to 3.3V. This was a no connect for the Bt868/9. The buffered crystal clock output pin should be floated if not used. This was a no connect for the Bt868/9. For CX25870/1-designs, a small (e.g. 33 ohm) series resistor should be added in series to XTL_BFO as close as possible to the signal source device. This reduces overshoot and undershoot on this signal as it changes states.
2 3
N/C N/C
VDD XTL_BFO
3-12
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
3.0 PC Board Considerations
3.6 Applications Information
Table 3-3. Hardware Modifications to Bt868/869-based PCB Required to Accommodate the CX25870/871 (2 of 3)
49 VDDMAX VDD_VREF Pin 49 has been renamed for the CX25870/1. For 3.3V swings on the interface signals for CX25870/1-designs, this pin should be tied directly to 3.3V as was the case with Bt868/9-designs. For lower voltage swings for the digital interface signals, using a voltage divider circuit or some other method, tie the CX25870/871's VDD_VREF input (pin 49) to (VDDL / 2). See Figure 3-5 for an illustration of this concept. If the desired video output at power-up is PAL, then a 10 k pull-up resistor is recommended for this pin for CX25870/1-designs. No pull-up resistor was advocated for Bt868/9-designs. If the desired video output at power-up is NTSC, then this pin should be tied directly to GND. If desired interface at power-up is slave or pseudo-master (i.e. slave video timing), then a 10 k pull-up resistor is recommended for this pin for CX25870/1-designs. No pull-up resistor was advocated for Bt868/9-designs. If desired interface at power-up is master (i.e. master video timing), then this pin should be tied directly to GND. If desired power management state at power-up is Normal Operation, then this pin should be tied directly to GND. If desired power management state at power-up is Sleep, then a 10 k pull-up resistor is recommended for this pin for CX25870/1-designs. No pull-up resistor was advocated for Bt868/9-designs. The recommended capacitor value from XTALIN to GND has been altered from 33 pF to 27 pF for a 20 pF load crystal. This ensures an output-to-input voltage gain sufficient to make up signal losses through the crystal since the ratio of CXTALOUT / CXTALIN = 1.1 to 1.5. The buffered clock crystal output frequency, which can be measured from the CX25870/1's XTL_BFO output port, should be within 25 ppM = +/- 337 Hz. of 13.5000 MHz. at all times. The high amount of tolerance is necessary so the encoder can generate sufficient accuracy for the subcarrier frequencies for SECAM, PAL, and NTSC. If this type of accuracy does not exist when using CXTALIN = 27 pF then CXTALIN should be increased to 30 pF or 33 pF and the frequency re-measured. Different PCBs exhibit different amounts of parasitic capacitance so one value for CXTALIN does not necessarily fit for all designs. For Bt868/9-designs, CXTALIN and CXTALOUT were recommended to be equal (33 pF). The 1 M resistor, a requirement of Bt868/9-designs as an external passive between these 2 pins, is no longer necessary with CX25870/1-designs. If it is present, then this has no adverse effects on the CX25870/1's overall video performance. Whether or not DACD is actually used as a video output within the CX25870/1 design, this pin must be tied to GND. For Bt868/9-based designs, this pin was a No Connect and for best performance should be tied to GND or left open. Pin 66 for the CX25870/1 is the fourth DAC = DACD. If DACD is used, connect this output to a video connector. If DACD is not used, leave this pin no connected for CX25870/1-designs. The circuitry for the low pass filter for DACD will also need to be added for CX25870/1 designs. For Bt868/9-based designs, this pin was a No Connect and for best performance should be tied to GND or left open. This is the power pin for DACD. Whether or not DACD is actually used within the design, this pin must be tied to VDD=VAA=3.3V for all CX25870/1-designs. For Bt868/9-based designs, this pin was a No Connect and for best performance should be tied to GND or left open.
50
PAL
PAL
51
SLAVE
SLAVE
52
SLEEP
SLEEP
62 63
XTALOUT XTALIN
XTALOUT XTALIN
65
N/C
AGND_DAC
66
N/C
DACD
67
N/C
VAA_DACD
100381B
Conexant
3-13
3.0 PC Board Considerations
3.6 Applications Information
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 3-3. Hardware Modifications to Bt868/869-based PCB Required to Accommodate the CX25870/871 (3 of 3)
75 COMP COMP A 0-10 ohm resistor between COMP and 0.1 F capacitor (which is connected to VAA) was originally recommended for Bt868/9-designs. The 0-10 ohm resistor placed between the 0.1 F cap and the COMP pin was recommended to better tune the COMP circuit to prevent an internal op-amp from oscillating. Based on the Bt868/9's DAC performance over time and the CX25870/1's continued usage of these same DACs, this resistor was deemed to not be necessary and should be removed for all CX25870/1 designs. Capacitor from VREF to GND must be 1.0 F for the CX25870/1. Capacitor from VREF to GND must be 0.1 F for the Bt868/9. RSET, the resistor from FSADJUST pin to GND, must be 75 , +/- 1% for all CX25870/1-based designs. RSET must be 100 ohm, +/- 1% for all Bt868/9-based designs.
76 78
VREF FSADJUST
VREF FSADJUST
NOTE(S):
N/C = No connect
To ensure proper operation of the CX25870/871, the designer must adhere to each recommendation contained in Table 3-3.
3-14
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
3.0 PC Board Considerations
3.6 Applications Information
3.6.2 Programmable Video Adjustment Controls
The quality of the TV Out picture can be altered depending on the digital input content, the settings of various output video adjustment control registers, and the TV itself. The values of the CX25870/871's Y_OFF, MY, Y_ATTEN, MCB, MCR, C_ATTEN, and PHASE_OFF registers all definitely impact the perceived quality of the analog NTSC/PAL/SECAM video signal. For this reason, for graphics cards that utilize the encoder, Conexant recommends the inclusion of a Graphical User Interface (GUI) for TV Out. By designing this intelligent control panel, the end-user can improve his TV image quality by adjusting the proper slider or other controls at his disposal. Behind these controls, intelligence must be embedded in the TV Out source code and driver so the values of certain registers get adjusted depending on the status of the radio button, checkbox, slider, or pulldown menu. An illustration of a sample GUI for TV Out is shown in Figure 3-6.
Figure 3-6. Conexant Recommended TV Out GUI for CX25870/871
100381_101
100381B
Conexant
3-15
3.0 PC Board Considerations
3.6 Applications Information
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
3.6.2.1 Contrast
Contrast is a video quality that refers to how far the whitest whites are from the blackest blacks in an analog video waveform. If the peak white is far away from the peak black, the image is said to have high contrast. With high contrast, the image is very pure like a black and white tile floor. If the two parameters are very close together, the image is said to have poor, or low, contrast. With low amounts of contrast, an image may be referred to as being washed-out. Instead of easily recognized black portions of the image versus white parts, the image with low contrast looks gray. Register MY[7:0] in conjunction with register Y_ATTENUATE[2:0] controls adjustment of contrast. Y_ATTENUATE has 8 possible values ranging from 1.0 gain (No attenuation) to 0 gain (Force Luminance to 0). Conexant recommends inclusion of an 8-level slider to control the Contrast level. Each single movement of the slider should reprogram this bit field to a different fractional value. Lab testing has shown that values from 3/4 gain (Y_ATTENUATE=011) to 15/16 gain (i.e., 001) yield the crispest TV picture. Register MY modifies the luminance multiplier allowing for a larger or smaller luminance range. For more drastic changes in the Contrast, change MY. For more subtle changes, shifting the Y_OFF register as the end-user moves the slider should be sufficient. Since the difference between contrast and brightness is usually understood by video professionals only, Conexant recommends the designer increment or decrement the YATTENUATE[2:0] field for either brightness or contrast adjustments. Saturation is the amount of color present. For example, a lightly saturated green looks olive-green to gray while a fully saturated green looks like the color of a pine tree. Saturation does not mean the brightness of a color, just how much pigment is used to make the color itself. The less pigment, the less saturated the color is, effectively adding white to the pure color. The amount of Saturation is controlled by the bit field named CATTENUATE[2:0]. CATTENUATE has eight possible values ranging from 1.0 gain (No attenuation) to 0 gain (Force Chrominance to 0). Conexant recommends inclusion of an 8-level slider to control Saturation level. Each single movement of the slider should reprogram this bit field to a different fractional value. Lab testing has shown that values from 3/4 gain (CATTENUATE=011) to 1.0 gain (i.e., 000) yield the crispest TV picture. Brightness is defined to be the intensity of the video level and refers to how much light is emitted from the display. The amount of Brightness is controlled by the register named Y_OFF[7:0]. Y_OFF[7:0] is a 2s complement number, such that a value of 0x00 is 0 IRE offset, a value of 0x7F is an increase of 22.14 IRE above black level. Active video will then be added to the offset level set by the Y_OFF value. Since the difference between contrast and brightness is usually understood by video professionals only, Conexant recommends the designer increment or decrement the YATTENUATE[2:0] field for either brightness or contrast adjustments.
3.6.2.2 Saturation
3.6.2.3 Brightness
3-16
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
3.0 PC Board Considerations
3.6 Applications Information
3.6.2.4 Hue
Hue refers to the wavelength of the color. That means that hue is the term used to represent the base color-red, green, magenta, yellow, and so forth. Hue is completely separate from the intensity or the saturation of the color. For example, a red hue could look brown at low saturation, fire-engine red at a higher level of saturation, or pink at a high brightness level. All three colors have the same hue however. Occasionally, the end user may need to alter the hue. The method for adjusting this parameter with the CX25870/871 is to program a different value to the HUE_ADJ register. This method changes the hue in the composite and S-Video signals for NTSC, PAL, and SECAM waveforms according to the following equation: Desired Phase Offset (in degrees) = [360 / 256] * (HUE_ADJ) A slider labeled `HUE' should be included in the GUI so minor alterations (20) in this parameter are possible. Major alterations(>20) in the phase offset are not recommended since dramatic hue shifts will result in different colors than the original. Occasionally, drastic phase shifts occur at the borders of dialog boxes within applications programs and with certain combinations of text and background colors. This is due to the primary and secondary colors being at opposite ends of the UV hue spectrum. The result of these phase differences is that the edges or text look blurry to the observer. The CX25870/871 has a bit field available named PKFIL_SEL[1:0] to sharpen these edges so they look crisper on the television. Four choices are available, each of which enables a different type of peaking filter. The 0 dB (Bypass) filter is the defaulted level while gains of 1 dB, 2 dB, and 3.5 dB are also possible. Dot crawl refers to a specific image artifact that is the result of the NTSC standard. When some computer generated text shows up on top of a video clip being shown, close viewing of the TV will show some pixels or jaggies rolling up or down the picture in the area of a dialog box's edges. Another term for this phenomenon is creepy-crawlies or the zipper effect. Conexant has derived software code to minimize the dot crawl. This is not a register or bit within the CX25870/871 but rather a complicated software algorithm that modifies the 90-degree color subcarrier shift exhibited in four consecutive NTSC fields. To obtain this code, file a request with your local Conexant sales office. The algorithm/function for dot crawl should be enabled with the NTSC Composite output only. It will have no effect for PAL or SECAM outputs.
3.6.2.5 Sharpness
3.6.2.6 Dot Crawl
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Conexant
3-17
3.0 PC Board Considerations
3.6 Applications Information
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
3.6.2.7 Standard and Adaptive Flicker Filter
Flicker occurs when the refresh rate of the video is too low. In digital encoders, flicker can also occur when processing an image that contains many fine vertical divisions such as lines that are only 1 or 2 lines wide. When the encoder stores, combines (by vertically interpolating data), and converts two consecutive incoming frames into 1 output field, portions of the image containing just a few lines can be placed on different analog output lines. Since the position of the output line is not equivalent from field to field, it appears to flicker at the vertical refresh rate. This annoying artifact can be eliminated by selecting an appropriate flicker filter setting, one that trades off vertical resolution and text clarity against flicker reduction. The flicker filter slider shown in Figure 3-6 modifies the F_SELY[2:0] and F_SELC[2:0] bit fields together anytime the end-user changes the particular level. Internal testing has shown that certain application programs such as spreadsheets look best with more flicker filtering while others, such as games and DVD movies, look best with less. In addition, the active resolution also affects the amount of flicker filtering required. 640x480 and lower resolutions rarely require a maximum flicker filter setting, whereas the 1024x768 resolution often does. With five standard flicker filter levels available, Conexant recommends programming the following bit values according to the slider level.
F_SELY[2:0]
000 = 5 line. DIS_FFILT = 0. 011 = 4 line. DIS_FFILT = 0. 010 = 3 line. DIS_FFILT = 0. 001 = 2 line. DIS_FFILT = 0. Do not care. DIS_FFILT = 1.
Flicker Filter Slider Level
Level 5 = Maximum Level 4 Level 3 Level 2 Level 1 = Minimum
F_SELC[2:0]
011 = 4 line. DIS_FFILT = 0. 010 = 3 line. DIS_FFILT = 0. 001 = 2 line. DIS_FFILT = 0. 001 = 2 line. DIS_FFILT = 0. Do not care. DIS_FFILT = 1.
NOTE:
The optimal performance for the Standard Flicker Filter is usually achieved by configuring F_SELC to 1 line less than F_SELY.
The CX25870/871 also has an adaptive flicker filter (i.e., Adaptive FF). This feature is explained in section 1 of the data sheet. The recommended TV Out Graphical User Interface allows the usage of the adaptive flicker filter only if the box to enable it is checked. Once this is done, the ADPT_FF bit should get set (=1).
3-18
Conexant
100381B
100381B Adaptive Flicker Filter Bit/Bit Field Settings Register 0x34 FFRTN
On Off On Off On 1 1 0 0 1 0 1 0 1 0 9B 9B 80 80 80
Table 3-4. CX25870 Optimal Adaptive Flicker Filter Bit Settings by Active Resolution Register 0x36 Final Hex Value
C0 24 92 64 F6
CX25870/871
Adaptive Flicker Filter Slider Level Y ALTFF
4-line 4-line 5-line 5-line 5-line 5-line 110 110 On 5-line 100 100 On 5-line 010 010 Off 4-line 100 100 Off 4-line 000 000 On
ADPT FF
C ALTFF
Y THRESH C THRESH
Y SELECT
BYYCR
CHROMA BW
Final Hex Value
Level 1=Min=640x480
On=Checked
Level 2
On=Checked
Level 3 = 800x600
On=Checked
Level 4
On=Checked
Flicker-Free Video Encoder with Ultrascale Technology
Level 5=Max=1024x768
On=Checked
Conexant
3.0 PC Board Considerations
3.6 Applications Information
3-19
3.0 PC Board Considerations
3.6 Applications Information
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
When the Adaptive Flicker Filter is on, the Standard Flicker Filter continues to work normally. Indeed, many of the lines and/or pixels will still be filtered at the more moderate standard flicker filter level. However, as the encoder analyzes and processes each pixel, it will periodically come across certain regions requiring a more aggressive filter setting. For these areas only, more forceful Adaptive Flicker Filter value is used. With the dynamic ability of the CX25870, the end-user can enjoy an optimal TV Out environment without having to manually adjust the amount of flicker filtering depending on his given application. The CX25870 provides this functionality so long as the Adaptive Flicker Filter slider and control boxes are included. When the adaptive element is turned on, an additional five flicker reduction settings can be applied by moving the control pad to another level. Through testing, Conexant recommends the following bit settings get reprogrammed according to the state of the Adaptive Flicker Filter slider. Integrating both flicker filter sliders and the correct intelligence behind them makes the CX25870/871 ideal for Internet browsing, DVD movie watching, or game playing by overcoming many of the quality problems like image flicker, illegible text, and low-definition graphics that plague other TV encoders. 3.6.2.8 Position There are many TV manufacturers, and most models display the active picture in a slightly different position relative to the bezel of the television itself. To allow the end-user the ability to position the TV picture directly in the middle of his screen, or any other reasonable location, Conexant recommends inclusion of several Position control buttons. There should be four directional controls included; two for horizontal adjustment and two for vertical adjustment. For practical usage, the maximum or limit adjustment amounts should be 25 pixels horizontally and 10 lines vertically from the default position. Values greater than these cause a good portion of the active region to be hidden behind the bezel of the TV thus rendering this area useless. From experience, Conexant recommends incrementing the graphics controller's HSYNC_START register by 5 pixels every time the LEFT(= `-') or RIGHT(= `+') button is clicked within the GUI. Every mouse click will also require reprogramming the CX25870/871's H_BLANKI register so the active data does not get chopped off on the opposite side. Vertically, the software driver should add or subtract two lines from the prior vertical position every time the UP(= `+') or DOWN(= `-') button is clicked within the GUI. This means that the VSYNC_START register should be increased or decreased by two lines for every vertical click by the end-user. The corresponding modification that needs to be made to the CX25870/871 is an add/subtract of two lines to the original value in its V_BLANKI register. As an illustration, assume the end user clicked on the Right button once. Internally, this action would mean that the graphics controller's new HSYNC_START register value needs to be {HSYNC_STARTdefault -5 pixels}. As the timing master, this would force the controller to issue its HSYNC* digital signal's leading edge five pixel clock cycles earlier in time. The software engineer also must add five pixels to the controller's HSYNC_END register to maintain the original HSYNC* pulse duration (8-20 pixels is common). Finally, within the CX25870/871, the H_BLANKI[9:0] register must be increased by five pixels so the encoder can accommodate the five extra pixels of blanking to start each line and still display the original active portion of the line.
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Flicker-Free Video Encoder with Ultrascale Technology
3.0 PC Board Considerations
3.6 Applications Information
Now, assume the end-user clicked on the Down button once. This action dictates that more blanking will exist before the active region is displayed. This operation requires decrementing the graphics controller's new VSYNC_START register value to (VSYNC_STARTdefault - 5 lines). As the timing master, this would force the controller to issue its VSYNC* digital signal's leading edge five lines earlier in time than before. The software engineer must also subtract five lines to the controller's VSYNC_END register to maintain the same VSYNC* pulse duration (nominally two-to-six lines). Within the encoder, the V_BLANKI[7:0] register must be incremented by 5 lines so the encoder can accommodate the five more lines of blanking required to start the field and still display the original active area of the frame. For an explanation of the Left and Up buttons, simply apply the opposite offsets to the values explained for the Right and Down operations. Remember that SYNC_START/END always works in the opposite direction of picture movement. If the Position control works correctly, the end user should see a gradual change to either the X and Y position of the active image after each corresponding mouse click. 3.6.2.9 Size This control pad is used by the end-user to change the active X and Y dimensions of the TV Out picture. This is done by modifying the amount of horizontal (X dimension) and vertical (Y dimension) overscan compensation. Ideally, there should be four directional controls included: two for horizontal adjustment and two for vertical adjustment. For practical usage, the maximum amounts of Horizontal Overscan Compensation (HOC) and Vertical Overscan Compensation (VOC) should be limited to 25 percent (or three mouse clicks in any direction). The minimal amounts of HOC and VOC should be capped at 10 percent since percentages smaller than this often make the TV image so large that all edges are behind the bezel of the TV, rendering the outer regions of the Windows desktop useless. Based on testing, Conexant recommends changing the HOC percentage by ~ 3 percent from its previous value for each`+ or - horizontal mouse click within the GUI. The + symbol denotes a larger picture size in that direction (and a decrease in the amount of horizontal blanking or HOC percent) and a - sign corresponds to smaller picture size. In addition, TV Out software designers should vary the VOC percentage by ~ 3 percent from its previous value for each + or - vertical mouse click within the GUI. The + symbol denotes a larger picture size in that direction and a - sign corresponds to smaller picture size (and an increase in the amount of vertical blanking or VOC percent). The overscan percentages horizontally and vertically are independent of each other. However, the TV Out picture looks best when HOC and VOC are equal or within 2 percent of each other. Having realized this fact, Conexant has incorporated many autoconfiguration modes that have a minimal difference (i.e., Delta) between the HOC and VOC ratios.
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3.6 Applications Information
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
The autoconfiguration modes for the CX25870/871 that pertain to the desktop resolutions are summarized in Figures 3-5 through 3-12.
Figure 3-7. CX25870/871 Autoconfiguration Modes for 640x480 RGB In, NTSC Out Desktop Resolutions
(# of Logical Clicks)
VOC
Increase Vert.
640 x 480 RGB in, NTSC out Autoconfig. Mode #0 13.78 % 13.58 %
+1
0
Decrease Vert. Vertically Const.
Autoconfig. Mode #32 18.34 % 19.34 % -1
Decrease Horiz.
-1
0
Horizontally Constant
+1
Increase Horiz.
HOC
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Figure 3-8. CX25870/871 Autoconfiguration Modes for 640x480 RGB In, PAL-BDGHI Out Desktop Resolutions
(# of Logical Clicks)
VOC
640 x 480 RGB in, PAL-BDGHI out Autoconfig. Mode #17
+1 13.63 % 13.19 % Autoconfig. Mode #1 0 16.55 % 16.66 % Autoconfig. Mode #33 -1 20.27 % 19.79 % -1 0 +1 HOC
(# of Logical Clicks)
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Flicker-Free Video Encoder with Ultrascale Technology
3.0 PC Board Considerations
3.6 Applications Information
Figure 3-9. CX25870/871 Autoconfiguration Modes for 800 x 600 RGB In, NTSC Out Desktop Resolutions
(# of Logical Clicks)
VOC Autoconfig. Mode #2 +1 21.62 % 11.52 %
800 x 600 RGB in, NTSC out Autoconfig. Mode #18 13.79 % 13.58 % Autoconfig. Mode #40
0
15.59 % 15.65 % Autoconfig. Mode #34
-1 19.26 % 19.34 % -1 0 +1 HOC
(# of Logical Clicks)
100381_079
Figure 3-10. CX25870/871 Autoconfiguration Modes for 800 x 600 RGB In, PAL-BDGHI Out Desktop Resolutions
(# of Logical Clicks)
VOC
800 x 600 RGB in, PAL-BDGHI out Autoconfig. Mode #3
+1 14.52 % 13.19 % Autoconfig. Mode #19 0 16.42 % 15.97 % Autoconfig. Mode #35 -1 19.03 % 18.40 % -1 0 +1 HOC
(# of Logical Clicks)
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3.6 Applications Information
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 3-11. CX25870/871 Autoconfiguration Modes for 1024 x 768 RGB In, NTSC Out Desktop Resolutions
(# of Logical Clicks)
VOC
Increase Vert.
1024 x 768 RGB in, NTSC out Autoconfig. Mode #26 11.97 % 11.93 % Autoconfig. Mode #10 15.11 % 14.81 % Autoconfig. Mode #42 18.04 % 18.11 % -1
Decrease Horiz.
+1
0
-1
Decrease Vert. Vertically Const.
0
Horizontally Constant
+1
Increase Horiz.
HOC
100381_081
Figure 3-12. CX25870/871 Autoconfiguration Modes for 1024 x 768 RGB In, PAL-BDGHI Out Desktop Resolutions
(# of Logical Clicks)
VOC
1024 x 768 RGB in, PAL-BDGHI out
+1
Autoconfig. Mode #11 0 13.44 % 14.24 % Autoconfig. Mode #43 -1 16.20 % 16.67 % -1 0 +1 HOC
(# of Logical Clicks)
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Flicker-Free Video Encoder with Ultrascale Technology
3.0 PC Board Considerations
3.6 Applications Information
Customers are urged to enable the autoconfiguration mode that is in the middle of each chart as the default Size for each active resolution. To accomplish this, the encoder's CONFIG[5:0] bit field must be programmed to the desired mode. In addition, the graphics controller's HTOTAL register must be programmed to match the CX25870/871's H_CLKI[10:0] value, and VTOTAL register must be programmed to match the CX25870/871's V_LINESI[10:0] value. Other minor modifications may be necessary. The specific procedure to follow to enable different overscan ratios is explained in an application note titled Supporting TV Out with Non-Standard Graphics Input Resolutions. Request this document from your local Conexant Sales representative for help on the Size video adjustment. A simpler alternative to independent horizontal and vertical size buttons is to replace the directional control pad with a slider. This slider would only have 3 tick marks and would cycle through the different sizes available based on the autoconfiguration modes that exist for the specific desktop resolution and video output type. This concept is illustrated in Figure 3-13.
Figure 3-13. Direction-less Size Control Pad
The slider would alter the horizontal and vertical size of the TV picture simultaneously by changing the overscan percentages by the same amount. Size control should only be effective for desktop resolutions such as 640x480, 800x600, and 1024x768. Nonstandard resolutions should choose a single size with a moderate amount of overscan compensation (HOC/VOC = 11 percent-16 percent) and not allow the end-user to deviate from this choice by graying out the Size slider.
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3.6 Applications Information
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
3.6.3 System Block Diagrams
The CX25870/871 can be designed into any system that requires analog standard definition television outputs (NTSC/PAL/SECAM/SCART) or high definition television outputs (YPBPR/HD RGB) based on a digital RGB or YCrCb set of inputs. The following system block diagrams are meant to illustrate several common applications which presently utilize the CX25870/871 encoder.
Figure 3-14. System Block Diagram for Desktop/Portable PC with TV Out
Intel Pentium IIITM or AMD K7TM Series CPU
CPU CLK
Analog RGB
AGP Graphics Controller
AGP Bus Control Address Data
VGA Monitor
CLKs
Memory Bus
North Bridge Core Logic
DIMM*2
CX25871 or Bt869 NTSC/PAL/SECAM Television or HDTV
Digital RGB or YCrCB Pixels
Core Logic CLK #1
Clock Generator Conexant VGA Encoder
Core Logic CLK #2
PCI Bus
SMBus
IEEE 1394 Host Controller
PCI/Legacy Audio Controller
Parallel Port
PCI CardBus PC Controller
PCI Riser Device South Bridge Core Logic
Serial Port IDE FDD i-f USB Ports ATA 33/066
AC '97
CODEC
PCMCIA Socket
BIOS Flash ROM
GPIO ACPI
Lin IN Lin OUT Mic IN
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Flicker-Free Video Encoder with Ultrascale Technology
3.0 PC Board Considerations
3.6 Applications Information
Figure 3-15. System Block Diagram for Graphics Card with TV Out
Analog RGB
AGP Graphics Controller
Graphics BIOS Flash ROM
Analog RGB
CLKs
VGA Monitor
SYNC*s and BLANK*
SGRAM*8 or SDRAM*8
Digital RGB or YCrCB Pixels
CX25871 or Bt869
DAC Outputs
Voltage Regulator
Conexant VGA Encoder
NTSC/PAL/SECAM Television or HDTV
AGP Bus
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3.6.4 Electrostatic Discharge and Latchup Considerations
Correct electrostatic discharge (ESD)-sensitive handling procedures are required to prevent device damage. Device damage can produce symptoms of catastrophic failure or erratic device behavior with leaky inputs. All logic inputs should be held low until power to the device has settled to the specified tolerance. DAC power decoupling networks with large time constants should be avoided; they could delay VAA and VDD power to the device. Ferrite beads must be used only for analog power VAA decoupling. Inductors cause a time-constant delay that induces latchup, and should not be substituted for a ferrite bead. Latchup can be prevented by ensuring that all VAA and VDD pins are at the same potential and by forcing all AGND and VSS pins to be at the same potential. The VAA and VDD supply voltage must be applied before the signal pin voltages. The correct power-up sequence ensures that any signal pin voltage will never exceed the power supply voltage.
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3.6 Applications Information
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
3.6.5 Clock and Subcarrier Stability
The color subcarrier frequency is derived directly from the XTALIN/XTALOUT ports when EN_XCLK=0. The color subcarrier frequency is derived directly from the main clock input, CLKI, when EN_XCLK=1 (slave interface). In either case any jitter or frequency deviation from 13.500 MHz (XTALIN/XTALOUT) or the CLKI (slave interface) rate will be transferred directly to the color subcarrier. Jitter within the valid clock cycle interval will result in hue noise on the color subcarrier on the order of 0.9-1.6 degrees per nanosecond. Random hue noise can result in degradation in the AM/PM noise ratio (typically around 40 dB for consumer media such as Videodiscs and VCRs). Periodic or coherent hue noise can result in differential phase error (which is limited to 10 degrees by FCC cable TV standards). Any frequency deviation of CLKI from the transmitted clock (i.e., CLKO) will challenge the subcarrier tracking capability of the destination receiver. This may range from a few parts-per-million (ppm) for broadcast equipment, to 100 ppm for industrial equipment and to >100 ppm for consumer equipment. Greater subcarrier tracking range generally results in poorer subcarrier decoding dynamic range. So, receivers that tolerate jitter and wide subcarrier frequency deviation will introduce more noise in the decoded image. Crystal-based clock sources with a maximum total deviation of 50 ppm (NTSC) or 25 ppm (PAL, SECAM) across the temperature range of 0 C to 70 C produce the best results for consumer and industrial applications. In rare cases, temperature-compensated clock sources with tighter tolerances may be warranted for broadcast or more stringent PAL (e.g., type I) applications. Some applications call for maintaining correct Subcarrier-Horizontal (SC-H) phasing for correct color framing. This requires subcarrier coherence within specified tolerances over a four-field interval for 525-line systems or 8 fields for 625-line systems. Any clock interruption (even during vertical blanking interval) which results in mis-registration of the CLKI input or nonstandard pixel counts per line, can result in SC-H excursions outside the NTSC limit of 40 degrees (reference EIA RS170A) or the PAL limit of 20 degrees (reference EBU D23-1984). In slave interface, any deviation exceeding the 50 ppm (NTSC) or 25 ppm (PAL, SECAM) limits of the number clock cycles between HSYNC* falling edges may result in a switch to Master Mode. A list of recommended crystals and crystal vendors is contained in Appendix B.
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Flicker-Free Video Encoder with Ultrascale Technology
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3.6 Applications Information
3.6.6 Filtering Radio Frequency Modulator Connection
The CX25870/871 internal upsampling filter alleviates external filtering requirements by moving significant sampling alias components above 19 MHz and reducing the sinx/x aperture loss up to the filter's passband cutoff of 5.75 MHz. While typical chrominance subcarrier decoders can handle the CX25870/871 output signals without analog filtering, the higher frequency alias products pose some EMI concerns and may create troublesome images when introduced to a radio frequency (RF) modulator. When the video is presented to an RF modulator, it should be free of energy in the region of the aural subcarrier (4.5 MHz for NTSC, 5.5-6.5 MHz for PAL). Hence some additional frequency traps may be necessary when the video signal contains fundamental or harmonic energy (as from unfiltered character generators) in that region. Where better frequency response flatness is required, some peaking in the analog filter is appropriate to compensate for residual digital filter losses with sufficient margin to tolerate 10 percent reactive components. A three-pole elliptic filter (one inductor, three capacitors) with a 6.75 MHz passband can provide at least 45 dB attenuation (including sinx/x loss) of frequency components above 20 MHz and provide some flexibility for mild peaking or special traps. An inductor value with a self-resonant frequency above 80 MHz is chosen so that its intrinsic capacitance contributes less than 10 percent of the total effective circuit value. The inductor itself may induce 1 percent (0.1 dB) loss. Any additional ferrites introduced for EMI control should have less than 5 impedance below 5 MHz to minimize additional losses. The capacitor to ground at the CX25870/871 output pin is compensating for the parasitic capacitance of the chip plus any protection diodes and lumped circuit traces (about 22 pF + 5 pF/diode). Some filter peaking can be accomplished by splitting the 75 source impedance across the reactive PI filter network. However, this will also introduce some chrominance-luminance delay distortion in the range of 10-20 ns for a maximum of 0.5 dB boost at the subcarrier frequency. The filter network feeding an RF modulator may include the aforementioned trap, which could take two forms depending on the depth of attenuation and type of resonator device employed. The trap circuitry can interact with the low-pass filter, compromising frequency response flatness. A simple PNP buffer can preserve the benefits of an oversampling encoder when simultaneous Composite Video Baseband Signals (CVBS) are required for driving external cables. In addition, an active video buffer, serves to isolate the RF modulator signal amplitude from anomalies in the external termination. This buffer can be implemented with a transistor array or video amplify IC which provides a gain of two (before series termination), capable of driving 740 A into the 75 destination, and is biased within its input/output compliance range. When simultaneous Y/C (s-video) outputs are not required, a second CVBS signal can be created (with a 600 mV sync to tip offset) by tying these pins together with a single termination resistor (typically 75 ) and driving the low-pass filter circuit. The RF modulator typically has a high input impedance (about 1 k 30 percent) and loose tolerance. Consequently, the amplitude variation at the modulator input will be greater, especially when the trap is properly terminated at the modulator input for maximum effect. Some modulators, video or aural fidelity, degrade dramatically when overdriven, so the value of the effective termination (nominally 37.5 ) may need to be adjusted downward to maintain sufficient linearity (or depth of modulation margin) in the RF signal.
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3.6 Applications Information
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
A two-section trap (with associated inductor) may be warranted to achieve better than 20 dB attenuation when stereo, SAP, or AM aural carriers are generated, or when >40 dB audio dynamic range is desired. Some impedance isolation (e.g., buffer) may be required before the trap to obtain the flattest frequency response.
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Flicker-Free Video Encoder with Ultrascale Technology
3.0 PC Board Considerations
3.7 CX870EVK Evaluation Kit
3.7 CX870EVK Evaluation Kit
A new reference design kit is available now to facilitate implementation of Conexant's VGA encoder into a graphics subsystem. This kit is called the GeForce2 MX-400 CX870EVK and can be obtained through your local Conexant Systems sales office. The new CX25870 Evaluation Kit uses the NVidia P36 model reference design AGP card, containing the popular NVidia GeForce2 MX-400TM graphics-processing unit (GPU), as a high-performance data master to provide digital data to the CX25870 PC video encoder. The Conexant device has been mounted directly on this graphics card along with all necessary passive components (resistors, capacitors, inductors, video connectors, etc.) to ensure proper device operation. This two-chip combination is controlled by a set of drivers for the graphics accelerator written by NVidia and a separate Windows program called Super Cockpit created by Conexant that allows direct manipulation of the encoder device by circumventing the driver software. All the necessary documents and cables have been within the kit as well. The multipronged DV-H cable from JIC USA is included with the kit and will be necessary for viewing of HDTV, 480i Component Video Out, S-Video, Composite, and any other TV output from the CX25870 encoder. To obtain the necessary CX870EVK software, find a PC with Internet access and visit the CX25870 https://site. For the site address, username, and password, contact your local Conexant Systems sales office. Once you have been given user identification information, you can download the GeForce2 MX-400 CX870EVK instruction manual, Super Cockpit, test images, and other pertinent software. The CX870EVK was designed to be both a demonstration unit and development unit depending on a customer's needs. For demonstration purposes, many script files have been created and will be automatically extracted and placed into a /ScriptFiles subdirectory under the CX870EVK's main directory. To execute a script file, launch a DOS-BOX, type the desired script filename (without the extension) on the command line, and then press the key. After execution, the script file will have configured both the CX25870 encoder and the GeForce2 MX-400 graphics controller to a specific mode in terms of resolution and video output. This is the most effective method for achieving the optimal TV Out picture quickly. For development purposes, several new pages have been added to Super Cockput including the handy Clipboard pages which allow the end-user to try out register values and restore them if the result is not desirable. All registers can be read from as well--an improvement over the Bt868/9. Write access to all the new bits and registers found within the CX25870 are also possible. Note that the GeForce2 MX-400 controller supports the CX25870 in a pseudo-master interface. As a result, HDTV YPRPB Output is possible with the GeForce2 MX-400 CX870EVK kit.
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3.7 CX870EVK Evaluation Kit
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
In addition, the ability to switch between the most popular desktop resolutions (640x480, 800x600, and 1024x768) and video output types (NTSC/PAL/SECAM) is much simpler now than with the original Bt868EVK. Finally, sliders commonly found on TV Out Display Properties pages such as brightness, contrast, saturation, flicker filtering and hue have been integrated into the Super Cockpit application itself on the Display page. Users are encouraged to manipulate these controls to achieve their desired TV outputs and save the encoder settings for future usage.
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3.8 Serial Interface
3.8 Serial Interface
3.8.1 Data Transfer on the Serial Interface Bus
Figure 3-16 illustrates the relationship between SID (Serial Interface Data) and SIC (Serial Interface Clock) to be used when programming the internal registers via the Serial Interface bus. If the bus is not being used, both SID and SIC lines must be left high. Every byte put onto the SID line should be 8 bits long (MSB first), followed by an acknowledge bit, which is generated by the receiving device. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always the slave device address byte. If this is the device's own address, the device will generate an acknowledge by pulling the SID line low during the ninth clock pulse, then accept the data in subsequent bytes (auto-incrementing the subaddress) until another stop condition is detected. The eighth bit of the address byte is the read/write bit (high = read from addressed device; low = write to the addressed device). Data bytes are always acknowledged during the ninth clock pulse by the addressed device.
NOTE:
During the acknowledge period, the transmitting device must leave the SID line high.
Premature termination of the data transfer is allowed by generating a stop condition at any time. When this happens, the CX25870/871 will remain in the state defined by the last complete data byte transmitted and any master acknowledge subsequent to reading the chip ID (subaddress 0x89 if ALTADDR pin is 0) is ignored. The maximum serial interface speed for the CX25870/871 is 400 kHz.
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3.8 Serial Interface
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 3-16. SID/SIC Serial Programming Diagram
Subsequent Bytes and Acknowledge Interpreted as Data Values for Auto-Incrementing Subaddress Locations
SIC
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
MSB
LSB
SID
Start Condition
(1)
(1)
(1)
Slave Main Address (XX)
Subaddress (XX)
Data (XX)
(2)
(2)
NOTE(S): (1) ACK = Acknowledge generated by CX25870/871. (2) Conditions generated by master device.
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4.0 Parametric Information
4.1 DC Electrical Parameters
DC electrical parameters are defined in Tables 4-1 through 4-3. AC electrical parameters are defined in Table 4-4. Figures 4-1 through 4-10 provide timing diagrams.
Table 4-1. Recommended Operating Condition Parameter
Power Supply Serial Input Supply (CX25870/871's serial bus always operates at 3.3 V.) Low Voltage Supply (For interface to 1.8 V master) Low Voltage Supply (For interface to 1.5 V master) Low Voltage Supply (For interface to 1.3 V master) Low Voltage Supply (For interface to 1.1 V master) Voltage Supply (For interface to 3.3 V master) Ambient Operating Temperature Total DAC Terminated Load Nominal RSET
Symbol
VAA, VDD VDD_SI VDDL, VDD_CO VDDL, VDD_CO VDDL, VDD_CO VDDL, VDD_CO VDDL, VDD_CO TA RTERM RSET
Min
3.15 3.15 1.71 1.425 1.235 1.045 3.15 0 -- 74.25
Typical
3.30 3.30 1.80 1.50 1.30 1.10 3.30 -- 37.5 75.0
Max
3.45 3.45 1.89 1.575 1.365 1.155 3.45 70 -- 75.75 V V V V V V V
Units
C
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4.0 Parametric Information
4.1 DC Electrical Parameters
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 4-2. Absolute Maximum Rating Parameter
VAA, VDD (measured to GND) VDD_SI (measured to GND) Voltage on Any Signal Pin (1) Analog Output Short Circuit Duration to Any Power Supply or Common Ground Storage Temperature Junction Temperature Vapor Phase Soldering (1 Minute) Thermal Resistance of Package
NOTE(S):
Symbol
-- -- -- ISC TS TJ TVSOL JA
Min
-- -- GND -0.5 -- -65 -- -- --
Typ
-- -- 7.0 7.0
Max
Units
V V V Sec C C C
VDD_SI+ 0.5 -- -- -- -- 38.5 Unlimited +150 +125 220 --
C/W
1. This device employs high-impedance CMOS circuitry on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply or ground voltage by more than 0.5 V can cause destructive latchup. 2. Stresses above those listed under "Absolute Maximum Ratings" can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods can affect device reliability.
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Flicker-Free Video Encoder with Ultrascale Technology
Table 4-3. DC Characteristics for CX25870/871 Parameter
Video D/A Resolution Output Current-DAC Code 1023 (Iout Full Scale) Output Voltage-DAC Code 1023 Video Level Error (Nominal Resistors) Output Capacitance (of DAC output) Input High Voltage @ 3.3 V (Normal Operation) Input High Voltage @ 1.8 V (Low voltage pins only) Input High Voltage @ 1.1 V (Low voltage pins only) Input Low Voltage @ 3.3 V (Normal Operation) Input Low Voltage @ 1.8 V (Low voltage pins only) Input Low Voltage @ 1.1 V (Low voltage pins only) Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f =1 MHz, Vin = 2.4 V) Input High Voltage (SIC, SID) Input Low Voltage (SIC, SID) Input High Voltage (CLKI) Input Low Voltage (CLKI) Output High Voltage (IOH = -400 A) Output Low Voltage (IOL = 3.2 mA) Three-State Current Output Capacitance
4.0 Parametric Information
4.1 DC Electrical Parameters
Symbol
-- -- -- -- -- VIH VIH VIH VIL VIL VIL IIH IIL CIN VIH VIL VIH VIL VOH VOL IOZ CDOUT
Min
10 -- -- -- -- 2.0 1.0 0.7 GND-0.5 GND - 0.5 GND - 0.5 -- -- -- 0.7* VDD GND - 0.5 2.4 GND - 0.5 2.4 GND -- --
Typical
10 34.13 1.28 -- 22 -- -- -- -- -- -- -- -- 7 -- -- -- -- -- -- -- 10
Max
10 -- -- 5 -- VDD + 0.5 VDDL + 0.5 VDDL + 0.5 0.8 0.45 0.2 1 -1 -- VDD + 0.5 0.3 * VDD VDD_I + 0.5 0.8 VDD 0.4 50 --
Units
Bits mA V % pF V V V V V V A A pF V V V V V V A pF
NOTE(S): The above parameters are guaranteed over the full temperature range (0 C to 70 C), temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 3.3 V.
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4.0 Parametric Information
4.2 AC Electrical Parameters
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
4.2 AC Electrical Parameters
Table 4-4. AC Characteristics for CX25870/871 (1 of 3) Parameter
Hue Accuracy(2) Chroma Amplitude Accuracy(2) Chroma AM Noise Chroma PM Noise Differential Gain Differential Phase RMS SNR (Unweighted 100 IRE Y Ramp Tilt Correct) Peak Periodic SNR @ 3.58 MHz 100 IRE Multiburst Multiburst @ 0.50 MHz Multiburst @ 1.25 MHz Multiburst @ 2.00 MHz Multiburst @ 3.00 MHz Multiburst @ 3.58 MHz Multiburst @ 4.05 MHz Chroma/Luma Gain Ineq Chroma/Luma Delay Ineq Short Time Distortion 100 IRE/PIXEL rising edge Luminance Nonlinearity Chroma/Luma Intermod Chroma Nonlinear Gain Chroma Nonlinear Phase Pixel/Control Setup Time (SETUP_HOLD_ADJ bit = 0) Pixel/Control Setup Time (SETUP_HOLD_ADJ bit = 1)
EIA/TIA 250C Ref
-- -- 1 MHz Red Field 1 MHz Red Field 6.2.2.1 6.2.2.2 6.3.1 6.3.2 6.1.1 -- -- -- -- -- -- 6.1.2.2 6.1.2 6.1.6 6.2.1 6.2.3 6.2.4.1 6.2.4.2 -- --
CCIR 567
-- -- -- -- C3.4.1.3 C3.4.1.4 -- -- -- -- -- -- -- -- -- C3.5.3.1 C3.5.3.2 -- -- -- -- -- -- --
Symbol
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1
Min
1.05 0.42 -65.70 -54.40 0.26 0.64 -53.70 -82.7 101.9 -0.15 -0.27 -0.45 -0.73 -0.88 -1.03 94.8 -7.00 1.70 0.20 0.00 -1.9 0.10 3 1.25
Typical
1.45 1.15 -64.90 -50.70 0.5 0.71 -51.04 -79.2 103.5 -0.1 -0.21 -0.36 -0.61 -0.74 -0.89 96.2 -3.04 1.79 0.82 0.28 -1.59 0.53 -- --
Max
1.64 1.64 -62.40 -47.90 0.7 1.19 -46.9 -73.4 105.4 -0.06 -0.16 -0.31 -0.54 -0.66 -0.81 97.1 -0.20 2.0 1.5 0.5 -1.30 1.30 -- --
Units
deg p-p % p-p dB rms dB rms % p-p
deg p-p
dB rms dB p-p IRE dB dB dB dB dB dB % ns % % p-p % % deg ns ns
4-4
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 4-4. AC Characteristics for CX25870/871 (2 of 3) Parameter
Pixel/Control Hold Time (SETUP_HOLD_ADJ bit = 0) Pixel/Control Hold Time (SETUP_HOLD_ADJ bit = 1) Control Output Delay Time(4) Control Output Hold Time(4) CLKI/O Frequency (standard mode) CLKI/O Pulse Width Low Duty Cycle(3) CLKI/O Pulse Width High Duty Cycle(3) CLKO to CLKI Delay SLAVE to HSYNC*/VSYNC* Three-state(3) SLAVE to HSYNC*/VSYNC* Active(3) VAA Supply Current (minimum 3 DACS on)(8) VDD Supply Current (minimum 3 DACS on)(8) Total Supply Current (minimum 3 DACS on)(8) Power-Down Current Power-Down Current (need a Hardware RESET to bring the part up)
4.0 Parametric Information
4.2 AC Electrical Parameters
EIA/TIA 250C Ref
-- -- -- -- --
CCIR 567
-- -- -- -- --
Symbol
2 2 3 4 --
Min
0 1.5 -- 2 --
Typical
-- -- -- -- --
Max
-- -- 10.0
Units
ns ns ns ns
53.333 3 60
MHz
--
--
--
40
50
%
--
--
--
40
50
60
%
-- --
-- --
7 5
-- 2
-- --
0.8 --
CLKO cycles CLKI cycles CLKI cycles mA
--
--
6
--
--
2
--
--
--
--
190
--
--
--
--
--
220
--
mA
--
--
--
--
410
--
mA
-- --
-- --
-- --
-- --
3(7) 1.5(6)
-- --
mA mA
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4.0 Parametric Information
4.2 AC Electrical Parameters
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 4-4. AC Characteristics for CX25870/871 (3 of 3) HDTV Output Timing Characteristics: 1080i (see Figure 4-9) Parameter
Lowsync width Start of line to end of active video Highsync width Rising edge of sync to start of broad pulse Start of line to start of active video Sync rise time Total line time Active line time
Symbol
-- --
Min
-- -- -- -- -- -- -- --
Typical
598.8 28.385 598.8 1.796 2.588 54.5 29.685 25.778
Max
-- -- -- -- -- -- -- --
Units
ns s ns s s ns s s
HDTV Output Timing Characteristics: 720p (see Figure 4-10) Parameter
Lowsync width Start of line to end of active video High sync width Rising edge of sync to start of broad pulse Rising edge of sync to start of active video Sync rise time Total line time Active line time
NOTE(S):
Symbol
a b c d e -- -- --
Min
-- -- -- -- -- -- -- --
Typical
548 20.54 548 3.53 3.53 54.7 22.2 17.16
Max
-- -- -- -- -- -- -- --
Units
ns s ns s s ns s s
1. Guaranteed by characterization; NTSC output, no vertical or horizontal scaling. Flicker Filter and other internal low-pass filters bypassed, and contrast, brightness, saturation levels set to full scale. (2) 100/7.5/100/7.5 Color bars normalized to burst. (3) Guaranteed by design. (4) Control pins are defined as: BLANK*, HSYNC*, VSYNC*, FIELD, CLKO, CLKI, RESET*, PAL, and SLAVE. (5) DAC output load < 75 pF. HSYNC*, VSYNC*, BLANK*, and FIELD output load < 75 pF. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 3.3 V. (6) There are numerous power-down options. This value was determined by setting SLEEP_EN, DIS_CLKI, DIS_CLKO, BY_PLL, XTL_BFO_DIS, XTAL_PAD_DIS bits and pulling the SLEEP pin high. (7) This value was determined by setting BY_PLL, SLEEP_ED, DIS_CLKI, DIS_CLKO, XTAL_BFO_DIS bits. (8) To ensure that the encoder performance falls within DC and AC electrical limits, no more than one DAC should be disabled at any time.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 4-1. Timing Details for All Interfaces
4.0 Parametric Information
4.2 AC Electrical Parameters
CLKO
7
CLKI
P[23:0]
1 2 1 2
HSYNC*,VSYNC*, BLANK* (Input)
1 2
CLKI (Internal Clock Source) HSYNC*,VSYNC* BLANK* (Output)
4 3 2.4 V .8 V
SLAVE
6 5
HSYNC*,VSYNC*
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4.0 Parametric Information
4.2 AC Electrical Parameters
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 4-2. Master Interface Timing Relationship/Noninterlaced RGB/YCrCb Input
CLKI
P[11:0] (Mux Mode) H_BLANKI - 3 P[23:0] (NonMux Mode) BLANK* (Input) CLKO HSYNC* (Output) Internal Sample Counter VSYNC* (Output) Internal Line Counter BLANK* (Output)
POL POH P1L P1H P2L P2H
PnH
P0
P1
P2
Pn
Sample Sample H_Blank_1 H_Blank_2
Sample H_Blank
Line 1
Line V_BLANK1 +1
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Flicker-Free Video Encoder with Ultrascale Technology
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CLKI HSYNC* (Input) VSYNC* (Input) BLANK* (Optional Input)
H_BLANKI[9:0] R7-0 G-lo B7-0 G-up R7-0 G-lo B7-0 G-up R7-0 G-lo B7-0 G-up R7-0 G-lo B7-0 G-up R7-0 G-lo B7-0 G-up R7-0 G-lo B7-0 G-up
CX25870/871
Minimum 2 CLKs
Figure 4-3. Pseudo-Master Interface Timing Relationship - Active Line/Noninterlaced RGB Input
Conexant
Many clks 3 ns. Minimum
..
[P11 - P0]
NOTE(S): 1. The leading edge pixel data (R pixel + G4, G3, G2, and G0 in the 24-bit RGB multiplexed case) and trailing edge pixel data (B pixel + G7, G6, G5, and G1) is clocked in on the rising and falling edge of CLKI, respectively. 2. The CX25870's HSYNCI and VSYNCI bits (register 0 x C6) must be set to 0 (=DEFAULT) in these timing diagrams. This configures the CX25870 to check for active low signals on the HSYNC* and VSYNC* pins from the graphics controller. 3. The {R[7:0], G4, G3, G2, and G0} - {B[7:0], G7, G6, G5, and G1} sequence begins with rising edge of BLANK* or the H_BLANKI[9:0] pixel count. 4. The clock frequency (i.e., CLKI) transmitted by the graphics controller must not deviate 25 pPM from the CLKO frequency sent by the CX25870/871. The CX25870 is the timing slave device to the Graphics Controller in pseudo-master interface. 5. 24-bit RGB multiplexed input format is illustrated in this diagram. It is assumed CX25870's IN_MODE[3:0] bits = 0000.
4.0 Parametric Information
4.2 AC Electrical Parameters
100381_058
4-9
Figure 4-4. Pseudo-Master Timing Relationship Blank Line/Noninterlaced RGB/YCrCb Input
4-10
CLKI Minimum 2 CLKs HSYNC* (Input) Minimum 2 CLKs Many Lines 3 ns. Minimum V_BLANKI[7:0] VSYNC* (Input) Start of Active Video BLANK* (Optional Input) [P11 - P0] Many Lines
4.2 AC Electrical Parameters
4.0 Parametric Information
Conexant
Flicker-Free Video Encoder with Ultrascale Technology
NOTE(S): 1. For noninterlaced data transmission, to start each frame, the leading edge of HSYNC* and the leading edge of VSYNC* must be coincident (within 1 CLKI clock cycle). The location of these signals' respective trailing edges is not important relative to each other. 2. The duration of the HSYNC* pulse MUST be at least 2 complete CLKI cycles. The duration of the VSYNC* pulse MUST be a minimum of 2 CLKI cycles as well. It is acceptable for the HSYNC* to remain low for longer than 2 CLKI cycles but the signal's rising edge must be received by the CX25870 at least 1 pixel before the next HSYNC* falling edge which denotes the start of the next line. Likewise, VSYNC* can stay low for much longer than 2 CLKI cycles but the signal's rising edge must be received by the CX870 at least 1 complete line before the next VSYNC* falling edge which denotes the start of the next frame. 3. If a BLANK* signal is not used as part of the physical interface to a graphics controller, then the CX25870's H_BLANK[9:0] and V_BLANKI[7:0] registers must be programmed with values equivalent to the correct amount of horizontal pixel blanking and vertical line blanking from the master.
CX25870/871
100381_059
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 4-5. Slave Interface Timing Relationship/Noninterlaced RGB/YCrCb Input
4.0 Parametric Information
4.2 AC Electrical Parameters
CLKO
CLKI
POL POH P1L P1H P2L
PnL PnH

H_BLANKI P0 P1 P2 Pn
BLANK* (Input)
HSYNC* (Input) Internal Sample Counter
Sample HCLKI Sample H_BLANKI -2 Sample H_BLANKI Sample H_BLANKI -1
Sample1
VSYNC* (Input) BLANK* (Output)
100381_024
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4.0 Parametric Information
4.2 AC Electrical Parameters
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 4-6. Slave Interface Timing Relationship/Interlaced Nonmultiplexed RGB Input (FLD_MODE = 10 - Default)
CLKO
CLKI
RGB0 BLANK* (Input)
RGB1
RGB2
RGB3
RGB4
RGB5
RGB6
RGB7
Many HSYNC*'s
HSYNC* (Input) Odd Field YSYNC* (Input)
HSYNC* (Input) Even Field YSYNC* (Input) At Least 4 CLKIs At Least 4 CLKIs
NOTE(S): 1. The CX25870's DIV2 bit must be set. 2. FLD_MODE[1:0] defined in Table 2-5.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
4.0 Parametric Information
4.2 AC Electrical Parameters
Figure 4-7. Slave Interface Timing Relationship/Interlaced Nonmultiplexed YCrCb Input (FLD_MODE = 01)
CLKO
CLKI
CB0 BLANK* (Input)
Y0
CR0
Y1
CB2
Y2
CR2
Y3
Many HSYNC*'s
HSYNC* (Input) Odd Field YSYNC* (Input)
HSYNC* (Input) Even Field YSYNC* (Input) At Least 4 CLKIs At Least 4 CLKIs
NOTE(S): 1. The CX25870's DIV2 bit must be set. 2. FLD_MODE[1:0] defined in Table 2-5.
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4.0 Parametric Information
4.2 AC Electrical Parameters
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 4-8. Slave Interface Timing Relationship/Interlaced Nonmultiplexed YCrCb Input (FLD_MODE = 00)
CLKO
CLKI
CB0 BLANK* (Input) 1/4 of a Line HSYNC* (Input) 1/4 of a Line
Y0
CR0
Y1
CB2
Y2
CR2
Y3
Many HSYNC*'s
Odd Field YSYNC* (Input) 1/4 of a Line HSYNC* (Input) Even Field YSYNC* (Input) 1/4 of a Line 1/4 of a Line
NOTE(S): 1. The CX25870's DIV2 bit must be set. 2. FLD_MODE[1:0] defined in Table 2-5.
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Flicker-Free Video Encoder with Ultrascale Technology
Figure 4-9. HDTV Output Horizontal Timing Details: 1080i
4.0 Parametric Information
4.2 AC Electrical Parameters
+300 BLANKING Vertical Sync (Interfaced) 0 BROAD PULSE -300 0H +350 +300 PB,PR (Outputs)
0
-300 -350
0H +700
+300 Y,R,G,B (Outputs)
0
-300 0H
z
NOTE(S): 1. Values for , , , , , and are given in Table 4-4. 2. Sync rise time () is not shown here. 3. Amplitudes are expressed in mV.
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4.0 Parametric Information
4.2 AC Electrical Parameters
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 4-10. HDTV Output Horizontal Timing Details: 720p
+300 mV BLANKING Vertical Sync (Interfaced) 0 mV
-300 mV d BROAD PULSE b 0H +350 mV +300 mV
PB,PR (Outputs)
0 mV
-300 mV -350 mV
+700 mV
+300 mV
Y,R,G,B (Outputs)
0 mV
-300 mV c a e b 0H
NOTE(S): 1. Values for a, b, c, d, and e are given in Table 4-4. 2. Sync rise time is not shown here. 3. Amplitudes are expressed in mV.
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Flicker-Free Video Encoder with Ultrascale Technology
4.0 Parametric Information
4.3 Mechanical Drawing for 80-Pin PQFP
4.3 Mechanical Drawing for 80-Pin PQFP
A detailed mechanical diagram for the CX25870 and the CX25871 intergrated circuit is illustrated in Figure 4-11.
Figure 4-11. 80-Pin PQFP Package Diagram
80 PQFP - 1.6/0.15 mm FORM
TOP VIEW
D D2
BOTTOM VIEW
D1
e
b
E2
E
E1
SIDE VIEW
A S Y M B O L A A1 A2 D D1 D2 E E1 E2 L L1 e b 1.60 REF. (.063)
100381_025
ALL DIMENSIONS IN MILLIMETERS MIN. ---0.05 16.95 NOM. MAX.
DETAIL A
A2
16.95
0.73
A1
L
0.25
---2.4 ---0.35 2.0 REF. ---17.45 14.0 REF. 12.35 REF. ---17.45 14.0 REF. 12.35 REF. 0.80 1.03 1.6 REF. 0.65 BSC. ---0.45
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4.0 Parametric Information
4.3 Mechanical Drawing for 80-Pin PQFP
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
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A49
Appendix A Scaling and I/0 Timing Register Calculations
The calculated values are used to program the registers controlling the total active pixels and lines in the input frame and the output field, as well as the vertical scaling register and the clock PLL registers. These calculations assume pixel resolution for synchronizing the graphics controller, master interface operation unless otherwise stated, and require the following input values: MFP--Minimum Front Porch Blanking in the Input in Clocks = max (12, Controller_Minimum_Front_Porch_Blanking_Clocks); MBP--Minimum Back Porch Blanking in the Input in Clocks = max (4, Controller_Minimum_Back_Porch_Blanking_Clocks); VOC--desired Vertical Overscan Compensation (e.g., 0.15) HOC--desired Horizontal Overscan Compensation (e.g., 0.15) V_ACTIVEI--Active Lines per Input Frame (e.g., 480 or 600 or 768) H_ACTIVE--Active Pixels per Input Line (e.g., 640 or 800 or 1024) ALO--Target Active Lines per Output Field (See Table A-3) TLO--Total Lines per Output Field (See Table A-3) ATO--Active Time per Output Line (See Table A-3) TTO--Total Time per Output Line (See Table A-3) Tables A-1 and A-2 contain details of the supported video output formats. Table A-3 details the constant software values depending on the video output. Figures A-1 through A-8 illustrate allowable overscan compensation pairs for the most common desktop active resolutions. Tables A-3 through A-27 list the most common overscan values for the 640 x 480, 800 x 600, and 1024 x 768 active resolutions that enable dual display on both the VGA monitor and TV.
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Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table A-1. Target Video Parameters for Standard Definition TV Output Formats (1 of 2) Parameter Description
HSYNC Width (s)
NTSC-M
4.7
NTSC-J
4.7 0.286 150
PAL-M
4.7 0.287 150
PAL-60
4.7 0.3 150
PALB,D,G,H,I
4.7 0.3 200(1)
PAL-N
4.7 0.2857 200
PAL-Nc
4.7 0.3 200
SECAM
4.7 0.3 200
HSYNC and 0.286 VSYNC Height (V) HSYNC Rise/Fall Time (10% to 90%) (ns) Burst or Subcarrier Start (s) Burst Width (s) Subcarrier Frequency(5) (Hz) Burst or Subcarrier Height (V) Phase Alternation Number of Lines per Frame Line Frequency (Hz) Field Frequency (Hz) Setup First Active Line Last Active Line HSYNC to Blank End (s) Blank Begin to HSYNC (s) Black to 100% White (V) 150
5.3
5.3
5.8
5.3
5.6
5.6
5.6
5.6
2.514 (9 cycles) 3579545
2.514 (9 cycles) 3579545
2.52 (9cycles)
2.25 (10 cycles)
2.25 (10 cycles)
2.25 (10 cycles)
2.51 (9 cycles)
N/A
3579611.49 4433618.75 4433618.75 4433618.75 3582056.25 for=4406250 fob=4250000 0.306 0.3 0.3 0.3 0.3 0.161
0.2857
0.2857
NO 525
NO 525
YES 525
YES 525 15734.264 59.94 NO 22(3) 262(3) 9.2 1.5 0.7
YES 625 15625 50 NO 23(4) 309(4)
YES 625 15625 50 YES 23(4) 309(4)
YES 625 15625 50 NO 23(4) 309(4) 10.5 1.5 0.7
NO 625 15625 50 NO 23(4) 309(4) 10.5 1.5 0.7
15734.264 15734.264 15734.264 59.94 YES 22(3) 262(3) 59.94 NO 22(3) 262(3) 59.94 YES 22(3) 262(3) 9.2 1.5 0.661
9.2[9.037] 9.2 1.5[1.185] 1.5 0.661 0.714
10.5[9.778] 9.2 1.5[0.889] 0.7 1.5 0.661
A-2
Conexant
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-1. Target Video Parameters for Standard Definition TV Output Formats (2 of 2) Parameter Description
Number of Lines each for Vertical Serration, Equalization
NOTE(S):
(1)
NTSC-M
3 3
NTSC-J
3
PAL-M
3
PAL-60
PALB,D,G,H,I
2.5 3
PAL-N
PAL-Nc
2.5
SECAM
2.5
Value for PAL-I is 250 ns. 2. ITU-R BT.601 blanking values given in square brackets []. (3) Using NTSC line numbering convention from ITU-R BT.470. (4) Using PAL line numbering convention from ITU-R BT.470. (5) When programming the subcarrier increment, use relationship of Fsc to Fh as given in ITU-R BT.470 instead of Fsc to Fclk.
Table A-2. Key Parameters for Supported Standard Definition Video Output Formats Mode
FSC (Hz) Burst Start Burst End HSYNC Width(1) HSYNC Frequency(1) Active Begin Image Center
NTSC
3,579,545 5.3 s 7.82 s 4.70 s 63.555 s 9.40 s 35.667 s
NTSC60Hz
3,579,545 5.3 s 7.82 s 4.70 s 64 s 9.40 s 35.667 s 1.50 s
PALBDGHI
4,433,618.75 5.60 s 7.85 s 4.70 s 64 s 10.5 s 36.407 s 1.50 s
PAL-N
4,433,618.75 5.60 s 7.85 s 4.70 s 64 s 9.40 s 35.667 s 1.50 s
PAL-Nc
3,582,056.25 5.60 s 8.11 s 4.70 s 64 s 10.5 s 36.407 s 1.50 s
PAL-M
3,575,611.88 5.80 s 8.32 s 4.70 s 63.555 s 9.40 s 35.667 s 1.50 s
PAL-60
4,433,619.49 5.60 s 7.85 s 4.70 s 64 s 10.5 s 36.407 s 1.50 s
Blank Begin to 1.50 s HSYNC(1)
NOTE(S):
(1)
HSYNC in this table refers to the analog horizontal synchronization pulse that starts every scan line.
Table A-3. Constant Values Dependent on Encoding Mode Interlaced Modes PAL
ALO TLO ATO TTO 288 312.5 52.0 s 64.0 s
NonInterlaced NTSC
243 262.5 52.65556 s 63.55556 s
PAL
288 312 52.0 s 64.0 s
NTSC
243 262 52.65556 s 63.55556 s
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Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure A-1. Allowable Overscan Compensation Ratios for Dual Display, 640x480 Input, NTSC Output with 20 Clock HBlank Period
Overscan Compensation Pecentage Pairs for 640x480 NTSC 22
20
Horizontal Overscan Compensation Percentage
18
16
14
12
10
8 8 Legend: = Pixel Clock Solution = 8-Cycle Character Clock Solution = 9-Cycle Character Clock Solution 10 12 14 16 18 Vertical Overscan Compensation Percentage 20 22
NOTE(S): Use this chart for PAL-M and PAL-60 allowable overscan ratios.
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Figure A-2. Allowable Overscan Compensation Ratios for Dual Display, 640x480 Input, PAL-BDGHI Output with 20 Clock HBlank Period
Overscan Compensation Pecentage Pairs for 640x480 PAL 24
22
Horizontal Overscan Compensation Percentage
20
18
16
14
12
10
8
8
10
12
14
16
18
20
22
Legend: = Pixel Clock Solution
Vertical Overscan Compensation Percentage
= 8-Cycle Character Clock Solution = 9-Cycle Character Clock Solution
NOTE(S): Use this chart for SECAM, PAL-N, and PAL-Nc allowable overscan compensation ratios.
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Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure A-3. Allowable Overscan Compensation Ratios for Dual Display, 800x600 Input, NTSC Output
Overscan Compensation Percentage Pairs for 800x600 NTSC 24
22
3 s
Horizontal Overscan Compensation Percentage
20
18
2 s
16
1 s
14
.75 s
12 0 s Horizontal Blanking 10
8
8
10
12
14
16
18
20
22
Legend: = Pixel Clock Solution = 8-Cycle Character Clock Solution = 9-Cycle Character Clock Solution
Vertical Overscan Compensation Percentage
NOTE(S): Use this chart for PAL-M and PAL-60 allowable overscan ratios.
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Figure A-4. Allowable Overscan Compensation Ratios for Dual Display, 800x600 Input, PAL-BDGHI Output, Standard Clocking Mode
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Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure A-5. Allowable Overscan Compensation Ratios for Dual Display, 800x600 Input, NTSC Output in 3:2 Clocking Mode
22
20
Horizontal Overscan Compensation Percentage
18
16
14
12
10
8 8 10 12 14 16 18 20 22 LEGEND = Pixel Clock Solution = 8-Cycle Character Clock Solution = 9-Cycle Character Clock Solution Vertical Overscan Compensation Percentage
NOTE(S): 1. All overscan solutions on this chart can be enabled by a data master that requires no more than 4 s of MBlank time per line. 2. Use this chart for PAL-M and PAL-60 allowable overscan ratios.
A-8
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Figure A-6. Allowable Overscan Compensation Ratios for Dual Display, 800x600 Input, PAL-BDGHI Output in 3:2 Clocking Mode
22
20 Horizontal Overscan Compensation Percentage
18
16
14
12
10
8 8 10 12 LEGEND = Pixel Clock Solution = 8-Cycle Character Clock Solution = 9-Cycle Character Clock Solution 14 16 18 Vertical Overscan Compensation Percentage 20 22
NOTE(S): 1. All overscan solutions on this chart can be enabled by a data master that requires no more than 8 s of HBlank time per line. 2. Use this chart for SECAM, PAL-N, and PAL-Nc allowable overscan compensation ratios.
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Flicker-Free Video Encoder with Ultrascale Technology
Figure A-7. Allowable Overscan Compensation Ratios for Dual Display, 1024x768 Input, NTSC Output
22
20
Horizontal Overscan Compensation Percentage
18 4 us
16
14
3 us 12
10
2 us 8 8 10
1.75 us 1.5 us 1 us Horizontal Blanking 12 14 16 18
0 us 20 22
LEGEND = Pixel Clock Solution = 8-Cycle Character Clock Solution = 9-Cycle Character Clock Solution
Vertical Overscan Compensation Percentage
NOTE(S): Use this chart for PAL-M and PAL-60 allowable overscan ratios.
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Figure A-8. Allowable Overscan Compensation Ratios for Dual Display, 1024x768 Input, PAL-BDGHI Output
24
22
Horizontal Overscan Compensation Percentage
20
18
16
14
12
10
8 8 10 12 14 16 Vertical Overscan Compensation Percentage 18 20 22 LEGEND = Pixel Clock Solution = 8-Cycle Character Clock Solution = 9-Cycle Character Clock Solution
NOTE(S): 1. All overscan solutions on this chart can be enabled by a data master that requires no more than 3 s of HBlank time per line. 2. Use this chart for SECAM, PAL-N, and PAL-Nc allowable overscan compensation ratios.
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Flicker-Free Video Encoder with Ultrascale Technology
Table A-4. Overscan Values, 640 x 480 NTSC, Pixel-Based Controller, 1-Pixel Resolution, 2.5 s HBlank (1 of 2) Controller Pixels Total H_CLKI
780 780 784 780 777 785 777 777 775 775 777 775 775 790 791 770 770 770 770 770 795 770 795 765 798 798 798 800 765 765 800
Encoder Pixels Overscan (Percent) Active Total H_CLKO
988 884 896 936 851 942 925 962 868 961 888 899 930 948 904 946 858 968 902 924 954 880 901 969 988 912 950 960 918 867 928
V_LINESI
665 595 600 630 575 630 625 650 588 651 600 609 630 630 600 645 585 660 615 630 630 600 595 665 650 600 625 630 630 595 609
V_ACTIVEO
190 212 210 200 220 200 202 194 215 194 210 207 200 200 210 196 216 191 205 200 200 210 212 190 194 210 202 200 200 212 207
Horizontal
21.81 12.61 13.79 17.47 9.23 18.00 16.49 19.70 11.00 19.62 13.01 14.07 16.94 18.51 14.55 18.34 9.97 20.20 14.36 16.40 19.03 12.22 14.26 20.28 21.81 15.30 18.69 19.53 15.85 10.90 16.76
Vertical
21.81 12.76 13.58 17.70 9.47 17.70 16.87 20.16 11.52 20.16 13.58 14.81 17.70 17.70 13.58 19.34 11.11 21.40 15.64 17.70 17.70 13.58 12.76 21.81 20.16 13.58 16.87 17.70 17.70 12.76 14.81
Resolution
0.00 -0.14 0.21 -0.23 -0.24 0.30 -0.38 -0.46 -0.52 -0.55 -0.57 -0.74 -0.76 0.82 0.97 -1.00 -1.14 -1.20 -1.28 -1.30 1.33 -1.36 1.51 -1.53 1.65 1.72 1.81 1.84 -1.84 -1.86 1.94
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-4. Overscan Values, 640 x 480 NTSC, Pixel-Based Controller, 1-Pixel Resolution, 2.5 s HBlank (2 of 2) Controller Pixels Total H_CLKI
798 763 800 805 760 805 805 805 756 756 805 810 755 805 756
Encoder Pixels Overscan (Percent) Active Total H_CLKO
874 872 896 966 912 943 920 989 936 900 897 972 906 874 864
V_LINESI
575 600 588 630 630 615 600 645 650 625 585 630 630 570 600
V_ACTIVEO
220 210 215 200 200 205 210 196 194 202 216 200 200 222 210
Horizontal
11.62 11.41 13.79 20.03 15.30 18.08 16.03 21.89 17.47 14.17 13.88 20.53 14.74 11.62 10.59
Vertical
9.47 13.58 11.52 17.70 17.70 15.64 13.58 19.34 20.16 16.87 11.11 17.70 17.70 8.64 13.58
Resolution
2.15 -2.17 2.26 2.34 -2.40 2.44 2.45 2.55 -2.69 -2.70 2.77 2.83 -2.96 2.97 -2.99
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Flicker-Free Video Encoder with Ultrascale Technology
Table A-5. Overscan Values, 640 x 480 NTSC, Character Clock-Based Controller, 8-Pixel Resolution, 2.5 s HBlank
Controller Pixels Total Encoder Pixels Overscan (Percent) Active Total
H_CLKI
784 800 800 800 760 840 840 840 840 840 840 840 840 720 840 840 720
V_LINESI
600 630 609 588 630 615 600 610 595 605 590 585 580 665 575 570 630
V_ACTIVEO
210 200 207 215 200 205 210 207 212 209 214 216 218 190 220 222 200
H_CLKO
896 960 928 896 912 984 960 976 952 968 944 936 928 912 920 912 864
Horizontal
13.79 19.53 16.76 13.79 15.30 21.50 19.53 20.85 18.86 20.20 18.17 17.47 16.76 15.30 16.03 15.30 10.59
Vertical
13.58 17.70 14.81 11.52 17.70 15.64 13.58 14.81 12.76 13.99 11.93 11.11 10.29 21.81 9.47 8.64 17.70
Resolution
0.21 1.84 1.94 2.26 -2.40 5.86 5.95 6.04 6.10 6.21 6.23 6.36 6.47 -6.51 6.57 6.66 -7.10
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-6. Overscan Values, 640 x 480 NTSC, Character Clock-Based Controller, 9-Pixel Resolution, 2.5 s HBlank
Controller Pixels Total Encoder Pixels Overscan (Percent) Active Total
H_CLKI
765 765 765 756 756 810 756 810 819 819 819 720 720 855 693 882 900 675
V_LINESI
665 630 595 650 625 630 600 595 600 625 575 665 630 595 650 575 574 665
V_ACTIVEO
190 200 212 194 202 200 210 212 210 202 220 190 200 212 194 220 220 190
H_CLKO
969 918 867 936 900 972 864 918 936 975 897 912 864 969 858 966 984 855
Horizontal
20.28 15.85 10.90 17.47 14.17 20.53 10.59 15.85 17.47 20.77 13.88 15.30 10.59 20.28 9.97 20.03 21.50 9.65
Vertical
21.81 17.70 12.76 20.16 16.87 17.70 13.58 12.76 13.58 16.87 9.47 21.81 17.70 12.76 20.16 9.47 9.47 21.81
Resolution
-1.53 -1.84 -1.86 -2.69 -2.70 2.83 -2.99 3.09 3.89 3.90 4.42 -6.51 -7.10 7.52 -10.20 10.57 12.03 -12.16
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Appendix A Scaling and I/0 Timing Register Calculations
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Flicker-Free Video Encoder with Ultrascale Technology
Table A-7. Overscan Values, 640 x 480 PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, 2.5 s HBlank (1 of 3)
Controller Pixels Total Encoder Pixels Overscan (Percent) Active Total
H_CLKI
945 946 944 947 943 948 942 949 941 950 950 940 950 950 951 939 952 938 953 937 954 936 955 935 956 934 957 933 958 932 959
V_LINESI
625 625 625 625 625 625 625 625 625 625 600 625 650 575 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625
V_ACTIVEO
240 240 240 240 240 240 240 240 240 240 250 240 231 261 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
H_CLKO
945 946 944 947 943 948 942 949 941 950 912 940 988 874 951 939 952 938 953 937 954 936 955 935 956 934 957 933 958 932 959
Horizontal
16.65 16.73 16.56 16.82 16.47 16.91 16.38 17.00 16.29 17.09 13.63 16.20 20.27 9.88 17.17 16.11 17.26 16.02 17.35 15.93 17.43 15.84 17.52 15.75 17.61 15.66 17.69 15.57 17.78 15.48 17.86
Vertical
16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 13.19 16.67 19.79 9.38 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67
Resolution
-0.02 0.07 -0.11 0.16 -0.20 0.24 -0.29 0.33 -0.37 0.42 0.44 -0.46 0.48 0.50 0.51 -0.55 0.59 -0.64 0.68 -0.73 0.77 -0.82 0.85 -0.91 0.94 -1.00 1.02 -1.09 1.11 -1.18 1.20
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-7. Overscan Values, 640 x 480 PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, 2.5 s HBlank (2 of 3)
Controller Pixels Total Encoder Pixels Overscan (Percent) Active Total
H_CLKI
931 960 930 961 962 929 963 928 964 927 925 965 926 966 925 967 925 924 968 923 969 922 970 921 971 920 972 973 919 974 918
V_LINESI
625 625 625 625 625 625 625 625 625 625 650 625 625 625 625 625 600 625 625 625 625 625 625 625 625 625 625 625 625 625 625
V_ACTIVEO
240 240 240 240 240 240 240 240 240 240 231 240 240 240 240 240 250 240 240 240 240 240 240 240 240 240 240 240 240 240 240
H_CLKO
931 960 930 961 962 929 963 928 964 927 962 965 926 966 925 967 888 924 968 923 969 922 970 921 971 920 972 973 919 974 918
Horizontal
15.39 17.95 15.30 18.03 18.12 15.21 18.20 15.12 18.29 15.03 18.12 18.37 14.94 18.46 14.84 18.54 11.30 14.75 18.63 14.66 18.71 14.57 18.79 14.47 18.88 14.38 18.96 19.04 14.29 19.13 14.19
Vertical
16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 19.79 16.67 16.67 16.67 16.67 16.67 13.19 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67
Resolution
-1.27 1.28 -1.36 1.37 1.45 -1.46 1.54 -1.55 1.62 -1.64 -1.67 1.71 -1.73 1.79 -1.82 1.88 -1.90 -1.91 1.96 -2.01 2.04 -2.10 2.13 -2.19 2.21 -2.29 2.30 2.38 -2.38 2.46 -2.47
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Appendix A Scaling and I/0 Timing Register Calculations
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Flicker-Free Video Encoder with Ultrascale Technology
Table A-7. Overscan Values, 640 x 480 PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, 2.5 s HBlank (3 of 3)
Controller Pixels Total Encoder Pixels Overscan (Percent) Active Total
H_CLKI
975 917 976 975 916 977 915 978 975 914 979 913 980
V_LINESI
625 625 625 600 625 625 625 625 575 625 625 625 625
V_ACTIVEO
240 240 240 250 240 240 240 240 261 240 240 240 240
H_CLKO
975 917 976 936 916 977 915 978 897 914 979 913 980
Horizontal
19.21 14.10 19.29 15.84 14.01 19.38 13.91 19.46 12.19 13.82 19.54 13.72 19.62
Vertical
16.67 16.67 16.67 13.19 16.67 16.67 16.67 16.67 9.38 16.67 16.67 16.67 16.67
Resolution
2.54 -2.57 2.63 2.65 -2.66 2.71 -2.75 2.79 2.81 -2.85 2.87 -2.94 2.96
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-8. Overscan Values, 640 x 480 PAL-BDGHI, Character Clock-Based Controller, 8-Pixel Resolution, 2.5 s HBlank
Controller Pixels Total Encoder Pixels Overscan (Percent) Active Total
H_CLKI
944 952 936 960 928 968 920 976 912 984 904 992 1000 896 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1008 888 880 872
V_LINESI
625 625 625 625 625 625 625 625 625 625 625 625 625 625 620 615 610 605 600 630 575 580 585 590 595 625 625 625 625
V_ACTIVEO
240 240 240 240 240 240 240 240 240 240 240 240 240 240 242 244 246 248 250 239 261 259 257 255 253 240 240 240 240
H_CLKO
944 952 936 960 928 968 920 976 912 984 904 992 1000 896 992 984 976 968 960 1008 920 928 936 944 952 1008 888 880 872
Horizontal
16.56 17.26 15.84 17.95 15.12 18.63 14.38 19.29 13.63 19.95 12.87 20.60 21.23 12.09 20.60 19.95 19.29 18.63 17.95 21.86 14.38 15.12 15.84 16.56 17.26 21.86 11.30 10.49 9.67
Vertical
16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 15.97 15.28 14.58 13.89 13.19 17.01 9.38 10.07 10.76 11.46 12.15 16.67 16.67 16.67 16.67
Resolution
-0.11 0.59 -0.82 1.28 -1.55 1.96 -2.29 2.63 -3.04 3.28 -3.80 3.93 4.56 -4.58 4.62 4.67 4.71 4.74 4.75 4.84 5.01 5.05 5.08 5.10 5.11 5.19 -5.37 -6.18 -7.00
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Flicker-Free Video Encoder with Ultrascale Technology
Table A-9. Overscan Values, 640 x 480 PAL-BDGHI, Character Clock-Based Controller, 9-Pixel Resolution, 2.5 s HBlank
Controller Pixels Total Encoder Pixels Overscan (Percent) Active Total
H_CLKI
945 954 936 963 927 972 918 981 909 990 900 900 999 891 1008 882 873
V_LINESI
625 625 625 625 625 625 625 625 625 625 650 625 625 625 625 625 625
V_ACTIVEO
240 240 240 240 240 240 240 240 240 240 231 240 240 240 240 240 240
H_CLKO
945 954 936 963 927 972 918 981 909 990 936 900 999 891 1008 882 873
Horizontal
16.65 17.43 15.84 18.20 15.03 18.96 14.19 19.71 13.35 20.44 15.84 12.48 21.15 11.59 21.86 10.69 9.77
Vertical
16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 19.79 16.67 16.67 16.67 16.67 16.67 16.67
Resolution
-0.02 0.77 -0.82 1.54 -1.64 2.30 -2.47 3.04 -3.32 3.77 -3.95 -4.19 4.49 -5.07 5.19 -5.97 -6.89
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-10. Overscan Values, 800 x 600 NTSC, Pixel-Based Controller, 1-Pixel Resolution (1 of 4) Controller Pixels Total H_CLKI
800 800 800 800 800 800 805 805 805 805 805 805 805 805 810 810 812 810 819 815 819 819 825 819 825 820 825 825 825 826 825
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1184 1248 1216 1152 1088 1120 1265 1196 1150 1173 1242 1104 1219 1127 1242 1188 1160 1134 1248 1141 1170 1209 1265 1131 1232 1148 1221 1254 1210 1180 1243
V_LINESI
777 819 798 756 714 735 825 780 750 765 810 720 795 735 805 770 750 735 800 735 750 775 805 725 784 735 777 798 770 750 791
V_ACTIVEO
203 193 198 209 221 215 191 202 210 206 195 219 199 215 196 205 210 215 197 215 210 204 196 218 201 215 203 198 205 210 200
Horizontal
18.45 22.63 20.59 16.18 11.25 13.79 23.67 19.26 16.03 17.68 22.25 12.54 20.79 14.32 22.25 18.72 16.76 14.85 22.63 15.37 17.47 20.13 23.67 14.62 21.62 15.89 20.92 23.00 20.20 18.17 22.32
Vertical
16.46 20.58 18.52 13.99 9.05 11.52 21.40 16.87 13.58 15.23 19.75 9.88 18.11 11.52 19.34 15.64 13.58 11.52 18.93 11.52 13.58 16.05 19.34 10.29 17.28 11.52 16.46 18.52 15.64 13.58 17.70
Resolution
1.98 2.05 2.07 2.19 2.20 2.26 2.27 2.39 2.45 2.45 2.50 2.66 2.68 2.80 2.91 3.08 3.18 3.33 3.70 3.85 3.89 4.08 4.33 4.34 4.34 4.37 4.46 4.48 4.56 4.59 4.62
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table A-10. Overscan Values, 800 x 600 NTSC, Pixel-Based Controller, 1-Pixel Resolution (2 of 4) Controller Pixels Total H_CLKI
825 825 825 825 825 825 825 825 833 830 840 840 835 840 840 840 840 840 840 840 840 840 840 840 840 840 840 847 850 845 850
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1199 1188 1177 1166 1155 1122 1144 1133 1190 1162 1248 1256 1169 1224 1264 1200 1232 1208 1240 1184 1216 1168 1192 1152 1176 1160 1144 1210 1258 1183 1224
V_LINESI
763 756 749 742 735 714 728 721 750 735 780 785 735 765 790 750 770 755 775 740 760 730 745 720 735 725 715 750 777 735 756
V_ACTIVEO
207 209 211 213 215 221 217 219 210 215 202 201 215 206 200 210 205 209 204 213 208 216 212 219 215 218 221 210 203 215 209
Horizontal
19.47 18.72 17.96 17.19 16.40 13.94 15.59 14.77 18.86 16.90 22.63 23.12 17.40 21.11 23.61 19.53 21.62 20.07 22.13 18.45 20.59 17.33 18.99 16.18 17.89 16.76 15.59 20.20 23.24 18.38 21.11
Vertical
14.81 13.99 13.17 12.35 11.52 9.05 10.70 9.88 13.58 11.52 16.87 17.28 11.52 15.23 17.70 13.58 15.64 13.99 16.05 12.35 14.40 11.11 12.76 9.88 11.52 10.29 9.05 13.58 16.46 11.52 13.99
Resolution
4.65 4.73 4.79 4.84 4.88 4.89 4.89 4.90 5.28 5.38 5.76 5.84 5.88 5.88 5.91 5.95 5.99 6.07 6.08 6.10 6.19 6.22 6.24 6.30 6.37 6.47 6.54 6.62 6.78 6.85 7.12
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-10. Overscan Values, 800 x 600 NTSC, Pixel-Based Controller, 1-Pixel Resolution (3 of 4) Controller Pixels Total H_CLKI
854 850 855 850 855 861 861 860 861 868 865 875 875 870 875 875 875 875 875 875 875 875 875 875 875 875 875 882 875 875 880
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1220 1190 1254 1156 1197 1230 1271 1204 1189 1240 1211 1270 1250 1218 1265 1245 1240 1260 1235 1255 1210 1230 1205 1225 1200 1195 1220 1260 1190 1215 1232
V_LINESI
750 735 770 714 735 750 775 735 725 750 735 762 750 735 759 747 744 756 741 753 726 738 723 735 720 717 732 750 714 729 735
V_ACTIVEO
210 215 205 221 215 210 204 215 218 210 215 207 210 215 208 211 212 209 213 210 217 214 218 215 219 220 216 210 221 217 215
Horizontal
20.85 18.86 23.00 16.47 19.33 21.50 24.03 19.80 18.79 22.13 20.26 23.97 22.75 20.72 23.67 22.44 22.13 23.36 21.81 23.06 20.20 21.50 19.87 21.18 19.53 19.20 20.85 23.36 18.86 20.53 21.62
Vertical
13.58 11.52 15.64 9.05 11.52 13.58 16.05 11.52 10.29 13.58 11.52 14.81 13.58 11.52 14.40 13.17 12.76 13.99 12.35 13.58 10.70 11.93 10.29 11.52 9.88 9.47 11.11 13.58 9.05 10.70 11.52
Resolution
7.27 7.33 7.36 7.42 7.81 7.92 7.98 8.28 8.50 8.55 8.74 9.15 9.17 9.20 9.26 9.27 9.37 9.37 9.47 9.48 9.50 9.56 9.58 9.65 9.66 9.73 9.74 9.78 9.80 9.83 10.10
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Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table A-10. Overscan Values, 800 x 600 NTSC, Pixel-Based Controller, 1-Pixel Resolution (4 of 4) Controller Pixels Total H_CLKI
889 882 885 890 895 900 900 900 900 905 903 910 925
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1270 1218 1239 1246 1253 1260 1248 1236 1224 1267 1247 1248 1258
V_LINESI
750 725 735 735 735 735 728 721 714 735 725 720 714
V_ACTIVEO
210 218 215 215 215 215 217 219 221 215 218 219 221
Horizontal
23.97 20.72 22.07 22.50 22.94 23.36 22.63 21.88 21.11 23.79 22.57 22.63 23.24
Vertical
13.58 10.29 11.52 11.52 11.52 11.52 10.70 9.88 9.05 11.52 10.29 9.88 9.05
Resolution
10.39 10.43 10.54 10.98 11.41 11.84 11.93 12.00 12.06 12.27 12.28 12.75 14.19
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-11. Overscan Values, 800 x 600 NTSC, Character Clock-Based Controller, 8-Pixel Resolution, 0-1.5 s HBlank Controller Pixels Total H_CLKI
800 800 800 800 800 800 840 840 840 840 840 840 840 840 840 840 840 840 840 840 840 840 880
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1184 1248 1216 1152 1088 1120 1248 1256 1224 1264 1200 1232 1208 1240 1184 1216 1168 1192 1152 1176 1160 1144 1232
V_LINESI
777 819 798 756 714 735 780 785 765 790 750 770 755 775 740 760 730 745 720 735 725 715 735
V_ACTIVEO
203 193 198 209 221 215 202 201 206 200 210 205 209 204 213 208 216 212 219 215 218 221 215
Horizontal
18.45 22.63 20.59 16.18 11.25 13.79 22.63 23.12 21.11 23.61 19.53 21.62 20.07 22.13 18.45 20.59 17.33 18.99 16.18 17.89 16.76 15.59 21.62
Vertical
16.46 20.58 18.52 13.99 9.05 11.52 16.87 17.28 15.23 17.70 13.58 15.64 13.99 16.05 12.35 14.40 11.11 12.76 9.88 11.52 10.29 9.05 11.52
Resolution
1.98 2.05 2.07 2.19 2.20 2.26 5.76 5.84 5.88 5.91 5.95 5.99 6.07 6.08 6.10 6.19 6.22 6.24 6.30 6.37 6.47 6.54 10.10
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Flicker-Free Video Encoder with Ultrascale Technology
Table A-12. Overscan Values, 800 x 600 NTSC, Character Clock-Based Controller, 9-Pixel Resolution, 0-3.0 s HBlank Controller Pixels Total H_CLKI
810 810 810 819 819 819 819 855 855 882 882 900 900 900 900
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1242 1188 1134 1248 1170 1209 1131 1254 1197 1260 1218 1260 1248 1236 1224
V_LINESI
805 770 735 800 750 775 725 770 735 750 725 735 728 721 714
V_ACTIVEO
196 205 215 197 210 204 218 205 215 210 218 215 217 219 221
Horizontal
22.25 18.72 14.85 22.63 17.47 20.13 14.62 23.00 19.33 23.36 20.72 23.36 22.63 21.88 21.11
Vertical
19.34 15.64 11.52 18.93 13.58 16.05 10.29 15.64 11.52 13.58 10.29 11.52 10.70 9.88 9.05
Resolution
2.91 3.08 3.33 3.70 3.89 4.08 4.34 7.36 7.81 9.78 10.43 11.84 11.93 12.00 12.06
A-26
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-13. Overscan Values 800 x 600 NTSC, Pixel-Based Controller, 1-Pixel Resolution, 3:2 Clocking Mode (1 of 4) Controller Pixels Total H_CLKI
1170 1170 1170 1176 1176 1175 1175 1155 1155 1155 1185 1155 1190 1155 1155 1150 1190 1155 1190 1150 1197 1197 1197 1200 1200 1197 1200 1200 1200 1140
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1144 1092 1196 1120 1232 1128 1222 1166 1188 1078 1106 1210 1156 1144 1122 1196 1224 1100 1088 1104 1216 1140 1178 1184 1216 1102 1152 1088 1120 1064
V_LINESI
770 735 805 750 825 756 819 795 810 735 735 825 765 780 765 819 810 750 720 756 800 750 775 777 798 725 756 714 735 735
V_ACTIVEO
205 215 196 210 191 209 193 199 195 215 215 191 206 202 206 193 195 210 219 209 197 210 204 203 198 218 209 221 215 215
Horizontal
15.59 11.57 19.26 13.79 21.62 14.40 20.98 17.19 18.72 10.43 12.69 20.20 16.47 15.59 13.94 19.26 21.11 12.22 11.25 12.54 20.59 15.30 18.03 18.45 20.59 12.38 16.18 11.25 13.79 9.25
Vertical
15.64 11.52 19.34 13.58 21.40 13.99 20.58 18.11 19.75 11.52 11.52 21.40 15.23 16.87 15.23 20.58 19.75 13.58 9.88 13.99 18.93 13.58 16.05 16.46 18.52 10.29 13.99 9.05 11.52 11.52
Delta
-0.04
0.05
-0.08
0.21 0.22 0.40 0.41
-0.92 -1.03 -1.10
1.17
-1.20
1.24
-1.28 -1.29 -1.31
1.36
-1.36
1.37
-1.46
1.66 1.72 1.98 1.98 2.07 2.09 2.19 2.20 2.26
-2.27
100381B
Conexant
A-27
Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table A-13. Overscan Values 800 x 600 NTSC, Pixel-Based Controller, 1-Pixel Resolution, 3:2 Clocking Mode (2 of 4) Controller Pixels Total H_CLKI
1134 1134 1134 1134 1215 1125 1125 1218 1125 1125 1125 1215 1125 1125 1125 1125 1125 1125 1125 1225 1120 1225 1225 1225 1225 1225 1225 1225 1120 1225
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1116 1188 1152 1080 1188 1170 1130 1160 1140 1180 1150 1134 1080 1090 1160 1070 1100 1110 1120 1232 1152 1190 1162 1204 1218 1176 1120 1148 1088 1134
V_LINESI
775 825 800 750 770 819 791 750 798 826 805 735 756 763 812 749 770 777 784 792 810 765 747 774 783 756 720 738 765 729
V_ACTIVEO
204 191 197 210 205 193 200 210 198 191 196 215 209 207 194 211 205 203 201 199 195 206 211 204 202 209 219 214 206 217
Horizontal
13.48 18.72 16.18 10.59 18.72 17.47 14.55 16.76 15.30 18.17 16.03 14.85 10.59 11.41 16.76 9.76 12.22 13.01 13.79 21.62 16.18 18.86 16.90 19.80 20.72 17.89 13.79 15.89 11.25 14.85
Vertical
16.05 21.40 18.93 13.58 15.64 20.58 17.70 13.58 18.52 21.40 19.34 11.52 13.99 14.81 20.16 13.17 15.64 16.46 17.28 18.11 19.75 15.23 13.17 16.05 16.87 13.99 9.88 11.93 15.23 10.70
Delta
-2.57 -2.68 -2.75 -2.99
3.08
-3.11 -3.15
3.18
-3.22 -3.23 -3.31
3.33
-3.40 -3.40 -3.41 -3.41 -3.42 -3.45 -3.50
3.52
-3.57
3.63 3.73 3.75 3.85 3.90 3.91 3.95
-3.98
4.15
A-28
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-13. Overscan Values 800 x 600 NTSC, Pixel-Based Controller, 1-Pixel Resolution, 3:2 Clocking Mode (3 of 4) Controller Pixels Total H_CLKI
1113 1230 1239 1100 1245 1250 1092 1260 1260 1260 1260 1260 1260 1260 1260 1085 1260 1260 1260 1260 1080 1075 1275 1281 1275 1275 1071 1071 1290 1295 1050
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1166 1148 1180 1144 1162 1200 1144 1224 1200 1232 1208 1184 1216 1168 1192 1116 1152 1176 1160 1144 1104 1118 1224 1220 1190 1156 1122 1088 1204 1184 1104
V_LINESI
825 735 750 819 735 756 825 765 750 770 755 740 760 730 745 810 720 735 725 715 805 819 756 750 735 714 825 800 735 720 828
V_ACTIVEO
191 215 210 193 215 209 191 206 210 205 209 213 208 216 212 195 219 215 218 221 196 193 209 210 215 221 191 197 215 219 191
Horizontal
17.19 15.89 18.17 15.59 16.90 19.53 15.59 21.11 19.53 21.62 20.07 18.45 20.59 17.33 18.99 13.48 16.18 17.89 16.76 15.59 12.54 13.63 21.11 20.85 18.86 16.47 13.94 11.25 19.80 18.45 12.54
Vertical
21.40 11.52 13.58 20.58 11.52 13.99 21.40 15.23 13.58 15.64 13.99 12.35 14.40 11.11 12.76 19.75 9.88 11.52 10.29 9.05 19.34 20.58 13.99 13.58 11.52 9.05 21.40 18.93 11.52 9.88 21.40
Delta
-4.21
4.37 4.59
-4.98
5.38 5.54
-5.81
5.88 5.95 5.99 6.07 6.10 6.19 6.22 6.24
-6.28
6.30 6.37 6.47 6.54
-6.81 -6.95
7.12 7.27 7.33 7.42
-7.46 -7.68
8.28 8.57
-8.86
100381B
Conexant
A-29
Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table A-13. Overscan Values 800 x 600 NTSC, Pixel-Based Controller, 1-Pixel Resolution, 3:2 Clocking Mode (4 of 4) Controller Pixels Total H_CLKI
1050 1050 1050 1050 1050 1050 1050 1305 1050 1050 1050 1050 1320 1323 1330 1029 1025 1350 1350
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1088 1108 1092 1076 1096 1080 1100 1218 1084 1064 1068 1072 1232 1218 1216 1078 1066 1236 1224
V_LINESI
816 831 819 807 822 810 825 735 813 798 801 804 735 725 720 825 819 721 714
V_ACTIVEO
194 190 193 196 192 195 191 215 194 198 197 196 215 218 219 191 193 219 221
Horizontal
11.25 12.85 11.57 10.26 11.90 10.59 12.22 20.72 10.92 9.25 9.59 9.92 21.62 20.72 20.59 10.43 9.42 21.88 21.11
Vertical
20.16 21.81 20.58 19.34 20.99 19.75 21.40 11.52 20.16 18.52 18.93 19.34 11.52 10.29 9.88 21.40 20.58 9.88 9.05
Delta
-8.92 -8.96 -9.00 -9.08 -9.09 -9.16 -9.18
9.20
-9.24 -9.27 -9.34 -9.42
10.10 10.43 10.72
-10.97 -11.16
12.00 12.06
A-30
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-14. Overscan Values 800 x 600 NTSC, Character Clocked-Based Controller, 8-Pixel Resolution, 3:2 Clocking Mode Controller Pixels Total H_CLKI
1176 1176 1200 1200 1200 1200 1200 1120 1120 1080 1320
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1120 1232 1184 1216 1152 1088 1120 1152 1088 1104 1232
V_LINESI
750 825 777 798 756 714 735 810 765 805 735
V_ACTIVEO
210 191 203 198 209 221 215 195 206 196 215
Horizontal
13.79 21.62 18.45 20.59 16.18 11.25 13.79 16.18 11.25 12.54 21.62
Vertical
13.58 21.40 16.46 18.52 13.99 9.05 11.52 19.75 15.23 19.34 11.52
Delta
0.21 0.22 1.98 2.07 2.19 2.20 2.26
-3.57 -3.98 -6.81
10.10
100381B
Conexant
A-31
Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table A-15. Overscan Values 800 x 600 NTSC, Character Clocked-Based Controller, 9-Pixel Resolution, 3:2 Clocking Mode (1 of 2) Controller Pixels Total H_CLKI
1170 1170 1170 1197 1197 1197 1197 1134 1134 1134 1134 1215 1125 1125 1125 1125 1125 1215 1125 1125 1125 1125 1125 1125 1125 1260 1260 1260 1260 1260
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1144 1092 1196 1216 1140 1178 1102 1116 1188 1152 1080 1188 1170 1130 1140 1180 1150 1134 1080 1090 1160 1070 1100 1110 1120 1224 1200 1232 1208 1184
V_LINESI
770 735 805 800 750 775 725 775 825 800 750 770 819 791 798 826 805 735 756 763 812 749 770 777 784 765 750 770 755 740
V_ACTIVEO
205 215 196 197 210 204 218 204 191 197 210 205 193 200 198 191 196 215 209 207 194 211 205 203 201 206 210 205 209 213
Horizontal
15.59 11.57 19.26 20.59 15.30 18.03 12.38 13.48 18.72 16.18 10.59 18.72 17.47 14.55 15.30 18.17 16.03 14.85 10.59 11.41 16.76 9.76 12.22 13.01 13.79 21.11 19.53 21.62 20.07 18.45
Vertical
15.64 11.52 19.34 18.93 13.58 16.05 10.29 16.05 21.40 18.93 13.58 15.64 20.58 17.70 18.52 21.40 19.34 11.52 13.99 14.81 20.16 13.17 15.64 16.46 17.28 15.23 13.58 15.64 13.99 12.35
Delta
-0.04
0.05
-0.08
1.66 1.72 1.98 2.09
-2.57 -2.68 -2.75 -2.99
3.08
-3.11 -3.15 -3.22 -3.23 -3.31
3.33
-3.40 -3.40 -3.41 -3.41 -3.42 -3.45 -3.50
5.88 5.95 5.99 6.07 6.10
A-32
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-15. Overscan Values 800 x 600 NTSC, Character Clocked-Based Controller, 9-Pixel Resolution, 3:2 Clocking Mode (2 of 2) Controller Pixels Total H_CLKI
1260 1260 1260 1260 1260 1260 1260 1080 1071 1071 1305 1323 1350 1350
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1216 1168 1192 1152 1176 1160 1144 1104 1122 1088 1218 1218 1236 1224
V_LINESI
760 730 745 720 735 725 715 805 825 800 735 725 721 714
V_ACTIVEO
208 216 212 219 215 218 221 196 191 197 215 218 219 221
Horizontal
20.59 17.33 18.99 16.18 17.89 16.76 15.59 12.54 13.94 11.25 20.72 20.72 21.88 21.11
Vertical
14.40 11.11 12.76 9.88 11.52 10.29 9.05 19.34 21.40 18.93 11.52 10.29 9.88 9.05
Delta
6.19 6.22 6.24 6.30 6.37 6.47 6.54
-6.81 -7.46 -7.68
9.20 10.43 12.00 12.06
100381B
Conexant
A-33
Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table A-16. Overscan Values, 800 x 600 PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, >2.5 s HBlank (1 of 2) Controller Pixels Total H_CLKI
945 950 950 940 950 950 950 955 935 960 930 925 925 965 925 925 970 920 975 975 975 915 975 980 910 985 900 905 900 990 900
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1134 1140 1178 1128 1102 1216 1254 1146 1122 1152 1116 1221 1184 1158 1147 1110 1164 1104 1209 1170 1248 1098 1131 1176 1092 1182 1188 1086 1152 1188 1116
V_LINESI
750 750 775 750 725 800 825 750 750 750 750 825 800 750 775 750 750 750 775 750 800 750 725 750 750 750 825 750 800 750 775
V_ACTIVEO
250 250 242 250 259 235 228 250 250 250 250 228 235 250 242 250 250 250 242 250 235 250 259 250 250 250 228 250 235 250 242
Horizontal
13.17 13.63 16.42 12.71 10.65 19.03 21.48 14.08 12.24 14.53 11.77 19.36 16.84 14.97 14.16 11.30 15.41 10.81 18.56 15.84 21.10 10.33 12.94 16.27 9.83 16.70 17.12 9.34 14.53 17.12 11.77
Vertical
13.19 13.19 15.97 13.19 10.07 18.40 20.83 13.19 13.19 13.19 13.19 20.83 18.40 13.19 15.97 13.19 13.19 13.19 15.97 13.19 18.40 13.19 10.07 13.19 13.19 13.19 20.83 13.19 18.40 13.19 15.97
Resolution
-0.02 0.44 0.44 -0.48 0.58 0.63 0.65 0.89 -0.95 1.34 -1.42 -1.47 -1.56 1.78 -1.81 -1.90 2.22 -2.38 2.59 2.65 2.70 -2.87 2.87 3.08 -3.36 3.50 -3.71 -3.86 -3.87 3.93 -4.20
A-34
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-16. Overscan Values, 800 x 600 PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, >2.5 s HBlank (2 of 2) Controller Pixels Total H_CLKI
995 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1194 1256 1240 1200 1248 1216 1232 1192 1168 1208 1224
V_LINESI
750 785 775 750 780 760 770 745 730 755 765
V_ACTIVEO
250 239 242 250 241 247 244 252 257 249 246
Horizontal
17.54 21.61 20.60 17.95 21.10 19.03 20.08 17.40 15.70 18.49 19.56
Vertical
13.19 17.01 15.97 13.19 16.32 14.24 15.28 12.50 10.76 13.54 14.58
Resolution
4.34 4.59 4.62 4.75 4.79 4.79 4.80 4.90 4.94 4.95 4.97
100381B
Conexant
A-35
Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table A-17. Overscan Values, 800 x 600 PAL-BDGHI, Character Clock-Based Controller, 8-Pixel Resolution Controller Pixels Total H_CLKI
960 920 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1040
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1152 1104 1256 1240 1200 1248 1216 1232 1192 1168 1208 1224 1184 1160 1152 1176 1144 1248
V_LINESI
750 750 785 775 750 780 760 770 745 730 755 765 740 725 720 735 715 750
V_ACTIVEO
250 250 239 242 250 241 247 244 252 257 249 246 254 259 261 256 263 250
Horizontal
14.53 10.81 21.61 20.60 17.95 21.10 19.03 20.08 17.40 15.70 18.49 19.56 16.84 15.12 14.53 16.27 13.93 21.10
Vertical
13.19 13.19 17.01 15.97 13.19 16.32 14.24 15.28 12.50 10.76 13.54 14.58 11.81 10.07 9.38 11.11 8.68 13.19
Resolution
1.34 -2.38 4.59 4.62 4.75 4.79 4.79 4.80 4.90 4.94 4.95 4.97 5.03 5.05 5.15 5.16 5.25 7.91
A-36
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-18. Overscan Values, 800 x 600 PAL-BDGHI, Character Clock-Based Controller, 9-Pixel Resolution Controller Pixels Total H_CLKI
945 900 900 990 900 1035
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1134 1188 1152 1188 1116 1242
V_LINESI
750 825 800 750 775 750
V_ACTIVEO
250 228 235 250 242 250
Horizontal
13.17 17.12 14.53 17.12 11.77 20.72
Vertical
13.19 20.83 18.40 13.19 15.97 13.19
Resolution
-0.02 -3.71 -3.87 3.93 -4.20 7.53
100381B
Conexant
A-37
Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table A-19. Overscan Values 800 x 600 PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, 3:2 Clocking Mode (1 of 3) Controller Pixels Total H_CLKI
1420 1415 1425 1425 1410 1425 1425 1425 1430 1400 1405 1435 1400 1440 1395 1445 1390 1450 1385 1375 1455 1375 1375 1380 1375 1375 1460 1375 1465 1370
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1136 1132 1140 1178 1128 1102 1216 1254 1144 1232 1124 1148 1120 1152 1116 1156 1112 1160 1108 1210 1164 1188 1122 1104 1144 1166 1168 1100 1172 1096
V_LINESI
750 750 750 775 750 725 800 825 750 825 750 750 750 750 750 750 750 750 750 825 750 810 765 750 780 795 750 750 750 750
V_ACTIVEO
250 250 250 242 250 259 235 228 250 228 250 250 250 250 250 250 250 250 250 228 250 232 246 250 241 236 250 250 250 250
Horizontal
13.33 13.02 13.63 16.42 12.71 10.65 19.03 21.48 13.93 20.08 12.40 14.23 12.09 14.53 11.77 14.83 11.46 15.12 11.14 18.63 15.41 17.12 12.24 10.81 13.93 15.56 15.70 10.49 15.99 10.16
Vertical
13.19 13.19 13.19 15.97 13.19 10.07 18.40 20.83 13.19 20.83 13.19 13.19 13.19 13.19 13.19 13.19 13.19 13.19 13.19 20.83 13.19 19.44 14.58 13.19 16.32 18.06 13.19 13.19 13.19 13.19
Delta
0.13
-0.17
0.44 0.44
-0.48
0.58 0.63 0.65 0.74
-0.75 -0.79
1.04
-1.11
1.34
-1.42
1.63
-1.74
1.92
-2.06 -2.21
2.22
-2.32 -2.34 -2.38 -2.39 -2.50
2.51
-2.70
2.79
-3.03
A-38
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-19. Overscan Values 800 x 600 PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, 3:2 Clocking Mode (2 of 3) Controller Pixels Total H_CLKI
1470 1365 1475 1480 1360 1350 1350 1485 1355 1350 1490 1495 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1505 1500 1500 1500 1500 1500 1325 1510
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1176 1092 1180 1184 1088 1188 1152 1188 1084 1116 1192 1196 1256 1240 1200 1248 1216 1232 1192 1168 1208 1224 1204 1184 1160 1152 1176 1144 1166 1208
V_LINESI
750 750 750 750 750 825 800 750 750 775 750 750 785 775 750 780 760 770 745 730 755 765 750 740 725 720 735 715 825 750
V_ACTIVEO
250 250 250 250 250 228 235 250 250 242 250 250 239 242 250 241 247 244 252 257 249 246 250 254 259 261 256 263 228 250
Horizontal
16.27 9.83 16.56 16.84 9.50 17.12 14.53 17.12 9.17 11.77 17.40 17.67 21.61 20.60 17.95 21.10 19.03 20.08 17.40 15.70 18.49 19.56 18.22 16.84 15.12 14.53 16.27 13.93 15.56 18.49
Vertical
13.19 13.19 13.19 13.19 13.19 20.83 18.40 13.19 13.19 15.97 13.19 13.19 17.01 15.97 13.19 16.32 14.24 15.28 12.50 10.76 13.54 14.58 13.19 11.81 10.07 9.38 11.11 8.68 20.83 13.19
Delta
3.08
-3.36
3.36 3.65
-3.69 -3.71 -3.87
3.93
-4.03 -4.20
4.20 4.48 4.59 4.62 4.75 4.79 4.79 4.80 4.90 4.94 4.95 4.97 5.03 5.03 5.05 5.15 5.16 5.25
-5.28
5.30
100381B
Conexant
A-39
Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table A-19. Overscan Values 800 x 600 PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, 3:2 Clocking Mode (3 of 3) Controller Pixels Total H_CLKI
1515 1520 1525 1530 1535 1540 1300 1545 1550 1555 1560 1565 1570 1275 1575 1275 1575 1250 1250 1250 1250 1250 1250 1250 1250 1625
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1212 1216 1220 1224 1228 1232 1144 1236 1240 1244 1248 1252 1256 1122 1260 1088 1218 1096 1100 1104 1108 1112 1084 1088 1092 1248
V_LINESI
750 750 750 750 750 750 825 750 750 750 750 750 750 825 750 800 725 822 825 828 831 834 813 816 819 720
V_ACTIVEO
250 250 250 250 250 250 228 250 250 250 250 250 250 228 250 235 259 229 228 227 226 225 231 230 229 261
Horizontal
18.76 19.03 19.29 19.56 19.82 20.08 13.93 20.34 20.60 20.85 21.10 21.36 21.61 12.24 21.86 9.50 19.16 10.16 10.49 10.81 11.14 11.46 9.17 9.50 9.83 21.10
Vertical
13.19 13.19 13.19 13.19 13.19 13.19 20.83 13.19 13.19 13.19 13.19 13.19 13.19 20.83 13.19 18.40 10.07 20.49 20.83 21.18 21.53 21.88 19.79 20.14 20.49 9.38
Delta
5.57 5.83 6.10 6.36 6.63 6.89
-6.90
7.14 7.40 7.66 7.91 8.16 8.41
-8.59
8.66
-8.90
9.09
-10.32 -10.34 -10.37 -10.39 -10.42 -10.62 -10.64 -10.65
11.73
A-40
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-20. Overscan Values 800 x 600 PAL-BDGHI, Character Clock-Based Controller, 8-Pixel Resolution, 3:2 Clocking Mode Controller Pixels Total H_CLKI
1400 1400 1440 1480 1360 1520 1560
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1232 1120 1152 1184 1088 1216 1248
V_LINESI
825 750 750 750 750 750 750
V_ACTIVEO
228 250 250 250 250 250 250
Horizontal
20.08 12.09 14.53 16.84 9.50 19.03 21.10
Vertical
20.83 13.19 13.19 13.19 13.19 13.19 13.19
Delta
-0.75 -1.11
1.34 3.65
-3.69
5.83 7.91
Table A-21. Overscan Values 800 x 600 PAL-BDGHI, Character Clock-Based Controller, 9-Pixel Resolution, 3:2 Clocking Mode Controller Pixels Total H_CLKI
1440 1395 1350 1350 1485 1350 1530 1575 1575
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1152 1116 1188 1152 1188 1116 1224 1260 1218
V_LINESI
750 750 825 800 750 775 750 750 725
V_ACTIVEO
250 250 228 235 250 242 250 250 259
Horizontal
14.53 11.77 17.12 14.53 17.12 11.77 19.56 21.86 19.16
Vertical
13.19 13.19 20.83 18.40 13.19 15.97 13.19 13.19 10.07
Delta
1.34
-1.42 -3.71 -3.87
3.93
-4.20
6.36 8.66 9.09
100381B
Conexant
A-41
Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table A-22. Overscan Values 1024 x 768 NTSC, Pixel-Based Controller, 1-Pixel Resolution, >1.50 s. Hblank (1 of 4) Graphics Controller Total H_CLKI
1173 1170 1170 1170 1175 1176 1170 1176 1165 1179 1175 1167 1182 1164 1160 1180 1185 1161 1188 1158 1155 1155 1155 1185 1155 1155 1190 1155 1155 1155 1190
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1564 1404 1508 1456 1504 1568 1560 1456 1398 1572 1410 1556 1576 1552 1392 1416 1580 1548 1584 1544 1386 1474 1496 1422 1452 1518 1564 1540 1430 1364 1496
V_LINESI
1050 945 1015 980 1008 1050 1050 975 945 1050 945 1050 1050 1050 945 945 1050 1050 1050 1050 945 1005 1020 945 990 1035 1035 1050 975 930 990
V_ACTIVEO
192 214 199 206 200 192 192 207 214 192 214 192 192 192 214 214 192 192 192 192 214 201 198 214 204 195 195 192 207 217 204
Horizontal
20.97 11.97 18.04 15.11 17.82 21.18 20.77 15.11 11.59 21.38 12.34 20.57 21.58 20.36 11.21 12.71 21.77 20.16 21.97 19.95 10.82 16.15 17.38 13.08 14.88 18.58 20.97 19.74 13.57 9.39 17.38
Vertical
20.99 11.93 18.11 15.23 17.7 20.99 20.99 14.81 11.93 20.99 11.93 20.99 20.99 20.99 11.93 11.93 20.99 20.99 20.99 20.99 11.93 17.28 18.52 11.93 16.05 19.75 19.75 20.99 14.81 10.7 16.05
Delta
-0.01 0.03 -0.07 -0.11 0.13 0.19 -0.22 0.3 -0.34 0.39 0.41 -0.42 0.59 -0.63 -0.73 0.78 0.79 -0.83 0.98 -1.04 -1.11 -1.14 -1.14 1.15 -1.17 -1.17 1.22 -1.25 -1.25 -1.31 1.33
A-42
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-22. Overscan Values 1024 x 768 NTSC, Pixel-Based Controller, 1-Pixel Resolution, >1.50 s. Hblank (2 of 4) Graphics Controller Total H_CLKI
1155 1152 1150 1190 1150 1149 1197 1197 1197 1197 1200 1200 1195 1146 1145 1200 1197 1143 1200 1200 1140 1140 1200 1137 1205 1134 1135 1134 1134 1134 1134
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1408 1536 1380 1428 1472 1532 1558 1482 1406 1520 1568 1536 1434 1528 1374 1472 1444 1524 1504 1440 1368 1520 1408 1516 1446 1476 1362 1368 1440 1512 1404
V_LINESI
960 1050 945 945 1008 1050 1025 975 925 1000 1029 1008 945 1050 945 966 950 1050 987 945 945 1050 924 1050 945 1025 945 950 1000 1050 975
V_ACTIVEO
210 192 214 214 200 192 197 207 218 202 196 200 214 192 214 209 213 192 205 214 214 192 219 192 214 197 214 213 202 192 207
Horizontal
12.22 19.53 10.44 13.45 16.03 19.32 20.67 16.6 12.09 18.69 21.18 19.53 13.81 19.11 10.05 16.03 14.41 18.9 17.82 14.17 9.65 18.69 12.22 18.47 14.52 16.26 9.25 9.65 14.17 18.26 11.97
Vertical
13.58 20.99 11.93 11.93 17.7 20.99 18.93 14.81 10.29 16.87 19.34 17.7 11.93 20.99 11.93 13.99 12.35 20.99 15.64 11.93 11.93 20.99 9.88 20.99 11.93 18.93 11.93 12.35 16.87 20.99 14.81
Delta
-1.36 -1.45 -1.5 1.51 -1.66 -1.66 1.74 1.79 1.8 1.81 1.83 1.84 1.88 -1.88 -1.89 2.04 2.06 -2.09 2.18 2.23 -2.28 -2.3 2.34 -2.52 2.59 -2.67 -2.68 -2.69 -2.7 -2.73 -2.85
100381B
Conexant
A-43
Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table A-22. Overscan Values 1024 x 768 NTSC, Pixel-Based Controller, 1-Pixel Resolution, >1.50 s. Hblank (3 of 4) Graphics Controller Total H_CLKI
1210 1215 1215 1218 1215 1125 1125 1125 1225 1125 1125 1125 1225 1125 1220 1225 1225 1225 1225 1225 1225 1225 1225 1225 1225 1230 1239 1235 1240 1245 1250
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1452 1566 1512 1508 1458 1410 1390 1370 1568 1420 1400 1380 1554 1360 1464 1540 1582 1526 1512 1498 1484 1428 1470 1442 1456 1476 1534 1482 1488 1494 1500
V_LINESI
945 1015 980 975 945 987 973 959 1008 994 980 966 999 952 945 990 1017 981 972 963 954 918 945 927 936 945 975 945 945 945 945
V_ACTIVEO
214 199 206 207 214 205 208 211 200 203 206 209 202 212 214 204 199 206 208 210 212 220 214 218 216 214 207 214 214 214 214
Horizontal
14.88 21.07 18.26 18.04 15.23 12.34 11.08 9.78 21.18 12.96 11.72 10.44 20.47 9.12 15.58 19.74 21.87 19.01 18.26 17.49 16.71 13.45 15.92 14.29 15.11 16.26 19.43 16.6 16.94 17.27 17.6
Vertical
11.93 18.11 15.23 14.81 11.93 15.64 14.4 13.17 17.7 16.46 15.23 13.99 16.87 12.76 11.93 16.05 18.11 15.23 14.4 13.58 12.76 9.47 11.93 10.29 11.11 11.93 14.81 11.93 11.93 11.93 11.93
Delta
2.94 2.97 3.03 3.22 3.29 -3.3 -3.32 -3.39 3.48 -3.5 -3.51 -3.56 3.59 -3.64 3.64 3.69 3.77 3.78 3.85 3.91 3.96 3.98 3.99 4 4 4.33 4.61 4.67 5 5.34 5.67
A-44
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-22. Overscan Values 1024 x 768 NTSC, Pixel-Based Controller, 1-Pixel Resolution, >1.50 s. Hblank (4 of 4) Graphics Controller Total H_CLKI
1260 1260 1260 1260 1260 1260 1260 1255 1260 1260 1260 1260 1260 1260 1260 1260 1260 1265 1270 1275
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1584 1576 1568 1536 1560 1544 1552 1506 1480 1488 1496 1504 1512 1520 1528 1464 1472 1518 1524 1564
V_LINESI
990 985 980 960 975 965 970 945 925 930 935 940 945 950 955 915 920 945 945 966
V_ACTIVEO
204 205 206 210 207 209 208 214 218 217 216 215 214 213 212 221 220 214 214 209
Horizontal
21.97 21.58 21.18 19.53 20.77 19.95 20.36 17.93 16.49 16.94 17.38 17.82 18.26 18.69 19.11 15.58 16.03 18.58 18.9 20.97
Vertical
16.05 15.64 15.23 13.58 14.81 13.99 14.4 11.93 10.29 10.7 11.11 11.52 11.93 12.35 12.76 9.05 9.47 11.93 11.93 13.99
Delta
5.92 5.94 5.95 5.95 5.96 5.96 5.96 6 6.2 6.24 6.27 6.3 6.32 6.34 6.35 6.52 6.57 6.64 6.97 6.98
100381B
Conexant
A-45
Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table A-23. Overscan Values 1024 x 768 NTSC, Character Clock-Based Controller, 8-Pixel Resolution, >1.50 s HBlank Controller Pixels Total H_CLKI
1176 1176 1160 1152 1200 1200 1200 1200 1200 1200 1240 1280 1320 1176 1176 1160 1152 1200 1200 1200 1200 1200 1200 1128 1240 1280
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1568 1456 1392 1536 1568 1536 1472 1504 1440 1408 1488 1536 1584 1568 1456 1392 1536 1568 1536 1472 1504 1440 1408 1504 1488 1536
V_LINESI
1050 975 945 1050 1029 1008 966 987 945 924 945 945 945 1050 975 945 1050 1029 1008 966 987 945 924 1050 945 945
V_ACTIVEO
192 207 214 192 196 200 209 205 214 219 214 214 214 192 207 214 192 196 200 209 205 214 219 192 214 214
Horizontal
21.18 15.11 11.21 19.53 21.18 19.53 16.03 17.82 14.17 12.22 16.94 19.53 21.97 21.18 15.11 11.21 19.53 21.18 19.53 16.03 17.82 14.17 12.22 17.82 16.94 19.53
Vertical
20.99 14.81 11.93 20.99 19.34 17.70 13.99 15.64 11.93 9.88 11.93 11.93 11.93 20.99 14.81 11.93 20.99 19.34 17.70 13.99 15.64 11.93 9.88 20.99 11.93 11.93
Delta
0.19 0.30
-0.73 -1.45
1.83 1.84 2.04 2.18 2.23 2.34 5.00 7.60 10.04 0.19 0.30
-0.73 -1.45
1.83 1.84 2.04 2.18 2.23 2.34
-3.17
5.00 7.60
A-46
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-24. Overscan Values 1024 x 768 NTSC, Character Clock-Based Controller, 9-Pixel Resolution (1 of 2) Controller Pixels Total H_CLKI
1170 1170 1170 1170 1179 1161 1188 1152 1197 1197 1197 1197 1197 1143 1134 1134 1134 1134 1134 1215 1215 1215 1125 1125 1125 1125 1125 1125 1125 1125
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1404 1508 1456 1560 1572 1548 1584 1536 1558 1482 1406 1520 1444 1524 1476 1368 1440 1512 1404 1566 1512 1458 1410 1430 1390 1370 1420 1400 1380 1360
V_LINESI
945 1015 980 1050 1050 1050 1050 1050 1025 975 925 1000 950 1050 1025 950 1000 1050 975 1015 980 945 987 1001 973 959 994 980 966 952
V_ACTIVEO
214 199 206 192 192 192 192 192 197 207 218 202 213 192 197 213 202 192 207 199 206 214 205 202 208 211 203 206 209 212
Horizontal
11.97 18.04 15.11 20.77 21.38 20.16 21.97 19.53 20.67 16.60 12.09 18.69 14.41 18.90 16.26 9.65 14.17 18.26 11.97 21.07 18.26 15.23 12.34 13.57 11.08 9.78 12.96 11.72 10.44 9.12
Vertical
11.93 18.11 15.23 20.99 20.99 20.99 20.99 20.99 18.93 14.81 10.29 16.87 12.35 20.99 18.93 12.35 16.87 20.99 14.81 18.11 15.23 11.93 15.64 16.87 14.40 13.17 16.46 15.23 13.99 12.76
Delta
0.03
-0.07 -0.11 -0.22
0.39
-0.83
0.98
-1.45
1.74 1.79 1.80 1.81 2.06
-2.09 -2.67 -2.69 -2.70 -2.73 -2.85
2.97 3.03 3.29
-3.30 -3.30 -3.32 -3.39 -3.50 -3.51 -3.56 -3.64
100381B
Conexant
A-47
Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table A-24. Overscan Values 1024 x 768 NTSC, Character Clock-Based Controller, 9-Pixel Resolution (2 of 2) Controller Pixels Total H_CLKI
1260 1260 1260 1260 1260 1260 1260 1260 1260 1260 1260 1260 1260 1260 1260 1260
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1584 1576 1568 1536 1560 1544 1552 1480 1488 1496 1504 1512 1520 1528 1464 1472
V_LINESI
990 985 980 960 975 965 970 925 930 935 940 945 950 955 915 920
V_ACTIVEO
204 205 206 210 207 209 208 218 217 216 215 214 213 212 221 220
Horizontal
21.97 21.58 21.18 19.53 20.77 19.95 20.36 16.49 16.94 17.38 17.82 18.26 18.69 19.11 15.58 16.03
Vertical
16.05 15.64 15.23 13.58 14.81 13.99 14.40 10.29 10.70 11.11 11.52 11.93 12.35 12.76 9.05 9.47
Delta
5.92 5.94 5.95 5.95 5.96 5.96 5.96 6.20 6.24 6.27 6.30 6.32 6.34 6.35 6.52 6.57
A-48
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-25. Overscan Values 1024 x 768 PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, >3 s Hblank (1 of 3)
Graphics Controller Total
H_CLKI
1425 1410 1425 1425 1425 1425 1425 1400 1400 1440 1395 1455 1450 1375 1380 1375 1375 1375 1375 1375 1375 1375 1375 1470 1365 1475 1485 1350 1350 1350 1350
Encoder Pixels Active Total
H_CLKO
1520 1504 1596 1444 1406 1558 1482 1456 1568 1536 1488 1552 1508 1562 1472 1496 1540 1430 1452 1518 1474 1408 1386 1568 1456 1534 1584 1476 1512 1404 1440
Overscan (Percent)
V_LINESI
1000 1000 1050 950 925 1025 975 975 1050 1000 1000 1000 975 1065 1000 1020 1050 975 990 1035 1005 960 945 1000 1000 975 1000 1025 1050 975 1000
V_ACTIVEO
240 240 229 253 260 235 247 247 229 240 240 240 247 226 240 236 229 247 243 232 239 250 254 240 240 247 240 235 229 247 240
Horizontal
17.09 16.2 21.03 12.72 10.36 19.11 14.96 13.44 19.62 17.95 15.3 18.79 16.43 19.31 14.38 15.75 18.16 11.87 13.2 16.98 14.5 10.49 9.07 19.62 13.44 17.84 20.44 14.61 16.65 10.23 12.48
Vertical
16.67 16.67 20.49 12.15 9.72 18.4 14.24 14.24 20.49 16.67 16.67 16.67 14.24 21.53 16.67 18.06 20.49 14.24 15.62 19.44 17.01 13.19 11.81 16.67 16.67 14.24 16.67 18.4 20.49 14.24 16.67
Delta
0.42 -0.46 0.55 0.57 0.64 0.7 0.72 -0.8 -0.86 1.28 -1.36 2.13 2.19 -2.21 -2.29 -2.3 -2.32 -2.37 -2.42 -2.47 -2.52 -2.7 -2.74 2.96 -3.23 3.61 3.77 -3.79 -3.84 -4 -4.19
100381B
Conexant
A-49
Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table A-25. Overscan Values 1024 x 768 PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, >3 s Hblank (2 of 3)
Graphics Controller Total
H_CLKI
1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1335 1500 1500 1515 1325 1320 1525 1300 1305 1550 1275 1275 1575
Encoder Pixels Active Total
H_CLKO
1600 1608 1616 1568 1576 1536 1584 1544 1512 1592 1552 1520 1560 1496 1472 1528 1504 1480 1424 1488 1464 1616 1484 1408 1586 1456 1392 1612 1428 1394 1596
Overscan (Percent)
V_LINESI
1000 1005 1010 980 985 960 990 965 945 995 970 950 975 935 920 955 940 925 1000 930 915 1000 1050 1000 975 1050 1000 975 1050 1025 950
V_ACTIVEO
240 239 238 245 244 250 243 249 254 242 248 253 247 257 261 252 256 260 240 259 263 240 229 240 247 229 240 247 229 235 253
Horizontal
21.23 21.62 22.01 19.62 20.03 17.95 20.44 18.37 16.65 20.83 18.79 17.09 19.21 15.75 14.38 17.52 16.2 14.84 11.5 15.3 13.91 22.01 15.07 10.49 20.54 13.44 9.46 21.82 11.74 9.59 21.03
Vertical
16.67 17.01 17.36 14.93 15.28 13.19 15.62 13.54 11.81 15.97 13.89 12.15 14.24 10.76 9.38 12.5 11.11 9.72 16.67 10.07 8.68 16.67 20.49 16.67 14.24 20.49 16.67 14.24 20.49 18.4 12.15
Delta
4.56 4.61 4.65 4.69 4.75 4.75 4.81 4.83 4.84 4.86 4.91 4.93 4.97 4.99 5.01 5.02 5.09 5.12 -5.17 5.23 5.23 5.34 -5.41 -6.18 6.3 -7.05 -7.21 7.58 -8.74 -8.81 8.88
A-50
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Appendix A Scaling and I/0 Timing Register Calculations
Table A-25. Overscan Values 1024 x 768 PAL-BDGHI, Pixel-Based Controller, 1-Pixel Resolution, >3 s Hblank (3 of 3)
Graphics Controller Total
H_CLKI
1575 1250 1250 1250 1250 1250 1250 1250 1250 1250 1250 1250 1625 1625
Encoder Pixels Active Total
H_CLKO
1554 1420 1408 1424 1396 1412 1384 1400 1416 1388 1404 1392 1612 1586
Overscan (Percent)
V_LINESI
925 1065 1056 1068 1047 1059 1038 1050 1062 1041 1053 1044 930 915
V_ACTIVEO
260 226 228 225 230 227 232 229 226 231 228 230 259 263
Horizontal
18.9 11.25 10.49 11.5 9.72 10.74 8.94 9.98 11 9.2 10.23 9.46 21.82 20.54
Vertical
9.72 21.53 20.83 21.88 20.14 21.18 19.44 20.49 21.53 19.79 20.83 20.14 10.07 8.68
Delta
9.18 -10.2 -10.3 -10.3 -10.4 -10.4 -10.5 -10.5 -10.5 -10.5 -10.6 -10.6 11.75 11.85
100381B
Conexant
A-51
Appendix A Scaling and I/0 Timing Register Calculations
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table A-26. 1024 x 768 PAL-BDGHI, Character Clock-Based Controller, 8-Pixel Resolution, >4 s Hblank Controller Pixels Total H_CLKI
1400 1400 1440 1320
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1456 1568 1536 1408
V_LINESI
975 1050 1000 1000
V_ACTIVEO
247 229 240 240
Horizontal
13.44 19.62 17.95 10.49
Vertical
14.24 20.49 16.67 16.67
Delta
-0.8 -0.86 1.28 -6.18
Table A-27. Overscan Values 1024 x 768 PAL-BDGHI, Character Clock-Based Controller, 9-Pixel Resolution Controller Pixels Total H_CLKI
1440 1395 1485 1350 1350 1350 1350 1305 1575 1575
Encoder Pixels Overscan (Percent) Active Total H_CLKO
1536 1488 1584 1476 1512 1404 1440 1392 1596 1554
V_LINESI
1000 1000 1000 1025 1050 975 1000 1000 950 925
V_ACTIVEO
240 240 240 235 229 247 240 240 253 260
Horizontal
17.95 15.3 20.44 14.61 16.65 10.23 12.48 9.46 21.03 18.9
Vertical
16.67 16.67 16.67 18.4 20.49 14.24 16.67 16.67 12.15 9.72
Delta
1.28 -1.36 3.77 -3.79 -3.84 -4 -4.19 -7.21 8.88 9.18
A-52
Conexant
100381B
B
Appendix B Approved Crystal Vendors
Conexant conducted a series of internal tests and used the results to generate this list of approved crystal vendors for the CX25870/871. Manufacturers not appearing in this list may be acceptable, but verification testing on the target PCB with samples is recommended.
Standard Crystal (El Monte, CA)
Phone Number: FAX Number: E-mail: (626) 443-2121 (626) 443-9049 stdxtl@pacbell.net
Part Numbers for 13.500 MHz, Fundamental, 20 pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: Half-Height/50 ppm: Full Height/25 ppm: AAL13M500000GXE20A AAK13M500000GXE20A Did Not Qualify
MMD Components (Irvine, CA)
Phone Number: FAX Number: E-mail: Internet: (949) 753-5888 (949) 753-5889 info@mmdcomp.com www.mmdcomp.com
Part Numbers for 13.500 MHz, Fundamental, 20 pF Load Crystal with an HC49U Type of Package: Full Height/50ppm Total Tolerance: Half-Height/50 ppm: Full Height/25 ppm: Half Height/25 ppm: A20BA1-13.500 MHz B20BA1-13.500 MHz MMC-135-13.500 MHz (not tested) MMC-136-13.500 MHz (not tested)
General Electronics Devices (San Marcos, CA)
Phone Number: FAX Number: E-mail: Internet: (760) 591-4170 (760) 591-4164 gedlm@4dcomm.com www.gedlm.com
Part Numbers for 13.500 MHz, Fundamental, 20 pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: Half-Height/50 ppm: Full Height/25 ppm: Half-Height/25 ppm: PKHC49-13.500-.020-.005 PKHC49/-13.500-.020-.005 PKHC49/-13.500-.020-.0025-15R PKHC49/-13.500-.020-.0025
100381B
Conexant
B-1
Appendix B Approved Crystal Vendors
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Fox Electronics (Fort Myers, FL)
Phone Number: FAX Number: E-mail: Internet: (941) 693-0099 (941) 693-1554 sales@foxonline.com www.foxonline.com
Part Numbers for 13.500 MHz, Fundamental, 20 pF Load Crystal with an HC49U Type of Package: Full-Height/50 ppm Total Tolerance: Half-Height/50 ppm: Full-Height/25 ppm: Half-Height/25 ppm: HC49U-13.500 /50/0/70/20 pF HC49S-13.500/50/0/70/20 pF HC49U-13.500 /25/0/70/20 pF HC49S-13.500 /25/0/70/20 pF (not tested)
Bomar Crystal Co. (Middlesex, NJ)
Phone Number: FAX Number: E-mail: Internet: (732) 356-7787 (732) 356-7362 sales@bomarcrystal.com www.bomarcrystal.com
Part Numbers for 13.500 MHz, Fundamental, 20 pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: Half Height/50 ppm: Full Height/25 ppm: Half Height/25 ppm: BRC1C14F-13.50000 or (BC1DDA120-13.50000) ACR-49S012025-13.50000 or (BC14DDA120-13.50000) BRCIH14F-13.50000 or (BC1AAA120-13.50000 BC14AAA120-13.50000 (not tested)
ILSI America (Reno, NV)
Phone Number: FAX Number: E-mail: Internet: (775) 851-8880x103 / (888)355-4574 (775) 851-8882 e-mail@ilsiamerica.com www.ilsiamerica.com
Part Numbers for 13.500 MHz, Fundamental, 20 pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: Half Height/50 ppm: Full Height/25 ppm: HC49U-25/25-13.500-20 HC49US-FB1F20-13.500 Did Not Qualify
B-2
Conexant
100381B
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Appendix B Approved Crystal Vendors
Cardinal Components (Wayne, NJ)
Phone Number: FAX Number: E-mail: Internet: (973) 785-1333 (973) 785-0053 cardinal@cardinalxtal.com www.cardinalxtal.com
Part Numbers for 13.500 MHz, Fundamental, 20 pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: Half Height/50 ppm: Full Height/25 ppm: Half Height/25 ppm C49-A4BRC7-50-13.5D20 CLP-A4BRC7-70-13.5D20 C49-A4B6C4-25-13.5D20 CLP-A4B6C4-25-13.5D20
Raltron Electronics Corp. (Miami, FL)
Phone Number: FAX Number: E-mail: Internet: (305) 593-6033 (305) 594-3973 Sales@raltron.com www.raltron.com
Part Numbers for 13.500 MHz, Fundamental, 20 pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: Half Height/50 ppm: Full Height/25 ppm: Half Height/25ppm: A-13.500-20-RS1 AS-13.500-20-RS1 A-13.500-20-RS1 AS-13.500-20-SMD-NV
Valpey-Fisher (Hopkinton, MA)
Phone Number: FAX Number: Internet: (508) 435-6831 (508) 435-5289 www.valpeyfisher.com
Part Numbers for 13.500 MHz, Fundamental, 20 pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: Half Height/50 ppm: Full Height/25 ppm: M490013.500020RSVM M49K013.50002099VM M490013.50002099VM
Corning Frequency Control (Mount Holly Springs, PA)
Phone Number: E-mail: Internet: (717) 486-3411 FAX Number:(717) 486-5920 sales@ofc.come www.corningfrequency.com
Part Numbers for 13.500 MHz, Fundamental, 20 pF Load Crystal with an HC49U Type of Package: Full Height/50 ppm Total Tolerance: Half Height/50 ppm: Full Height/25 ppm: Half Height/25 ppm: TQ RSD 13.5FH50 TQ RSD 13.5LP50 TQ RSD 13.5FH25 TQ RSD 13.5LP25 (not tested)
100381B
Conexant
B-3
Appendix B Approved Crystal Vendors
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
B-4
Conexant
100381B
C
Appendix C Autoconfiguration Mode Register Values and Details
Table C-1. CX25870/871 Register Values for Autoconfiguration Modes 0-4 (1 of 3) Autoconfiguration Mode #
Auto-Config Register (index 0xB8) Hexadecimal Value: Purpose of mode: Type of Digital Input: Active Resolution: Overscan Ratio: Horizontal Overscan Ratio/Percentage (HOC): Vertical Overscan Ratio/Percentage (VOC): Overscan Percentages Delta (HOC - VOC): H_CLKI = HTOTAL VLINES_I = VTOTAL H_BLANKI = Horizontal Blanking Region V_BLANKI = Vertical Blanking Region Type of Video Output: Frequency of CLK (Hz) Type of Clock:
0
00 Desktop RGB 640x480 Lower 13.79 13.58 0.21 784 600 126 75 NTSC 28195793 Pixel or Character
1
01 Desktop RGB 640x480 Standard 16.56 16.67 -0.11 944 625 266 90 PAL-BDGHI 29500008 Pixel or Character
2
02 Desktop RGB 800x600 Alternate 21.62 11.52 10.10 880 735 66 86 NTSC 38769241 Pixel or Character
3
03 Desktop RGB 800x600 Lower 14.53 13.19 1.34 960 750 140 95 PAL-BDGHI 36000000 Pixel or Character
4
04 Desktop YCrCb 640x480 Lower 13.79 13.58 0.21 784 600 126 75 NTSC 28195793 Pixel or Character
100381B
Conexant
C-1
Appendix C Autoconfiguration Mode Register Values and Details
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table C-1. CX25870/871 Register Values for Autoconfiguration Modes 0-4 (2 of 3) Autoconfiguration Mode # Register Address
0x38 0x76 0x78 0x7A 0x7C 0x7E 0x80 0x82 0x84 0x86 0x88 0x8A 0x8C 0x8E 0x90 0x92 0x94 0x96 0x98 0x9A 0x9C 0x9E 0xA0 0xA2 0xA4 0xA6 0xA8 0xAA 0xAC 0xAE
0 Register Value
00 00 80 84 96 60 7D 22 D4 27 00 10 7E 03 58 4B E0 36 92 54 0E 88 0C 0A E5 76 79 44 85 00
1 Register Value
00 60 80 8A A6 68 C1 2E F2 27 00 B0 0A 0B 71 5A E0 36 00 50 72 1C 0D 24 F0 58 81 49 8C 0C
2 Register Value
00 A0 20 B6 CE B4 55 20 D8 39 00 70 42 03 DF 56 58 3A CD 9C 14 3B 11 0A E5 74 77 43 85 BA
3 Register Value
00 00 20 AA CA 9A 0D 29 FC 39 00 C0 8C 03 EE 5F 58 3A 66 96 00 00 10 24 F0 57 80 48 8C 18
4 Register Value
00 00 80 84 96 60 7D 22 D4 27 00 10 7E 03 58 4B E0 36 92 54 0E 88 0C 0A E5 76 79 44 85 00
C-2
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100381B
CX25870/871
Appendix C Autoconfiguration Mode Register Values and Details
Flicker-Free Video Encoder with Ultrascale Technology
Table C-1. CX25870/871 Register Values for Autoconfiguration Modes 0-4 (3 of 3) Autoconfiguration Mode #
0xB0 0xB2 0xB4
NOTE(S):
0
00 80 20
1
8C 79 26
2
E8 A2 17
3
28 87 1F
4
00 80 20
1. RGB digital input denotes that the CX25870/871 will be configured to receive the RGB default pixel input mode after an autoconfiguration command which is 24-bit, RGB-multiplexed (i.e., IN_MODE[3:0] = 0000). If the desired RGB pixel input mode is NOT 24-bit RGB-multiplexed, the CX25870/871's IN_MODE[3:0] bits must be programmed to the desired RGB pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 2. YCrCb digital input denotes that the CX25870/871 will be configured to receive YCrCb pixel data after an autoconfiguration command. The CX25870/871's IN_MODE[3:0] bits must be programmed to the desired YCrCb pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 3. CX25870/871 registers not listed in this table (including IN_MODE[3:0]) do not get reprogrammed as a result of an autoconfiguration command. 4. Pixel or Character signifies that this overscan ratio is acceptable for 8-clock per character graphics controllers or pixel-clock controllers. 5. The CX25870/871 will be in master interface immediately after any autoconfiguration mode EXCEPT Mode 28 and Mode 29. 6. Mode 44 would ideally have 858 clocks per line. However, since 858 is not a multiple of 8, then 880 clocks per line was utilized instead. 7. These autoconfiguration values assume a 13.500 MHz crystal resides between the XTALIN and XTALOUT pins. If the 14318_XTAL bit is set, then these autoconfiguration values will automatically change to reflect the presence of a 14.318 MHz crystal.
100381B
Conexant
C-3
Appendix C Autoconfiguration Mode Register Values and Details
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table C-2. CX25870/871 Register Values for Autoconfiguration Modes 5-10 (1 of 2) Autoconfiguration Mode #
Auto-Config Register (index 0xB8) Hexadecimal Value: Purpose of Mode: Type of Digital Input: Active Resolution: Overscan Ratio: Horizontal Overscan Ratio/Percentage (HOC): Vertical Overscan Ratio/Percentage (VOC): Overscan Percentages Delta (HOC - VOC): H_CLKI = HTOTAL VLINES_I = VTOTAL H_BLANKI = Horizontal Blanking Region V_BLANKI = Vertical Blanking Region Type of Video Output: Frequency of CLK (Hz) Type of Clock: 05 Desktop YCrCb 640x480 Standard 16.56 16.67 -0.11 944 625 266 90 PAL-BDGHI 29500008 Pixel or Character
5
06
6
07
7
10
8
11
9
12
10
Desktop YCrCb 800x600 Alternate 21.62 11.52 10.10 880 735 66 86 NTSC 38769241 Pixel or Character
Desktop YCrCb 800x600 Lower 14.53 13.19 1.34 960 750 140 95 PAL-BDGHI 36000000 Pixel or Character
Boot-Up Screen RGB 640x400 Standard 17.47 17.70 -0.23 936 525 259 76 NTSC 29454552 Pixel or Character
Boot-Up Screen RGB 640x400 Standard 15.12 13.19 1.93 1160 500 363 64 PAL-BDGHI 28999992 Pixel or Character
Desktop RGB 1024x768 Standard 15.11 14.81 0.30 1176 975 133 130 NTSC 68727276 Pixel or Character
Register Address
0x38 0x76 0x78 0x7A 0x7C 0x7E 0x80 0x82 0x84 0x86 0x88 0x8A
Register Value
00 60 80 8A A6 68 C1 2E F2 27 00 B0
Register Value
00 A0 20 B6 CE B4 55 20 D8 39 00 70
Register Value
00 00 20 AA CA 9A 0D 29 FC 39 00 C0
Register Value
00 50 80 8A 9C 6A A9 27 CA 27 00 A8
Register Value
00 40 80 88 A2 64 AF 29 FC 27 00 88
Register Value
20 60 00 D8 F2 EE 71 24 D0 4B 00 98
C-4
Conexant
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CX25870/871
Appendix C Autoconfiguration Mode Register Values and Details
Flicker-Free Video Encoder with Ultrascale Technology
Table C-2. CX25870/871 Register Values for Autoconfiguration Modes 5-10 (2 of 2) Autoconfiguration Mode #
0x8C 0x8E 0x90 0x92 0x94 0x96 0x98 0x9A 0x9C 0x9E 0xA0 0xA2 0xA4 0xA6 0xA8 0xAA 0xAC 0xAE 0xB0 0xB2 0xB4
NOTE(S):
5
0A 0B 71 5A E0 36 00 50 72 1C 0D 24 F0 58 81 49 8C 0C 8C 79 26 42 03 DF 56 58 3A CD 9C 14 3B 11 0A E5 74 77 43 85 BA E8 A2 17
6
8C 03 EE 5F 58 3A 66 96 00 00 10 24 F0 57 80 48 8C 18 28 87 1F
7
03 0B 0D 4C 90 36 00 50 46 17 0D 0A E5 75 79 44 85 C7 71 1C 1F
8
6B 0C F4 40 90 35 9A 49 8E E3 0C 24 F0 58 82 49 8C E9 5D 23 27
9
85 04 CF 82 00 3F 6E AB A3 8B 1E 0A E5 74 77 43 85 00 00 00 14
10
1. RGB digital input denotes that the CX25870/871 will be configured to receive the RGB default pixel input mode after an autoconfiguration command, which is 24-bit, RGB-multiplexed (i.e., IN_MODE[3:0] = 0000). If the desired RGB pixel input mode is NOT 24-bit RGB-multiplexed, the CX25870/871's IN_MODE[3:0] bits must be programmed to the desired RGB pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 2. YCrCb digital input denotes that the CX25870/871 will be configured to receive YCrCb pixel data after an autoconfiguration command. The CX25870/871's IN_MODE[3:0] bits must be programmed to the desired YCrCb pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 3. CX25870/871 registers not listed in this table (including IN_MODE[3:0]) do not get reprogrammed as a result of an autoconfiguration command. 4. Pixel or Character signifies that this overscan ratio is acceptable for 8-clock per character graphics controllers or pixel-clock controllers. 5. The CX25870/871 will be in master interface immediately after any autoconfiguration mode EXCEPT Mode 28 and Mode 29. 6. Mode 44 would ideally have 858 clocks per line. However, since 858 is not a multiple of 8, then 880 clocks per line was utilized instead. 7. These autoconfiguration values assume a 13.500 MHz crystal resides between the XTALIN and XTALOUT pins. If the 14318_XTAL bit is set, then these autoconfiguration values will automatically change to reflect the presence of a 14.318 MHz crystal.
100381B
Conexant
C-5
Appendix C Autoconfiguration Mode Register Values and Details
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table C-3. CX25870/871 Register Values for Autoconfiguration Modes 11-15 (1 of 2) Autoconfiguration Mode #
Auto-Config Register (index 0xB8) Hexadecimal Value: Purpose of Mode: Type of Digital Input: Active Resolution: Overscan Ratio: Horizontal Overscan Ratio/Percentage (HOC): Vertical Overscan Ratio/Percentage (VOC): Overscan Percentages Delta (HOC - VOC): H_CLKI = HTOTAL VLINES_I = VTOTAL H_BLANKI = Horizontal Blanking Region V_BLANKI = Vertical Blanking Region Type of Video Output: Frequency of CLK (Hz) Type of Clock: 13 Desktop RGB 1024x768 Standard 13.44 14.24 -0.80 1400 975 329 131 PAL-BDGHI 68249989 Pixel or Character
11
14 Game RGB
12
15 Game RGB
13
16
14
17
15
Desktop YCrCb 1024x768 Higher 15.11 14.81 0.30 1176 975 133 130 NTSC 68727276 Pixel or Character
Desktop YCrCb 1024x768 Higher 13.44 14.24 -0.80 1400 975 329 131 PAL-BDGHI 68249989 Pixel or Character
320x240, Pix_Double Set Standard 13.79 13.58 0.21 1568 300 349 37 NTSC 28195793 Pixel or Character
320x240, Pix_Double Set Standard 15.84 19.79 -3.95 1800 325 385 50 PAL-BDGHI 29250000 Pixel or Character
Register Address
0x38 0x76 0x78 0x7A 0x7C 0x7E 0x80 0x82 0x84 0x86 0x88 0x8A
Register Value
20 60 00 D6 FE E6 87 2B F8 4B 00 78
Register Value
40 00 80 84 96 60 7D 22 D5 27 00 20
Register Value
40 50 80 8A A4 66 B7 32 EA 27 00 08
Register Value
20 60 00 D8 F2 EE 71 24 D0 4B 00 98
Register Value
20 60 00 D6 FE E6 87 2B F8 4B 00 78
C-6
Conexant
100381B
CX25870/871
Appendix C Autoconfiguration Mode Register Values and Details
Flicker-Free Video Encoder with Ultrascale Technology
Table C-3. CX25870/871 Register Values for Autoconfiguration Modes 11-15 (2 of 2) Autoconfiguration Mode #
0x8C 0x8E 0x90 0x92 0x94 0x96 0x98 0x9A 0x9C 0x9E 0xA0 0xA2 0xA4 0xA6 0xA8 0xAA 0xAC 0xAE 0xB0 0xB2 0xB4
NOTE(S):
11
49 0D CF 83 00 3F EC A1 55 55 1E 24 F0 56 7F 47 8C 57 F8 F1 18
12
5D 1E 2C 25 F0 31 49 42 0E 88 0C 0A E5 76 79 44 85 00 00 80 20
13
81 1F 45 32 F0 31 A4 40 00 00 0D 24 F0 58 81 49 8C 32 BB CD 26
14
85 04 CF 82 00 3F 6E AB A3 8B 1E 0A E5 74 77 43 85 00 00 00 14
15
49 0D CF 83 00 3F EC A1 55 55 1E 24 F0 56 7F 47 8C 57 F8 F1 18
1. RGB digital input denotes that the CX25870/871 will be configured to receive the RGB default pixel input mode after an autoconfiguration command, which is 24-bit, RGB-multiplexed (i.e., IN_MODE[3:0] = 0000). If the desired RGB pixel input mode is NOT 24-bit RGB multiplexed, the CX25870/871's IN_MODE[3:0] bits must be programmed to the desired RGB pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 2. YCrCb digital input denotes that the CX25870/871 will be configured to receive YCrCb pixel data after an autoconfiguration command. The CX25870/871's IN_MODE[3:0] bits must be programmed to the desired YCrCb pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 3. CX25870/871 registers not listed in this table (including IN_MODE[3:0]) do not get reprogrammed as a result of an autoconfiguration command. 4. Pixel or Character signifies that this overscan ratio is acceptable for 8-clock per character graphics controllers or pixel-clock controllers. 5. The CX25870/871 will be in master interface immediately after any autoconfiguration mode EXCEPT Mode 28 and Mode 29. 6. Mode 44 would ideally have 858 clocks per line. However, since 858 is not a multiple of 8, then 880 clocks per line was utilized instead. 7. These autoconfiguration values assume a 13.500 MHz crystal resides between the XTALIN and XTALOUT pins. If the 14318_XTAL bit is set, then these autoconfiguration values will automatically change to reflect the presence of a 14.318 MHz crystal.
100381B
Conexant
C-7
Appendix C Autoconfiguration Mode Register Values and Details
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table C-4. CX25870/871 Register Values for Autoconfiguration Modes 16-21 (1 of 2) Autoconfiguration Mode #
Auto-Config Register (index 0xB8) Hexadecimal Value: Purpose of Mode: Type of Digital Input: Active Resolution: Overscan Ratio: Horizontal Overscan Ratio/Percentage (HOC): Vertical Overscan Ratio/Percentage (VOC): Overscan Percentages Delta (HOC - VOC): H_CLKI = HTOTAL VLINES_I = VTOTAL H_BLANKI = Horizontal Blanking Region V_BLANKI = Vertical Blanking Region Type of Video Output: Frequency of CLK (Hz) Type of Clock:
16
Reserved 21
17
22
18
23
19
20
Reserved 25
21
Desktop RGB 640x480 Lower 13.63 13.19 0.44 950 600 271 76 PAL-BDGHI 28500011 Pixel Only
Desktop RGB 800x600 Lower 13.79 13.58 0.21 1176 750 329 94 NTSC 52867138 Pixel or Character
Desktop RGB 800x600 Standard 16.42 15.97 0.45 950 775 131 109 PAL-BDGHI 36812508 Pixel Only
Desktop YCrCb 640x480 Lower 13.63 13.19 0.44 950 600 271 76 PAL-BDGHI 28500011 Pixel Only
Register Address
0x38 0x76 0x78 0x7A 0x7C 0x7E 0x80 0x82 0x84 0x86 0x88 0x8A 0x8C
Register Value
00 20 80 86 A0 60 9D 29 FC 27 00 B6 0F
Register Value
20 C0 20 A6 BA 98 D9 22 D4 38 00 98 49
Register Value
00 34 20 AE CE A0 2B 2D F4 39 00 B6 83
Register Value
00 20 80 86 A0 60 9D 29 FC 27 00 B6 0F
C-8
Conexant
100381B
CX25870/871
Appendix C Autoconfiguration Mode Register Values and Details
Flicker-Free Video Encoder with Ultrascale Technology
Table C-4. CX25870/871 Register Values for Autoconfiguration Modes 16-21 (2 of 2) Autoconfiguration Mode #
0x8E 0x90 0x92 0x94 0x96 0x98 0x9A 0x9C 0x9E 0xA0 0xA2 0xA4 0xA6 0xA8 0xAA 0xAC 0xAE 0xB0 0xB2 0xB4
NOTE(S):
16
17
0B 58 4C E0 36 B8 4E AB AA 0C 24 F0 58 82 49 8C 2C 25 D3 27
18
0C EE 5E 58 3A B7 5D 1B 7F 17 0A E5 74 78 43 85 00 00 00 1A
19
03 07 6D 58 3B AE 97 72 5C 10 24 F0 57 80 48 8C 01 04 D5 1E
20
21
0B 58 4C E0 36 B8 4E AB AA 0C 24 F0 58 82 49 8C 2C 25 D3 27
1. RGB digital input denotes that the CX25870/871 will be configured to receive the RGB default pixel input mode after an autoconfiguration command, which is 24-bit, RGB-multiplexed (i.e., IN_MODE[3:0] = 0000). If the desired RGB pixel input mode is NOT 24-bit RGB-multiplexed, the CX25870/871's IN_MODE[3:0] bits must be programmed to the desired RGB pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 2. YCrCb digital input denotes that the CX25870/871 will be configured to receive YCrCb pixel data after an autoconfiguration command. The CX25870/871's IN_MODE[3:0] bits must be programmed to the desired YCrCb pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 3. CX25870/871 registers not listed in this Table (including IN_MODE[3:0]) do not get reprogrammed as a result of an autoconfiguration command. 4. Pixel or Character signifies that this overscan ratio is acceptable for 8-clock per character graphics controllers or pixel-clock controllers. 5. The CX25870/871 will be in master interface immediately after any autoconfiguration mode EXCEPT Mode 28 and Mode 29. 6. Mode 44 would ideally have 858 clocks per line. However, since 858 is not a multiple of 8, then 880 clocks per line was utilized instead. 7. These autoconfiguration values assume a 13.500 MHz crystal resides between the XTALIN and XTALOUT pins. If the 14318_XTAL bit is set, then these autoconfiguration values will automatically change to reflect the presence of a 14.318 MHz crystal.
100381B
Conexant
C-9
Appendix C Autoconfiguration Mode Register Values and Details
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table C-5. CX25870/871 Register Values for Autoconfiguration Modes 22-26 (1 of 2) Autoconfiguration Mode #
Auto-Config Register (index 0xB8) Hexadecimal Value: Purpose of Mode: Type of Digital Input: Active Resolution: Overscan Ratio: Horizontal Overscan Ratio/Percentage (HOC): Vertical Overscan Ratio/Percentage (VOC): Overscan Percentages Delta (HOC - VOC): H_CLKI = HTOTAL VLINES_I = VTOTAL H_BLANKI = Horizontal Blanking Region V_BLANKI = Vertical Blanking Region Type of Video Output: Frequency of CLK (Hz) Type of Clock: 26 Desktop YCrCb 800x600 Lower 13.79 13.58 0.21 1176 750 329 94 NTSC 52867138 Pixel or Character
22
27
23
30
24
31
25
32
26
Desktop YCrCb 800x600 Standard 16.42 15.97 0.45 950 775 131 109 PAL-BDGHI 36812508 Pixel Only
Boot-Up Screen RGB 720x400 Standard 17.47 17.70 -0.23 1053 525 291 76 NTSC 33136345 Pixel or 9-Character only
Boot-Up Screen RGB 720x400 Standard 15.12 13.19 1.93 1305 500 411 64 PAL-BDGHI 32625000 Pixel or 9-Character only
Desktop RGB 1024x768 Lower 11.97 11.93 0.04 1170 945 127 115 NTSC 66272724 Pixel Only
Register Address
0x38 0x76 0x78 0x7A 0x7C 0x7E 0x80 0x82 0x84 0x86 0x88
Register Value
20 C0 20 A6 BA 98 D9 22 D4 38 00
Register Value
00 34 20 AE CE A0 2B 2D F4 39 00
Register Value
00 3A D0 9C B0 88 DD 27 CA 28 00
Register Value
00 28 D0 9A B6 80 E3 29 FC 28 00
Register Value
20 F8 00 D0 EA E0 37 21 D7 4A 00
C-10
Conexant
100381B
CX25870/871
Appendix C Autoconfiguration Mode Register Values and Details
Flicker-Free Video Encoder with Ultrascale Technology
Table C-5. CX25870/871 Register Values for Autoconfiguration Modes 22-26 (2 of 2) Autoconfiguration Mode #
0x8A 0x8C 0x8E 0x90 0x92 0x94 0x96 0x98 0x9A 0x9C 0x9E 0xA0 0xA2 0xA4 0xA6 0xA8 0xAA 0xAC 0xAE 0xB0 0xB2 0xB4
NOTE(S):
22
98 49 0C EE 5E 58 3A B7 5D 1B 7F 17 0A E5 74 78 43 85 00 00 00 1A
23
B6 83 03 07 6D 58 3B AE 97 72 5C 10 24 F0 57 80 48 8C 01 04 D5 1E
24
1D 23 0C 0D 4C 90 36 00 50 2E BA 0E 0A E5 75 78 43 85 95 81 A7 1B
25
19 9B 0D F4 40 90 35 9A 49 00 80 0E 24 F0 57 80 48 8C 97 1A CA 22
26
92 7F 04 B1 73 00 3F 9A A9 5D 74 1D 0A E5 74 77 43 85 2F A1 BD 14
1. RGB digital input denotes that the CX25870/871 will be configured to receive the RGB default pixel input mode after an autoconfiguration command, which is 24-bit, RGB-multiplexed (i.e., IN_MODE[3:0] = 0000). If the desired RGB pixel input mode is NOT 24-bit RGB multiplexed, the CX25870/871's IN_MODE[3:0] bits must be programmed to the desired RGB pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 2. YCrCb digital input denotes that the CX25870/871 will be configured to receive YCrCb pixel data after an autoconfiguration command. The CX25870/871's IN_MODE[3:0] bits must be programmed to the desired YCrCb pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 3. CX25870/871 registers not listed in this table (including IN_MODE[3:0]) do not get reprogrammed as a result of an autoconfiguration command. 4. Pixel or Character signifies that this overscan ratio is acceptable for 8-clock per character graphics controllers or pixel-clock controllers. 5. The CX25870/871 will be in master interface immediately after any autoconfiguration mode EXCEPT Mode 28 and Mode 29. 6. Mode 44 would ideally have 858 clocks per line. However, since 858 is not a multiple of 8, then 880 clocks per line was utilized instead. 7. These autoconfiguration values assume a 13.500 MHz crystal resides between the XTALIN and XTALOUT pins. If the 14318_XTAL bit is set, then these autoconfiguration values will automatically change to reflect the presence of a 14.318 MHz crystal.
100381B
Conexant
C-11
Appendix C Autoconfiguration Mode Register Values and Details
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table C-6. CX25870/871 Register Values for Autoconfiguration Modes 27-30 (1 of 2) Autoconfiguration Mode #
Auto-Config Register (index 0xB8) Hexadecimal Value: Purpose of Mode: Type of Digital Input: Active Resolution: Overscan Ratio: Horizontal Overscan Ratio/Percentage (HOC): Vertical Overscan Ratio/Percentage (VOC): Overscan Percentages Delta (HOC - VOC): H_CLKI = HTOTAL VLINES_I = VTOTAL H_BLANKI = Horizontal Blanking Region V_BLANKI = Vertical Blanking Region Type of Video Output: Frequency of CLK (Hz) Type of Clock:
27
Reserved 34
28(5)
35
29(5)
36 Desktop YCrCb
30
"DVD/CCIR601 Input, Slave interface" YCrCb 720x480 None (DVD Playback) 0.00 0.00 0.00 858 262 10 19 NTSC 27000000 Pixel or Character
"DVD/CCIR601 Input, Slave interface" YCrCb 720x576 None (DVD Playback) 0.00 0.00 0.00 864 312 10 22 PAL-BDGHI 27000000 Pixel or Character
1024x768 Lower 11.97 11.93 0.04 1170 945 127 115 NTSC 66272724 Pixel Only
Register Address
0x38 0x76 0x78 0x7A 0x7C 0x7E 0x80 0x82 0x84 0x86 0x88 0x8A 0x8C
Register Value
10 B4 D0 7E 90 58 03 14 F0 26 15 5A 0A
Register Value
10 C0 D0 7E 98 54 15 17 20 A6 FA 60 0A
Register Value
20 F8 00 D0 EA E0 37 21 D7 4A 00 92 7F
C-12
Conexant
100381B
CX25870/871
Appendix C Autoconfiguration Mode Register Values and Details
Flicker-Free Video Encoder with Ultrascale Technology
Table C-6. CX25870/871 Register Values for Autoconfiguration Modes 27-30 (2 of 2) Autoconfiguration Mode #
0x8E 0x90 0x92 0x94 0x96 0x98 0x9A 0x9C 0x9E 0xA0 0xA2 0xA4 0xA6 0xA8 0xAA 0xAC 0xAE 0xB0 0xB2 0xB4
NOTE(S):
27
28(5)
13 06 13 F0 31 00 40 00 00 8C 0A E5 76 C1 89 9A 1F 7C F0 21
29(5)
13 38 16 20 35 00 40 00 00 8C 24 F0 59 CF 93 A4 CB 8A 09 2A
30
04 B1 73 00 3F 9A A9 5D 74 1D 0A E5 74 77 43 85 2F A1 BD 14
1. RGB digital input denotes that the CX25870/871 will be configured to receive the RGB default pixel input mode after an autoconfiguration command, which is 24-bit, RGB-multiplexed (i.e., IN_MODE[3:0] = 0000). If the desired RGB pixel input mode is NOT 24-bit RGB multiplexed, the CX25870/871's IN_MODE[3:0] bits must be programmed to the desired RGB pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 2. YCrCb digital input denotes that the CX25870/871 will be configured to receive YCrCb pixel data after an autoconfiguration command. The CX25870/871's IN_MODE[3:0] bits must be programmed to the desired YCrCb pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 3. CX25870/871 registers not listed in this table (including IN_MODE[3:0]) do not get reprogrammed as a result of an autoconfiguration command. 4. Pixel or Character signifies that this overscan ratio is acceptable for 8-clock per character graphics controllers or pixel-clock controllers. (5) The CX25870/871 will be in master interface immediately after any autoconfiguration mode EXCEPT Mode 28 and Mode 29. 6. Mode 44 would ideally have 858 clocks per line. However, since 858 is not a multiple of 8, then 880 clocks per line was utilized instead. 7. These autoconfiguration values assume a 13.500 MHz crystal resides between the XTALIN and XTALOUT pins. If the 14318_XTAL bit is set, then these autoconfiguration values will automatically change to reflect the presence of a 14.318 MHz crystal.
100381B
Conexant
C-13
Appendix C Autoconfiguration Mode Register Values and Details
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table C-7. CX25870/871 Register Values for Autoconfiguration Modes 31-36 (1 of 2) Autoconfiguration Mode #
Auto-Config Register (index 0xB8) Hexadecimal Value: Purpose of Mode: Type of Digital Input: Active Resolution: Overscan Ratio: Horizontal Overscan Ratio/Percentage (HOC): Vertical Overscan Ratio/Percentage (VOC): Overscan Percentages Delta (HOC - VOC): H_CLKI = HTOTAL VLINES_I = VTOTAL H_BLANKI = Horizontal Blanking Region V_BLANKI = Vertical Blanking Region Type of Video Output: Frequency of CLK (Hz) Type of Clock:
31
Reserved 40
32
41
33
42
34
43
35
44
36
Desktop RGB 640x480 Higher 18.34 19.34 -1.00 770 645 113 100 NTSC 29769241 Pixel Only
Desktop RGB 640x480 Higher 20.27 19.79 0.48 950 650 271 104 PAL-BDGHI 30875015 Pixel Only
Desktop RGB 800x600 Higher 19.26 19.34 -0.08 1170 805 323 125 NTSC 56454552 Pixel Only
Desktop RGB 800x600 Higher 19.03 18.40 0.63 950 800 131 122 PAL-BDGHI 37999992 Pixel Only
Desktop YCrCb 640x480 Higher 18.34 19.34 -1.00 770 645 113 100 NTSC 29769241 Pixel Only
Register Address
0x38 0x76 0x78 0x7A 0x7C 0x7E 0x80 0x82 0x84 0x86 0x88 0x8A 0x8C
Register Value
00 64 80 8C 9E 6E B5 2A C5 27 00 02 71
Register Value
00 B8 80 92 AC 72 F3 33 E9 27 00 B6 0F
Register Value
20 58 20 B0 C8 AC 2D 2A C5 39 00 92 43
Register Value
00 80 20 B2 D4 AA 57 31 EC 39 00 B6 83
Register Value
00 64 80 8C 9E 6E B5 2A C5 27 00 02 71
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Appendix C Autoconfiguration Mode Register Values and Details
Flicker-Free Video Encoder with Ultrascale Technology
Table C-7. CX25870/871 Register Values for Autoconfiguration Modes 31-36 (2 of 2) Autoconfiguration Mode #
0x8E 0x90 0x92 0x94 0x96 0x98 0x9A 0x9C 0x9E 0xA0 0xA2 0xA4 0xA6 0xA8 0xAA 0xAC 0xAE 0xB0 0xB2 0xB4
NOTE(S):
31
32
03 85 64 E0 36 50 57 14 3B 0D 0A E5 75 79 44 85 F2 40 C8 1E
33
0B 8A 68 E0 36 48 51 E4 B8 0D 24 F0 58 81 48 8C 3D E7 C2 24
34
0C 25 7D 58 3B 11 A1 46 17 19 0A E5 74 77 43 85 21 0B 59 18
35
03 20 7A 58 3B F6 98 8E E3 10 24 F0 57 7F 48 8C E1 5B DE 1D
36
03 85 64 E0 36 50 57 14 3B 0D 0A E5 75 79 44 85 F2 40 C8 1E
1. RGB digital input denotes that the CX25870/871 will be configured to receive the RGB default pixel input mode after an autoconfiguration command, which is 24-bit, RGB-multiplexed (i.e., IN_MODE[3:0] = 0000). If the desired RGB pixel input mode is NOT 24-bit RGB multiplexed, the CX25870/871's IN_MODE[3:0] bits must be programmed to the desired RGB pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 2. YCrCb digital input' denotes that the CX25870/871 will be configured to receive YCrCb pixel data after an autoconfiguration command. The CX25870/871's IN_MODE[3:0] bits must be programmed to the desired YCrCb pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 3. CX25870/871 registers not listed in this table (including IN_MODE[3:0]) do not get reprogrammed as a result of an autoconfiguration command. 4. Pixel or Character signifies that this overscan ratio is acceptable for 8-clock per character graphics controllers or pixel-clock controllers. 5. The CX25870/871 will be in master interface immediately after any autoconfiguration mode EXCEPT Mode 28 and Mode 29. 6. Mode 44 would ideally have 858 clocks per line. However, since 858 is not a multiple of 8, then 880 clocks per line was utilized instead. 7. These autoconfiguration values assume a 13.500 MHz crystal resides between the XTALIN and XTALOUT pins. If the 14318_XTAL bit is set, then these autoconfiguration values will automatically change to reflect the presence of a 14.318 MHz crystal.
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Appendix C Autoconfiguration Mode Register Values and Details
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table C-8. CX25870/871 Register Values for Autoconfiguration Modes 37-42 (1 of 2) Autoconfiguration Mode #
Auto-Config Register (index 0xB8) Hexadecimal Value: Purpose of Mode: Type of Digital Input: Active Resolution: Overscan Ratio: Horizontal Overscan Ratio/Percentage (HOC): Vertical Overscan Ratio/Percentage (VOC): Overscan Percentages Delta (HOC - VOC): H_CLKI = HTOTAL VLINES_I = VTOTAL H_BLANKI = Horizontal Blanking Region V_BLANKI = Vertical Blanking Region Type of Video Output: Frequency of CLK (Hz) Type of Clock: 45 Desktop YCrCb 640x480 Higher 20.27 19.79 0.48 950 650 271 104 PAL-BDGHI 30875015 Pixel Only
37
46
38
47
39
50
40
51 Game RGB
41
52
42
Desktop YCrCb 800x600 Higher 19.26 19.34 -0.08 1170 805 323 125 NTSC 56454552 Pixel Only
Desktop YCrCb 800x600 Higher 19.03 18.40 0.63 950 800 131 122 PAL-BDGHI 37999992 Pixel Only
Desktop RGB 800x600 Standard 15.59 15.64 -0.05 1170 770 323 105 NTSC 54000000 Pixel Only
Desktop RGB 1024x768 Higher 18.04 18.11 -0.07 1170 1015 127 150 NTSC 71181793 Pixel Only
320x200, Pix_Double Set Standard 21.86 30.90 -9.04 2000 315 453 65 PAL-BDGHI 31500000 Pixel or Character
Register Address
0x38 0x76 0x78 0x7A 0x7C 0x7E 0x80 0x82 0x84 0x86 0x88 0x8A
Register Value
00 B8 80 92 AC 72 F3 33 E9 27 00 B6
Register Value
20 58 20 B0 C8 AC 2D 2A C5 39 00 92
Register Value
00 80 20 B2 D4 AA 57 31 EC 39 00 B6
Register Value
20 F0 20 AA BE 9E F3 25 CE 38 00 92
Register Value
40 E0 80 94 B0 78 09 42 CA 27 00 D0
Register Value
20 C8 00 E0 FC FA AB 28 C8 4B 00 92
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Appendix C Autoconfiguration Mode Register Values and Details
Flicker-Free Video Encoder with Ultrascale Technology
Table C-8. CX25870/871 Register Values for Autoconfiguration Modes 37-42 (2 of 2) Autoconfiguration Mode #
0x8C 0x8E 0x90 0x92 0x94 0x96 0x98 0x9A 0x9C 0x9E 0xA0 0xA2 0xA4 0xA6 0xA8 0xAA 0xAC 0xAE 0xB0 0xB2 0xB4
NOTE(S):
37
0F 0B 8A 68 E0 36 48 51 E4 B8 0D 24 F0 58 81 48 8C 3D E7 C2 24
38
43 0C 25 7D 58 3B 11 A1 46 17 19 0A E5 74 77 43 85 21 0B 59 18
39
83 03 20 7A 58 3B F6 98 8E E3 10 24 F0 57 7F 48 8C E1 5B DE 1D
40
43 0C 02 69 58 3B EF 5E 00 00 18 0A E5 74 78 43 85 17 5D 74 19
41
C5 1F 3B 41 C8 31 21 80 00 00 0E 24 F0 58 81 48 8C D3 2D 08 24
42
7F 04 F7 96 00 3F DE AD E8 A2 1F 0A E5 74 77 43 85 C2 72 4F 13
1. RGB digital input denotes that the CX25870/871 will be configured to receive the RGB default pixel input mode after an autoconfiguration command, which is 24-bit, RGB-multiplexed (i.e., IN_MODE[3:0] = 0000). If the desired RGB pixel input mode is NOT 24-bit RGB multiplexed, the CX25870/871's IN_MODE[3:0] bits must be programmed to the desired RGB pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 2. YCrCb digital input denotes that the CX25870/871 will be configured to receive YCrCb pixel data after an autoconfiguration command. The CX25870/871's IN_MODE[3:0] bits must be programmed to the desired YCrCb pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 3. CX25870/871 registers not listed in this table (including IN_MODE[3:0]) do not get reprogrammed as a result of an autoconfiguration command. 4. Pixel or Character signifies that this overscan ratio is acceptable for 8-clock per character graphics controllers or pixel-clock controllers. 5. The CX25870/871 will be in master interface immediately after any autoconfiguration mode EXCEPT Mode 28 and Mode 29. 6. Mode 44 would ideally have 858 clocks per line. However, since 858 is not a multiple of 8, then 880 clocks per line was utilized instead. 7. These autoconfiguration values assume a 13.500 MHz crystal resides between the XTALIN and XTALOUT pins. If the 14318_XTAL bit is set, then these autoconfiguration values will automatically change to reflect the presence of a 14.318 MHz crystal.
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Appendix C Autoconfiguration Mode Register Values and Details
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table C-9. CX25870/871 Register Values for Autoconfiguration Modes 43-47 (1 of 2) Autoconfiguration Mode #
Auto-Config Register (index 0xB8) Hexadecimal Value: Purpose of Mode: Type of Digital Input: Active Resolution: Overscan Ratio: Horizontal Overscan Ratio/Percentage (HOC): Vertical Overscan Ratio/Percentage (VOC): Overscan Percentages Delta (HOC - VOC): H_CLKI = HTOTAL VLINES_I = VTOTAL H_BLANKI = Horizontal Blanking Region V_BLANKI = Vertical Blanking Region Type of Video Output: Frequency of CLK (Hz) Type of Clock: 53 Desktop RGB 1024x768 Higher 16.20 16.67 -0.47 1410 1000 337 147 PAL-BDGHI 70499989 Pixel Only
43
54
44
55 Game RGB
45
56
46
57
47
DVD/noninterlaced input RGB 720x480 Very Low (DVD Playback) 1.24 1.23 0.01 880 525 140 36 NTSC 27692310 Pixel or Character
Desktop for Brazil RGB 640x480 Standard 13.79 13.58 0.21 784 600 126 75 PAL-M (Brazil) 28195793 Pixel Only
Desktop for Argentina RGB 640x480 Standard 16.56 16.67 -0.11 944 625 266 90 PAL-Nc (Argentina) 29500008 Pixel Only
320x200, Pixel_Double Set Standard 20.20 21.40 -1.20 1848 275 429 43 NTSC 30461552 Pixel or Character
Register Address
0x38 0x76 0x78 0x7A 0x7C 0x7E 0x80 0x82 0x84 0x86 0x88
Register Value
24 C0 00 DC 08 F0 BF 2F F1 4B 00
Register Value
00 E0 D0 82 92 5C 1B 13 F2 26 00
Register Value
40 90 80 90 A2 72 CD 2B C2 27 00
Register Value
00 00 80 84 A4 6A 7D 22 D4 27 00
Register Value
00 60 80 8A A6 70 C1 2E F2 27 00
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Appendix C Autoconfiguration Mode Register Values and Details
Flicker-Free Video Encoder with Ultrascale Technology
Table C-9. CX25870/871 Register Values for Autoconfiguration Modes 43-47 (2 of 2) Autoconfiguration Mode #
0x8A 0x8C 0x8E 0x90 0x92 0x94 0x96 0x98 0x9A 0x9C 0x9E 0xA0 0xA2 0xA4 0xA6 0xA8 0xAA 0xAC 0xAE 0xB0 0xB2 0xB4
NOTE(S):
43
82 51 0D E8 93 00 3F 33 A3 55 55 1F 24 F0 56 7E 47 8C 9B 29 26 18
44
70 8C 03 0D 24 E0 36 00 50 C5 4E 0C 0A E5 76 79 44 85 D1 45 17 21
45
38 AD 1F 13 2B C8 31 C3 40 D9 89 0D 0A E5 75 78 44 85 33 28 15 1E
46
10 7E 03 58 4B E0 36 92 54 0E 88 0C 2A F0 57 80 48 8C 6E DB 76 20
47
B0 0A 0B 71 5A E0 36 00 50 72 1C 0D 24 F0 57 80 48 8C 1E C0 15 1F
1. RGB digital input denotes that the CX25870/871 will be configured to receive the RGB default pixel input mode after an autoconfiguration command, which is 24-bit, RGB-multiplexed (i.e., IN_MODE[3:0] = 0000). If the desired RGB pixel input mode is NOT 24-bit RGB multiplexed, the CX25870/871's IN_MODE[3:0] bits must be programmed to the desired RGB pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 2. YCrCb digital input denotes that the CX25870/871 will be configured to receive YCrCb pixel data after an autoconfiguration command. The CX25870/871's IN_MODE[3:0] bits must be programmed to the desired YCrCb pixel input mode immediately before initiating a write to the CONFIG[5:0] bits. 3. CX25870/871 registers not listed in this table (including IN_MODE[3:0]) do not get reprogrammed as a result of an autoconfiguration command. 4. Pixel or Character signifies that this overscan ratio is acceptable for 8-clock per character graphics controllers or pixel-clock controllers. 5. The CX25870/871 will be in master interface immediately after any autoconfiguration mode EXCEPT Mode 28 and Mode 29. 6. Mode 44 would ideally have 858 clocks per line. However, since 858 is not a multiple of 8, then 880 clocks per line was utilized instead. 7. These autoconfiguration values assume a 13.500 MHz crystal resides between the XTALIN and XTALOUT pins. If the 14318_XTAL bit is set, then these autoconfiguration values will automatically change to reflect the presence of a 14.318 MHz crystal.
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Appendix C Autoconfiguration Mode Register Values and Details
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Flicker-Free Video Encoder with Ultrascale Technology
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D
Appendix D Closed Caption Pseudo Code
/* Filename: CC_870_Function.C */
//Causes CX870/871 encoder to encode 2 bytes of data on every Odd Field=Field 1 #include stdio.h #include conio.h <#include other necessary header files> char ables CCdatabyte1, CCdatabyte2; // Define global vari-
//Any graphics controller/MPEG2 Decoder is assumed to be the I2C master for this design //Controller/Data Master sends the CX870/871 the digital CC bytes necessary for encoding into the Composite Video signal or Luma signal for S-Video output //H_CLKO[11:0] value should exist in hex format. This register equals bits3-0 //of register 0x86 and bits 7-0 of register 0x76
870_CCEncoding_onField1(int CCdatabyte1, int CCdatabyte2, int H_CLKO) { int CBITS, CC_PIPE1, CC_ADD_HEX, CCR_START_HEX, CCSEL, ReadBit; int ReadBitArray[8] = {0}; //initializes all element of ReadBitArray to 0 float CC_ADD; float CCR_START; CBITS = 17; CC_PIPE1=60; CCSEL = 4; //CCSEL[3:0] = 0100 so CC data is encoded on line 21 //for 525-line systems and line 23 for 625-line systems //Initialization Section Write ECCGATE to 1; //this is bit 3 of register C4 for the CX870/871 //no further closed caption encoding
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Appendix D Closed Caption Pseudo Code
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
will be performed //until CCF1B1 & CCF1B2 registers are again written; //null will be transmitted on appropriate CC line in this case Write ECCF1 to 1; //this is bit 4 of register C4 for the CX870/871 //Enables CC encoding on Field 1 Write ECCF2 to 0; //this is bit 5 of register C4 for the CX870/871 //Disables CC encoding for Field 2 if (625LINE == 0) { //"625LINE" = bit 2 of register 0xA2 // 525-line format=NTSC is being transmitted //by CX870/871. This assumes PAL-M = another //525 line format is not allowed
[equation] CC_ADD = ($pow(2, CBITS+5)/1716)*1716.0/H_CLKO;
//equation to determine CC_ADD register for NTSC
CC_ADD_hex = DEC_TO_HEX_CONVERSION(float CC_ADD); //assumes DEC_TO_HEX_CONVERSION fxn //this should already exist //somewhere in customer's code Write CC_ADD(CC_ADD_hex);
//CC_ADD[11:0] register is //comprised of bits[3:0] of //register 0xD4 and bits[7:0] of //CX870/871 register 0xD2 [equation] CCR_START = H_CLKO*10.003*27/1716 + CC_PIPE1; //eqn to determine CCR_START register for NTSC CCR_START_hex = DEC_TO_HEX_CONVERSION(float CCR_START);
//assumes DEC_TO_HEX_CONVERSION
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Appendix D Closed Caption Pseudo Code
fxn //this should already exist //somewhere in customer's code Write CCR_START(CCR_START_hex); //CCR_START[8:0] register is //comprised of bit[4] of register //0xD4 and bits[7:0] of CX870/871 //register 0xD0 }
else { // 625-line format = PAL is being transmitted by CX870/871 //this assumes PAL-M with its' 525 line format is not allowed
= ($pow(2, CBITS+5)/1716)*1728.0/H_CLKO;
//eqn to determine CC_ADD register for PAL
[equation] CC_ADD
CC_ADD_hex = DEC_TO_HEX_CONVERSION(float CC_ADD); //assumes DEC_TO_HEX_CONVERSION fxn //this should already exist //somewhere in customer's code Write CC_ADD(CC_ADD_hex);
//CC_ADD[11:0] register is //comprised of bits[3:0] of //register 0xD4 and bits[7:0] of //CX870/871 register 0xD2 [equation] CCR_START =
H_CLKO*10.003*27/1728
+ CC_PIPE1;
//eqn to determine CCR_START register for PAL
CCR_START_hex = DEC_TO_HEX_CONVERSION(float CCR_START);
//assumes DEC_TO_HEX_CONVERSION fxn //already exists somewhere in //customer's code
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Appendix D Closed Caption Pseudo Code
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Write CCR_START(CCR_START_hex); //CCR_START[8:0] register is //comprised of bit[4] of register //0xD4 and bits[7:0] of CX870/871 //register 0xD0
} //Previous Initialization Code only needs to be performed once by I2C master //Closed Caption Encoding Operation ReadBitArray[] = CX870ReadbackFxn(ESTATUS = 01); //CCSTAT_O will be ReadBitArray[3] after this function executes Or ReadBit = ReadCCSTAT_O(); //CX870/871 has full readback ability of all bits. //No longer is it necessary to use legacy Bt869 method of reading //back status bits if (ReadBitArray[3] == 0) //alternative IF statement could be `if (ReadBit == 0)' { //Closed Caption bytes for Field 1 = Odd Field have already been //encoded and CCSTAT_O has been cleared
Write CCF1B1(CCdatabyte1); //assumes CCdatabyte1
is in hex format //already. Encode new CC data.
Write CCF1B2(Ccdatabyte2); //assumes CCdatabyte2
is in hex format //already. Encode new CC data. //data is not latched until second of the 2 byte data sequence is written //this prevents writing of partial data sequence //for this reason, data must be written in order of Byte 1 and then Byte 2 //CCSTAT_O will be automatically be set by the CX870/871 until CC bytes for odd //field = Field 1 have been encoded } else
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix D Closed Caption Pseudo Code
//CCSTAT_O = 1 because CC data has already been written for Field 1=ODD field //& has not yet been encoded onto analog video output signal for the odd field //CCSTAT_O will be reset immediately after the clock run-in online 284 for NTSC //and line 335 for PAL return 0; //CCSTAT_0 = 1 so CC bytes were not encoded on this pass //through the 869_CCEncoding_onField1 procedure return 0; } //**************************************************** Bt869ReadbackFxn(int ESTATUS) //Unlike the previous Conexant VGA encoder, the CX870/871 does have //registers than can be directly read-back. As a result this //Bt869ReadbackFxn should only be used IF the software engineer seeks to use //the legacy method of readback found in the Bt868/869. { int ReadMONSTAT_CCArray[8] = {0}; //entire array now holds 0 Write ESTATUS; //ESTATUS[1:0]= {bits 7(MSb) and 6 of register 0xC4} // ESTATUS[1:0]= 01 from function call. // 00 and 10 possible for ESTATUS as well // yielding different readback information Graphics controller issues 0x89 or 0x8B for the CX870/871's device address; //no subaddress required here since the CX870/871 //only has 1 read register to check with the legacy method //This step has the effect of reading a single byte //of data from the CX870/871 //Table 2-2 Readback bit map says that MONSTAT_A,B,C //bits = bits 7-5 //while Bit 4 = CCSTAT_E, bit 3 = CCSTAT_O, // bits 2-0 = FIELD[2:0] // This ensures the least significant bit of the device
write portion of //the transaction is '1' which indicates to the encoder that it must //send a byte of data on the next I2C transaction. Do not write a //subaddress to the CX870/871(this is not necessary since the CX870/871 //only appears to have 1 read register with the legacy method) and then //read the "next" byte after the ACK. Controller_Transmits_I2C_STOP; //I2C Master must issue an I2C STOP to
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Appendix D Closed Caption Pseudo Code
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology //finish the Read transaction. An ACK is //not necessary before closing the //transaction because the CX870/871 just //ignores the ACK anyways
return(ReadMONSTAT_CCArray[]); }
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E
Appendix E HDTV Output Mode
NOTE(S): Warning: Conexant is Pursuing Multiple Patents surrounding this Function
E.1 Introduction
A high definition television system can display images that are better than existing standard definition TV formats such as NTSC, PAL, and SECAM. HDTV pictures are more true-to-life because the resolution of the TV image is much higher, and the colors are more accurate. Many HDTVs are being equipped with a HD Input port that accepts analog Component YPBPR or analog RGB or both. Recognizing this fact, Conexant has included an HDTV Output Mode within the CX25870/871 which generates the analog Component YPBPR or analog RGB outputs necessary for driving an HDTV's HD Input port(s). While in HDTV mode, the device will output either analog RGB or analog YPBPR signals and automatically insert trilevel synchronization pulses (when necessary) and vertical synchronizing broad pulses. The output waveforms and requirements related to the input timing and data on the input side of the CX25870/871 are explained in this section and in the various SMPTE standards governing the HDTV resolutions as listed in Table E-5.
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Appendix E HDTV Output Mode
E.2 Allowable Interfaces for HDTV Output Mode
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
E.2 Allowable Interfaces for HDTV Output Mode
The interface that the CX25870/871 must use in HD Output Mode is either type of video timing slave interface. In this configuration, the HSYNC* and VSYNC* signals must be received as inputs while the BLANK* signal's usage is optional. The encoder cannot transmit the timing signals that initiate the start of a line or the start of a frame in this mode at all. The CX25870/871 can provide a reference clock output--CLKO, or not transmit it, as needed. The EN_OUT bit will control whether or not a CLKO signal is active. The BLANK* signal will not be required for the HDTV Output Mode interface if the graphics controller outputs the digital codes for the analog blanking level. For analog RGB component video outputs, the digital code for blanking is 00 hex for digital R, G, and B. For offset analog RGB component video outputs, the digital code for blanking is 10 hex for the digital R, G, and B pixel inputs. Finally, for analog Component YPBPR video outputs, the digital code for blanking is 10 hex for digital Y and 80 hex for digital Pr and Pb. If the graphics controller does not possess the ability to output specific digital codes, then a BLANK* signal is a necessary part of this interface.
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CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Appendix E HDTV Output Mode
E.2 Allowable Interfaces for HDTV Output Mode
The allowable interfaces for HDTV Output Mode are illustrated in Figures E-1 and E-2.
Figure E-1. CX25870/871's Pseudo-Master interface with a Graphics Controller as the Timing Master
Clock
Clock Delay Graphics Controller R or PR Digital RGB or YPrPb HSYNC* VSYNC* BLANK* (Optional)
100381_030a
CX25870/ CX25871
G or Y B or PB
Figure E-2. CX25870/871's Slave interface with a Graphics Controller as the Timing Master
Clock R or PR Digital RGB Graphics Controller or YPrPb HSYNC* VSYNC* BLANK* Optional)
100381_031
CX25870/ CX25871
G or Y B or PB
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Appendix E HDTV Output Mode
E.3 Interface Bit Functionality in HDTV Output Mode:
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
E.3 Interface Bit Functionality in HDTV Output Mode:
When the CX25870 is transmitting High-Definition Outputs, several interface bits behave differently than their operation while broadcasting standard-definition television. These bits and their technical functionality are summarized in the following list: * The BLANK* pin must be an input regardless of the slave or pseudo-master interface. If the blank function is not enabled with the BLANK* pin, then the BLANK* pin (#38) should be tied high permanently. The EN_BLANKO bit has no effect because the BLANK* signal MUST be an input. The same rule holds for VGA(R/G/B) - DAC Output operation. The EN_DOT bit has no effect. This bit is related to the standard flicker filter. The FLD_MODE[1:0] bit field has no effect. For 1080i or any other HD-related interlaced input, VSYNC*'s leading edge must be received within 5 clock cycles of the middle of the total line length. For 1080i, this means the VSYNC* leading edge must be received on any clock period between the (2200 / 2) 5 clocks = 1095th and 1106th clock pulse. The polarity reversing bits (HSYNCI, VSYNCI, and BLANKI) perform the same operations as they do with standard definition outputs.
*
* *
*
E-4
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix E HDTV Output Mode
E.4 Interface Timing between the HDTV Source Device (Master)
E.4 Interface Timing between the HDTV Source Device (Master) and CX25870/ CX25871(Timing Slave)
While in HDTV Output Mode, the CX25870/871 encoder should receive interface signals from the MPEG2 decoder or display processor. The interface signals that should be shared between the two devices are the HSYNC*, VSYNC*, BLANK*, CLKI, and Pixel Data lines (P[23:0]). The BLANK* signal is optional. This signal is only necessary if the data master cannot transmit the digital codes representing the BLANK levels to the CX25870/871. To reiterate, the codes for the digital blanking levels of the R, G, B inputs are equal to 00 hex. The digital codes for blanking change to 10 hex for the R, G, and B pixel inputs if conversion to offset analog RGB component video outputs is desired. Finally, the values for digital Y must be 10 hex and for Pr and Pb, digital samples have to equal 80 hex for the BLANK period for Component Video Out (YPBPR). CLKO will only be necessary if Pseudo-Master is used as the chosen interface. To switch the CX25870/871 encoder into HDTV Output mode, the serial master must program both the OUT_MODE[1:0] bits to 11(DAC Mode) and set the HDTV_EN bit to 1(bit 7 of the HDTV Register). Immediately after these and all other steps listed in Table E-1 and Table E-2, the encoder will be set up to properly generate a set of HDTV Outputs so long as the synchronization, clock, and data signals are transmitted in accordance with the timing diagrams found at the back of Appendix E by the master device.
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Appendix E HDTV Output Mode
E.4 Interface Timing between the HDTV Source Device (Master) and CX25870/ CX25871(Timing Slave)
CX25870/871
Flicker-Free Video
Table E-1. CX25870 Register Settings for Alternate 24-bit RGB Multiplexed In--HDTV YPBPR Out and HDTV RGB Out ATSC Resolution CX25870 Register Address
0xD6
1080i
0C
720p
0C
480p
0C
Explanation
OUT_MODE [1:0] field set to 11=DAC Mode to turn on HDTV outputs. Video[0-3] is HDTV Output Mode. HDTV_EN bit must be set as well. Video[0] = HD R or PR, Video[1] = HD G or Y, Video[2] = HD B or PB HDTV_EN set. RGB2YPRPB set. RASTER_SEL[1:0] field adjusted for each ATSC resolution. HD_SYNC_EDGE set for 480p resolution only. For RGB out, RGB2YPRPB bit must be 0 so this register will be 83 / 82 / and 85. For EIA770.3 compliance, disable the trilevel sync on both the PR and PB outputs by setting the RPR_SYNC_DIS(bit 5) and BPB_SYNC_DIS(bit 3) bits. SETUP_HOLD_ADJ bit is bit 4. CSC_SEL bit set for hi-frequency ATSC resolutions only. MCOMPY stays the same for 480p/720p/1080i in, Y/PR/PB out. or RGB out. MCOMPU must be changed for 480p and 720p/1080i in, Y/PR/PB out. MCOMPU must be changed to 80hex for 480p/720p/1080i in, RGB out. MCOMPV must be changed for 480p and 720p/1080i in, Y/PR/PB out. MCOMPV must be changed to 80hex for 480p/720p/1080i in, RGB out. State of EN_OUT varies according to interface used with master device. Hex value of 01 for this register corresponds to Pseudo-Master without a BLANK* interface. State of EN_BLANKO & EN_DOT varies according to interface used with master device. Hex value of 80 for this register corresponds to Pseudo-Master without a BLANK* interface. IN_MODE[2:0] = 000 - defines input format as 24-bit RGB multiplexed. Adjust this register as necessary to route Y/PR/PB out from the CX25870's 4 DACs OUT_MUXD[1:0]= 00 =Video[0] = PR = R {Disabled from DACDISD=1} OUT_MUXC[1:0]= 10 =Video[2] = PB = B OUT_MUXB[1:0]= 01 =Video[1] = Y = G OUT_MUXA[1:0]= 00 =Video[0] = PR = R PLL_INT[5:0] = 21 for 720p @ 74.25 MHz *PLL_INT[5:0] = 20 for 720p @ 74.16 MHz PLL_FRACT[15:8] = 00 for 720p @ 74.25 MHz **PLL_FRACT[15:8] = F5 for 720p @ 74.16 MHz PLL_FRACT[7:0] = 00 for 720p @ 74.25 MHz **PLL_FRACT[7:0] = C3 for 720p @ 74.16 MHz SLAVER set. Interface is slave timing (pseudo-master or slave) HSYNC*/VSYNC* sent to CX25870. DACD disabled. PR/Y/PB transmitted from DACA/DACB/DACC Ready encoder for timing reset operation. 75 ms = many factors of safety. Set TIMING_RESET bit. Cleared automatically.
0x2E
C3
C2
C5
0x32 0x3C 0x3E 0x40 0xC4 0xC6
01 80 45 51 01 80
01 80 45 51 01 80
00 80 48 5B 01 80
0xCE
24
24
24
0xA0 0x9E 0x9C 0xBA
21 00 00 28
21* 00** 00** 28
8C 00 00 28
WAIT state = 75 ms. 0x6C
Yes C6
Yes C6
Yes C6
(*) = If graphics controller is character based with 8 pixel clocks/character, PLL_INT should be modified to generate a 74.16000 MHz. CLKO and CLKI frequency. (**) = If graphics controller is character based with 8 pixel clocks/character, PLL_FRACT should be modified to generate a 74.16000 MHz. CLKO and CLKI frequency.
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix E HDTV Output Mode
E.4 Interface Timing between the HDTV Source Device (Master)
Table E-2. CX25870 Register Settings for 24-bit YPrPb Multiplexed In--HDTV YPBPR Out ATSC Resolution
CX25870 Register Address
0xD6
1080i
720p
480p
Explanation
0C
0C
0C
OUT_MODE [1:0] field set to 11=DAC Mode to turn on HDTV Outputs. Video[0-3] is HDTV Output Mode. HDTV_EN bit must be set as well. Video[0] = HD PR, Video[1] = HD Y, Video[2] = HD PB HDTV_EN set. RGB2YPRPB off. RASTER_SEL[1:0] field adjusted for each ATSC resolution. HD_SYNC_EDGE set for 480p resolution only. For EIA770.3 compliance, the trilevel sync has been disabled on both the PR and PB outputs by setting the RPR_SYNC_DIS(bit 5) and BPB_SYNC_DIS(bit 3) bits. DRVS[1:0] = 00 for 3.3V interfacing. Should be adjusted to nonzero value for low voltage interface. IN_MODE[3] = 1 = input format is Alternate 24bit YPRPB multiplexed SETUP_HOLD_ADJ bit is bit 4. CSC_SEL bit set for hi-frequency ATSC resolutions only. MCOMPY stays the same for 480p/720p/1080i in, Y/PR/PB out. MCOMPU stays the same for 480p/720p/1080i in, Y/PR/PB out. MCOMPV stays the same for 480p/720p/1080i in, Y/PR/PB out. State of EN_OUT varies according to interface used with master device. Hex value of 01 for this register corresponds to Pseudo-Master without a BLANK* interface. State of EN_BLANKO & EN_DOT varies according to interface used with master device. Hex value of 80 for this register corresponds to Pseudo-Master without a BLANK* interface. IN_MODE[2:0] = [1]100 - input format is Alternate 24bit YPRPB multiplexed Adjust this register as necessary to route Y PR PB out from the CX25870's 4 DACs OUT_MUXD[1:0]= 00 =Video[0] = PR {Disabled from DACDISD=1} OUT_MUXC[1:0]= 10 =Video[2] = PB OUT_MUXB[1:0]= 01 =Video[1] = Y OUT_MUXA[1:0]= 00 =Video[0] = PR PLL_INT[5:0] = 21 for 720p @ 74.25 MHz *PLL_INT[5:0] = 20 for 720p @ 74.16 MHz PLL_FRACT[15:8] = 00 for 720p @ 74.25 MHz **PLL_FRACT[15:8] = F5 for 720p @ 74.16 MHz PLL_FRACT[7:0] = 00 for 720p @ 74.25 MHz **PLL_FRACT[7:0] = C3 for 720p @ 74.16 MHz SLAVER set. Interface is slave timing (pseudo-master or slave) HSYNC* & VSYNC* sent to CX25870. DACD disabled. PR transmitted from DACA, Y transmitted from DACB, and PB transmitted from DACC Ready encoder for timing reset operation. 75 ms = many factors of safety. Set TIMING_RESET bit. Cleared automatically.
0x2E
AB***
AA***
AD***
0x32
09
09
08
0x3C 0x3E 0x40 0xC4 0xC6
80 80 80 01 84
80 80 80 01 84
80 80 80 01 84
0xCE
24
24
24
0xA0 0x9E 0x9C 0xBA
21 00 00 28
21* 00** 00** 28
8C 00 00 28
WAIT state = 75 ms 0x6C
Yes C6
Yes C6
Yes C6
NOTE(S): (*) = If graphics controller is character based with 8 pixel clocks/character, PLL_INT should be modified to generate a 74.16000 MHz CLKO and CLKI frequency. (**) = If graphics controller is character based with 8 pixel clocks/character, PLL_FRACT should be modified to generate a 74.16000 MHz CLKO and CLKI frequency. (***) = Conversion from YPrpb digital input to HDTV RGB Out not possible with CX25870/871.
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Appendix E HDTV Output Mode
E.4 Interface Timing between the HDTV Source Device (Master) and CX25870/ CX25871(Timing Slave)
CX25870/871
Flicker-Free Video
In the default format, the HSYNC* signal is active low and must always be received as an input in HDTV Output Mode. Its function is to allow the graphics controller to tell the encoder when the start of a line occurs. Check the timing diagrams that appear later in this section for proper HSYNC* timing. In the default format, the VSYNC* signal is active low and must always be received as an input in HDTV Output Mode. Its function is to allow the graphics controller to tell the encoder when the start of a frame occurs. Check the timing diagrams that appear later in this section for proper VSYNC* timing. By default, the clock output signal will be transmitted via the CLKO port. Therefore, the CX25870/871 will be in Pseudo-Master interface. To switch into Slave interface, the user must reset the EN_OUT bit to turn off CLKO. Table E-2 summarizes the default Pseudo-Master HDTV interface.
Table E-3. Default State of CX25870/871 Immediately After Switch into HDTV Output Mode Input Signals CLKO BLANK*
Optional
State of the CX25870/871 VSYNC*
H Active
HSYNC*
H
State of Encoder in HDTV Output Mode
Digital RGB--Analog HD RGB or Digital YPRPB--Analog HD YPBPR DAC Conversion Start of a New Line Start of a New Frame
Optional Optional
L L
H L
Active Active
The timing diagrams found at the end of this Appendix (Figures E-5 through E-9) must be replicated with actual timing by the MPEG2 Decoder or Display Processor for the encoder to provide correct HDTV analog RGB or analog YPBPR component video outputs.
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix E HDTV Output Mode
E.5 Automatic Trilevel Sync Generation
E.5 Automatic Trilevel Sync Generation
The CX25870/871 will automatically generate an analog synchronization pulse with three distinct voltage levels for every leading edge it receives at its HSYNC* input (so long as RASTER_SEL[1:0] = 10 or 11). This trilevel pulse will be comprised of a -300 mV LOWSYNC level, a +300 mV HIGHSYNC level, and a 0 mV BLANKING level offset by +350 mVDC because the CX25870/871 cannot output negative voltages. Figure 3, "Analog and Digital Timing Relationships", of the SMPTE-274M specification, shows a very detailed diagram of the trilevel sync and start of a line in 1080i mode. Figure 11 of this same SMPTE standard illustrates the horizontal timing and trilevel sync in more detail. For those formats which require trilevel syncs, such as 1080i and 720p, the timing for certain portions of the synchronization pulses differ slightly. For instance, the amount of time each pulse is at a voltage level of -300 mV (LOWSYNC) is not the same from one resolution (ATSC format) to another. For 1080i, the time for the LOWSYNC level each line is 44T(44 clock periods = 44*(1/74.25 MHz)= 592.5 ns For 720p, the same interval is 40T periods long which equates to 40 * (1/74.25 MHz)= 538.7 ns. In 480p resolution, in accordance with the SMPTE-293M specification, the CX25870/871 outputs only bilevel analog synchronization pulses. As Figure 3 "Analog and Digital Timing Relationships" of the SMPTE-274M and -296M standards show, the period of time for the HIGHSYNC also varies when moving from 1080i mode to 720p mode. In this first case, the HIGHSYNC output level will be active for 44 clock periods. For 1080i, 44 clock periods * (1/74.25 MHz) = 592.6 ns. In 720p resolution, the HIGHSYNC output signal will be active for 40 clock periods per output line. For 720p, 40 clock periods * (1/74.25 MHz)= 538.7ns, so the HIGHSYNC signal will only be active for 538.7 ns per output line. Due to these discrepancies, the data master will need to program the CX25870/871's RASTER_SEL[1:0] bits properly so the encoder knows exactly which ATSC format it is going to encode. The encoder will then take care of outputting the proper analog voltage levels (see Figures E-5 through E-9) for the appropriate amounts of time depending on the resolution.
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Appendix E HDTV Output Mode
E.5 Automatic Trilevel Sync Generation
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
The table below summarizes the different permutations of the RASTER_SEL[1:0] bits and the resolutions/modes supported with each option.
Table E-4. CX25870/CX25871 RASTER_SEL[1:0] Bit Functionality RASTER_SEL [1]
1 1 0 0
NOTE(S):
(1)
RASTER_SEL [0]
1 0 1 0
HDTV/ATSC Mode
1080i = SMPTE 274M (1) 720p = SMPTE 296M(2) 480p = SMPTE 293M Trilevel sync periods dictated by HSYNC*&VSYNC* input levels
LOWSYNC period (ns)
44 clock periods = 592.6 ns 40 clock periods = 538.7ns 63 clock periods = 2.36 s. LOWSYNC period = width of VSYNC* input
HIGHSYNC period (ns)
44 clock periods = 592.6 ns 40 clock periods = 538.7ns No HIGHSYNC period HIGHSYNC period = width of HSYNC* input
The CX25870/871 can also be programmed for EIA-770.3 1080i format compliance. To do so, set RASTER_SEL[1:0] = 11 and set the BPB_SYNC_DIS and RPR_SYNC_DIS bits to 1 to disable the trilevel sync on the PB and PR signals. (2) The CX25870/871 can also be programmed for EIA-770.3 720p format compliance. To do so, set RASTER_SEL[1:0] = 10 and set the BPB_SYNC_DIS and RPR_SYNC_DIS bits to 1 to disable the trilevel sync on the PB and PR signals. (3) To obtain any of these SMPTE specifications, visit Global Engineering Documents at: http://global.ihs.com/
The inserted syncs will adhere to Figure 3 and the analog and digital timing relationships found in the various SMPTE specifications. All lines of the First and Second Fields of an Interlaced System will contain the trilevel syncs. This includes lines #1-5 and #564-567 of the 1080i format. Line 563 is an extraordinary case and the reader should defer to the SMPTE 274M specification for more details on this topic. An illustration of the typical trilevel sync output from the CX25870/871is shown on the next page. Note that the CX25870/871 cannot transmit negative voltages. As a result, the video output is offset by +350mV to accommodate the negative sync levels listed in the governing specifications.
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Appendix E HDTV Output Mode
E.5 Automatic Trilevel Sync Generation
Figure E-3. 1080i and 720p Trilevel Sync provided by CX25870/871
Start of the Analog 40T Line (for 296M) 40*(1/74.25 MHz) = 538.7 ns 44T (for 274M) 44*(1/74.25 MHz) = 592.5 ns 650 mV
350 mV
50 mV 44T 44T 44*(1/74.25 MHz) = (for 274M) 44*(1/74.25 MHz) = 592.5 ns 592.5 ns 70T (for 296M) 70*(1/74.25 MHz) = 942.8 ns 40T (for 296M) 40*(1/74.25 MHz) = 538.7 ns
NOTE(S): 1. Trilevel Sync applies to Y PB, PR output signals as well as HD RGB output signals. 2. 720p Trilevel Sync timing differences are listed in RED.
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Appendix E HDTV Output Mode
E.6 Allowable Resolutions
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
E.6 Allowable Resolutions
Table E-5 summarizes the most popular HD resolutions or ATSC video formats supported by the CX25870/871.
Table E-5. CX25870/CX25871 HDTV Supported Formats Active Format (H x V )
1920x1080 = 1080i (contains trilevel syncs) 1280x720 = 720p (contains trilevel syncs) 720x480 = 480p (does not contain trilevel syncs)
Governing Standards
SMPTE-274M & EIA-770.3 SMPTE-296M & EIA-770.3 SMPTE-293M
Input Data Format (can be muxed or nonmuxed)
15, 16, or 24 bit RGB or 16 or 24 bit Digital YPBPR 15, 16, or 24 bit RGB or 16 or 24 bit Digital YPBPR 15, 16, or 24 bit RGB or 16 or 24 bit Digital YPBPR
OutputAspect Ratio
16 : 9
Frame Rate
30 Hz. interlaced 60 Hz. noninterlaced 60 Hz. noninterlaced
16 : 9
16 : 9
Conceivably, any HD format with a clock less than or equal to 80 MHz can be displayed with the RASTER_SEL[1:0] = 00 option. This flexibility allows the CX25870/871 to receive resolutions not yet standardized. All HDTV Output Mode resolutions will generate the new WSS wide screen format that provides an aspect ratio of 16:9 yielding a movie-theatre like viewing experience. When the encoder is in HDTV Output Mode, the internal FIFO and flicker filter blocks are bypassed. Therefore, the Y/PB/PR and R/G/B video outputs do not have any flickering filtering nor any overscan compensation applied to them. For 480p, 720p, and other progressive input formats, the lack of flicker filtering causes no degradation whatsoever in the video output quality as compared to the digital input. For 1080i and other interlaced input formats, the lack of flicker filtering sets off the appearance of minor flickering in screen regions with small vertical dimensions. The lack of overscan compensation in HDTV Output Mode results in the outer horizontal and vertical edges of the active image to appear behind the bezel of the television. This annoyance can be overcome by the insertion of a solid colored border around the active image itself by the data master in the digital domain.
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Appendix E HDTV Output Mode
E.7 720p Support with Character Clock Based Data Masters
E.7 720p Support with Character Clock Based Data Masters
Character clock based graphics controllers with 8 pixel clocks per character will experience difficulty supporting the 720p ATSC resolution. The reason for this is because the total line length (i.e., Samples per Total Line = S/TL) of 1650 pixels for 720P is not evenly divisible by 8. Thus, each line is comprised of an amount of characters that contains a non-zero fraction (206 + 1/4 of a character or 206.25 total characters). To get around this shortcoming, the graphics controller must set its total line length to 1648 (HTOTAL) pixels and change the pixel clock frequency to 74.1600 MHz. instead of the values of 1650 pixels and 74.2500 MHz. respectively as specified in the SMPTE-296M standard that governs the 720p resolution. All of the analog timing will then fall within the guidelines listed in the SMPTE-296M specification and the CX25870 will generate the desired analog representation of the 720p ATSC resolution. Internal analysis of different portions of the 720p R/G/B and Y/PB/PR waveforms has revealed that this approach is valid. All of the analog timing falls within the tolerances of the SMPTE-296M standard including the length of the broad pulse. In terms of clock periods, using the 74.1600 MHz. clock yields a broad pulse length in time of 20.766 s in duration. Using a 74.2500 MHz. clock yields a broad pulse of 20.741 s in duration. This tiny deviation will not cause a problem for any High Definition television set. To change the pixel clock frequency the encoder transmits and expects in return, the CX25870's PLL_INT and PLL_FRACT registers must be modified. For 720p support with Character Clock Based Data Masters, change the PLL_INT[5:0] bit field from 21 hex (for 74.25 MHz.) to 20hex for 74.1600 MHz. operation. Furthermore, reduce the 2-byte wide PLL_FRACT[15:0] from 0000 hex (for 74.25 MHz.) to F5C3 hex for 74.1600 MHz. operation. This reduction in the PLL_INT and PLL_FRACT registers will ensure the encoder transmits the modified 720p clock of 74.1600 MHz. to the data master through CLKO and expects to receive data at this frequency coming back (via CLKI). This step must be done to render 720p via Character Clock Based Data Masters with the CX25870. Programming the data master's HTOTAL register to 1648 is vital as well. Modifying the CX25870's H_CLKI register to 1648 decimal is optional because this register will have no effect while the encoder is outputting HDTV . In summary, for data masters which are character clock based with 8 and 9 pixel clocks per character and wish to support the 720p resolution, slow down the pixel input clock frequency (CLKI) by 90 kHz. to 74.1600 MHz and compensate by reducing HTOTAL by 2 pixels per line to 1648 pixels.
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Appendix E HDTV Output Mode
E.8 Automatic Insertion of Broad Pulses
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
E.8 Automatic Insertion of Broad Pulses
In HD televisions, a frame shall begin with five vertical sync lines each containing a broad pulse. Broad pulses are the HD equivalent to the vertical synchronizing Serration and Equalization pulses used with present-day analog TVs. In response to the correct timing provided through the VSYNC* input which triggers the start of a new frame, the CX25870/871 will automatically insert broad pulses and trilevel syncs on the first 5 lines of the First Field(#1-#5) and the first 5 lines in the Second Field (563-568 for 1080i format). These broad pulses will adhere to the timing and voltage amplitudes found in various SMPTE specifications. Figure E-6 illustrates the proper interface timing between the HDTV Source Device (master) and CX25870/ CX25871(timing slave) during lines that include a BROAD PULSE in 1080i format. Figure E-8 shows the relationship between the digital input signals and HDTV output for lines that include a broad pulse in 720p format.
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Flicker-Free Video Encoder with Ultrascale Technology
Appendix E HDTV Output Mode
E.9 HDTV Output Mode Register and Bit Definitions
E.9 HDTV Output Mode Register and Bit Definitions
Table E-6. Register Bitmap for HDTV-Specific Registers 8-Bit Address
2E 32
NOTE(S):
D7
HDTV_EN* AUTO_CHK
D6
RGB2YPRPB*
D5
RPR_SYNC _DIS*
D4
GY_SYNC_ DIS* SETUP_ HOLD_ADJ
D3
BPB_SYNC_ DIS* IN_MODE[3]
D2
HD_SYNC_ EDGE* DATDLY_RE
D1
D0
RASTER_SEL[1:0]* OFFSET_RG B* CSC_ SEL*
DRVS[1:0]
* = HDTV-specific bits
Table E-7. CX25870/871 Registers 0x2E & 0x32-HDTV Output Mode Bit Descriptions (1 of 2) Bit/Register Names
HDTV_EN
Bit/Register Definition
Enable HDTV Output Mode. OUT_MODE[1:0] register bits must be set to 11(VGA Mode). 0 = Enables VGA mode. DACs will output analog R, G, B with standard bilevel(-40 IRE) analog syncs. (DEFAULT) 1 = Enables HDTV Output mode. DACs will output HDTV compatible R/G/B or component video (Y/PR/PB) outputs. Trilevel syncs and vertical synchronizing/broad pulses will be inserted automatically if RASTER_SEL[1:0] = nonzero. Note: EN_SCART bit must be 0 for HDTV Output Mode to be functional. HDTV output switching bit. This bit is only effective when HDTV_EN = 1 and IN_MODE[3:0] = an RGB Input format. 0 = Digital RGB Input to Analog HDTV RGB Output (DEFAULT) 1 = Digital RGB Input to Analog HDTV YPRPB Output 0 = Enables trilevel sync on Red or PR output. (DEFAULT) 1 = Disables trilevel sync on Red or PR output. This bit will have to be set manually for EIA-770.3 compliance. 0 = Enables trilevel sync on Green or Y output. (DEFAULT) 1 = Disables trilevel sync on Green or Y output 0 = Enables trilevel sync on Blue or PB output. (DEFAULT) 1 = Disables trilevel sync on Blue or PB output. This bit will have to be set manually for EIA-770.3 compliance. This bit is only effective when HDTV_EN = 1 and RASTER_SEL is nonzero. 0 = Trilevel sync edges transition time is equal to 4 input clocks. (DEFAULT) 1 = Trilevel sync edges transition time is equal to 2 input clocks. This bit is only effective when HDTV_EN = 1. 00 = Device does not generate trilevel sync automatically in HDTV output mode. Trilevel sync periods dictated by active HSYNC* input signal (as HIGHSYNC) and active VSYNC* input signal (as LOWSYNC). (DEFAULT) 01 = Bilevel sync generation for 480P format 10 = Trilevel sync generation for 720P format 11 = Trilevel sync generation for 1080i format
RGB2YPRPB
RPR_SYNC_DIS
GY_SYNC_DIS
BPB_SYNC_DIS
HD_SYNC_EDGE
RASTER_SEL[1:0]
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Appendix E HDTV Output Mode
E.9 HDTV Output Mode Register and Bit Definitions
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table E-7. CX25870/871 Registers 0x2E & 0x32-HDTV Output Mode Bit Descriptions (2 of 2)
OFFSET_RGB 0 = Standard RGB graphic digital input. Range is 0-255 decimal (DEFAULT) 1 = HDTV OFFSET RGB graphic digital input. Range is 16-235 decimal. 0 = Standard color space conversion for RGB to Y (R-Y) (B-Y) based on Y = 0.299R + 0.587G + 0.114B (DEFAULT) 1 = HDTV color space conversion for RGB to Y (R-Y) (B-Y) based on Y = 0.2126R + 0.7152G + 0.0722B
CSC_SEL
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Appendix E HDTV Output Mode
Flicker-Free Video Encoder with Ultrascale Technology E.10 Color Space Conversion Functionality to Support Analog RGB
E.10 Color Space Conversion Functionality to Support Analog RGB or YPBPR Component Video Outputs
The CX25870/871 has the ability to receive a digital RGB stream prevalent in graphics controllers or chipsets with integrated graphics with a width of 15/16/or 24-bits per pixel and transform it to a set of HDTV-compatible analog YPBPR component video outputs. The option of not converting the digital RGB stream to analog YPBPR is available as well. In this case, the CX25870/871 would output a set of HDTV-compatible analog RGB component video outputs based on the same 15/16/or 24-bits per pixel RGB digital input. The CX25870/871 can support the conversion from the HDTV color-difference digital YPBPR color space directly to analog YPBPR component video outputs seamlessly. No color space conversion nor register reprogramming is necessary for this case. However, the HDTV color-difference digital YPBPR color space is slightly different from the standard digital 4:2:2 YCrCb (i.e., CCIR601) stream found within consumer applications such as set-top boxes. As a result, the CX25870/871 must be reprogrammed to new register values not found in Table E-1 to accommodate for the differences in the two formats. For this complete register set, contact your local Conexant Field Applications Engineer. Once obtained, program up the CX25870 as specified and it will provide analog YPBPR video outputs based on standard 4:2:2 YCrCb MPEG2 input data. The resulting outputs will be of high quality and viewable on SMPTE274M and SMPTE 296M standard HDTVs. For design simplicity, Conexant recommends the data master just send digital YPRPB for consumer applications instead of YCrCb. For reference these matrix equations for conversion into digital Pb and digital Pr are listed below: Pb = {0.5 / (1 - 0.0722)} (B' - Y') Where (B' - Y') = Cb Pr = {0.5 / (1 - 0.2126)} (R' - Y') Where (R' - Y') = Cr
NOTE(S):
1. The CX25870/871's MCOMPU register must contain a value of 45 hex prior to performing a color space conversion from digital RGB to analog YPBPR. The CX25870/871's MCOMPV register must contain a value of 51 hex prior to performing a color space conversion from digital RGB to analog YPBPR. 2. Digital Pb and Digital Pr are expressed as P'B and P'R in the SMPTE specifications.
Finally, the CX25870/871 cannot provide analog RGB video outputs from either color-difference digital YPrPb or 4:2:2 YCrCb MPEG2 input data. The encoder will not perform this color space conversion whatsoever. For analog RGB component HD out, a digital RGB input stream must be sent by the data master.
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Appendix E HDTV Output Mode
E.11 Recommended Output Filters for HDTV & SDTV
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
E.11 Recommended Output Filters for HDTV & SDTV
According to the SMPTE274M standard that governs the 1080i ATSC resolution, "the Y signal for Component HD video output shall have a bandwidth nominally of 30 MHz. In addition, the PR and PB signals shall have the same bandwidth as that of the associated Y signal at the analog originating equipment." Other filter criteria found in the various SMPTE standards include the amplitude limit for ripple tolerance in the passband of +/- 0.5 dB relative to insertion loss at 100 kHz. For Group-Delay, SMPTE states that the "group delay in the filters (should be) sufficiently tight to produce good performance while allowing the practical implementation of the filters themselves" (from SMPTE 274M and SMPTE293M(720p) standards). As result of these criteria, during High Definition Output Mode, each CX25870 DAC output requires a low pass filter with a passband from DC to 30 MHz. while adhering to the aforementioned group delay and passband ripple tolerances. Unfortunately, the filtering requirements for standard definition television are quite different in several areas than filtering for HDTV. The most important difference is that standard definition standards such as NTSC, PAL, and SECAM require a much lower 8 MHz. passband starting at DC than HDTV. This bandwidth difference coupled with the differing voltage amplitudes of the signals themselves forced Conexant to design a new low pass filter with a wider passband to accommodate the HD outputs. After extensive testing and cost/benefit trade-offs, the company recommends that any customer using the encoder for both its standard definition and high definition capabilities design-in the low pass filter found in Figure E-4. This filter has been shown to exhibit many of the desired roll off, ripple, and passband characteristics defined in the aforementioned SMPTE standards.
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Appendix E HDTV Output Mode
E.11 Recommended Output Filters for HDTV & SDTV
Figure E-4. Recommended Low Pass Filter Configuration for each CX25870 DAC for Generation of High Definition and NTSC/PAL/SECAM TV Outputs
HD Filter D9 BAT54S SOT-23 5443R10-004 VAA 3.3 V
C8 33 pF 0805 5%
DAC A
DOUT R11 75.0 0805 1% L1 0.27 H 1210 C9 62 pF 5% 0805 5% 3
2
CVBS = Composite #1 or HD PB
1 3
C10 75 pF 0805 5%
2
1
HD Filter D7 BAT54S SOT-23 5443R10-004 VAA 3.3 V
C8 33 pF 0805 5%
CX25870/871
DAC B
BOUT R2 75.0 0805 1% L1 0.27 H 1210 C9 62 pF 5% 0805 5% 3
2
Y = Luma or HD Y
1 3
C10 75 pF 0805 5%
2
1
HD Filter D8 BAT54S SOT-23 5443R10-004 VAA 3.3 V
C8 33 pF 0805 5%
DAC C
COUT R7 75.0 0805 1% L1 0.27 H 1210 C9 62 pF 5% 0805 5% 3
2
C = Chroma or HD PR
1 3
C10 75 pF 0805 5%
2
1
SD Filter D9 BAT54S SOT-23 5443R10-004 VAA 3.3 V
22 pF 0805 5%
DAC D
2 R11 75.0 0805 1% L1 1.8 H 1210 C21 270 pF 5% 0805 5%
CVBS = Composite #2
3
C22 330 pF 0805 5%
NOTE(S): 1. HD Filter imparts a passband of DC to 30 MHz. 2. SD Filter imparts a passband of DC to 8 MHz.
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2
1
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Conexant
1
3
E-19
Appendix E HDTV Output Mode
E.12 Timing Diagrams for HDTV Output Mode
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
E.12 Timing Diagrams for HDTV Output Mode
Review the next five pages (Figures E-4 through E-8) for illustrations of the relationship between the digital inputs received by the CX25870/871 and the HDTV Output signals transmitted by the encoder while in HDTV Output Mode.
E-20
Conexant
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Flicker-Free Video Encoder with Ultrascale Technology
Figure E-5. Proper Interface Timing between the HDTV Source Device (Master) and CX25870/871 (Timing Slave): Active Line in 1080i and 720p ATSC Format (RASTER SEL[1:0] = 11 or 10) for R, G, B, and Y Analog Outputs
100381B
Automatically Generated by CX25870
40T (for 720p) 40*(1/74.25 MHz) = 538.7 ns
CX25870/871
1050 mV
BLANK Period (Generated by Controller) Low Sync Period Hi-Sync Period Sync BLANK Period 44T (for 1080i) 44*(1/74.25 MHz) = 592.5 ns RGB Conversion Period (Digital Data Sent by Controller
70T (for 720p) 40T 70*(1/74.25 MHz) = (for 720p) 942.8 ns 40*(1/74.25 MHz) = 538.7 ns 44T (for 1080i) 44T 44*(1/74.25 MHz) = 44*(1/74.25 MHz) = 592.5 ns 592.5 ns
650 mV
....
13.468 ns.
350 mV
R, G, B, and Y (Analog Outputs) 50 mV CLKI
Conexant
.....
RGB1 RGB2 RGB3 RGB4
....
RGB5 RGB6 RGB7 RGB8 RGB9
Not to Scale
11 CLK Pipeline Delay 11 CLK Pipeline Delay 132 CLKs
[P23-P0] HSYNC* (Input to CX25870) 1 VSYNC* (Input to CX25870)
{
BLANK* has no effect when either SYNC* is active or in the tri-level sync period
11 CLK Pipeline Delay
Min. 4 CLKs
BLANK* (Input to CX25870)
11 CLKs Pipeline Delay
*Assumes 24-Bit Non-MUX RGB Digital Input
Appendix E HDTV Output Mode
E.12 Timing Diagrams for HDTV Output Mode
100381_067
E-21
Figure E-6. Proper Interface Timing between the HDTV Source Device (Master) and CX25870/871 (Timing Slave): Active Line in 1080i and 720p ATSC Format (RASTER SEL[1:0] = 11 or 10) for PB and PR Analog Outputs
E-22
Automatically Generated by CX25870
40T (for 720p) 40*(1/74.25 MHz) = 538.7 ns Low Sync Period 44T (for 1080i) 44*(1/74.25 MHz) = 592.5 ns RGB Conversion Period (Digital Data Sent by Controller Hi-Sync Period Sync BLANK Period
BLANK Period (Generated by Controller)
Appendix E HDTV Output Mode
700 mV 650 mV
E.12 Timing Diagrams for HDTV Output Mode
70T (for 720p) 70*(1/74.25 MHz) = 942.8 ns 40T (for 720p) 40*(1/74.25 MHz) = 538.7 ns
44T (for 1080i) 44*(1/74.25 MHz) = 592.5 ns 44T 44*(1/74.25 MHz) = 592.5 ns
350 mV
....
132 CLKs 13.468 ns.
PB and PR (Analog Outputs)
Conexant
50 mV 0 mV
.....
RGB1 RGB2 RGB3
....
RGB4 RGB5 RGB6 RGB7 RGB8 RGB9
CLKI [P23-P0] HSYNC* (Input to CX25870)
Not to Scale
11 CLK Pipeline Delay 11 CLK Pipeline Delay 132 CLKs
{
BLANK* has no effect when either SYNC* is active or in the tri-level sync period
11 CLK Pipeline Delay
Min. 4 CLKs
1 VSYNC* (Input to CX25870)
BLANK* (Input to CX25870)
11 CLKs Pipeline Delay
Flicker-Free Video Encoder with Ultrascale Technology
CX25870/871
*Assumes 24-Bit Non-MUX RGB Digital Input with Color Space Conversion Done Internally
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Flicker-Free Video Encoder with Ultrascale Technology
Figure E-7. Proper Interface Timing between the HDTV Source Device (Master) and CX25870/871 (Timing Slave): Broad Pulse Line in 1080i ATSC Format (RASTER SEL[1:0] = 11)--Odd Field
100381B
Automatically Generated by CX25870
CX25870/871
Time scale compressed.
Low Sync Period Hi-Sync Period BLANK Period
BLANK Period (Generated by Controller)
Broad Pulse Period (Generated by CX25870 Encoder)
44T (for 1080i) 44*(1/74.25 MHz) = 592.5 ns
700 mV
650 mV
44T 44T (for 1080i) 44*(1/74.25 MHz) = 44*(1/74.25 MHz) = 592.5 ns 592.5 ns
....
350 mV
R, G, B, and Y, PBPR 50 mV [P23-P0] HSYNC* (Input to CX25870)
11 CLK Pipeline Delay
Conexant
11 CLK Pipeline Delay
(Analog Outputs)
Min. 4 CLKs
Min. 4 CLKs
1 VSYNC* (Input to CX25870)
BLANK* (Input to CX25870)
BLANK* has no effect when either SYNC* is active or in the tri-level sync period
11 CLK Pipeline Delay
11 CLK Pipeline Delay
Appendix E HDTV Output Mode
E.12 Timing Diagrams for HDTV Output Mode
NOTE(S): a. CX25870/871 automatically generates a BROAD PULSE levels and timing. If a BLANK* signal is not used, adhere to notes b. and c. b. R, G, B, and Y digital samples have to equal 00 hex = 0 decimal for the BLANK Period. c. Pr and Pb digital samples have to equal 80 hex = 128 decimal for the BLANK Period.
100381_069
E-23
Figure E-8. Proper Interface Timing between the HDTV Source Device (Master) and CX25870/871 (Timing Slave): Two Successive Active Fields in 1080i ATSC Format (RASTER SEL[1:0] = 11)
E-24
Automatically Generated by CX25870
40T (for 720p) 40*(1/74.25 MHz) = 538.7 ns.
Time scale compressed.
BLANK Period Sync and Blank Period Active Period for ODD FIELD Active Period for EVEN FIELD Sync and Blank Period
BLANK Period (Generated by Controller) Low Sync Period 44T (for 1080i) 44*(1/74.25 MHz) = 592.5 ns. Hi-Sync Period
Appendix E HDTV Output Mode
40T 70T (for 720p) (for 720p) 40*(1/74.25 MHz) = 70*(1/74.25 MHz) = 538.7 ns. 942.8 ns.
650 mV
44T 44T (for 1080i) 44*(1/74.25 MHz) = 44*(1/74.25 MHz) = 592.5 ns. 592.5 ns.
E.12 Timing Diagrams for HDTV Output Mode
....
350 mV
R, G, B, and Y, PBPR
Line
(Analog Outputs)
....
50 mV
Conexant
Min. 4 CLKs 11 CLK Pipeline Delay 11 CLK Pipeline Delay 562 1/2 Lines
HSYNC* (Input to CX25870)
VSYNC* pulse must be received within +/- 5 clock periods of middle of the last line of the ODD Field. For 1080i, this VSYNC* leading edge must occur between the 1095th and 1105th clock on the 563rd line.
ODD FIELD Begins EVEN FIELD Begins 11 CLK Pipeline Delay
1 VSYNC* (Input to CX25870)
BLANK* (Input to CX25870)
BLANK* has no effect when either SYNC* is active or in the tri-level sync period
Flicker-Free Video Encoder with Ultrascale Technology
CX25870/871
NOTE(S): a. CX25870/871 automaticall generates a BROAD PULSE levels and timing. If a BLANK* signal is not used, adhere to notes b. and c. b. R, G, B, and Y digital samples have to equal 00 hex = 0 decimal for the BLANK Period. c. Pr and Pb digital samples have to equal 80 hex = 128 decimal for the BLANK Period.
100381_070
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Flicker-Free Video Encoder with Ultrascale Technology
Figure E-9. Proper Interface Timing between the HDTV Source Device (Master) and CX25870/871 (Timing Slave): Broad Pulse Line in 720p ATSC Format (RASTER SEL[1:0] = 10)
100381B
Automatically Generated by CX25870
40T (for 720p) 40*(1/74.25 MHz) = 538.7 ns Hi-Sync Period BLANK Period
CX25870/871
Low Sync Period
BLANK Period (Generated by Controller)
Broad Pulse Period
700 mV
(Generated by CX25870 Encoder)
40T 70T (for 720p) (for 720p) 40*(1/74.25 MHz) = 70*(1/74.25 MHz) = 538.7 ns 942.8 ns 44T
650 mV
70T
....
350 mV
R, G, B, and Y, PBPR 50 mV CLKI
(Analog Outputs)
Conexant
BLANK* has no effect when either SYNC* is active or in the tri-level sync period
[P23-P0] HSYNC* (Input to CX25870)
Min. 4 CLKs
11 CLK Pipeline Delay
Min. 4 CLKs
11 CLK Pipeline Delay
1 VSYNC* (Input to CX25870)
Appendix E HDTV Output Mode
E.12 Timing Diagrams for HDTV Output Mode
NOTE(S): a. CX25870/871 automatically generates a BROAD PULSE level and timing. If a BLANK* signal is not used, adhere to notes b. and c. b. R, G, B, and Y digital samples have to equal 00 hex = 0 decimal for the BLANK Period. c. Pr and Pb digital samples have to equal 80 hex = 128 decimal for the BLANK Period.
100381_071a
E-25
Appendix E HDTV Output Mode
E.12 Timing Diagrams for HDTV Output Mode
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
E-26
Conexant
100381B
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