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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by: DSP56167/D, Rev. 1
DSP56167
Advance Information
16-BIT DIGITAL SIGNAL PROCESSOR
The general-purpose, programmable DSP56167 is an enhanced version of the DSP56166 with added features. Designed primarily for speech coding and digital communications, the DSP56167 has a built-in codec and Phase Lock Loop (PLL). This MPU-style DSP also contains memories and digital peripherals that provide a cost effective, high performance solution to many DSP applications. On-Chip Emulation (OnCETM) circuitry provides convenient and inexpensive debug facilities normally available only through expensive external hardware. This RAM-based DSP contains a 2 K x 16 Program RAM and a 4 K x 16 data RAM. The Central Processing Unit (CPU) consists of three execution units operating in parallel allowing up to six operations to occur in an instruction cycle. This parallelism greatly increases the effective processing speed of the DSP56167. The MPU-style programming model and instruction set allow straightforward generation of efficient, compact code. The DSP56167 is a member of Motorola's DSP56100 family of 16-bit Digital Signal Processors (DSPs).
Port B or Host
15 7+10
IM
Bootstrap ROM 64 x 16 Program Control Unit Program Decode Controller Program Address Generator 4 RESET
Address Generation Unit Peripheral Address Generation Unit
IN
XAB1 XAB2 PAB Program RAM 2 K x 16 Data RAM 4 K x 16 XDB PDB GDB Program Interrupt Controller Data ALU 16 x 16 + 40 40-Bit MAC Two 40-Bit Accumulators MODA/IRQA MODB/IRQB MODC/IRQC
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External Address Bus Switch Bus Control External Data Bus Switch External Chip Enables 16 Bits
On-Chip Peripherals: Host, SSI0, SSI1, Timer GPIO, Codec Internal Data Bus Switch and Bit Manipulation Unit Clock and PLL OnCETM
EL PR
EXTAL SXFC CLKO
Codec, Port C and/or SSI0, SSI1, Timer
Figure 1 DSP56167 Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change without notice.
(c)1996, 1997 MOTOROLA, INC.
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Address 16 Port A 10 16 Data 2 AA0771
Table of Contents
TABLE OF CONTENTS SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5 SIGNAL/PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
FOR TECHNICAL ASSISTANCE:
Telephone: Email: Internet:
1 (800) 521-6274
Data Sheet Conventions
This data sheet uses the following conventions:
PR
Examples: Note:
EL
"asserted" "deasserted" Signal/Symbol PIN PIN PIN PIN
OVERBAR
IM
Used to indicate a signal that is active when pulled low; for example, the RESET pin is active when low Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
ii
IN
DSP56167/D, Rev. 1
dsphelp@dsp.sps.mot.com
http://www.motorola-dsp.com
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MOTOROLA
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DESIGN CONSIDERATIONS (INCLUDES NOTES FOR DSP56166 TO DSP56167 DESIGN CONVERSION) . . . . . . . . 4-1
Features
FEATURES
* Digital Signal Processing Core - - - - - - - - - - - - - - - - Up to 30 Million Instructions Per Second (MIPS) at 60 MHz with 33.3 ns instruction cycle Single-cycle 16 x 16-bit parallel Multiply-Accumulate 2 x 40-bit accumulators with extension byte
Highly parallel instruction set with unique DSP addressing modes Nested hardware DO loops including infinite loops and DO zero loop Two instruction LMS adaptive filter loop Fast auto-return interrupts
Three external interrupt request pins
Three 16-bit internal data and three 16-bit internal address buses Individual programmable wait states on the external bus for program, data, and peripheral memory spaces Programmable absolute short addressing mode Off-chip memory-mapped peripheral space with programmable access time and separate peripheral enable pin Peripheral Address Generation Unit (PAGU) On-chip memory-mapped peripheral registers On-Chip Emulation (OnCETM) port for unobtrusive, processor speedindependent debugging with DR line static latch with Reset
PR
- - - - -
MOTOROLA
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* Memory -
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64 x 16-bit bootstrap ROM
Modified Harvard architecture permits simultaneous accesses to program and data memories 2 K x 16-bit on-chip Program RAM 4 K x 16-bit on-chip data RAM
External memory expansion with 16-bit address and data buses with static latches with Reset and software-controlled BG pull-down Bootstrap loading from external byte-wide Program ROM, Host Interface, or 16-bit Synchronous Serial Interface (SSI0)
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DSP56167/D, Rev. 1
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Fractional and integer arithmetic with support for multiprecision arithmetic
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iii
Features
*
Peripherals - - - Up to twenty-five General Purpose Input/Output (GPIO) pins, depending on which peripherals are enabled Byte-wide Host Interface with Direct Memory Access (DMA) support (or up to fifteen Port B GPIO lines) On-chip voice band codec, Analog-to-Digital (A/D) and Digital-toAnalog (D/A) * * - - - - - Internal voltage reference (1/2 of positive power supply) and splitvoltage operation (with respect to the core) No off-chip components required
16-bit SSI support: two 4-pin ports (or up to eight Port C GPIO lines) One 16-bit timer/event counter (or two Port C GPIO lines) Double-buffered peripherals
*
PR
iv DSP56167/D, Rev. 1 MOTOROLA
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-
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Energy Efficient Design - -
Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer for the DSP core clock with a wide input frequency range (12.2 KHz to 60 MHz) that initializes to a preset low frequency operation during hardware reset
Power-saving Wait and Stop modes
Fully static, HCMOS design allows operation from 60 MHz down to DC operating frequencies 112-pin plastic Thin Quad Flat Pack (TQFP) surface-mount package
IN
Independent external chip enables BR and PEREN during Bus Master mode
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Product Documentation
PRODUCT DOCUMENTATION
The three documents listed in the following table are required for a complete description of the DSP56167 and are necessary to design properly with the part. Documentation is available from one of the following locations (see back cover for detailed information): * * * * A local Motorola distributor
A Motorola Literature Distribution Center
Table 1 DSP56167 Documentation
Name DSP56100 Family Manual DSP56167 User's Manual DSP56167 Technical Data Note: Description
Detailed description of the DSP56100 family processor core and instruction set
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DSP56167/D, Rev. 1
Detailed functional description of the DSP56167 memory configuration, operation, and register programming DSP56167 features list and physical, electrical, timing, and package specifications
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MOTOROLA
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The DSP56167 User's Manual is currently being developed and will not be available for general release until the end of the second quarter of 1997. The DSP56167 is a feature expanded, enhanced version of the DSP56166 and is entirely software compatible. Until the DSP56167 User's Manual is available, the user can refer to the DSP56166 User's Manual, order number DSP56166UM/AD for information common to both chips and Section 4 of this document for a description of the added features and enhanced capability of the DSP56167.
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See note below DSP56167/D
The World Wide Web (WWW) (the source for the latest information)
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Order Number DSP56100FM/AD
A Motorola semiconductor sales office
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Product Documentation
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vi DSP56167/D, Rev. 1 MOTOROLA
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IN
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SECTION
1
SIGNAL/PIN DESCRIPTIONS
INTRODUCTION
Table 1-1 Signal Functional Group Allocations
Functional Group Power (VDDX) Ground (VSSX) PLL and Clock Address Bus Data Bus Bus Control
IN
Port A1 Port B2 Port C3
IM
EL
Host Interface (HI) Port Codec
Interrupt and Mode Control
16-Bit Synchronous Serial Interface (SSI0) Port 16-Bit Synchronous Serial Interface (SSI1) Port Timer
PR
Note: 1. 2. 3.
On-Chip Emulation (OnCE) Port
Port A signals define the External Memory Interface port. Port B signals are GPIO signals multiplexed on the external pins also used with the HI signals. Port C signals are GPIO signals multiplexed on the external pins also used by the SSI ports and the Timer.
Figure 1-1 is a diagram of DSP56167 signals by functional group.
MOTOROLA
DSP56167/D, Rev. 1
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Number of Signals 11 16 3 16 16 10 4 15 7 4 4 2 4
DSP56167 signals are organized into thirteen functional groups as summarized in Table 1-1.
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Detailed Description Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 1-6 Table 1-7 Table 1-8 Table 1-9 Table 1-10 Table 1-11 Table 1-12 Table 1-13 Table 1-14
1-1
Signal/Pin Descriptions Introduction
DSP56167 Power Inputs: PLL and Clock Address and Data Bus Bus Control Internal Logic Port B Codec Port C Grounds: PLL and Clock Address and Data Bus Bus Control Internal Logic Port B Codec Port C MODA/IRQA MODB/IRQB MODC/IRQC RESET
VDDS VDDA/D VDDC VDDQ VDDPB VDDA VDDPC
4 2
Interrupt/ Mode Control
EXTAL CLKO SXFC
PLL and Clock
IM
16 16
External Address Bus External Data Bus External Bus Control
IN
Codec 16-Bit Synchronous Serial Interface (SSI0) Port2 16-Bit Synchronous Serial Interface (SSI1) Port2 Timer2 OnCE Port
GNDS VSSA/D VSSC VSSQ VSSPB VSSA VSSPC
8 2 2
A0-A15 D0-D15 BS PS/DS PEREN WR RD R/W TA BR BG BB
EL
Note:
PR
1. The HI port signals are multiplexed with the Port B GPIO signals (PB0-PB14). 2. The 16-bit SSI and Timer signals are multiplexed with the Port C GPIO signals (PC0-PC2, PC4-PC7, and PC9-PC11).
AA0772
Figure 1-1 Signals Identified by Functional Group
1-2
DSP56167/D, Rev. 1
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MIC AUX SPKP SPKM VRAD VRDA VDIV PC0/STD0 PC1/SRD0 PC2/SCK0 PC4/SFS0 PC5/STD1 PC6/SRD1 PC7/SCK1 PC9/SFS1 PC10/TIN PC11/TOUT DSI/OS0 DSCK/OS1 DSO DR
Host Interface Port1
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8 3
PB0/H0-PB7/H7 PB8/HA0-PB10/HA2 PB11/HR/W PB12/HEN PB13/HREQ PB14/HACK
MOTOROLA
Signal/Pin Descriptions Power
POWER
Table 1-2 Power
Power Names VDDS Description Synthesizer Power--This line is dedicated to the PLL circuits and must remain noise-free to ensure stable PLL frequency and performance. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the VDD power rail. Use a 0.1 F capacitor and a 0.01 F capacitor located as close as possible to the chip package to connect between the VDDS line and the GNDS line. Address and Data Bus Power--These lines supply power to the address and data busses. Bus Control Power--This line supplies power to the bus control logic.
VDDA/D VDDC VDDQ
VDDPB VDDA VDDPC
Port B Power--These lines supply power to the Port B HI logic. Codec Power--This line supplies power to the codec logic.
PR
MOTOROLA DSP56167/D, Rev. 1
EL
1-3
IM
Port C Power--This line supplies power to the SSI and Timer logic.
IN
Quiet Power--These lines supply a quiet power source to the internal logic circuits. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the VDD power rail. Use a 0.1 F bypass capacitor located as close as possible to the chip package to connect between the VDDQ lines and the VSSQ lines.
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Signal/Pin Descriptions Ground
GROUND
Table 1-3 Ground
Ground Names GNDS Description Synthesizer Ground--This line supplies a dedicated quiet ground connection for the PLL and clock circuits and must remain relatively noise-free to ensure stable PLL frequency and performance. Ensure that this line connects through an extremely low impedance path to ground. Use a 0.1 F capacitor and a 0.01 F capacitor located as close as possible to the chip package to connect between the VDDS line and the GNDS line. Address and Data Bus Ground--These lines connect system ground to the address bus. Bus Control Ground--This line connects ground to the bus control logic. Quiet Ground--These lines supply a quiet ground connection for the internal logic circuits. Ensure that this line connects through an extremely low impedance path to ground. Use a 0.1 F bypass capacitor located as close as possible to the chip package to connect between the VDDQ line and the VSSQ line. Port B Host Interface Ground--These lines supply ground connections for the Port B HI logic. Codec Power--This line supplies a ground connection to the codec logic.
VSSA/D VSSC VSSQ (4)
VSSPB VSSA VSSPC
PR
1-4 DSP56167/D, Rev. 1 MOTOROLA
EL
IM
Port C Power--This line supplies a ground connection to the SSI and Timer logic.
IN
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Signal/Pin Descriptions PLL and Clock
PLL AND CLOCK
Table 1-4 PLL and Clock Signals
Signal Name EXTAL Signal Type Input State during Reset Input Signal Description External Clock/Crystal Input--This input should be connected to an external crystal or to an external oscillator. A sine wave with a minimum swing of 1 VP can be applied to this pin. After being squared, the input clock can provide the DSP core clock directly. Internally, the clock is divided to produce a four-phase instruction clock (T0, T1, T2, and T3) with the instruction clock period being equal to two input clock periods. This input clock can also be selected as the input clock for the on-chip codec and PLL.
CLKO
Output
Chipdriven
SXFC
Input
PR
Signal Names Signal Type A0-A15 Output
ADDRESS BUS
EL
State during Reset
IM
Note: Input
Tri-stated Address Bus--These signals change in T0 and specify the address for external program and data memory accesses. If there is no external bus activity, A0-A15 remain at their previous values to reduce power consumption.
MOTOROLA
IN
* * *
PLL Output Clock--This buffered clock signal output can be one of three signals, selected by programming the two bits, CS1 and CS2 in the PLL Control Register (PLCR): A squared version of the EXTAL input A squared version of the EXTAL input divided by 2 A delayed version of the DSP core master clock
CLKO can be disabled by setting the Clockout Disable (CD) Bit 7 of the Operating Mode Register (OMR). For information about programming the PLCR or OMR, see the DSP56100 Family Manual.
External Filter Capacitor--Connect an external capacitor to the filter circuit of the PLL between this input and VDDS. See Section 2 of this document for additional information about capacitor size selection.
Table 1-5 Address Bus Signals
Signal Description
DSP56167/D, Rev. 1
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1-5
Signal/Pin Descriptions Data Bus
DATA BUS
Table 1-6 Data Bus Signals
Signal Names D0-D15 Signal Type Input/ Output State during Reset Signal Description
BUS CONTROL
Signal Name BS
Signal Type
State during Reset
PS/DS
Output Tri-stated
PR
WR
1-6
EL
PEREN Output Tri-stated Output Tri-stated
IM
Output Pulled high
IN
DSP56167/D, Rev. 1
Table 1-7 Bus Control Signals
Bus Select--BS is asserted when the DSP accesses the external bus, and it acts as an early indication of imminent external bus access by the DSP56167. It may also be used with the bus wait input WT to generate wait states. BS is pulled high when the BG or RESET signal is asserted. Program/Data Memory Select--This signal is asserted high for external program memory access and low for external data memory access. The timing is the same as for the Address Bus signals A0- A15. If the external bus is not used during an instruction cycle, PS/ DS goes high at the next T0. Peripheral Enable--This output is asserted only when the external peripheral data memory space (X:$FF00-X:$FF7F) is referenced. The timing is the same as for the Address Bus signals A0-A15. The signal is asserted and deasserted in T0. PEREN is driven high for any program space access and for any data memory access outside of the peripheral data memory address range.
Write Enable--WR is asserted low during external memory write cycles. When WR is asserted in T1, the data bus signals (D0-D15) become outputs. The DSP puts data on the bus on the leading edge of T2. When WR is deasserted in T3, the data should be latched in the external device. The signal qualifies A0-A15 and PS/DS. WR is tri-stated when the DSP is not the bus master. WR can be connected directly to the WE pin of a Static RAM chip.
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Signal Description
Tri-stated Data Bus--These signals provide the bidirectional data bus for external program and data memory accesses. Read data is sampled in by the trailing edge of T2, while write data output is enabled by the leading edge of T2 and tri-stated at the leading edge of T0. D0-D15 are tri-stated when there is no bus activity.
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MOTOROLA
Signal/Pin Descriptions Bus Control
Table 1-7 Bus Control Signals (Continued)
Signal Name RD Signal Type State during Reset Signal Description Read Enable--RD is asserted low during external memory read cycles. When RD is asserted in late T0/early T1, the data bus signals (D0-D15) become inputs and an external device is enabled on the data bus. When RD is deasserted in T3, the data is latched in the DSP. The signal qualifies A0-A15 and PS/DS. RD is tri-stated when the DSP is not the bus master. RD can be connected directly to the OE pin of a ROM or Static RAM.
Output Tri-stated
R/W
Output Tri-stated
Read/Write--The timing for this signal is the same as the bus address lines, providing an early write signal. R/W changes in T0 and is high for a read access and low for a write access. If the external bus is not used during an instruction cycle, R/W goes high at the next T0. Transfer Acknowledge--When there is external bus cycle activity, TA can be used to insert Wait States (WS) in the external bus cycle. TA is sampled on the leading edge of the clock input. If TA is sampled high, the bus cycle will end 2T after TA is sampled low, assuming the Bus Control Register (BCR) is not programmed to insert its own WS. The number of WS is determined by TA and the BCR and is equal to the larger of the two determining sources. TA continues to be sampled as the BCR WS number decrements. If TA is sampled low, but there are remaining WS required by the BCR, the bus cycle continues until the BCR requirement is satisfied. If the BCR requirement is satisfied, but TA has not been sampled low, the WS continue until 2T after TA is sampled low. To be sampled high at the start of the bus cycle, TA must be driven high in T3 on the previous instruction cycle. If TA is sampled low at T0 of a bus cycle and no WS are specified by the BCR, no WS are inserted in the external bus cycle. If there is no external bus activity, the DSP ignores TA.
TA
Input
Input
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MOTOROLA DSP56167/D, Rev. 1
EL
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IN
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1-7
Signal/Pin Descriptions Bus Control
Table 1-7 Bus Control Signals (Continued)
Signal Name BR Signal Type State during Reset Signal Description Bus Request--After reset, this signal is an input (Slave mode). When the BR input is asserted, an external device, such as another processor or DMA controller, becomes the master of the external address and data buses. The DSP asserts the BG output signal after a few T states (i.e., T0, T1, etc.) to acknowledge the BR input. The DSP releases control of the external bus at the earliest possible time consistent with proper synchronization. At release, the DSP tristates PEREN, PS/DS, RD, WR, and R/W, and deasserts the BB signal to indicate the bus is released. While the bus is released, the DSP may continue internal operations using internal memory spaces. If external access is required, the DSP bus controller inserts WS until the bus is available. Bus control returns to the DSP when the BR and BB inputs are both deasserted.
Input Input or Output
EL
Note: Note:
PR
1-8
IM
IN
Note: Note:
Interrupts are not serviced while a DSP instruction is waiting for the bus. BR cannot interrupt the execution of a read-modify-write instruction.
If the master bit in the Operating Mode Register (OMR) is set, this signal is an output (Master mode). In this mode the DSP is not the default bus master and must assert BR to gain control of the external bus. After asserting BR, the DSP bus controller inserts WS until the BG input is asserted. The DSP begins processing external accesses on the rising edge of the clock after BB is sampled high. BR remains asserted until the DSP no longer needs the bus. In Master mode, the Request Hold (RH) bit in the BCR allows BR to be asserted under software control. During external accesses caused by an instruction executed out of external program memory, BR remains asserted for consecutive external X data memory accesses and continues toggling for consecutive external program memory accesses until RH in the BCR is set. In Master mode, BR can also be used for non-arbitration uses. If BG is always asserted, BR is asserted in T0 of every external bus access. In this case, BR can act as a chip select signal to enable and disable an external memory device between external and internal accesses. In this case, the BR timing is similar to A0-A15, R/W, and PS/DS and is asserted and deasserted in T0.
DSP56167/D, Rev. 1
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MOTOROLA
Signal/Pin Descriptions Bus Control
Table 1-7 Bus Control Signals (Continued)
Signal Name BG Signal Type State during Reset Signal Description Bus Grant--After reset, this signal is an output (Slave mode) that is asserted to acknowledge an external device request for bus control (i.e., assertion of a BR input). The DSP asserts the BG output signal after a few T states to acknowledge receipt of the BR input. The DSP releases control of the external bus at the earliest possible time consistent with proper synchronization. At release, the DSP tristates PEREN, PS/DS, RD, WR, and R/W and deasserts the BB output. When the BR and BB inputs are deasserted, the DSP regains control of the bus and the BG output is deasserted. Note:
Output Driven or Input high
BG may be asserted in the middle of an instruction that requires more than one external bus cycle for execution, but never during a read-modify-write instruction.
BB
Input Input or Output
PR
MOTOROLA DSP56167/D, Rev. 1
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IN
If the master bit in the OMR is set, this signal is an input (Master mode). In this mode the external bus master asserts BG to acknowledge the BR signal generated by the DSP to request control of the bus. The DSP begins processing external accesses on the rising edge of the clock after the BB input generated by the other bus master is sampled high. When the BG input is deasserted, the DSP releases the bus as soon as the current transfer is complete. Bus Busy--After reset, this signal is an input. An external master asserts this input signal to indicate that it has control of the bus and is performing a bus access. When the DSP acquires control of the external bus and performs and external access, it asserts BB as an output signal to the other bus master devices. The DSP deasserts BB and it again becomes an input when the DSP releases bus control.
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1-9
Signal/Pin Descriptions Interrupt and Mode Control
INTERRUPT AND MODE CONTROL
Table 1-8 Interrupt and Mode Control Signals
Signal Name MODA/IRQA Signal Type Input State during Reset Input Signal Description Mode Select A/External Interrupt Request A -- This input has two functions: 1. to select the initial chip operating mode, and
MODB/IRQB
PR
1-10
EL
IM
Input Input 2.
MODA is read and internally latched in the DSP when the processor exits the Reset state. MODA, MODB, and MODC select the initial chip operating mode. Several clock cycles (depending on PLL stabilization time) after leaving the Reset state, the MODA signal changes to external interrupt request IRQA. The chip operating mode can be changed by software after reset. The IRQA input is a synchronized external interrupt request that indicates that an external device is requesting service. It may be programmed to be level-sensitive or negative-edge-sensitive. If level-sensitive triggering is selected, an external pull up resistor is required for wired-OR operation. If the processor is in the Stop state and IRQA is asserted, the processor will exit the Stop state. Mode Select B/External Interrupt Request B -- This input has two functions: 1. to select the initial chip operating mode, and after internal synchronization, to allow an external device to request a DSP interrupt.
IN
DSP56167/D, Rev. 1
MODB is read and internally latched in the DSP when the processor exits the Reset state. MODA, MODB, and MODC select the initial chip operating mode. Several clock cycles (depending on PLL stabilization time) after leaving the Reset state, the MODB signal changes to external interrupt request IRQB. After reset, the chip operating mode can be changed by software. The IRQB input is an external interrupt request that indicates that an external device is requesting service. It may be programmed to be level-sensitive or negative-edgetriggered. If level sensitive triggering is selected, an external pull up resistor is required for wired-OR operation.
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2.
after synchronization, to allow an external device to request a DSP interrupt.
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MOTOROLA
Signal/Pin Descriptions Interrupt and Mode Control
Table 1-8 Interrupt and Mode Control Signals (Continued)
Signal Name MODC/IRQC Signal Type Input State during Reset Input Signal Description Mode Select C/External Interrupt Request C-- This input has two functions: 1. to select the initial chip operating mode, and 2. after synchronization, to allow an external device to request a DSP interrupt.
RESET
Input
Input
PR
MOTOROLA DSP56167/D, Rev. 1
EL
1-11
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IN
MODC is read and internally latched in the DSP when the processor exits the Reset state. MODA, MODB, and MODC select the initial chip operating mode. Several clock cycles (depending on PLL stabilization time) after leaving the Reset state, the MODC signal changes to external interrupt request IRQC. After reset, the chip operating mode can be changed by software. The IRQC input is an external interrupt request that indicates that an external device is requesting service. It may be programmed to be level-sensitive or negative-edgetriggered. If level sensitive triggering is selected, an external pull up resistor is required for wired-OR operation.
Reset -- This input is a direct hardware reset on the processor. When RESET is asserted low, the DSP is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, and MODC signals. The internal reset signal is deasserted synchronous with the internal clocks.
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Signal/Pin Descriptions Host Interface (HI) Port
HOST INTERFACE (HI) PORT
Table 1-9 HI Signals
Signal Name H0-H7 Signal Type State during Reset Signal Description
PB0-PB7
Port B GPIO 0-7 (PB0-PB7)--These signals are GPIO signals (PB0-PB7) when the Host Interface is not selected. After reset, the default state for these signals is GPIO input.
HA0-HA2
Input
PB8-PB10
Input/ Output
HR/W
PR
PB12
1-12
EL
PB11 Input/ Output HEN Input
IM
Input
Tri-stated Host Read/Write--This input selects the direction of data transfer for each host processor access. If HR/W is high and HEN is asserted, H0-H7 are outputs and DSP data is transferred to the host processor. If HR/W is low and HEN is asserted, H0- H7 are inputs and host data is transferred to the DSP. HR/W is stable when HEN is asserted. Port B GPIO 11 (PB11)--This signal is a GPIO signal (PB11) when the Host Interface is not being used. After reset, the default state for this signal is GPIO input.
Tri-stated Host Enable--This input enables a data transfer on the host data bus. When HEN is asserted and HR/W is high, H0-H7 are outputs and DSP data is transferred to the host processor. If HR/W is low and HEN is asserted, H0-H7 are inputs and host data is transferred to the DSP. This input may be used as a chip Input/ select input from the external host. Output Port B GPIO 12 (PB12)--This signal is a GPIO signal (PB12) when the Host Interface is not being used. After reset, the default state for this signal is GPIO input.
IN
DSP56167/D, Rev. 1
Tri-stated Host Address 0 - Host Address 2 (HA0-HA2)--These inputs provide the address selection for each Host Interface register and are stable when HEN is asserted. Port B GPIO 8-10 (PB8-PB10)--These signals are GPIO signals (PB8-PB10) when the Host Interface is not selected. After reset, the default state for these signals is GPIO input.
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MOTOROLA
Input/ Tri-stated Host Data Bus (H0-H7)--This data bus transfers data between Output the host processor and the DSP56167. The bus signals are inputs except when HR/W is high and HEN is asserted (host read).
Signal/Pin Descriptions Host Interface (HI) Port
Table 1-9 HI Signals (Continued)
Signal Name HREQ Signal Type State during Reset Signal Description
PB13
Input/ Output
Port B GPIO 13 (PB13)--This signal is a General Purpose (not open-drain) I/O signal (PB13) when the Host Interface is not selected. After reset, the default state for this signal is GPIO input.
HACK
Input
Tri-stated Host Acknowledge-- This input has two functions:
PB14
PR
MOTOROLA DSP56167/D, Rev. 1
EL
IM
Input/ Output
IN
1. 2.
Host Acknowledge handshake signal--HACK may be used as a data strobe for HI DMA data transfers
MC68000 Host Interrupt Acknowledge--This function enables the HI Interrupt Vector Register (IVR) onto the HI data bus if the HREQ output is asserted. In this case, all other HI control pins are ignored and the HI state is not affected.
Port B GPIO 14 (PB14)--This signal is a GPIO signal (PB14) when the Host Interface is not selected. After reset, the default state for this signal is GPIO input.
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Y
1-13
Open Tri-stated Host Request-- This signal is used by the Host Interface to drain request service from the host processor, DMA controller, or a Output simple external controller. HREQ is asserted when an enabled request occurs in the HI. The signal is deasserted when the request is cleared or masked, the DMA controller asserts HACK, or the DSP is reset.
Signal/Pin Descriptions Codec
CODEC
Table 1-10 Codec Signals
Signal Name AUX Signal Type Input State during Reset Input Signal Description Auxiliary Input--This signal is selected as the analog input to the A/D converter when the INS bit in Codec Control Register 1 (CCR1) is set. Leave this pin floating when the codec is not used.
SPKP
Output
Speaker Output 1--This signal is the negative analog output from the on-chip D/A converter. Leave this pin floating when the codec is not used. In the codec Power Down mode, this signal connects internally to VDIV through a high impedance path.
SPKM
Output
VRDA
PR
Note:
1-14
EL
VDIV Output
The SPKP and SPKM outputs consist of a fully differential driver stage, with each output having an operating range of 1.0 VP from VRDA. The output op-amp can provide up to 0.35 mA of current which can drive a resistive load of 3 k in series with 15 nF capacitance between the differential outputs.
IM
Output
VRAD
Output
IN
DSP56167/D, Rev. 1
Speaker Output 2--This signal is the positive analog output from the on-chip D/A converter. Leave this pin floating when the codec is not used. In the codec Power Down mode, this signal connects internally to VDIV through a high impedance path.
Voltage Reference Output for A/D-- This is the output from the op-amp buffer in the A/D sections reference voltage generator. It has a value of 1/2 VDDA. This voltage is used as the analog ground internal to the A/D block. Always connect this pin to ground through two capacitors even when the codec is not used. In codec Power Down mode, the VRAD signal is tri-stated. Voltage Reference Output for D/A-- This is the output from the op-amp buffer in the D/A sections reference voltage generator. It has a value of 1/2 VDDA. This voltage is used as the analog ground internal to the D/A block. Always connect this pin to ground through two capacitors even when the codec is not used. In codec Power Down mode, the VRDA signal is tri-stated. Voltage Division Output--This is the input to the op-amp buffer in the reference voltage generator. It is connected to a resistor divider network located within the codec block that provides a voltage equal to 1/2 VDDA. Leave this pin floating when the codec is not used. This output is not affected by codec Power Down mode.
AR
MIC
Input
Input
Microphone Input--This signal is selected as the analog input to the A/D converter when the INS bit in CCR1 is cleared. Leave this pin floating when the codec is not used.
Y
MOTOROLA
Signal/Pin Descriptions 16-Bit Synchronous Serial Interface 0 Port
16-BIT SYNCHRONOUS SERIAL INTERFACE 0 PORT
Table 1-11 16-Bit Synchronous Serial Interface 0 (SSI0) Signals
Signal Name STD0 Signal Type State during Reset Signal Description Serial Transmit Data 0 (STD0)--This output transmits serial data from the SSI0 Transmit Shift Register (TSR0).
PC0
After reset, the default state is GPIO input. SRD0 Input Tristated
Serial Receive Data 0 (SRD0)--The input receives serial data into the SSI0 Receive Shift Register (RSR0).
SCK0
Input/ TriOutput stated
PC2
PR
MOTOROLA
EL
SFS0 Input/ TriOutput stated PC4
IM
IN
DSP56167/D, Rev. 1
PC1
Port C GPIO 1 (PC1)-- This signal is a GPIO signal (PC1) when the SSI0 SRD0 function is not being used. After reset, the default state is GPIO input. Serial Clock 0 (SCK0)--This bidirectional signal provides the serial bit rate clock for the SSI0 interface. The clock signal can be continuous or gated and is used by both the transmitter and receiver. Port C GPIO 5 (PC5)-- This signal is a GPIO signal (PC2) when the SSI0 SCK0 function is not being used. After reset, the default state is GPIO input. Serial Frame Sync 0-- This bidirectional signal is used by the SSI0 serial interface for frame sync I/O or flag I/O. The SFS0 is used by both the transmitter and receiver to synchronize data transfer and can be an input or an output. Port C GPIO 4 (PC4)-- This signal is a GPIO signal (PC4) when the SSI0 SFS0 function is not being used. After reset, the default state is GPIO input.
AR
Port C GPIO 0 (PC0)-- This signal is a GPIO signal (PC0) when the SSI0 STD0 function is not being used.
Y
1-15
Output Tristated
Signal/Pin Descriptions 16-Bit Synchronous Serial Interface 1 Port
16-BIT SYNCHRONOUS SERIAL INTERFACE 1 PORT
Table 1-12 16-Bit Synchronous Serial Interface 1 (SSI1) Signals
Signal Name STD1 Signal Type State during Reset Signal Description Serial Transmit Data 1 (STD1)--This output transmits serial data from the SSI1 Transmit Shift Register (TSR1).
PC5
After reset, the default state is GPIO input. SRD1 Input Tristated
Serial Receive Data 0 (SRD0)--The input receives serial data into the SSI1 Receive Shift Register (RSR1).
SCK1
Input/ TriOutput stated
PC7
PR
1-16
EL
SFS0 Input/ TriOutput stated PC9
IM
IN
DSP56167/D, Rev. 1
PC6
Port C GPIO 6 (PC6)-- This signal is a GPIO signal (PC6) when the SSI1 SRD1 function is not being used. After reset, the default state is GPIO input. Serial Clock 1 (SCK1)--This bidirectional signal provides the serial bit rate clock for the SSI1 interface. The clock signal can be continuous or gated and is used by both the transmitter and receiver. Port C GPIO 7 (PC7)-- This signal is a GPIO signal (PC7) when the SSI1 SCK1 function is not being used. After reset, the default state is GPIO input. Serial Frame Sync 1-- This bidirectional signal is used by the SSI1 serial interface for frame sync I/O or flag I/O. The SFS1 is used by both the transmitter and receiver to synchronize data transfer and can be an input or an output. Port C GPIO 9 (PC9)-- This signal is a GPIO signal (PC9) when the SSI1 SFS1 function is not being used. After reset, the default state is GPIO input.
AR
Port C GPIO 5 (PC5)-- This signal is a GPIO signal (PC5) when the SSI1 STD1 function is not being used.
Y
MOTOROLA
Output Tristated
Signal/Pin Descriptions Timer
TIMER
Table 1-13 Timer Signals
Signal Name TIN Signal Type Input State during Reset Tristated Signal Description Timer Input --This input signal receives external pulses to be counted by the on-chip 16-bit timer when external clocking is selected. The pulses are internally synchronized to the DSP core internal clock. Port C GPIO 10 (PC10)-- This signal is a GPIO signal (PC10) when the Timer function is not being used. Input/ TriOutput stated Timer Output--This output generates pulses, toggles on a timer overflow event, or toggles on a compare event.
PC10 TIO1
PR
MOTOROLA DSP56167/D, Rev. 1
EL
1-17
IM
IN
PC11
Port C GPIO 11 (PC11)--This signal is a GPIO signal (PC11) when the Timer function is not being used.
AR
Y
Signal/Pin Descriptions On-Chip Emulation Port
On-CHIP EMULATION PORT
Table 1-14 On-Chip Emulation (OnCE) Port Signals
Signal Name DSI/OS0 Signal Type Input/ Output State during Reset Signal Description
DSCK/OS1
Input/ Output
PR
1-18
EL
DSO Output Pulled high
IM
Low Debug Serial Clock/Chip Status 1--The DSCK/OS1 signal Output supplies the serial clock to the OnCE port when it is an input. The serial clock provides pulses required to shift data into and out of the OnCE serial port. (Data is clocked into the OnCE port on the falling edge and is clocked out of the OnCE serial port on the rising edge.) The debug serial clock frequency must be no greater than 1/8 of the processor clock frequency. When switching from input to output, the signal is tri-stated. When it is an output, this signal works with the OS0 signal to provide information about the chip status. The DSCK/OS1 signal is an output when the chip is not in Debug mode. Debug Serial Output--Data contained in one of the OnCE port controller registers is provided through the DSO output signal, as specified by the last command received from the external command controller. Data is always shifted out the OnCE serial port MSB first. Data is clocked out of the OnCE serial port on the rising edge of DSCK. The DSO signal also provides acknowledge pulses to the external command controller. When the chip enters the Debug mode, the DSO signal will be pulsed low to indicate (acknowledge) that the OnCE is waiting for commands. After the OnCE receives a read command, the DSO signal will be pulsed low to indicate that the requested data is available and the OnCE serial port is ready to receive clocks in order to deliver the data. After the OnCE receives a write command, the DSO signal will be pulsed low to indicate that the OnCE serial port is ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided.
IN
DSP56167/D, Rev. 1
AR
Low Debug Serial Input/Chip Status 0--Serial data or commands Output are provided to the OnCE controller through the DSI/OS0 signal when it is an input. The data received on the DSI signal will be recognized only when the DSP has entered the Debug mode of operation. Data is latched on the falling edge of the DSCK serial clock. Data is always shifted into the OnCE serial port Most Significant Bit (MSB) first. When the DSI/OS0 signal is an output, it works in conjunction with the OS1 signal to provide chip status information. The DSI/OS0 signal is an output when the processor is not in Debug mode. When switching from output to input, the signal is tri-stated.
Y
MOTOROLA
Signal/Pin Descriptions On-Chip Emulation Port
Table 1-14 On-Chip Emulation (OnCE) Port Signals (Continued)
Signal Name DR Signal Type Input State during Reset Input Signal Description Debug Request--The debug request input (DR) allows the user to enter the Debug mode of operation from the external command controller. When DR is asserted, it causes the DSP to finish the current instruction being executed, save the instruction pipeline information, enter the Debug mode, and wait for commands to be entered from the DSI line. While in Debug mode, the DR signal lets the user reset the OnCE controller by asserting it and deasserting it after receiving acknowledge. It may be necessary to reset the OnCE controller in cases where synchronization between the OnCE controller and external circuitry is lost. DR must be deasserted after the OnCE port responds with an acknowledge on the DSO signal and before sending the first OnCE command. Asserting DR will cause the chip to exit the Stop or Wait state. Having DR asserted during the deassertion of RESET will cause the DSP to enter Debug mode.
PR
MOTOROLA DSP56167/D, Rev. 1
EL
1-19
IM
IN
AR
Y
Signal/Pin Descriptions On-Chip Emulation Port
PR
1-20 DSP56167/D, Rev. 1 MOTOROLA
EL
IM
IN
AR
Y
SECTION
2
SPECIFICATIONS
GENERAL CHARACTERISTICS
Table 2-1 Absolute Maximum Ratings (VSS = 0 V)
Rating Supply Voltage All Input Voltages Symbol VDD VIN I
AR
Value -0.3 to +7.0 (VSS - 0.5) to (VDD + 0.5) 10 -55 to +150 Tstg
The DSP56167 is fabricated in high-density HCMOS with TTL compatible inputs and outputs.
IN
CAUTION DSP56167/D, Rev. 1
Current Drain per Pin excluding VDD and VSS Storage Temperature
PR
MOTOROLA
EL
IM
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this highimpedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or VDD).
Y
Unit V V mA C
2-1
Specifications General Characteristics
Table 2-2 Recommended Operating Conditions
Rating Supply Voltage Operating Temperature Range Symbol VDD TJ Value 4.5 to 5.5 -40 to 105 Unit V C
Table 2-3 Thermal Characteristics for 112-pin TQFP Package
Thermal Resistance Junction-to-Ambient Junction-to-Case (estimated) Thermal characterization parameter
Note: 1. 2.
3.
PR
2-2
EL
DSP56167/D, Rev. 1 MOTOROLA
IM
IN
See discussion under Design Considerations, Heat Dissipation, page 4-1. Junction-to-ambient thermal resistance is based on measurements on a horizontal, single-sided, printed circuit board per SEMI G38-87 in natural convection. SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Road, Mountain View, CA 94043, (415) 964-5111. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88 with the exception that the cold plate temperature is used for the case temperature.
AR
RJA RJC JT 38.4 5.5 2.3
Symbol
Y
Value Rating C/W C/W C/W
Specifications DC Electrical Characteristics
DC ELECTRICAL CHARACTERISTICS
Table 2-4 DC Electrical Characteristics
Characteristics Supply Voltage Input High Voltage * EXTAL - DC coupled - AC coupled * RESET * MODA, MODB, MODC * All other inputs Input Low Voltage * EXTAL - DC coupled - AC coupled * MODA, MODB, MODC * All other inputs Symbol VDD VIHC VIHR VIHM VIH Min 4.5 Typ 5.0 Max 5.5 Units V
AR IN
IIN -1 ITSI VOHC VOH VOLC VOL -10 VDD - 0.1 2.4 -- -- ICCI ICCW ICCS ICCPLL ICCA -- -- -- -- -- -- -- CIN VILC VILC VILM VIL -0.5 -0.5 -0.5 -0.5 -- -- -- -- -- 0.2 x VDD VDD - 1 2.0 0.8 1 -- -- -- -- -- 10 -- -- 0.1 0.4 100 11 400 2 10 75 10 --
0.7 x VDD 1.0 2.5 3.5 2.0
Input Leakage Current EXTAL, RESET, MODA/IRQA, MODB/IRQB, MODC/IRQC, BR Tri-state (Off-state) Input Current (@ 2.4 V/0.4 V) Output High Voltage (IOH = -10 A) Output Low Voltage (IOH = 10 A)
IM
Output High Voltage (IOH = -0.4 mA)
EL PR
PLL current when active Analog Current * Codec enabled * Codec disabled Input Capacitance
Note: 1. current.
Output Low Voltage (IOL = 3.2 mA) R/W IOL = 1.6 mA, open-drain HREQ IOL = 6.7 mA, TXD IOL = 6.7 mA Internal Supply Current1 * Normal mode with codec and PLL disabled * Wait mode with codec and PLL disabled * Stop mode with PLL and CLKO disabled
Section 4 Design Considerations describes how to calculate the external supply
MOTOROLA
DSP56167/D, Rev. 1
Y
-- -- -- -- -- VDD VDD VDD VDD VDD V V V V V V V V A A V V V V mA mA A mA mA A pF
2-3
Specifications AC Electrical Characteristics
AC ELECTRICAL CHARACTERISTICS
The timing waveforms in the AC Electrical Characteristics are tested with a VIL maximum of 0.5 V and a VIH minimum of 2.4 V for all pins, except EXTAL, RESET, MODA, MODB, and MODC. These pins are tested using the input levels set forth in the DC Electrical Characteristics. AC timing specifications that are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal's transition. DSP56167 output levels are measured with the production test machine VOL and VOH reference levels set at 0.8 V and 2.0 V, respectively.
VIH
Input Signal
Low
Midpoint1 Fall Time
VIL
Note:
The midpoint is VIL + (VIH - VIL)/2.
IN
DSP56167/D, Rev. 1
AR
Pulse Width High Rise Time
Figure 2-1 Signal Measurement Reference
PR
2-4
EL
MOTOROLA
IM
Y
90% 50% 10% AA0179
Specifications Clock Operation
CLOCK OPERATION
The system clock must be externally supplied by connecting a square wave voltage source to EXTAL. Figure 2-2 shows the recommended connection of the external source to EXTAL and the external filter capacitor to SFXC.
1 nF XFC1 SXFC 0.01 F 0.1 F GNDS
EXTAL 1000 pF
100 K
/ 1 to / 16 ID3 - ID0
PFD
PS = 0 CS1 - CS0 CLKO /2
IM
Note:
EL PR
MOTOROLA
1. Must be a low leakage capacitor and must be located very close to the SXFC and VDDS pins.
AA0773
Figure 2-2 Connecting EXTAL and the External Filter Capacitor
IN
PS = 1 Internal Phase PH0 at Fosc
PLL
DSP56167/D, Rev. 1
AR
VDDS LF VCO / 1 to / 256 YD7 - YD0
Y
PD3 - PD0 PLLE = 1 / 20 to / 215 Fosc PLLE = 0
2-5
Specifications Clock Operation
Table 2-5 Clock Operation
60 MHz Num 1 2 3 4 5 6 7 8
Note: 1.
Characteristics Frequency of Operation (EXTAL input) Instruction Cycle Time = 2 x TC Wait State = TC = 2 T EXTAL cycle period EXTAL rise EXTAL fall time1 time1 high2,3,4
Symbol Min Ef ICYC WS TC 0 33 16.6 -- -- 8 8 16.6 Max 60 3 3
Unit MHz ns ns ns
AR
TH TL
90% 10%
EXTAL width
(48-52% duty cycle)
EXTAL width low2,3,4 (48-52% duty cycle)
2.
3. 4.
IM
TH TL
Rise and fall time may be relaxed to 12 ns maximum if the EXTAL input frequency is 20 MHz. If Ef is between 20 MHz and 40 MHz, rise and fall time should be 4 ns maximum. If Ef is between 40 MHz and 60 MHz, rise and fall time should meet the specified value (3 ns maximum). The duty cycle may be relaxed to 43-57% if the EXTAL input frequency is 20 MHz. If the EXTAL input frequency is between 20MHz and 40MHz, the duty cycle should be such that TH and TL are 12 ns minimum. If the EXTAL input frequency is between 40 MHz and 60 MHz, the duty cycle should be such that TH and TL meet the specified values in the 60 MHz column (8 ns minimum). T = ICYC/4 is used in the electrical characteristics. The exact length of each T is affected by the duty cycle of the external clock input. Duty cycles and EXTAL widths are measured at the EXTAL input signal midpoint when AC coupled and at VDD/2 when DC coupled.
IN
8 6 4 2
EL
7
EXTAL
PR
Figure 2-3 External Clock Timing
2-6
DSP56167/D, Rev. 1
Y
ns ns ns ns VIHC Midpoint VILC 5
AA0774
MOTOROLA
Specifications Phase Lock Loop (PLL) and Other Clock Timing
PHASE LOCK LOOP (PLL) AND OTHER CLOCK TIMING
Table 2-6 PLL and Other Clock Characteristics
Characteristics PLL output frequency EXTAL input clock amplitude
Note: 1. 2.
Min 10 1
Max Maximum f VDD
1
Unit MHz VP
RESET, STOP, MODE SELECT, AND INTERRUPT TIMING
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (60 MHz)
Num 10 11 Characteristics Min -- Max 21.0 Unit ns
Minimum Stabilization Duration1 OMR Bit 6 = 0 OMR Bit 6 = 1
IM
RESET Assertion to Address, Data and control signals High Impedance
IN
DSP56167/D, Rev. 1
VDD = 5.0 V 10%; TJ = -40 to +115C; CL = 50 pF + 2 TTL loads WS = number of wait states programmed into the external bus access using BCR (WS = 0-15)
AR
600KT 60T 16T 5 16T + 3 4.8 4.0 8.0 -- -- 18T + 15 cyc - 2 16T + 16 -- -- -- 11T + 3 19T + 3 22T + 3 -- -- --
12 13
EL
14
Asynchronous RESET Deassertion to First External Address Output7 Synchronous Reset Setup Time from RESET Deassertion to Rising Edge of CLKO Synchronous Reset Delay Time from CLKO High to the First External Access7
PR
15 16 17 18
Mode Select Setup Time Mode Select Hold Time Edge-Triggered Interrupt Request Width
Delay from IRQA, IRQB, IRQC Assertion to External Data Memory Access Out Valid -- Caused by First Interrupt Instruction Fetch -- Caused by First Interrupt Instruction Execution
19
Delay from IRQA, IRQB, IRQC Assertion to General Purpose Output Valid Caused by the Execution of the First Interrupt Instruction
MOTOROLA
Y
ns ns ns ns ns ns ns ns ns ns ns
Maximum DSP operating frequency An AC coupling capacitor is required on EXTAL if the levels are out of the normal CMOS level range (VILC > 0.2 x VDD or VIHC < 0.7 x VDD).
2-7
Specifications RESET, Stop, Mode Select, and Interrupt Timing
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (60 MHz) (Continued)
Num 20 Characteristics Delay from External Data Memory Address Output Valid Caused by First Interrupt Instruction Execution to Interrupt Request Deassertion for Level Sensitive Fast Interrupts2 Delay from General-Purpose Output Valid Caused by the Execution of the First Interrupt Instruction to IRQA, IRQB, IRQC Deassertion for Level Sensitive Fast Interrupts--If 2nd Interrupt Instruction is: Single Cycle2 Two Cycles Synchronous setup time from IRQA, IRQB, IRQC assertion to Synchronous falling edge of CLKO5,6 Min -- Max 5T - 22 + cyc x WS Unit ns
21
22 23 24 25
AR
12 -- 27T + 3 17 27T + 16 -- 524303T + 3 47T + 3 -- -- 524303T 47T -- -- 524303T + 3 47T + 3 8 18cyc 29cyc 18cyc 10 29cyc 262157cyc -- -- cyc+8 -- -- -- 10cyc -- --
Falling Edge of CLKO to First Interrupt Vector Address Out Valid after Synchronous recovery from Wait State3,5 IRQA Width Assertion to Recover from STOP State4
IN
DSP56167/D, Rev. 1
Delay from IRQA Assertion to Fetch of first instruction (exiting STOP)1,3 OMR Bit 6 = 0 OMR Bit 6 = 1
28
Duration for Level Sensitive IRQA Assertion to Cause the Fetch of First IRQA Interrupt Instruction (exiting STOP)1,3 OMR Bit 6 = 0 OMR Bit 6 = 1 Delay from Level Sensitive IRQA Assertion to First Interrupt Vector Address Out Valid (exiting STOP)1,3 OMR bit 6 = 0 OMR bit 6 = 1 DR Asserted to CLK low (Setup Time for Synchronous Recovery from Wait State) CLK low to DSO (ACK) Valid (Enter Debug Mode) After Synchronous Recovery from Wait State DR to DSO (ACK) Valid (Enter Debug Mode) After Asynchronous Recovery from Stop Mode After Asynchronous Recovery from Wait Mode
IM
29
EL
30 31 32 33
PR
DR Assertion Width Recovery from Wait/Stop without entering Debug Short wakeup from Wait/Stop and enter Debug Long wakeup from Stop enter Debug
2-8
Y
-- -- cyc - 26 3cyc - 26 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MOTOROLA
Specifications RESET, Stop, Mode Select, and Interrupt Timing
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (60 MHz) (Continued)
Num
Note: 1.
Characteristics
Min
Max
Unit
2.
3. 4.
5. 6. 7.
RESET 10
IN
11
IM
13
D0-D15 A0-A15 PS/DS R/W, BS PEREN
AR
VIHR 12 14
Circuit stabilization delay is required during reset when using an external clock in two cases: * after power-on reset, and * when recovering from Stop mode. When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 20 and 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the Deasserted Edge-Triggered mode is recommended when using fast interrupt. Long interrupts are recommended when using Level-Sensitive mode. The interrupt instruction fetch is visible on the pins only in Mode 3. The minimum is specified for the duration of an edge triggered IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. Timing 22 is for all IRQx interrupts while timing #23 is only when exiting the Wait state Timing 22 triggers off T1 in the normal state and off phi1 when exiting the Wait state. The instruction fetch is visible on the pins only in Mode 2 and Mode 3.
Figure 2-4 Asynchronous Reset Timing
PR
EL
CLKO RESET A0-A15, PS/DS BS, R/W PEREN
AA0776
Figure 2-5 Synchronous Reset Timing
MOTOROLA
DSP56167/D, Rev. 1
Y
First Fetch
AA0775
2-9
Specifications RESET, Stop, Mode Select, and Interrupt Timing
VIHR RESET 15 VIHM MODA, MODB MODC VILM 16
VIH VIL IRQA, IRQB, IRQC
AA0777
Figure 2-6 Operating Mode Select Timing
IRQA, IRQB NMI
AR
17 20 21
A0-A15 PS/DS BS, R/W PEREN 18
IRQA IRQB IRQC
PR
EL
General Purpose I/O IRQA IRQB NMI 19
IM
a) First Interrupt Instruction Execution
IN
b) General Purpose I/O
Figure 2-7 External Interrupt Timing (Negative Edge-Triggered)
First Interrupt Instruction Execution/Fetch
Figure 2-8 External Level-Sensitive Fast Interrupt Timing
2-10
DSP56167/D, Rev. 1
Y
AA0778 AA0779
MOTOROLA
Specifications RESET, Stop, Mode Select, and Interrupt Timing
CLKO
T0, T2 22
T1, T3
IRQA, IRQB NMI 23 A0-A15 PS/DS BS, R/W PEREN
Figure 2-9 Synchronous Interrupt from Wait State Timing
24 IRQA 25
A0-A15 PS/DS BS, R/W PEREN
IN IM
28 29
AR
First Instruction Fetch not IRQA Interrupt Vector
AA0781
Figure 2-10 Recovery from Stop State Using Asynchronous Interrupt Timing
IRQA
EL
A0-A15 PS/DS BS, R/W PEREN
PR
Figure 2-11 Recovery from Stop State Using IRQA Interrupt Service
MOTOROLA
DSP56167/D, Rev. 1
Y
AA0780
First Interrupt Instruction Fetch
First IRQA Interrupt Instruction Fetch
AA0782
2-11
Specifications RESET, Stop, Mode Select, and Interrupt Timing
CLKO (Output)
T0, T2
T1, T3 33
DR (Input)
DSO (Output)
AR
Figure 2-12 Recovery from Wait State Using DR--Synchronous Timing
33
DSO (Output)
IM
IN
32
AA0784
DR (Input)
Figure 2-13 Recovery from Wait/Stop State Using DR--Asynchronous Timing
PR
2-12
EL
DSP56167/D, Rev. 1 MOTOROLA
Y
AA0783
30
31
Specifications External Bus Synchronous Timing
EXTERNAL BUS SYNCHRONOUS TIMING
VDD = 5.0 V 10%; TJ = -40 to +115C; CL = 50 pF + 1 TTL load Capacitance Derating: The DSP56167 external bus timing specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the external bus pins (A0-A15, D0-D15, PS/DS, RD, WR, BS, PEREN) derates linearly at 1 ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C pins (HI, SSI, and Timer) derate linearly at 1 ns per 5 pF of additional capacitance from 50 pF to 250 pF of loading. When an internal memory access follows an external memory access, the PS/DS, R/W, RD, WR, BS, and PEREN strobes remain deasserted and A0-A15 do not change from their previous state. Table 2-8 External Bus Synchronous Timing
Num 34 35 Characteristics CLK in (EXTAL) High to CLKO High
AR
60 MHz Min 2.2 -- -- -- -- 14.6 T + 4.0 -- 6.5 6.5 2.0 2.0 -- 4.0 4.0 0.0 -- -- 1.0 1.0 -- 0 0 0 Max 10.0 4.0 4.0 4.0 4.0 -- T + 6.0 7.4 -- -- -- -- 4.0 -- -- -- 3.0 3.0 -- -- 8.0 -- -- --
CLKO High to a. A0-A15 Valid b. PS/DS, PEREN Assertion, R/W Valid c. BS Assertion d. RD Assertion BS Width Deassertion CLKO High to WR Assertion Low CLKO High to BS Deassertion
IN
DSP56167/D, Rev. 1
36 37 40 41 42
IM
a.TA Assertion to CLKO High (Setup) b.TA Deassertion to CLKO High (Setup) a. CLKO High to TA Assertion (Hold) b. CLKO High to TA Deassertion (Hold) CLKO High to D0-D15 Out Valid
EL
43 44 45 46 47
CLKO High to D0-D15 Out Invalid (Hold) D0-D15 In Valid to CLKO Low (Setup) CLKO Low to D0-D15 In Invalid (Hold) CLKO Low to a. WR Deassertion b. RD Deassertion
PR
48
a. WR Hold Time from CLKO Low b. RD Hold Time from CLKO Low CLKO High to D0-D15 tri-stated CLKO High to D0-D15 Out Active CLKO High to a. A0-A15 Invalid b. PS/DS, PEREN, R/W Invalid
49 50 51
MOTOROLA
Y
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2-13
Specifications External Bus Synchronous Timing
EXTAL (Input)
T0
T1
T2
T3
T0
T1
T2
T3
T0
34 CLKO (Output) A0-A15, PS/DS,R/W PEREN Note 1 35 51
35 BS (Output) 37 WR (Output) 35 RD (Output) 42
40
IM
41 43 44 Data Out 50 45 Data In
TA (Input)
EL
D0-D15 (Output) D0-D15 (Input) Note:
PR
During read-modify-write instructions and internal instructions, the address lines do not change state.
IN
47 48 47 48 41 46 49
AA0785
Figure 2-14 External Bus Synchronous Timing--No Wait States
2-14
DSP56167/D, Rev. 1
AR
MOTOROLA
36
Y
Specifications External Bus Synchronous Timing
EXTAL (Input)
T0
T1
T2
Tw
T2
Tw
T2
T3
T0
34 CLKO (Output) A0-A15, PS/DS,R/W PEREN Note 1 35 51
35 BS (Output) 37 WR (Output) 35 RD (Output) 41
IN
41 42 43 Data Out 45 50
IM
TA (Input)
EL
D0-D15 (Output) D0-D15 (Input)
PR
AR
40 47 48 47 48 42 49 44 46 Data In
AA0786
Figure 2-15 External Bus Synchronous Timing--Two Wait States
MOTOROLA
DSP56167/D, Rev. 1
Y
36
2-15
Specifications External Bus Asynchronous Timing
EXTERNAL BUS ASYNCHRONOUS TIMING
VDD = 5.0 V 10%; TJ = -40 to +115C; CL = 50 pF + 1 TTL load cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles WS = Number of Wait States, as determined by BCR (WS = 0 to 31) WT = WS x cyc = 2T x WS Table 2-9 External Bus Asynchronous Timing
No. 52 53 54 55 56 57 58 Characteristics WR and RD Deassertion High to BS Assertion Low (Two Successive Bus Cycles) Address Valid to WR Assertion WR Width Assertion
AR
14 -- 6.4 -- 12.5 3.3 -- -- 10.4 4.0 -- -- -- -- -- -- -- -- 22 WT + 3T - 5 2.0 -- -- -- -- -- 5.0 WT + T - 3.3 4.0 22.1 18 WT + 3T - 7 -- -- -- 18.6 6.8 8.5 13.1 16.0
WR Deassertion to R/W, Address Invalid WR Assertion to D0-D15 Out Valid
IN
DSP56167/D, Rev. 1
Data Out Hold Time from WR Deassertion
59 60 62
RD Deassertion to Address not valid Address valid to RD Deassertion RD Assertion width a. WS = 0 b. WS > 0
IM
Data Out Set up Time to WRDeassertion a. WS = 0 b. WS > 0
EL
63 64 Address valid to RD Assertion 65 66 WR Deassertion to RD Assertion RD Deassertion to RD Assertion 67 68 69
Address valid to input data valid a. WS = 0 b. WS > 0
PR
RD Assertion to input data valid
WR Deassertion to WR Assertion
RD Deassertion to WR Assertion
2-16
Y
60 MHz Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min Max
MOTOROLA
Specifications External Bus Asynchronous Timing
A0-A15, PS/DS, R/W PEREN 60 BS 64 RD 55 52 68 WR 56 58 D0-D15 Note: 54 66 62 67 59
53
During Read-Modify-Write instructions and internal instructions, the address lines do not change state.
AA0787
PR
MOTOROLA DSP56167/D, Rev. 1
EL
2-17
IM
Figure 2-16 External Bus Asynchronous Timing
IN
Data Out
AR
69 65 63 57 Data In
Y
52
Specifications Bus Arbitration Timing--Slave Mode
BUS ARBITRATION TIMING--SLAVE MODE
VDD = 5.0 V 10%; TJ = -40 to +115C; CL = 50 pF + 1 TTL load cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles WS = Number of Wait States for X or P external memory, determined by BCR or BCR2 (WS = 0 to 31) WT = WS x cyc = 2T x WS WX = Number of Wait States for X external memory, determined by BCR or BCR2 (WS = 0 to 31) WP = Number of Wait States for P external memory, determined by BCR (WS = 0 to 31) Table 2-10 Slave Mode Bus Arbitration Timing
No. Characteristics
AR
60 MHz Min 2.8 Max -- 25 5T + 6.6 3T + 6.6 5T + 6.6 -- T+6.6 -- 5T + 3.7 5T + 3.7 5T + 3.4 -- 2T + 3.3 3T + 3.4 -- 7.0 -- -- -- 1.0 -- 1.0 -- -- 9T +3.1 9T+WT+3.1 26T+ 4T x WX + 2T x WP + 2.7 -- 3T + 2.7 10.2 -- -- -- -- -- -- 8.0 -- 18.0 8.5 15.0 -- 9.4 -- 9.7
70 BR Input to CLKO low setup time
72 CLKO high to BG Output Assertion
IM
Stop mode--external bus released and BG asserted Wait mode
IN
DSP56167/D, Rev. 1
71 Delay from BR Input Assertion to BG Output Assertion No external access by the DSP External read or write access External read-modify-write access
EL
78 CLKO High to BG Deassertion 79 CLKO High to BB Output Active 80 CLKO High to BB Output Assertion
73 BG Output Deassertion duration for two consecutive BR No external access by the DSP External read or write access External read-modify-write access Stop mode--external bus released and BG asserted Wait mode External DSP accesses pending 74 CLKO High to Control Bus high impedance 75 CLKO High to BB Output Deassertion
PR
76 CLKO High to BB Output (tri-stated) 77 BR Input Deassertion to BG Output Deassertion
81 CLKO High to Address and Control Bus Active 82 CLKO High to Address and Control Bus Valid
2-18
Y
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MOTOROLA
Specifications Bus Arbitration Timing--Slave Mode
Table 2-10 Slave Mode Bus Arbitration Timing (Continued)
60 MHz No. Characteristics Min 83 BR Assertion to BB Deassertion No external access by the DSP External read or write access External read-modify-write access Stop mode--external bus released and BG asserted Wait mode 84 BR Assertion to Address/Data/Control lines tri-stated No external access by the DSP External read or write access External read-modify-write access Max 9T + 3.1 9T + WT + 3.1 26T + 4T x WX + 2T x WP + 2.7 -- 3T + 2.7 9T + 8.0 9T + WT + 8.0 26T + 4T x WX + 2T x WP + 2.7 -- 3T + 2.7 ns ns ns ns ns ns ns ns Unit
PR
MOTOROLA DSP56167/D, Rev. 1
EL
2-19
IM
IN
Stop mode--external bus released and BG asserted Wait mode
AR
Y
Specifications Bus Arbitration Timing--Slave Mode
CLKO (Output) 70 BR (Input) 72 BG (Output) 73 71
BB (I/O)
D0-D15
IM
IN
74 84 74
AA0788
A0-A15, PS/DS R/W PEREN
Figure 2-17 External Bus Arbitration Bus Release Timing--Slave Mode
PR
2-20 DSP56167/D, Rev. 1 MOTOROLA
EL
AR
75 83 76 84
Y
Specifications Bus Arbitration Timing--Slave Mode
CLKO (Output) 70 BR (Input) 77 BG (Output) BB (I/O) 78
IN
DSP56167/D, Rev. 1
A0-A15, PS/DS R/W PEREN
AR
79 80 82 80
AA0789
Figure 2-18 External Bus Arbitration Bus Acquisition Timing--Slave Mode
PR
MOTOROLA
EL
2-21
IM
Y
Specifications Bus Arbitration Timing--Master Mode
BUS ARBITRATION TIMING--MASTER MODE
VDD = 5.0 V 10%; TJ = -40 to +115C; CL = 50 pF + 1 TTL load Table 2-11 Master Mode Bus Arbitration Timing
60 MHz No. 85 86 87 88 89 90 91 Characteristics CLKO high to BR Output Valid BG Input Valid to CLKO Low (Setup) Unit ns
AR
1.9 -- 2.0 -- 2.0 -- 2.0 -- -- 11.4 -- -- -- 48.3 64.9 -- -- -- -- -- -- -- -- 3 -- -- -- -- -- -- 53.3 69.9 -- --
CLKO Low to BG Input Deassertion (Hold)
BB Input Deassertion to CLKO Low (Setup) CLKO Low to BB Input Deassertion (Hold) CLKO High to BB Output Assertion CLKO Low to BG Input Assertion No external access by the DSP External read or write access
IN
DSP56167/D, Rev. 1
92
93
PR
2-22
EL
BG Deassertion to Address/Data/Control lines tri-stated No external access by the DSP External read or write access External read-modify-write-access Stop mode - external bus released and BG asserted Wait mode
IM
BG Deassertion to BB Deassertion No external access by the DSP External read or write access External read-modify-write-access Stop mode - external bus released and BG asserted Wait mode
Y
Min -- Max 9.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MOTOROLA
Specifications Bus Arbitration Timing--Master Mode
CLKO (Output) 85 BR (Output) 87 BG (Input) 86 88 BB (I/O) 89 A0-A15, PS/DS R/W PEREN
IN
81 91 75 92
AR
Tri-state 90 82
AA0790
Figure 2-19 External Bus Arbitration Bus Acquisition Timing--Master Mode
IM
86
CLKO (Output)
BR (Output)
PR
BB (I/O) A0-A15, D0-D15, PS/DS, BS, R/W, RD, WR, PEREN
EL
BG (Input)
Output
76 93
Figure 2-20 External Bus Arbitration Bus Release Timing--Master Mode
MOTOROLA
DSP56167/D, Rev. 1
Y
85 74
AA0791
2-23
Specifications Host I/O (HI) Timing
HOST I/O (HI) TIMING
VDD = 5.0 V 10%; TJ = -40 to +115C; CL = 50 pF + 1 TTL load T = ICYC / 4 cyc = Clock cycle = 1/2 Instruction cycle = 2 T cycle tHSDL = Host Synchronization Time Delay tSUH = Host processor data setup time Note: Active low lines should be "pulled up" in a manner consistent with the AC and DC specifications. Table 2-12 Host I/O Timing
Num 100 101 Characteristics Host Synchronous Delay1 HEN/HACK assertion width a. CVR,ICR, ISR Read2,4 b. Read c. Write
AR
Min T Max 3T -- -- -- 2T + 30 25 27 27 4T + 30 3 9 -- -- -- 5 4 4 4 3 0 6 6 tHSDL + 3T + 4 tHSDL + 2T + 4 4 -- -- -- -- 24 24 17 -- -- -- -- -- -- -- 2T + 35 -- -- --
102 103 104 105 106 107 108 109
HEN/HACK deassertion width2
IN
assertion3
Minimum cycle time between two HEN assertions for Consecutive CVR, ICR, ISR reads
Host data input setup time before HEN/HACK deassertion Host data input hold time after HEN/HACK deassertion HEN/HACK assertion to output data active from tri-state HEN/HACK assertion to output data valid
IM
EL
110 111 112 113 114 115 116 117
HEN/HACK deassertion to output data tri-stated Output data hold time after HEN/HACK deassertion
HR/W low setup time before HEN assertion
HR/W low hold time after HEN deassertion HR/W high setup time to HEN assertion HR/W high hold time after HEN/HACK deassertion
PR
HA0-HA2 setup time before HEN assertion HA0-HA2 hold time after HEN deassertion
DMA HACK assertion to HREQ deassertion3 DMA HACK deassertion to HREQ for DMA RXL Read for DMA TXL Write for All Other Cases
2-24
DSP56167/D, Rev. 1
Y
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MOTOROLA
Specifications Host I/O (HI) Timing
Table 2-12 Host I/O Timing (Continued)
Num 118 119 120
Note:
Characteristics Delay from HEN deassertion to HREQ assertion for RXL read3 Delay from HEN deassertion to HREQ assertion for TXL write3 Delay from HEN assertion to HREQ deassertion for RXL read, TXL write3
1.
Min tHSDL + 3T + 4 tHSDL + 2T + 4 13.7
Max -- -- 2T + 16.4
Unit ns ns ns
2. 3. 4.
External 100 Internal
IN
103 101 102 113 107 Data Valid 108 109
IM
112 106
AR
100
"Host synchronization delay (tHSDL)" is the time period required for the DSP56167 to sample any external asynchronous input signal, determine whether it is high or low, and synchronize it to the internal clock. See Host Port Considerations in the section on Design Considerations. HREQ is pulled up by 1 k. Only if two consecutive reads from one of these registers are executed
Figure 2-21 Host Synchronization Delay
HREQ (Output)
PR
EL
HACK (Input) HR/W (Input) H0-H7 (Output)
Figure 2-22 Host Interrupt Vector Register (IVR) Read
MOTOROLA
DSP56167/D, Rev. 1
Y
AA0792 AA0793
2-25
Specifications Host I/O (HI) Timing
120 HREQ (Output) 103 HEN (Input) 114 HA2-HA0 (Input) Address Valid 112 HR/W (Input) 107 106 H0-H7 (Output) Data Valid 108 113 RXH Read 101 102 115 Address Valid 118 RXL Read
IN
Data Valid 120 119 TXL Write 115 Address Valid 111 102 105 Data Valid
AR
109 Data Valid
AA0794
Figure 2-23 Host Read Cycle (Non-DMA Mode)
HREQ (Output)
EL
101 114 HA2-HA0 (Input) Address Valid 110 HR/W (Input) 104 Data Valid H0-H7 (Input)
HEN (Input)
IM
103 TXH Write
PR
Figure 2-24 Host Write Cycle (Non-DMA Mode)
2-26
DSP56167/D, Rev. 1
Y
Address Valid Address Valid Data Valid
AA0795
MOTOROLA
Specifications Host I/O (HI) Timing
HREQ (Output) 116 101 HACK (Input) 106 H0-H7 (Output) Data Valid RXH Read 107 108 109 Data Valid 102 RXL Read 117
AR
TXL Write Data Valid Data Valid
Figure 2-25 Host DMA Read Cycle
HREQ (Output) 116 101 HACK (Input) TXH Write 104 102
H0-H7 (Input)
IM
Data Valid
IN
117 105
AA0797
Figure 2-26 Host DMA Write Cycle
PR
MOTOROLA
EL
DSP56167/D, Rev. 1 2-27
Y
Data Valid
AA0796
Specifications Codec Analog I/O Characteristics
CODEC ANALOG I/O CHARACTERISTICS
VDDA = 5.0 V 10%; TJ = -40 to +115C Table 2-13 Codec Analog I/O Characteristics
Characteristic Input impedance of MIC and AUX when selected as the A/D input: -6 dB, MGS[1:0] = 00 0 dB, MGS[1:0] = 01 6 dB, MGS[1:0] = 10 17 dB, MGS[1:0] = 11 Input impedance of MIC and AUX when not selected as the A/D input Min Typ Max Unit
AR
100 -- 140 24 -- -- -- -- 10 -- -- -- -- -- -- -- -- G 1.414 0.707 0.354 0.100 G + 0.83 G - 0.92 G - 1.49 G G + 1.27 G - 1.39 G G + 1.20 -- 2.500 0.010 -- 42.5 2.500 0.005 -- -- 2.500 0.050 350 -- 2.500 0.025 50 100 -- -- -- -- --
60 45 30 30
Maximum source or sink current of MIC or AUX when not selected as the A/D input Input capacitance on MIC and AUX
Absolute gain variation due to VDDA variation for all A/D and D/A gain settings (0.83 dB due to 10% variation on VDDA) A/D absolute gain variation due to internal circuitry for all A/D gain settings (variation from ideal VRAD of 0.5 VDDA)
IM
Peak input voltage on the MIC/AUX input for full scale linearity at VDDA = 5.000 V: -6 dB, MGS[1:0] = 00 0 dB 1, MGS[1:0] = 01 6 dB, MGS[1:0] = 10 17 dB, MGS[1:0] = 11
IN
DSP56167/D, Rev. 1
EL
VDIV AC input impedance
D/A absolute gain variation due to internal circuitry for all D/A gain settings (variation from ideal VRDA of 0.5 VDDA) VRDA and VRAD output voltage plus offset (assumes no leakage current on the VDIV pin and VDDA = 5.000 V) SPKP, SPKM, VRDA, and VRAD output current VDIV I/O voltage plus offset (assumes there is not leakage current on the I/O and VDDA = 5.000 V)
PR
Differential DC offset between SPKP and SPKM Single-ended DC offset of SPKP and SPKM with respect to VRDA
2-28
Y
100 75 50 50 140 105 70 70 k k k k k A pF VP VP VP VP dB dB dB V A k V mV mV
MOTOROLA
Specifications Codec Analog I/O Characteristics
Table 2-13 Codec Analog I/O Characteristics (Continued)
Characteristic A/D output DC offset (assuming input is at VRAD): -6 dB, MGS[1:0] = 00 0 dB, MGS[1:0] = 01 6 dB, MGS[1:0] = 10 17 dB, MGS[1:0] = 11 Allowable differential load capacitance between SPKP and SPKM (with 3 k in series, 4 kHz maximum frequency) Min Typ Max Unit
--
AR
-- -- 30 -- -- 50 -- -- 25 -- -- -- -- -- -- -- -- -- -- 0.125 0.223 0.397 0.707 1.000 -- -- -- -- -- 2.8 5.6 -- 140 -- -- -- -- -- -- -- -- 50 200 -- 0.250 0.446 0.794 1.414 2.000 -- -- -- 280 15
Allowable single-ended load capacitance on SPKP and SPKM (with 1.5 k in series, 4 kHz maximum frequency)2 Allowable single-ended shunt capacitance to ground Allowable differential shunt capacitance Maximum linear range of single-ended signal output level at VDDA = 5.000 V: -15 dB, VC[3:0] = 0000 -10 dB, VC[3:0] = 0001 -5 dB, VC[3:0] = 0010 0 dB3, VC[3:0] = 0011 5-40 dB, VC[3:0] > 0011 Maximum linear range of single-ended signal output level at VDDA = 5.000 V: -15 dB, VC[3:0] = 0000 -10 dB, VC[3:0] = 0001 -5 dB, VC[3:0] = 0010 0 dB3, VC[3:0] = 0011 5-40 dB, VC[3:0] > 0011 Single-ended load resistance (referenced from 0.5 VDDA) Differential load resistance
IN
DSP56167/D, Rev. 1
IM
EL PR
Output impedance of SPKP and SPKM at 0 Hz to 4 kHz
Note: 1. 2. 3. 4.
Output impedance of SPKP and SPKM during power down Output transition time of SPKP and SPKM from codec power up condition4
0 dBm0 corresponds to 3.00 dB below the input saturation level of 1.0 VP with VDDA = 5.0 V. AC coupling is necessary in Single-Ended mode when the load resistor is not tied to VRDA. 0 dBm0 corresponds to 3.00 dB below the output saturation level of 1.0 VP single-ended with VDDA = 5.0 V. During power down and during the first 15 s after a power up event, the maximum current loading for SPKP and SPKM pins is 1.0 A.
MOTOROLA
Y
-- 15 nF nF pF pF VP VP VP VP VP VP VP VP VP VP k k k s
$FF00 $FE00 $FC00 $F800
$0000 $0000 $0000 $0000
$0100 $0200 $0400 $0800
2-29
Specifications Codec A/D and D/A Performance
CODEC A/D AND D/A PERFORMANCE
VDDA = 5.0 V 10%; TJ = -40 to +115C Table 2-14 Codec Performance Levels
Characteristic A/D Signal-to-Noise plus distortion ratio S /( N + THD) D/A Signal-to-Noise plus distortion ratio S / (N + THD)
Note: 1. 2.
0 dBm0 -50 dBm0 0 dB -50 dB
55 15 55 15
AR
60 15 -- --
-47.8 -35.84 -38.85 -41.85 -44.85 -50.81 -53.77 -56.76 59.76 -62.83 -65.67 -68.79 -71.91 -74.58
80
S/N
70
60 50
40 30 20 10
PR
0
-2.86
-5.85
-8.84
-11.85
-14.85
-17.85
-20.86
-23.86
-26.85
EL
0
-29.89
-32.85
IM
Input Signal in dB S in dB
AA0900
S/(N+THD)
dB
IN
DSP56167/D, Rev. 1
0 dB gain on the A/D and D/A; codec clock at 2.048 MHz with 128 decimation/interpolation ratio 0 dBm0 corresponds to 3.00 dB below the input saturation level of 1.0 VP single-ended with VDDA = 5.0 V.
Figure 2-27 An Example of S/N and S/(N + THD) Performance for the Codec A/D Section
2-30
MOTOROLA
-77.91
Y
65 20 -- -- dB dB dB dB
Input Signal Level
Min.
Typical1
Max.
Unit
Specifications Other On-Chip Codec Characteristics
OTHER ON-CHIP CODEC CHARACTERISTICS
VDD = 5.0 V 10%; TJ = -40 to +115C; CL = 50 pF + 1 TTL load Table 2-15 Codec I/O Device Characteristics
Characteristic Codec master clock Codec sampling rate A/D section group delay D/A section group delay Min. 1 7812 0.06 0.07 Typical 2.048 0.17 0.17 Max. 3 Unit MHz Hz ms ms
16000
PR
MOTOROLA DSP56167/D, Rev. 1
EL
2-31
IM
IN
AR
0.37
Y
46150 0.40
Specifications 16-Bit Synchronous Serial Interface (SSI) Timing
16-BIT SYNCHRONOUS SERIAL INTERFACE (SSI) TIMING
VDD = 5.0 V 10%; TJ = -40 to +115C; CL = 50 pF + 1 TTL load T = ICYC / 4 SCK = Serial Clock SFS = Transmit/Receive Frame Sync i ck = Internal Clock and Frame Sync x ck = External Clock and Frame Sync bl = bit length wl = word length TS = SCK/2
Note: All the timings for the 16-bit SSI are given for a non-inverted serial clock polarity (SCKP = 0 in CRB) and a non-inverted frame sync (FSI = 0 in CRB). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal SCK and/or the frame sync SFS in the tables and in the figures.
Num 134 135 136 137 138 139 140 141 142 143 144 145 146 150 153 154 155
Characteristics
IN
Table 2-16 SSI Timing
Min -- 16.7 -- -- 3.0 8.5 -- -- -- -- -- -- -- 27 -- -- 6
AR
60 MHz Case Max 20.4 -- 20.4 TS x 2 -- -- 21 16.0 20.4 1.2 10 16.7 16.7 -- 10 3.3 -- i ck i ck i ck i ck i ck i ck i ck i ck i ck i ck i ck i ck i ck x ck x ck x ck x ck
SCK Rising Edge to SFS In (bl) Low
IM
DSP56167/D, Rev. 1
SCK Rising Edge to SFS In (bl) High
SCK Rising Edge to SFS In (wl) High SCK Rising Edge to SFS In (wl) Low
Data In Setup Time Before SCK Falling Edge Data In Hold Time After SCK Falling Edge SCK Rising Edge to SFS Out (bl) High SCK Rising Edge to SFS Out (wl) High SCK Rising Edge to SFS Out Low
EL
SCK Clock Cycle1 SCK Clock Rise/Fall Time
PR
SCK Rising Edge to Data Out Enable from High Impedance SCK Rising Edge to Data Out Valid SCK Rising Edge to Data Out Invalid SCK Rising Edge to Data Out High Impedance
SCK Rising Edge to SFS Out (bl) High SCK Rising Edge to SFS Out (bl) Low
2-32
Y
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MOTOROLA
Specifications 16-Bit Synchronous Serial Interface (SSI) Timing
Table 2-16 SSI Timing (Continued)
60 MHz Num 156 157 158 159 160 161 162 163 164 165 166
Note:
Characteristics Min SCK Rising Edge to SFS Out (wl) High SCK Rising Edge to SFS Out (wl) Low Data In Setup Time Before SCK Falling Edge Data In Hold Time After SCK Falling Edge SCK Rising Edge to SFS In (bl) High SCK Rising Edge to SFS In (bl) Low SCK Rising Edge to SFS In (wl) High -- -- 7 13.2 -- -- -- Max 20.5 35.0 -- -- 26.1 30
Case x ck x ck x ck x ck x ck
Unit ns ns ns ns ns ns ns ns ns ns ns
SCK Rising Edge to Data Out Enable from High Impedance SCK Rising Edge to Data Out Valid SCK Rising Edge to Data Out Invalid
1.
SCK Rising Edge to Data Out High Impedance
IN
--
For internal clock, External Clock Cycle is defined by Icyc and SSI Control Register.
PR
MOTOROLA DSP56167/D, Rev. 1
EL
2-33
IM
AR
x ck -- 7.5 x ck -- 20.5 x ck -- 10.4 x ck 19.7 x ck
Y
13.0 x ck
Specifications 16-Bit Synchronous Serial Interface (SSI) Timing
SCK Continuous (Output)
134 SFS (Bit Early) (Input) 136 SFS (Word Early) (Input) 134 SFS (Bit) (Input) 136 SFS (Word) (Input) 143
135
IN
138 142 139 142 142
STD (Output)
IM
144 141 140 141
SRD (Input)
PR
SFS (Word Early) (Output) SFS (Bit) (Output) SFS (Word) (Output)
EL
140 SFS (Bit Early) (Output)
AR
137 135 137 146 145 142
AA0801
Figure 2-28 SSI Internal Clock Timing
2-34
DSP56167/D, Rev. 1
Y
MOTOROLA
SCK Gated (Output)
Specifications 16-Bit Synchronous Serial Interface (SSI) Timing
150 SCK Continuous (Input) 153
154 SFS (Bit Early) (Output) 156 SFS (Word Early) (Output) 154 SFS (Bit) (Output) 156 SFS (Word) (Output) 163
155
IN
158 162 159 162 162
STD (Output)
IM
164 161 160 161
SRD (Input)
PR
SFS (Word Early) (Input) SFS (Bit) (Input) SFS (Word) (Input)
EL
160 SFS (Bit Early) (Input)
AR
157 155 157 166 165 162
AA0802
Figure 2-29 SSI External Clock Timing
MOTOROLA
DSP56167/D, Rev. 1
Y
2-35
SCK Gated (Input)
Specifications Timer Timing
TIMER TIMING
VDD = 5.0 V 10%; TJ = -40 to +115C; CL = 50 pF + 1 TTL load Table 2-17 Timer Timing (60 MHz)
Num 170 171 172 173 174 175 Characteristics TIN Valid to CLKO low (Setup time) CLKO Low to TIN Invalid (Hold time) CLKO High to TOUT Asserted CLKO High to TOUT Deasserted Tin Period Tin High/Low Period Min 8 0 3.5 0 8T Max -- 8.0 -- 14.0 -- Unit ns ns ns
AR
4T -- 172 173
170 TIN (Input) TOUT (Output)
IM
IN
171
CLKO (Output)
Figure 2-30 Timer Timing
PR
2-36
EL
DSP56167/D, Rev. 1 MOTOROLA
Y
ns ns ns
AA0803
Specifications GPIO Timing
GPIO TIMING
VDD = 5.0 V 10%; TJ = -40 to +115C; CL = 50 pF + 1 TTL load Table 2-18 GPIO Timing
Num 201 202 203 204 Characteristics CLKO edge to GPIO output valid (GPIO output delay time) Min -- 0 Max 19.7 -- Unit ns
CLKO edge to GPIO output not valid (GPIO output hold time) GPIO input valid to CLKO edge (GPIO input setup time)
CLKO edge to GPIO input not valid (GPIO input hold time)
AR
4.0 -- 201 202
CLKO (Output)
GPIO (Output) 203
GPIO (Input)
IM
Valid
IN
204
Figure 2-31 GPIO Timing
PR
MOTOROLA
EL
DSP56167/D, Rev. 1 2-37
Y
ns 10.0 -- ns ns
AA0804
Specifications OnCE Port Timing
OnCE PORT TIMING
VDD = 5.0 V 10%; TJ = -40 to +115C; CL = 50 pF + 1 TTL load Table 2-19 OnCE Port Timing
Num 180 181 182 183 184 185 186 187 188 Characteristics DSCK High to DSO Valid DSI valid to DSCK low (setup) DSCK low to DSI invalid (hold) DSCK high1 DSCK low1 DSCK cycle time1 CLKO high to OS0-OS1 valid CLKO high to OS0-OS1 invalid OS0-OS12 Min -- Max 27.6 -- Unit ns
AR
33 -- 2TC 4TC -- -- -- -- 14.5 21.7 -- -- -- -- -- -- -- -- -- 10T + TD +14.5 10T + TD +13.5 21T + TD +13.5 3TC 34 51 6TC 7 19.4 184 183 185
Last DSCK high to Last DSCK high to ACK active (data)2 Last DSCK high to ACK active (command)2 DSO (ACK) asserted to first DSCK high
IN
DSP56167/D, Rev. 1
190 191
IM
DSO (ACK) width asserted: a. when entering Debug mode b. when acknowledging command/data transfer Last DSCK low of read register to first DSCK high of next command DSCK high to DSO invalid2
192 193
EL
194
Note: 1. 2.
DR asserted to DSO (ACK) asserted
45-55% duty cycle TD = DSCK high (timing number 183)
PR
DSCK (Input)
Figure 2-32 OnCE Serial Clock Timing
2-38
Y
15 5 ns -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
AA0805
MOTOROLA
Specifications OnCE Port Timing
DR (Input) 194 DSO (Output) (ACK)
AA0806
Figure 2-33 OnCE Acknowledge Timing
DSCK (Input) 180 DSO (Output) DSI (Input) 181 Note: (Last)
1. Tri-state, external pull-down resistor
IN
182 190 180 181 182
AR
193 Note 1 (ACK) (OS0) 188
AA0807
OS1 (Output)
IM
191
Figure 2-34 OnCE Data I/O To Status Timing
EL
DSO (Output) OS0 (Output)
(DSCK Input)
(DSO Output)
PR
Note 1: Tri-stated, external pull-down resistor
AA0808
Figure 2-35 OnCE Data I/O To Status Timing
MOTOROLA
DSP56167/D, Rev. 1
Y
(OS1) (DSI Input)
2-39
Specifications OnCE Port Timing
239 OS1 (Output) 241 240 DSO (Output) (See Note) (DSCK Input)
(DSO Output)
241
Note:
High Impedance, external pull-down resistor
AR
(See Note) 236 237 192
OS0 (Output)
Figure 2-36 OnCE Data I/O To Status Timing
CLKO (Output) OS0-1 (Output)
IM
187 186 (Read Register)
IN
AA0809
Figure 2-37 OnCE Clock to Status Timing
EL
DSCK (Input)
PR
Figure 2-38 OnCE DSCK Next Command After Read Register Timing
2-40
DSP56167/D, Rev. 1
Y
(DSI Input)
AA0503
(Next Command)
AA0810
MOTOROLA
SECTION PACKAGING
PIN-OUT AND PACKAGE INFORMATION
3
PR
MOTOROLA DSP56167/D, Rev. 1
EL
3-1
IM
IN
AR
Top and bottom views of the TQFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs.
Y
Packaging Pin-out and Package Information
IM
MIC AUX VRAD BG VDDQ BR BB VDDC WR VSSC RD PS/DS BS R/W DSO DSCK/OS1 DSI/OS0 CLKO VSSQ VSSS SXFC VDDS EXTAL SFS1/PC9 VSSPB PEREN SCK1/PC7 H7/PB7
VSSA/D D2 D3 VDDA/D D4 D5 VSSA/D D6 D7 D8 D9 VSSA/D D10 D11 VDDA/D D12 D13 VSSA/D D14 D15 TA DR VDDA SPKP SPKM VSSA VDIV VRDA
1 Orientation Mark
85
D1 D0 A15 A14 VSSA/D A13 A12 A11 VSSQ VDDA/D A10 VSSA/D A9 A8 A7 A6 VDDQ VSSA/D A5 A4 VDDA/D A3 A2 VSSA/D A1 A0 MODC/IRQC MODB/IRQB
(Top View)
PR
Note:
EL
3-2
An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
AA0811
Figure 3-1 Top View of the 112-pin Plastic (FV) Thin Quad Flat Package
29
57
MODA/IRQA RESET STD0/PC0 SRD0/PC1 SCK0/PC2 VSSPC SFS0/PC4 TIN/PC10 VDDPC TOUT/PC11 HA0/PB8 VSSPC HA1/PB9 HA2/PB10 HR/W/PB11 HEN/PB12 HACK/PB14 HREQ/PB13 H0/PB0 H1/PB1 STD1/PC5 SRD1/PC6 H4/PB4 H3/PB3 H2/PB2 VDDPB H5/PB5 H6/PB6
IN
DSP56167/D, Rev. 1
AR
Y
MOTOROLA
Packaging Pin-out and Package Information
85
MODB/IRQB MODC/IRQC A0 A1 VSSA/D A2 A3 VDDA/D A4 A5 VSSA/D VDDQ A6 A7 A8 A9 VSSA/D A10 VDDA/D VSSQ A11 A12 A13 VSSA/D A14 A15 D0 D1 MODA/IRQA RESET STD0/PC0 SRD0/PC1 SCK0/PC2 VSSPC SFS0/PC4 TIN/PC10 VDDPC TOUT/PC11 HA0/PB8 VSSPC HA1/PB9 HA2/PB10 HR/W/PB11 HEN/PB12 HACK/PB14 HREQ/PB13 H0/PB0 H1/PB1 STD1/PC5 SRD1/PC6 H4/PB4 H3/PB3 H2/PB2 VDDPB H5/PB5 H6/PB6
1 Orientation Mark (on Top side)
(Bottom View)
IM
57
VSSA/D D2 D3 VDDA/D D4 D5 VSSA/D D6 D7 D8 D9 VSSA/D D10 D11 VDDA/D D12 D13 VSSA/D D14 D15 TA DR VDDA SPKP SPKM VSSA VDIV VRDA
IN
H7/PB7 SCK1/PC7 PEREN VSSPB SFS1/PC9 EXTAL VDDS SXFC VSSS VSSQ CLKO DSI/OS0 DSCK/OS1 DSO R/W BS PS/DS RD VSSC WR VDDC BB BR VDDQ BG VRAD AUX MIC
PR
Note:
EL
MOTOROLA
An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
AA0812
Figure 3-2 Bottom View of the112-pin Plastic (FV) Thin Quad Flat Package
DSP56167/D, Rev. 1
29
AR
Y
3-3
Packaging Pin-out and Package Information
The DSP56167 signals that may be programmed as General Purpose I/O are listed with their primary function in Table 3-1. Table 3-1 DSP56167 General Purpose I/O Pin Identification
Pin Number 66 65 60 61 62 58 57 56 74 72 71 70 69 67 68 82 81 80 78 64 63 55 52 77 75 Primary Function H0 H1 H2 H3 H4 H5 H6 H7 Port B GPIO ID PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 C PC0 PC1 PC2 PC4 PC5 PC6 PC7 PC9 PC10 PC11
EL
3-4
PR
IM
HEN HREQ HACK STD0 SRD0 SCK0 SFS0 STD1 SRD1 SCK1 SFS1 TIN TOUT
IN
HA0 HA1 HA2 HR/W
DSP56167/D, Rev. 1
AR
MOTOROLA
Y
Packaging Pin-out and Package Information
Table 3-2 DSP56167 Signal Identification by Pin Number
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Signal Name VSSA/D D2 D3 VDDA/D D4 D5 VSSA/D D6 D7 D8 D9 VSSA/D D10 D11 Pin No. 26 27 28 29 30 31 32 33 34 35 Signal Name VSSA VDIV VRDA MIC AUX VRAD BG Pin No. 51 52 53 54 Signal Name EXTAL SFS1/PC9 VSSPB
55 56
IN
36 VDDC WR 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 37 38 39 VSSC RD 40 PS/DS BS 41 42 R/W DSO 43 44 DSCK/OS1 DSI/OS0 CLKO VSSQ VSSS SXFC
VDDS
IM
VDDA/D D12 D13 VSSA/D D14 D15 TA 45 46 47 48 49 50 DR VDDA SPKP SPKM
EL
20 21
PR
22 23 24 25
MOTOROLA
DSP56167/D, Rev. 1
AR
H7/PB7 57 58 59 60 H6/PB6 H5/PB5 VDDPB VDDQ BR BB H2/PB2 H3/PB3 H4/PB4 SRD1/PC6 STD1/PC5 H1/PB1 H0/PB0 HREQ/PB13 HACK/PB14 HEN/PB12 HR/W/PB11 HA2/PB10 HA1/PB9 VSSPC HA0/PB8 TOUT/PC11
Y
PEREN SCK1/PC7
3-5
Packaging Pin-out and Package Information
Table 3-2 DSP56167 Signal Identification by Pin Number (Continued)
Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 Signal Name VDDPC TIN/PC10 SFS0/PC4 VSSPC SCK0/PC2 SRD0/PC1 STD0/PC0 RESET MODA/IRQA MODB/IRQB MODC/IRQC A0 A1 Pin No. 89 90 91 92 93 94 95 96 97 98 99 Signal Name VSSA/D A2 A3 VDDA/D A4 A5 Pin No. 102 103 104 105 Signal Name A10 VDDA/D VSSQ A11
IN
A8 A9 112 100 101 VSSA/D
PR
3-6 DSP56167/D, Rev. 1 MOTOROLA
EL
IM
AR
VSSA/D VDDQ A6 A7 108 109 VSSA/D A14 110 111 A15 D0 D1
Y
106 A12 107 A13
Packaging Pin-out and Package Information
Power and ground pins have special considerations for noise immunity. See the section Design Considerations. Table 3-3 DSP56167 Power Supply Pins
Pin Number 23 26 92 103 89 95 101 108 4 15 1 7 12 18 36 38 Power Supply VDDA VSSA VDDA/D Circuit Supplied Codec
VSSA/D
IN
VDDA/D VSSA/D VDDC VSSC VDDPB VSSPB VDDPC VSSPC VDDQ VSSQ VDDS VSSS
IM
DSP56167/D, Rev. 1
EL
59 53 76 73
PR
79 33 96 47 104 50 48
MOTOROLA
AR
Data Bus Buffers Bus Control Buffers Port B/Host Interface Buffers Port C/SSI and Timer Buffers Internal Logic PLL and Clock
Y
Address Bus Buffers
3-7
Packaging Pin-out and Package Information
4X PIN 1 IDENT 1
0.20 T L-M N
112
4X 28 TIPS 85 84
0.20 T L-M N
J1 J1
4X
P
C L X X=L, M OR N
VIEW Y
108X
G
B
V
L
M B1 V1
28
57
AR
F D 0.13 M T L-M N SECTION J1-J1
29
56
N A1 S1 A S
C2 C
0.050
IM
2 3
R
IN
NOTES:
VIEW AB 0.10 T
112X SEATING PLANE
1.Dimensioning and tolerancing per ASME Y14.5M-1994. 2.Dimensions in millimeters. 3.Datums L, M and N to be determined at the seating plane. Datum T. 4.Dimensions S and V to be determined at seating plane. Datum T. 5.Dimensions A and B do not include mold protrusion. Allowable protrusion is 0.25 per side. Dimensions A and B include mold mismatch. 6.Dimension D does not include dambar protrusion. Allowable dambar protrusion shall not cause the "D" dimension to exceed 0.46 .
EL
R2
R
T
PR
R1
0.25
GAGE PLANE
C1
(K) E (Y) (Z)
1
VIEW AB
CASE 987-01 ISSUE A
Figure 3-3 112-pin Thin Plastic Quad Flat Pack (TQFP) Mechanical Information
3-8
DSP56167/D, Rev. 1
Y
J AA
BASE METAL ROTATED 90 COUNTERCLOCKWISE DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3 MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 0 8 3 7 11 13 11 13
VIEW Y
MOTOROLA
Packaging Ordering Drawings
ORDERING DRAWINGS
Complete mechanical information regarding DSP56167 packaging is available by facsimile through Motorola's MfaxTM system. Call the following number to obtain information by facsimile:
(602) 244-6591
The Mfax automated system requests the following information: * *
The receiving facsimile telephone number including area code or country code The caller's Personal Identification Number (PIN)
Note: For first time callers, the system provides instructions for setting up a PIN, which requires entry of a name and telephone number. * The type of information requested: - - - -
Instructions for using the system A literature order form
A total of three documents may be ordered per call. The DSP56167 112-pin TQFP package mechanical drawing is referenced as 987-01.
PR
MOTOROLA DSP56167/D, Rev. 1
EL
3-9
IM
Specific part technical information or data sheets Other information described by the system messages
IN
AR
Y
Packaging Ordering Drawings
PR
3-10 DSP56167/D, Rev. 1 MOTOROLA
EL
IM
IN
AR
Y
SECTION
4
DESIGN CONSIDERATIONS
HEAT DISSIPATION
Equation 1: T J = T A + ( P D x R JA ) Where:
TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: R JA = R JC + R CA Where:
PR
MOTOROLA
EL
RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or otherwise change the thermal dissipation capability of the area surrounding the device on a printed circuit board. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the printed circuit board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool.
IM
IN
DSP56167/D, Rev. 1
AR
An estimation of the chip junction temperature, TJ, in C can be obtained from the equation:
Y
4-1
Design Considerations Heat Dissipation
The thermal performance of plastic packages is more dependent on the temperature of the Printed Circuit Board (PCB) to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages:
*
To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ - TT)/PD.
*
PR
4-2
EL
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, Thermal Characterization Parameter or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface, and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. Note: Table 2-2 Recommended Operating Conditions on page 2-2 contains the package thermal values for this chip.
IM
IN
DSP56167/D, Rev. 1
AR
Y
MOTOROLA
*
To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink.
Design Considerations Electrical Design Considerations
ELECTRICAL DESIGN CONSIDERATIONS
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or VDD).
Use the following list of recommendations to assure correct DSP operation: * * * Provide a low-impedance path from the board power supply to each VDD pin on the DSP. Provide a low-impedance path from the board ground to each VSS pin. Use at least six 0.01-0.1 F bypass capacitors, positioned as close as possible to the four sides of the package, to connect between the VDD power source and VSS. Refer to the following section Analog I/O Considerations for special requirements for the codec circuitry. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS pins are less than 0.5 inch per capacitor lead.
PR
* *
MOTOROLA
EL
* *
IM
Use at least a four-layer PCB with two inner layers for VDD and VSS. Refer to the following section Analog I/O Considerations for special requirements for the codec circuitry. Because the DSP output signals have fast rise and fall times, PCB trace lengths should be less than 6 inches maximum. This recommendation particularly applies to the address and data buses, as well as the PS/DS, BS, RD, WR, R/ W, PEREN, IRQA, IRQB, IRQC, HEN, HR/W, and HACK pins. When calculating capacitance, consider all device loads including parasitic capacitance due to PCB traces,. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits.
IN
DSP56167/D, Rev. 1
AR
4-3
Y
Design Considerations Analog I/O Considerations
*
If possible, do not have digital signals running over the analog VDD and ground planes. Decouple analog VDD and ground planes as close as possible to the DSP. Do not route clock signal lines across multiple signal lines. Keep the clock signals away from the analog power and ground lines and all analog signal lines.
*
*
ANALOG I/O CONSIDERATIONS
PR
4-4 DSP56167/D, Rev. 1 MOTOROLA
EL
IM
Figure 4-1 shows the recommended analog I/O and power supply configurations.
IN
This section discusses the requirements of the on-chip codec. The two analog inputs (MIC and AUX) are electrically identical. When one is not used, it can be left floating. When an input is used, an AC coupling capacitor is required. The value of the capacitor combines with the input impedance of MIC or AUX to determine the cutoff frequency of a high pass filter. The input impedance of MIC and AUX varies with respect to the Microphone Gain Select value (MGS[1:0]). An AC coupling capacitor of 10 F defines a high pass filter pole of 3 Hz. A smaller capacitor value moves this pole higher in frequency.
AR
Y
Take special care to minimize noise levels on the PLL supply pins (both VDD and VSS).
Design Considerations Analog I/O Considerations
5.6 K
VRDA
VDDA INS bit MIC
MGS[1:0]
10 F
-6 dB
600 0.001 F 600
5.6K
MUX
VRAD VSSA AUX
6 dB
modulator
0.001F 15 F + 0.1F
VRAD 2.5 V 10% (1/2 VDD) VDDA
15 F
VSSA ( 0.35 mA) VRDA + 0.1 F VSSA VDIV
85 K 85 K VSSA
15 F
+ 0.1 F VSSA SPKP 15 nF 3 K
IN
Active RC Reconstruction Filter SPKM VDDA + VSSA 15 F 0.1 F Analog Decoupling near DSP VSSA
(MAX 1 VP when single ended on 1.5 K) Digital VDD Digital VSS 0.01 F 220 F + GND
Max 2 VP
Ext. GND Ext. Supply
IM
+5 V Single trace
Single trace
AR
G
VC3-VC0
PR
MOTOROLA
EL
Figure 4-1 Recommended Analog I/O Configuration
DSP56167/D, Rev. 1
Y
17 dB 1-bit DAC Modulator
AA0798
10 F
4-5
Design Considerations Analog I/O Considerations
Figure 4-2 shows three possible output configurations. Configuration A is highly recommended, because the termination impedance between SPKP and SPKM is matched. Configurations B and C require an AC coupling capacitor because the load resistor is tied to VSSA.
VRDA VDDA + - VSSA 20 k (a) 40 k SPKM NC SPKM 10 k SPKP 20 k 1.5 k 0 < C 30 nF SPKP 0 < C 30 nF 1.5 k SPKP
Figure 4-2 Codec Output Configurations
IM
84 1
Figure 4-3 shows a recommended layout for power and ground planes. A four-layer board is recommended. The top layer (directly under the parts) and the bottom layers should be interconnected layers. The two center layers should be power and ground. Ground and power planes should be completely separated, and the digital and analog power/ground planes should not overlap. All codec pins and all codec signal traces should be over the analog planes. The analog planes should not encompass any digital pins.
PR
EL
112 28
85
Digital Ground and Power Planes
Analog Ground and Power Planes
Figure 4-3 Recommended Ground and Power Plane Layout
4-6
DSP56167/D, Rev. 1
29
56
IN
57
AR
1.5 k (c) (b)
Y
0 < C 30 nF SPKM AA0799
MOTOROLA
Design Considerations Analog I/O Considerations
Figure 4-4 shows that 0.1 F bypass capacitors should be located as close to the pins being bypassed as possible. Connect the ground side of the bypass capacitors to VSSA by short traces.
VRAD AUX MIC SPKM SPKP VRDA VDDA VSSA VDIV
0.1 F
28
0.1 F
65 F 15 F
Figure 4-4 Suggested Top Layer Bypassing
PR
MOTOROLA
EL
If possible, use the output differentially. Shield analog signal traces by running traces connected to the analog ground next to them. All unused board area (on both interconnect levels) should be copper-filled and connected to analog ground. For clarity and simplicity, copper fill is indicated by text, but not shown in. The ADC input anti-aliasing filtering should be done with respect to VRAD. Figure 4-6 on page 4-9 shows four examples of good power supply connections.
IM
The pins requiring 0.1 F bypass capacitors are VRDA, VRAD, and VDDA. These pins and the VDIV pin should have bypass capacitors of the largest size practical; 10 F should be considered a minimum size for the larger capacitors (65 F may be used on VDIV). The capacitors should be placed near the package, but do not have to be immediately next to the pins. As shown in Figure 4-5 on page 4-8, run the DAC outputs (SPKP and SPKM) next to each other.
IN
DSP56167/D, Rev. 1
AR
0.1 F 0.1 F
15 F
29
Y
15 F
4-7
Design Considerations Analog I/O Considerations
VRAD
MIC
20 k
PR
4-8
EL
SPK OUT
IM
+ -
20 k
Figure 4-5 Suggested Bottom Layer Routing
IN
40 k 10 k
DSP56167/D, Rev. 1
AR
VRDA
SPKM
SPKP
VDDA
VSSA
VDIV
28
29
Y
1 nF 1 F MIC IN
AUX
5.6 k
MOTOROLA
Design Considerations Analog I/O Considerations
VRAD AUX MIC
10
VRAD AUX MIC SPKM
SPKM
VRDA
SPKP
SPKP
28
VRDA
VDDA
VDDA
IM
10 VRAD AUX
IN
10 MIC
Ideal Choice-- Two separate power supplies, one for digital and one for analog. Ground planes connected with a single trace as close as possible to the VDDA on the codec.
EL
SPKM VRDA SPKP VDIV VSSA VDDA
29
SPKM
SPKP
28
VRDA
VDDA
VSSA
VDIV
28
Voltage Regulator
Third Choice-- One power supply. One regulator for the analog supply. Digital supplies driven directly by voltage source. Ground planes connected with a 10 resistor as close as possible to the VDDA on the codec.
Fourth Choice-- One power supply. Ground planes connected at source. Ground planes connected with a 10 resistor as close as possible to the VDDA on the codec.
PR
Figure 4-6 Four Possible Power Supply Connections
MOTOROLA
DSP56167/D, Rev. 1
29
AR
Voltage Regulator
Y
VSSA VDIV
29
VSSA
VDIV
28
Second Choice-- One power supply, Voltage two regulators, one Regulator for digital and one for analog. Ground planes connected with a 10 resistor as close as possible to the VDDA on the codec.
VRAD AUX MIC
29
4-9
Design Considerations Power Consumption
POWER CONSUMPTION
Power dissipation is a key issue in portable DSP applications. The following describes some factors which affect current consumption. Current consumption is described by the formula: Equation 3: I = C x V x f
- 12 6 Equation 4: I = 50 x 10 x 5.5 x 15 x 10 = 4.125mA
PR
4-10
EL
The following steps are recommended for applications requiring very low current consumption: 1. Minimize external memory accesses; use internal memory accesses instead. 2. Minimize the number of pins that are switching. 3. Minimize the capacitive load on the pins. 4. Connect unused digital inputs to VDD or VSS. Connect unused I/O pins through 10 k resistors to VDD or VSS. 5. All Port A input pins and bidirectional pins must have a valid state at all times when Port A is released to minimize power consumption; therefore the pins must be pulled up or down or driven by another device. 6. When the codec is not used, connect VDDA to VDD and VSSA to VSS and decouple VRAD and VARD. Leave all other codec pins floating.
IM
The maximum internal current value (ICCI-max), reflects the maximum ICC expected when running a test code. This represents "typical" internal activity, and is included as a point of reference. Some applications may consume more or less current depending on the code used. The typical internal current value (ICCI-typ) reflects what is typically seen when running the given code.
IN
DSP56167/D, Rev. 1
For example, for an address pin loaded with a 50 pF capacitance and operating at 5.5 V with a 60 MHz clock, toggling at its maximum possible rate (which is 15 MHz), the current consumption is:
AR
where:
I = current in A C = node/pin capacitance in F V = voltage swing in V f = frequency of node/pin toggle (in Hz)
Y
MOTOROLA
Design Considerations PLL Usage Considerations
PLL USAGE CONSIDERATIONS
The PLL can be used to generate the DSP core system clock. The specific operating frequency is determined by choosing the appropriate input frequency (EXTAL) and the ID, YD, and PD counter divider ratios. These ratios are defined in the PLL Control Register 0 (PCR0), using the following formula:
The External Filter Capacitor (XFC) is another parameter affecting lock time and stability of the PLL system. This low-leakage capacitor should be connected between SXFC and GNDS, as close as possible to the pins. The PLL pins (VDDS, GNDS, and SXFC) should be isolated, as much as possible, from any external noise, preferably in a separate ground plane. The PLL modifies the voltage on the VCO by varying the charge on the capacitor connected to XFC. In effect, the PLL can be viewed as a second-order control system in which the SFC influences the natural frequency and damping factor for the system. If the capacitor is too small, the system will be severely underdamped and unstable, which yields a large jitter. If the capacitor is too large, the PLL becomes overdamped and may not be able to adjust to voltage changes within a reasonable lock time. The PLL lock detection circuitry does not require the system to be underdamped.
PR
MOTOROLA DSP56167/D, Rev. 1
EL
A recommended connection diagram is shown in Figure 4-7 on page 4-12.
IM
IN
AR
The best PLL performance is attained when the ID and YD counter values are kept in a small range to minimize lock time and jitter. A higher input frequency to the PLL will result in a higher correction rate, therefore producing a more stable output clock. For example, with an input EXTAL frequency of 10 MHz, a PLCR0 value of $0317 will result in a more stable 60 MHz system clock than will a PLCR0 value of $0F5F. A programming ratio of EXTAL/(ID + 1) 1 MHz is recommended.
Y
YD + 1 Fosc = ------------------------------------ x EXTAL PD ( ID + 1 ) x 2
4-11
Design Considerations PLL Usage Considerations
1 nF XFC1 SXFC
0.01 F 0.1 F GNDS VDDS PD3 - PD0 PLLE = 1 / 20 to / 215 Fosc PLLE = 0
EXTAL 1000 pF
LF
PS = 0 CS1 - CS0 CLKO /2
PS = 1
Note:
IM
1. Must be a low leakage capacitor and must be located very close to the SXFC and VDDS pins.
AA0773
Figure 4-7 Connecting EXTAL and the External Filter Capacitor
PR
4-12 DSP56167/D, Rev. 1 MOTOROLA
EL
IN
AR
PLL
/ 1 to / 256 YD7 - YD0
Internal Phase PH0 at Fosc
Y
100 K
/ 1 to / 16 ID3 - ID0
PFD
VCO
Design Considerations Host Port Usage Considerations
HOST PORT USAGE CONSIDERATIONS
Careful synchronization is required when reading multibit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected. The situation exists in the Host port. The considerations for proper operation are discussed below.
Host Programmer Considerations
*
Unsynchronized Reading of Receive Byte Registers--When reading receive byte registers, RXH or RXL, the host programmer should use interrupts or poll the RXDF flag which indicates that data is available. This assures that the data in the receive byte registers will be stable. Overwriting Transmit Byte Registers--The host programmer should not write to the transmit byte registers, TXH or TXL, unless the TXDE bit is set indicating that the transmit byte registers are empty. This guarantees that the transmit byte registers will transfer valid data to the HRX register. Synchronization of Status Bits from DSP to Host--HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF (refer to DSP56167 User's Manual, I/O Interface section, Host/DMA Interface Programming Model for descriptions) status bits are set or cleared from inside the DSP and read by the host processor. The Host can read these status bits very quickly without regard to the clock rate used by the DSP, but the possibility exists that the state of the bit could be changing during the read operation. This is generally not a system problem, since the bit will be read correctly in the next pass of any Host polling routine. However, if the Host asserts the HEN for more than timing number 101 (T101), with a minimum cycle time of timing number 103 (T103), then the status is guaranteed to be stable.
*
*
PR
MOTOROLA
EL
Note: A potential problem exists when reading status bits HF3 and HF2 as an encoded pair. If the DSP changes HF3 and HF2 from 00 to 11, there is a small probability that the Host could read the bits during the transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has significance, the Host could read the wrong combination. Solution: a. Read the bits twice and check for consensus. b. Assert HEN access for T101a so that status bit transitions are stabilized.
IM
IN
DSP56167/D, Rev. 1
AR
Y
4-13
Design Considerations Host Port Usage Considerations
*
Overwriting the Host Vector--The host programmer should change the Host Vector register only when the Host Command bit (HC) is clear. This change will guarantee that the DSP interrupt control logic will receive a stable vector. Cancelling a Pending Host Command Exception--The host processor may elect to clear the HC bit to cancel the Host Command Exception request at any time before it is recognized by the DSP. Because the Host does not know exactly when the exception will be recognized (due to exception processing synchronization and pipeline delays), the DSP may execute the Host exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the same time the HC bit is cleared.
*
DSP Programmer Considerations
PR
4-14 DSP56167/D, Rev. 1 MOTOROLA
EL
IM
Note: A potential problem exists when reading status bits HF1 and HF2 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have significance). A very small probability exists that the DSP will read the status bits synchronized during transition. The solution to this potential problem is to read the bits twice for consensus.
IN
When reading HF0 and HF1 as an Encoded Pair, the DMA, HF1, HF0, and HCP, HTDE, and HRDF (refer to DSP56167 User's Manual, I/O Interface section, Host/ DMA Interface Programming Model for descriptions) status bits are set or cleared by the host processor side of the interface. These bits are individually synchronized to the DSP clock.
AR
Y
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
SPECIAL DESIGN CONSIDERATIONS FOR CONVERSIONS FROM DSP56166 TO DSP56167
There are several areas to consider when converting a design using a DSP56166 to a design using the DSP56167. Although the DSP56167 is software and pin compatible with the DSP56166, some external component changes are required. Not only have additional features been added in the DSP56167, but there are also changes to existing circuitry that affect DSP operation and circuit design. In addition, several errata in the DSP56166 have been fixed in the DSP56167. The following sections provide detailed information about these design changes. Note: All references to RSSI are now listed as SSI.
New Feature Descriptions
New features added to the DSP56167 include: * * *
Programmable absolute short addressing mode (PASAM) Peripheral Address Generation Unit (PAGU)
* *
*
PR
MOTOROLA
EL
The following sections provide a detailed description of these new features and provide guidelines for use in applications.
PROGRAMMABLE ABSOLUTE SHORT ADDRESSING MODE (PASAM)
Previously on the DSP56166, the absolute short addressing mode allowed the user to access the first 32 locations, from X:$0000 throughX:$001F, of the data memory space using a one word move or bitfield instruction. This feature has been enhanced to allow the user to access any 32 locations within the data memory space, from X:$0000 to X:$FFFF. The block of 32 locations or page of the data memory space is selected by programming the upper 11 bits of the Address ALU Programmable Absolute Short Addressing Mode register (PASAM --X:$FFCA), wait one instruction cycle due to the pipeline delay, and then access the new page using the same absolute short addressing mode instruction. Figure 4-8 on page 4-16 shows the PASAM architecture.
IM
Independent external chip enable signals BR and PEREN Port A BG pull-down under software control Port A and OnCE port DR signal line keepers with reset External program memory access disable
IN
DSP56167/D, Rev. 1
AR
4-15
Y
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
GDB[15:0] 11 PASAM 16 5 ALU
XAB1[15:0]
Figure 4-8 Programmable Absolute Short Addressing Mode Architecture
Note: The lower 5 bits of the PASAM register are reserved bits and should be written with zeros for future compatibility. They are read as zeros whenever PASAM is read. The changes affect the following instructions:
move(s) X:,D move(s) S,X: bftst/bfset/bfchg/bfclr#iiii,X:
PASAM Register
The register defined in Figure 4-9 has been added to the DSP56100 core to allow implementation of this function.
IM
15 14 13 12 11 10 p p p p p p 9 8 7 p p p
IN
6 p 5 p 4 * 3 * 2 * 1 * 0 * X:$FFCA
PR
Using PASAM 4-16
EL
Where: p programmable bits; preset to 0 during processor reset * reserved bits; write 0 for future compatibility
Figure 4-9 Programmable Absolute Short Addressing Mode Register (PASAM)
To use this function, write the starting address of the selected block into the Programmable Absolute Short Addressing Mode (PASAM) register to point to the desired block or page. You can access the selected block at any time.
DSP56167/D, Rev. 1
AR
Y
MOTOROLA
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
PERIPHERAL ADDRESS GENERATION UNIT (PAGU)
A Peripheral Address Generation Unit (PAGU) has been added to the DSP56167. The PAGU allows the DSP to generate external peripheral addresses. To support this function, some control bits have been added to DSP56100 core registers and a number of new core registers and functional units have been added. Core changes to support the PAGU include:
- - *
Peripheral Address Generation Unit Registers (pointers) 0-2 (PAGUR0- PAGUR2] Peripheral Address Generation Unit Compare registers 0-2 (PAGUC0- PAGUC2]
New Units--There are two new processing units: - Post Update Address Generation Unit (PUAGU) supports three postupdate modes: * * * No Update [(Rn)],
*
PR
MOTOROLA
EL
The interrupt feature of the PAGU can be enabled by programming the two interrupt enable/priority encoding bits in the IPR2 register. The PAGU interrupt can also be de-asserted if the Peripheral Enable (PE) bit 9 of the Operating Mode Register (OMR), (i.e., the PAGU is disabled). Since the hardware reset clears PE, it also deasserts the PAGU interrupt request. Once the PAGU is enabled, every time a post update operation occurs, the post updated address will be compared against the value in the corresponding PAC register. When the two values matched, an interrupt request signal will be asserted. When the DSP core recognizes the PAGU interrupt, the interrupt vector corresponding to the updated Peripheral Address Pointer is taken. Its corresponding interrupt request signal is cleared as the interrupt is being serviced. If the Peripheral Address Pointer and/or the PAC register pair values are changed before the corresponding interrupt is serviced, the interrupt will remain pending.
IM
Post-decrement [(Rn)-] -
Post-increment [(Rn)+], and
Comparator--Address Comparator and Interrupt Control Unit.
New Interrupt Vectors--There are 3 separate interrupt vectors, one for each Peripheral Address Compare Register, located at addresses P:$0030, P:$0032 and P:$0034, respectively.
IN
DSP56167/D, Rev. 1
AR
*
New Registers--These registers and pointers are used as matched pairs (i.e., PAGUR0 is used with PAGUC0):
Y
4-17
*
Defined Interrupt Priority Register (IPR2) bits 1 and 0--this is the DSP second X memory mapped interrupt priority register at address X:$FFDD.
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
Note: The PAGUC0 compare interrupt has precedence over the PAGUC1 compare interrupt, and the PAGUC1 compare interrupt has precedence over the PAGUC2 compare interrupt.
GDB[15:0]
PAGUC 1 PAGUC 2 PAGUR0 PAGUR1 PAGUR2
PAGU Programming Environment
The following tables and figures describe the PAGU programming environment.
EL
PAGU Register PAGUR0 PAGUR1 PAGUR2 PAGUC0 PAGUC1 PAGUC2
IM
XAB1[15:0]
Figure 4-10 PAGU With Address Compare Interrupt Architecture
Table 4-1 PAGU X Memory-Mapped Registers
X Memory Mapped Address X:$FFD7 X:$FFD6 X:$FFD5 X:$FFCF X:$FFCE X:$FFCD
PR
4-18
IN
AGU
DSP56167/D, Rev. 1
AR
Comparator Interrupt Service Request
PAGUC 0
Y
MOTOROLA
GDB Buffer
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
IPR2 15 14 13 12 11 10 9 * * * * * * * 8 * 7 * 6 5 4 3 2 1 0
* ICL ICL * 21
* PL PL 10
Note: IPR2 is reset to zero
Figure 4-11 Interrupt Priority Register IPR2 (X:$FFDD)
Table 4-2 Interrupt Priority Level
PL1
0 0 1 1
IN
PL0
0 1 0 1
IM EL PR
Priority Highest Lowest Exception Hardware RESET Stack Error SWI Illegal Instruction PAGU Interrupt PAGUC0 Compare Interrupt PAGUC1 Compare Interrupt PAGUC2 Compare Interrupt Enabled By -- -- -- --
Table 4-3 PAGU Interrupt Vectors
Interrupt Vector Address P:$0030 P:$0032 P:$0034
Table 4-4 Level 3 Non-maskable Interrupts
IP Reg. Bit No. -- -- -- -- Control Register Address -- -- -- --
MOTOROLA
DSP56167/D, Rev. 1
AR
Enabled
No Yes Yes Yes
Y
PAGU IPL IRQC mode Reserved
IPL
0 1 2
4-19
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
Table 4-5 Level 0, 1, 2 Maskable Interrupts
Priority Highest Exception IRQA (External Interrupt) IRQB (External Interrupt) IRQC (External Interrupt) PAGU Address Compare 0 PAGU Address Compare 1 PAGU Address Compare 2 Codec RX/TX Enabled By IRQA mode bit IRQB mode bit IRQC mode bit IP Reg. Bit No. 0,1 3,4 IPR2 4,5 Control Register Address X:$FFDF X:$FFDF X:$FFDD -
Host Command
IN
HCIE HRIE HTIE RIE RIE TIE TIE RIE RIE TIE TIE OIE OIE
Host/DMA RX Data Host/DMA TX Data
IM
SSI0 RX Data SSI0 TX Data with Exception Status SSI0 TX Data SSI1 RX Data with Exception Status SSI1 RX Data SSI1 TX Data with Exception Status SSI1 TX Data Timer Overflow Timer Compare
SSI0 RX Data with Exception Status
EL
Lowest
PR
4-20
DSP56167/D, Rev. 1
AR
IPR2 0,1 IPR2 0,1 IPR2 0,1 6,7 8,9 8,9 COIE X:$FFC8 X:$FFC4 X:$FFC4 X:$FFC4 X:$FFD1 X:$FFD1 X:$FFD1 X:$FFD1 X:$FFD9 X:$FFD9 X:$FFD9 X:$FFD9 X:$FFEC X:$FFEC 8,9 10,11 10,11 10,11 10,11 12,13 12,13 12,13 12,13 14,15 14,15
Y
MOTOROLA
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
Table 4-6 Interrupt Vectors Space Mapping
Interrupt Starting Address $0000 $0002 $0004 $0006 $0008 $000A $000C $000E $0010 $0012 $0014 $0016 $0018 IPL 3 3 3 3 3 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 Interrupt Source Hardware RESET Illegal Instruction Stack Error Reserved SWI IRQA
EL
$0022 $0024 $0026 $0028
PR
$002A $002C $002E $0030 $0032 $0034
MOTOROLA
IM
$001A $001C $001E $0020 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2
IN
SSI0 Receive Data SSI0 Transmit Data SSI1 Receive Data SSI1 Transmit Data Timer Overflow Timer Compare Host Receive Data Host Transmit Data
DSP56167/D, Rev. 1
AR
IRQB IRQC SSI0 Receive Data with Exception Status SSI0Transmit Data with Exception Status SSI1 Receive Data with Exception Status SSI1 Transmit Data with Exception Status Host DMA Receive Data Host DMA Transmit Data Host Command (default) Codec Receive/Transmit PAGU Address 0 Compare PAGU Address 1 Compare PAGU Address 2 Compare
Y
4-21
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
Table 4-6 Interrupt Vectors Space Mapping (Continued)
Interrupt Starting Address $0036 $0038 $003A . . . $007E IPL 0-2 0-2 0-2 . . . 0-2 Interrupt Source Available for Host Command Available for Host Command Available for Host Command . . .
OMR 15 14 13 12 11 10 9 * * * * * 8 7 6 5
* PE * CD SD R SA EX MC MB MA
IM
4-22
PR
EL
PE is cleared by processor reset.
Figure 4-12 DSP56100 Operating Mode Register (OMR)
IN
4 3 2 1 0 Operating Mode Bus Arbitration Mode External X Memory Saturation Rounding Stop Delay Clockout Disable Peripheral AGU Enable Reserved
DSP56167/D, Rev. 1
AR
Available for Host Command
Y
MOTOROLA
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
MR 15 14 13 12 11 10 9 8 7 6 5
CCR 4 3 2 1 0
LF FV AD * S1 S0 I1 I0
S
L
E
U
N
Z
V
C
AD is cleared by processor reset
PR
MOTOROLA DSP56167/D, Rev. 1
EL
4-23
IM
Figure 4-13 DSP56167 Status Register (SR)
IN
Interrupt Mask Scaling Mode Reserved Address Disable ForeVer Flag Loop Flag
AR
Y
Carry Overflow Zero Negative Unnormalized Extension Limit Sticky Bit
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
PAGU Operation
The following figures and tables summarize PAGU operation. Table 4-7 PAGU Operation Summary
PE
0
AD
-
Fast Interrupt
-
Core AALU
Drives XAB1 Addr. Reg. Updated Drives XAB1 Addr. Reg. Updated Disabled
PAGU
Disabled
1
0
No
1
-
1
1
EL
4-24
IM
; PE, AD reset to 0 bfset #$0200,omr nop ; PE bit set . . . move x:(r0)+,b move a,x:(r1)+ move r1,x:(r2)+ add a,bb,x:(r3)+ PE = 1 AD = 0 (PAGU Not Enabled)
Main Program
PR
Figure 4-14 PAGU Operation During Fast Interrupt
IN
Host Fast Interrupt
move x:(r0)+,x:TX move x1,y1 PE = 1 AD Ignored (PAGU Enabled)
DSP56167/D, Rev. 1
AR
Yes Drives XAB1Addr. Reg. Updated Drives XAB1 Addr. Reg. Updated Disabled
Y
Disabled
MOTOROLA
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
Main Program
SSI Fast Interrupt
SSI Interrupt Handler
Timer Fast Interrupt
Timer Interrupt Handler
jsr ssi_handler
IN
PE = 1 AD = 1 (PAGU Enabled)
Figure 4-15 PAGU Operation During Normal and Nested Long Interrupt Service Routine
Allowed Move Operations
PR
* * *
MOTOROLA
EL
*
The PAGU is used for all post update single or multi-cycle moves. The following conditions apply when using the PAGU: BRA(Rn), Lea(Rn) and Norm(Rn) instructions and move instructions with (Rn), (Rn+Nn), and (R2+xx) addressing modes all use the Core AALU registers. Immediate and move peripheral addressing modes work as normal. During reduced DALU instructions with dual reads, the first parallel move is executed out of the PAGU and the second parallel move is executed out of the Core AALU. During DALU instructions with only one parallel move, the parallel move is executed from the PAGU.
IM
PE = 1 AD = 0 (PAGU Not Enabled)
DSP56167/D, Rev. 1
AR
jsr tmr_handler
; PE, AD reset to 0 bfset #$0200,omr ; PE bit set . . . move x:(r0)+,b move a,x:(r1)+ move r1,x:(r2)+ add a,bb,x:(r3)+ . . .
. move x:(r0)+,x1 add x1,a . . . rti
Y
Set AD
. Set . AD
bfclr #$2000,sr ; AD bit cleared. . . . asl a move a,x:(r1)+ . . . rti
PE = 1 AD = 0 (PAGU Not Enabled)
4-25
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
*
During move from peripheral to X memory instruction, the X memory address comes from the PAGU and the peripheral address comes from the Core AALU. During moves to and from program memory, the program memory address is output from the Core AALU and the X memory source or destination address, if needed, is output from the PAGU.
*
Restrictions
The following restrictions apply when using this feature: * It is illegal to use (r3), (r3)+, (r3)-, and (Rn)+Nn addressing modes when the PAGU is active and the R3 part of the move is not associated with a parallel move. Modulo or reverse carry addressing modes is not allowed.
* * *
Must wait one instruction cycle before using the values written to the PAGURn & PAGUCn registers. Must wait one instruction cycle before using the PAGU/Core addressing modes after the OMR[PE] and/or SR[AD} bits are changed.
INDEPENDENT EXTERNAL CHIP ENABLE SIGNALS BR AND PEREN
PR
4-26
EL
The DSP56167 independent chip enable feature allows the DSP to disable or power down the external memory when it is not being accessed even when the external peripheral device is being accessed. As before, the external peripheral device can be disabled using the PEREN pin since this signal is deasserted high whenever the external peripheral space is not being accessed. This feature is enabled when the CHIPEN bit 15 of the Bus Control Register2, (BCR2[15]) is set to 1. It is disabled when CHIPEN is cleared. While in the Bus Master mode of operation (i.e., bit 2 of the OMR is set), the user has the option of enabling BR and PEREN to act as two independent external chip enable signals.
Note: This feature is not available while the chip is in the Bus Slave Mode of operation, (i.e., OMR[2] is cleared).
IM
On the DSP56166, while the DSP is in the Master Mode of bus operation, BR is asserted for each external memory and external peripheral accesses. When the external peripheral space is accessed, PEREN is also asserted. As a result, it is possible to use BR as an external chip enable. However, since both BR and PEREN are asserted for external peripheral space accesses, it is not possible to disable or powerdown an external memory versus an external peripheral separately.
IN
DSP56167/D, Rev. 1
AR
Y
MOTOROLA
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
Programming Environment:
A new control bit called External Chip Enable (ECHIPEN) has been added to the Bus Control Register 2 (BCR2[15] at X:$FFDA), to switch BR and PEREN from their current mode of operation to the new one.
EC
*
*
*
*
*
*
*
*
*
*
P4 P3 P2 P1 P0
Where: EC External Chip Enable; preset to 0 during processor reset P External Peripheral Wait States; preset to 0 during processor reset * reserved bits; write 0 for future compatibility
Figure 4-16 Port A Bus Control Register 2 (BCR2), X:$FFDA
External Chip Enable Operation
Note: Since, this feature does not alter the BR and PEREN functions while the DSP is in the Bus Slave Mode of operation, all subsequent discussion assume that the external bus is in the Bus Master Mode of operation. ECHIPEN is preset to 0 during processor reset. Therefore, upon coming out of reset, BR and PEREN function as in the DSP56166. This means that BR asserts during external memory access (both program and data) and during external peripheral access. PEREN is asserted during external peripheral accesses only.
PR
MOTOROLA DSP56167/D, Rev. 1
EL
When ECHIPEN is set to 1 via software programming, BR only asserts during external memory (program and data) access and PEREN asserts only during external peripheral accesses.
If ECHIPEN is now cleared to 0 via software programming, then BR and PEREN functionality reverts back to be the same as when the chip has just come out of reset.
IM
IN
AR
4-27
Y
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
BR DSP56167 PEREN
Memory
Peripheral
A[15:0] (BCR2[15]) = 0 (default) BR
RAM Access
Peripheral Access
PEREN
(BCR2[15]) = 1
BR
PR
4-28
EL
PORT A BG PULL-DOWN UNDER SOFTWARE CONTROL
After the BG pin is initialized high during hardware reset in bus Master Mode, the BG pin can be optionally pulled low by setting Bus Grant Pull Down bit (BGPD) in the Bus Control Register (BCR[13]). This allows the DSP to become the permanent bus master while in bus Master Mode without having to add an external pull-up resistor. When BGPD is cleared, BG retains the last logic state that was driven by either the DSP or by an external bus master. Note: BGPD is cleared by the hardware reset allowing BG to be pulled up as the default state so as not to interfere with any existing bus design.
IM
PEREN
Figure 4-17 External Chip Select Operation
IN
DSP56167/D, Rev. 1 MOTOROLA
AR
Y
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
PORT A AND OnCE PORT DR SIGNAL LINE KEEPERS WITH RESET
Active pull-up and/or pull-down resistors have always been required for the external bus interface pins to keep them at a valid logic state when the DSP gives up the bus to another bus master. This is also true during hardware reset. Adding on-chip static latches or keepers eliminates the need of including external resistors on board when no external memory or peripherals are attached to the DSP. When external memory and/or peripherals are desired, most if not all of the external resistors can be eliminated. The on-chip static latch for the OnCE DR pin eliminates the need for the eternal resistor when the OnCE is not needed.
10 Resistors
PSDS PEREN RD WR R/W BS BR BG BB DF A0-A15 D0-D15 TA
IN
PSDS PEREN RD WR R/W BS BR BG BB DF A0-A15 D0-D15 TA
IM
33 Resistors
EL
DSP56166
DSP56167
PR
MOTOROLA
External pull-up/pull-down resistors required in all cases.
Stand-alone DSP56167 DSP56167 with external memory/ No pull-up/pull-down peripheral interface. Three pull-up resistors required. resistors required. (maximum). *required only when used as output enable.
Figure 4-18 DSP56167 Pull-Up/Pull-Down Resistors
DSP56167/D, Rev. 1
AR
PSDS PEREN RD WR R/W BS BR BG BB DF A0-A15 D0-D15 TA
The external bus interface control signals and the OnCE DR pins have built in reset circuitry to guarantee that they will be initialized to the desired functional state when the DSP comes out of hardware reset.
Y
3 Resistors * * DSP56167
4-29
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
EXTERNAL PROGRAM MEMORY ACCESS DISABLE
For those users that run strictly from internal program memory, it is now possible to disable the external program memory access as a power-saving measure. Note: This has no effect on external data memory or external peripheral accesses. When this feature is enabled, the internal path from the PAB bus to the Port A address pins is disabled, eliminating unnecessary switching inside the DSP.
External Program Memory Access Disable Programming Environment:
15 14
13
12
11 10
9
8
PR
4-30
EL
External Program Memory Access Disable Operation
EPABDIS is preset to 0 during processor reset. So, coming out of reset the Port A bus functions exactly as the DSP56166. When EPABDIS is set to 1 via software programming, Port A access is restricted to external data memory or external peripheral accesses. Note: Attempts to access external program memory while this bit is set result in an incorrect address appearing at the Port A address pins. The results of the operation will be incorrect. If EPABDIS is cleared to 0 via software programming, then Port A functionality will revert back to be the same as when the chip just came out of reset. However, due to pipeline delays inside the DSP, there should be at least 1 instruction cycle between when EPABDIS is cleared and external program memory is accessed.
IM
Where: BH BS BGPD EPABDIS X P *
Bus Request Hold; preset to 0 during processor reset Bus State Status; Read Only Bus Grant Pull-Down; preset to 0 during processor reset External PAB Disable; preset to 0 during processor reset External Data Memory Wait States; preset to 1 during processor reset External Program Memory Wait States; preset to 1 during processor reset reserved bits; write 0 for future compatibility
Figure 4-19 Port A Bus Control Register (BCR), X:$FFDE
IN
DSP56167/D, Rev. 1
BH BS BGPDEPABDIS *
* X4 X3
AR
7 6 5 4 3 2 1 0 X2 X1 X0 P4 P3 P2 P1 P0
A new control bit called External PAB Disable (EPABDIS) has been added to the Bus Control Register, BCR[12] at X:$FFDE, to disable the external program memory access.
Y
MOTOROLA
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
Feature Changes Description
Changes to DSP56166 functionality in the DSP56167 include: * * * * * Codec input circuitry can be single-ended or differential Codec input impedance is software selectable
Codec output drive capability (for VRDA, VRAD, SPKP, and SPKM) is now 0.35 mA
Codec single-ended small signal output (SPKP and SPKM) impedance has changed to a range of 4.0-16.0 for 300 Hz and a range of 12.6-50.4 for 3000 Hz Codec DAC outputs (absolute single-ended) now can swing between 0.35 V and VDD - 0.4 V.
*
DSP56166 Chip Errata Fixed in the DSP56167
The following DSP56166 chip errata (some of which required hardware workarounds) have been fixed in the DSP56167: * * CHKAAU instruction does not operate correctly if there is a killed instruction between the last valid AALU update and CHKAAU The second read from internal data memory of a dual read instruction will transfer the wrong data if it is preceded by a conditional transfer instruction with the condition being false (i.e., the transfer is aborted). The OnCE NOS0 status flag does not get updated correctly when the DSP enters the Wait or Stop mode of operation. The SSI RS/TX interrupt occurs when the interrupt is enabled even though the RE and TE bits are cleared (i.e., function disabled). The SSI receiver does not operate independently from the transmitter in Gated Clock mode. In External Gated Clock mode, the SSI STD signal can remain tri-stated during the first two bits of the transmitted word. In External Gated Clock mode, the STD signal should not be tri-stated until the end of the transmitted word regardless when the TE bit is cleared (i.e., the function is disabled).
PR
* * * *
MOTOROLA
EL
*
IM
IN
DSP56167/D, Rev. 1
Refer to the section titled Analog I/O Considerations on page 4-4 for a detailed description of design requirements for the on-chip codec.
AR
Y
4-31
Codec output reference voltages (VRDA and VRAD) are now 1/2 VDDA
Design Considerations Special Design Considerations for Conversions from DSP56166 to DSP56167
*
The SSI TDE and TUE bits can be incorrectly set after being cleared if the clear operation is performed is performed during the last half bit period of the current word, or during the first half bit period of the next word. The PLL may lock at the maximum VCO frequency during power up at low voltage and high temperature. (The recommended workaround was to connect the SXFC to GND and not VCC).
*
*
*
*
PR
4-32 DSP56167/D, Rev. 1 MOTOROLA
EL
IM
IN
Due to SXFC external filter capacitor leakage and noise, the PLL frequency may jitter by as much as 25 MHz at the PLL input frequency rate (output from the ID divider). (The workaround was to use a faster reference clock, a smaller Multiplication Factor, a low-leakage capacitor for the SXFC loop filter capacitor, and to reduce the coupled noise level into the PLL by careful board design.)
AR
The PLL may lock at the maximum VCO frequency when coming out of Stop mode of operation. (The workaround was to connect a 10 M resistor between SXFC and GND.)
Y
The PLL Lock bit failed to be asserted properly in an over-damped system. (The recommended workaround was to use a software time loop of at least 5 ms instead of the "lock bit" polling loop.)
SECTION
5
ORDERING INFORMATION
Table 5-1 DSP56167 Ordering Information
Part DSP56167 Supply Voltage 5V Package Type Pin Count 112
Thin Quad Flat Pack (TQFP)
PR
MOTOROLA DSP56167/D, Rev. 1
EL
5-1
IM
IN
AR
Frequency (MHz) 60
Y
Order Number XC56167FV60
DSP56167 ordering information in the table below lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts.
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