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Integrated Circuit Systems, Inc.
ICS853014
LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
FEATURES
* 5 differential LVPECL/ECL outputs * 2 selectable differential LVPECL clock inputs * PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Maximum output frequency: > 2GHz * Output skew: 13ps (typical) * Part-to-part skew: 60ps (typical) * Propagation delay: 460ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V * -40C to 85C ambient operating temperature * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS853014 is a low skew, high performance 1-to-5, 2.5V/3.3V Differential-to-LVPECL/ECL HiPerClockSTM Fanout Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS853014 has two selectable clock inputs.
ICS
Guaranteed output and par t-to-part skew characteristics make the ICS853014 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
nEN D Q LE PCLK0 nPCLK0 PCLK1 nPCLK1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC nEN VCC nPCLK1 PCLK1 VBB nPCLK0 PCLK0 CLK_SEL VEE
00 11
Q0 nQ0 Q1 nQ1
CLK_SEL Q2 nQ2 V BB Q3 nQ3 Q4 nQ4
ICS853014
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View
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LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Type Description Differential output pair. LVPECL / ECL interface levels. Differential output pair. LVPECL / ECL interface levels. Differential output pair. LVPECL / ECL interface levels. Differential output pair. LVPECL / ECL interface levels. Differential output pair. LVPECL / ECL interface levels. Negative supply pin. Clock select input. When HIGH, selects CLK1, nCLK1 inputs. Pulldown When LOW, selects CLK0, nCLK0 inputs. LVTTL / LVCMOS interface levels. Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Bias voltage. Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 8 9, 10 11 12 13 14 15 16 17 18, 20 Name Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3 Q4, nQ4 VEE CLK_SEL PCLK0 nPCLK0 VBB PCLK1 nPCLK1 VCC Output Output Output Output Output Power Input Input Input Output Input Input Power
Positive supply pins. Synchronizing clock enable. When LOW, clock outputs follow clock input. 19 nEN Input Pulldown When HIGH, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN RVCC/2 Parameter Input Pulldown Resistor Pullup/Pulldown Resistors Test Conditions Minimum Typical 75 50 Maximum Units k k
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LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Inputs Outputs Selected Source PCLK0, nPCLK0 PCLK1, nPCLK1 PCLK0, nPCLK0 Q0:Q4 Disabled; LOW Disabled; LOW Enabled nQ0:nQ4 Disabled; HIGH Disabled; HIGH Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
nEN 1 1 0 CLK_SEL 0 1 0
0 1 PCLK1, nPCLK1 Enabled Enabled After nEN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the PCLK0, nPCLK0 and PCLK1, nPCLK1 inputs as described in Table 3B.
Disabled Enabled
nPCLK0, nPCLK1 PCLK0, PCLK1
nEN
nQ0:nQ4 Q0:Q4
FIGURE 1. nEN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs PCLK0 or PCLK1 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nPCLK0 or nPCLK1 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 LOW HIGH LOW HIGH HIGH LOW Outputs Q0:Q4 nQ0:nQ4 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) to the device. These ratings are stress specifi-0.5V to VCC + 0.5V cations only. Functional operation of product at 0.5V to VEE - 0.5V these conditions or any conditions beyond those 50mA 100mA 0.5mA -65C to 150C 73.2C/W (0 lfpm) listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current VBB Sing/Source, IBB Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40C to +85C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 Maximum 3.8 75 Units V mA
TABLE 4B. DC CHARACTERISTICS, VCC = 3.3V, VEE = 0V
Symbol VOH VOL VIH VIL VBB VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Input High Voltage Common Mode Range; NOTE 3, 4 Input D0, D1, D2, D3 High Current nD0, nD1,n D2, nD3 D0, D1, D2, D3 Input Low Current nD0, nD1,n D2, nD3 Min
2.175 1.405 2.075 1.43 1.86 1.2
-40C Typ
2.275 1.545
Max
2.38 1.68 2.36 1.765 1.98 3.3 150
Min
2.225 1.425 2.075 1.43 1.86 1.2
25C Typ
2.295 1.52
Max
2.375 1.615 2.36 1.765 1.98 3.3 150
Min
2.22 1.44 2.075 1.43 1.86 1.2
85C Typ
2.295 1.535
Max
2.365 1.63 2.36 1.765 1.98 3. 3 150
Units
V V V V V V A A A
-10 -150
-10 -150
-10 -150
Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPLCK0 and PCLK1, nPCLK1 is VCC + 0.3V.
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LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
-40C Min
1.375 0.605 1.275 0.63 1.2
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol VOH VOL VIH VIL VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 Input Low Current PCLK0, PCLK1 25C Max
1.58 0.88 1.56 0.965 2.5 150 -10 -10
85C Max
1.57 0.815 1.56 0.965 2.5 150 -10
Typ
1.475 0.745
Min
1.425 0.625 1.275 0.63 1.2
Typ
1.495 0.72
Min
1.42 0.64 1.275 0.63 1. 2
Typ
1.495 0.735
Max
1.565 0.83 -0.83 0.965 2.5 150
Units
V V V V V A A A
-150 -150 -150 nPCLK0, nPCLK1 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
Symbol VOH VOL VIH VIL VBB VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 Input Low Current PCLK0, PCLK1 -40C Min
-1.125 -1.895 -1.225 -1.87 -1.44 VEE+1.2V
25C Max
-0.92 -1.62 -0.94 -1.535 -1.32 0
85C Max
-0.93 -1.685 -0.94 -1.535 -1.32 0
Typ
-1.025 -1.755
Min
-1.075 -1.875 -1.225 -1.87 -1.44 VEE+1.2V
Typ
-1.005 -1.78
Min
-1.08 -1.86 -1.225 -1.87 -1.44 VEE+1.2V
Typ
-1.005 -1.765
Max
-0.935 -1.67 -0.94 -1.535 -1.32 0
Units
V V V V V V
150 -10 -10
150 -10
150
A A A
-150 -150 -150 nPCLK0, nPCLK1 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
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LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
-40C Min 355 Typ >2 440 13 150 90 100 20 0 800 15 0 50 140 525 25 105 1800 210 15 0 90 100 200 800 150 50 140 37 6 Max Min 25C Typ >2 460 13 550 25 105 1800 210 150 90 100 200 800 150 50 140 40 0 Max Min 85C Typ >2 500 12 595 25 130 1800 210 Max
TABLE 5. AC CHARACTERISTICS, VCC = 2.375V TO 3.8V, TA = -40C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 5 Par t-to-Par t Skew; NOTE 3, 5 Peak-to-Peak Input Voltage; NOTE 4 Output Rise/Fall Time Clock Enable Setup Time Clock Enable Hold Time 20% to 80% Units GHz ps ps ps mV ps ps ps
tsk(o) tsk(pp)
V PP tR/tF tS tH
All parameters tested 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: The VCMR and VPP levels should be such that input low voltage never goes below VEE. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
SCOPE
VCC
LVPECL
nQx
nPCLK0, nPCLK1
V
PP
Cross Points
V
CMR
VEE
PCLK0, PCLK1 V EE
-0.375V to -1.8V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
nQx Qx nQy Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
80% Clock Outputs
80% VSW I N G
nPCLK0, nPCLK1 PCLK0, PCLK1 nQ0:nQ4 Q0:Q4
tPD
20% tR tF
20%
OUTPUT RISE/FALL TIME
nPCLK0, nPCLK1 PCLK0, PCLK1 nEN
PROPAGATION DELAY
t HOLD t SET-UP
SETUP
AND
HOLD TIME
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LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows an example of the differential input that can be wired to accept single ended levels. The reference voltage level VBB generated from the device is connected to the negative input.
The C1 capacitor should be located as close as possible to the input pin.
VDD(or VCC)
CLK_IN
+ VBB -
C1 0.1uF
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION
FOR
3.3V LVPECL OUTPUTS
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
125
FOUT FIN
125
Zo = 50 FOUT FIN
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
Zo = 50 84 84
FIGURE 3A. LVPECL OUTPUT TERMINATION
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FIGURE 3B. LVPECL OUTPUT TERMINATION
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LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
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ICS853014
LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
gested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the HiPerClockS PCLKx/nPCLKx input driven by the most common driver types. The input interfaces sug-
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK
Zo = 60 Ohm 2.5V
2.5V 3.3V R3 120 SSTL Zo = 60 Ohm PCLK R4 120
R2 50
Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
nPCLK
HiPerClockS PCLK/nPCLK
R1 120
R2 120
FIGURE 5A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 5B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerCloc kS Input
Zo = 50 Ohm R5 100 C2
3.3V 3.3V
R4 125
3.3V Zo = 50 Ohm LVDS C1 R3 1K R4 1K PCLK
nPCLK
HiPerClockS PC L K/n PCL K
R1 1K
R2 1K
FIGURE 5C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R5 100 - 200
R6 100 - 200
R1 125
R2 125
FIGURE 5E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
put is driven by an LVPECL driver. CLK_SEL is set at logic high to select PCLK1/nPCLK1 input.
SCHEMATIC EXAMPLE
This application note provides general design guide using ICS853014 LVPECL buffer. Figure 6 shows a schematic example of the ICS853014 LVPECL clock buffer. In this example, the in-
Zo = 50 + Zo = 50 R2 50 R1 50
3.3V R12 3.3V Zo = 50 3.3V Zo = 50 C2 0.1u LVPECL Driv er R9 50 R10 50 C1 0.1u 1K 11 12 13 14 15 16 17 18 19 3.3V 20
U1
VEE CLK_SEL PCLK0 nPCLK0 VBB PCLK1 nPCLK1 VCC nEN VCC
nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 nQ0 Q0
10 9 8 7 6 5 4 3 2 1
R3 50
C3 0.1u
Zo = 50 + Zo = 50
ICS853014 R5 50 R4 50
-
C5 0.1u
R7 50
R11 1K R6 50 C4 0.1u
FIGURE 6. EXAMPLE ICS853014 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC
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LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853014. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS853014 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 75mA = 285mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 30.94mW = 154.7mW
Total Power_MAX (3.8V, with all outputs switching) = 285mW + 154.7mW = 439.7mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.440W * 66.6C/W = 114.3C. This is well below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
20-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS853014
LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT
RL
50 VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 0.935V
-V
OH_MAX
) = 0.935V =V - 1.67V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.67V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CC_MAX
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.935V)/50] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50] * 1.67V = 11.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853014 is: 373 Pin compatible with MC100LVEP14 and SY100EP14U
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20 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum
Reference Document: JEDEC Publication 95, MO-153
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Integrated Circuit Systems, Inc.
ICS853014
LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Marking Package 20 lead TSSOP 20 lead TSSOP 20 lead "Lead-Free" TSSOP 20 lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS853014BG ICS853014BGT ICS853014BGLF ICS853014BGLFT ICS853014BG ICS853014BG ICS853014BGL ICS853014BGL
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and may be registered in certain jurisdictions. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853014BG
www.icst.com/products/hiperclocks.html
16
REV. C MAY 13, 2005
Integrated Circuit Systems, Inc.
ICS853014
LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change * 3.3V LVPECL table - VOH values changed @ 85 to 2.22V min. and 2.295V typical from 2.295V min. and 2.33V typical. * 3.3V LVPECL table - VOH values changed @ 85 to 2.22V min. and 2.295V typical from 2.295V min. and 2.33V typical. * 3.3V LVPECL table - VOH values changed @ 85 to 2.22V min. and 2.295V typical from 2.295V min. and 2.33V typical. * Revised LVPECL Output Termination drawings. Date
Rev
Table T4B T4C
Page pg. 4 pg. 5 pg. 5 pg. 8
B
T4D
9/10/03
T4B - T4D C C
pg. 10 * Revised Figure 5D. pgs. 4-5 * LVPECL & ECL tables - deleted VPP row. 3/18/04 pg. 6 1 16 * AC Table - added VPP row and changed max. value from 1200mV to 1800mV. Features Section - added Lead-Free bullet. Ordering Information Table - added Lead-Free par t number. 5/13/05
T9
853014BG
www.icst.com/products/hiperclocks.html
17
REV. C MAY 13, 2005

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