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Integrated Circuit Systems, Inc.
ICS8701I LOW SKEW 1, 2
CLOCK GENERATOR
FEATURES
* 20 LVCMOS outputs, 7W typical output impedance * Output frequency up to 250MHz * 200ps bank skew, 250ps output skew, 300ps multiple frequency skew, 600ps part-to-part skew * LVCMOS / LVTTL clock input * LVCMOS control inputs * Bank enable logic allows unused banks to be disabled in reduced fanout applications * 3.3V or mixed 3.3V input, 2.5V output operating supply modes * 48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm package body, 0.5mm package lead pitch * -40C to 85C ambient operating temperature * Other divide values available on request
GENERAL DESCRIPTION
The ICS8701I is a low skew, /1, /2 Clock Generator and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The low impedance LVCMOS outputs are designed to drive 50W series or parallel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines.
,&6
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The bank enable inputs, BANK_EN0:1, support enabling and disabling each bank of outputs individually. The master reset input, nMR/ OE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The ICS8701I is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics make the ICS8701I ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
LVCMOS_CLK
PIN ASSIGNMENT
GND QB2 GND QB3 VDDO QB4 QC0 VDDO QC1 GND QC2 GND
1 2
1 QAO - QA4 0 QC3 VDDO QC4 QD0 VDDO QD1 GND QD2 GND QD3 VDDO QD4
DIV_SELA 1 QB0 - QB4 0 DIV_SELB 1 QC0 - QC4 0 DIV_SELC 1 QD0 - QD4 0 DIV_SELD nMR/OE BANK_EN0 BANK_EN1 Bank Enable Logic
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ICS8701I
QB1 VDDO QB0 QA4 VDDO QA3 GND QA2 GND QA1 VDDO QA0
8701I
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DIV_SELA DIV_SELB LVCMOS_CLK GND VDDI BANK_EN0 GND BANK_EN1 VDDI nMR/OE DIV_SELC DIV_SELD
48-Pin LQFP Y Package Top View
REV. A MARCH 16, 2001
Integrated Circuit Systems, Inc.
ICS8701I LOW SKEW 1, 2
CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number 2, 5, 11, 26, 32, 35, 41, 44 7, 9, 18, 21, 28, 30, 37, 39, 46, 48 16, 20 25, 27, 29, 31, 33 34, 36, 38, 40, 42 43, 45, 47, 1, 3 4, 6, 8, 10, 12 22 13 14 23 24 17, 19 15 Name VDDO Power Type Description Output power supply. Connect to 3.3V or 2.5V.
GND VDDI QA0, QA1, QA2, QA3, QA4 QB0, QB1, QB2, QB3, QB4 QC0, QC1, QC2, QC3, QC4 QD0, QD1, QD2, QD3, QD4 LVCMOS_CLK DIV_SELD DIV_SELC DIV_SELB DIV_SELA BANK_EN1, BANK_EN0 nMR/OE
Power Power Output
Ground. Connect to ground. Input power supply. Connect to 3.3V. Bank A outputs. LVCMOS interface levels. 7W typical output impedance. Bank B outputs. LVCMOS interface levels. 7W typical output impedance. Bank C outputs. LVCMOS interface levels. 7W typical output impedance. Bank D outputs. LVCMOS interface levels 7W typical output impedance. Pulldown Clock input. LVCMOS interface levels. Controls frequency division for bank D outputs. Pullup LVCMOS interface levels. Controls frequency division for bank C outputs. Pullup LVCMOS interface levels. Controls frequency division for bank B outputs. Pullup LVCMOS interface levels. Controls frequency division for bank A outputs. Pullup LVCMOS interface levels. Pullup Pullup Enables and disables outputs by banks. LVCMOS interface levels. Master reset and output enable. Enables and disables all outputs. LVCMOS interface levels.
Output
Output
Output Input Input Input Input Input Input Input
8701I
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REV. A MARCH 16, 2001
Integrated Circuit Systems, Inc.
ICS8701I LOW SKEW 1, 2
CLOCK GENERATOR
Maximum Units pF
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter LVCMOS_CLK DIV_SELA, DIV_SELB, Input Capacitance DIV_SELC, DIV_SELD, BANK_EN0, NMR/OE, BANK_EN1, Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance VDDI, VDDO = 3.465V VDDI = 3.465V, VDDO = 2.625V 7 Test Conditions Minimum Typical
CIN
RPULLUP RPULLDOWN CPD
51 51
KW KW pF pF
ROUT
W
TABLE 3. FUNCTION TABLE
Inputs nMR/OE 0 1 1 1 1 1 1 1 1 BANK_EN1 X 0 1 0 1 0 1 0 1 BANK_EN0 X 0 0 1 1 0 0 1 1 DIV_SELx X 0 0 0 0 1 1 1 1 QA0 - QA4 Hi Z Active Active Active Active Active Active Active Active QB0 - QB4 Hi Z Hi Z Active Active Active Hi Z Active Active Active Outputs QC0 - QC4 Hi Z Hi Z Hi Z Active Active Hi Z Hi Z Active Active QD0 - QD4 Hi Z Hi Z Hi Z Hi Z Active Hi Z Hi Z Hi Z Active Qx frequency zero fIN/2 fIN/2 fIN/2 fIN/2 fIN fIN fIN fIN
8701I
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REV. A MARCH 16, 2001
Integrated Circuit Systems, Inc.
ICS8701I LOW SKEW 1, 2
CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Inputs Outputs Ambient Operating Temperature Storage Temperature 4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V -40C to 85C -65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDI=VDDO=3.3V5%, TA=-40C TO 85C
Symbol VDDI VDDO IDD Parameter Input Power Supply Voltage Output Power Supply Voltage Quiescent Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 100 Units V V mA
VDDI = VIH = 3.465V VIL = 0V
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDDI=VDDO=3.3V5%, TA=-40C TO 85C
Symbol Parameter Input High Voltage DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE LVCMOS_CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE LVCMOS_CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE LVCMOS_CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE LVCMOS_CLK Test Conditions VDDI = 3.465V VDDI = 3.465V VDDI = 3.465V VDDI = 3.465V VDDI = VIN = 3.465V VDDI = VIN = 3.465V VDDI = 3.465V, VIN = 0V VDDI = 3.465V, VIN = 0V VDDI = VDDO = 3.135V IOH = -36mA VDDI = VDDO = 3.135V IOL = 36mA -150 -5 2.6 0.5 Minimum 2 2 -0.3 -0.3 Typical Maximum 3.8 3.8 0.8 1.3 5 150 Units V V V V A A A A V V
VIH
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
VOH VOL
Output High Voltage Output Low Voltage
8701I
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REV. A MARCH 16, 2001
Integrated Circuit Systems, Inc.
ICS8701I LOW SKEW 1, 2
CLOCK GENERATOR
Maximum 250 0MHZ f 200MHz 0MHZ f 200MHz Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 30% to 70% 30% to 70% 0MHZ f 200MHz 200 200 tCYCLE/2 - 0.6 1.9 2.2 2.2 3.6 3.6 200 250 300 600 900 900 tCYCLE/2 + 0.6 3.1 Units MHz ns ns ps ps ps ps ps ps ns ns ns ns
TABLE 5A. AC CHARACTERISTICS, VDDI=VDDO=3.3V5%, TA=-40C TO 85C
Symbol fMAX tpLH tpHL tsk(b) tsk(o) tsk(w) tsk(pp) tR tF tPW Parameter Maximum Input Frequency Propagation Delay, Low-to-High Propagation Delay, High-to-Low Bank Skew; NOTE 2 Output Skew; NOTE 3 Multiple Frequency Skew; NOTE 4 Par t to Par t Skew; NOTE 5 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Pulse Width Test Conditions Minimum Typical
tCYCLE/2
f = 200MHz 2.5 Output Enable Time; f = 10MHz 6 tEN NOTE 6 Output Disable Time; tDIS f = 10MHz 6 NOTE 6 NOTE 1: All parameters measured at 200MHz unless noted otherwise. All outputs terminated with 50W to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defined as the skew at different outputs on different devices operating at the same supply voltages and with equal load conditions. NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
8701I
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REV. A MARCH 16, 2001
Integrated Circuit Systems, Inc.
ICS8701I LOW SKEW 1, 2
CLOCK GENERATOR
Maximum 3.465 2.625 100 Units V V mA
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDDI=3.3V5%, VDDO=2.5V5%, TA=-40C TO 85C
Symbol VDDI VDDO IDD Parameter Input Power Supply Voltage Output Power Supply Voltage Quiescent Power Supply Current Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5
VDDI = VIH = 3.465V VIL = 0V
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDDI=3.3V5%, VDDO=2.5V5%, TA=-40C TO 85C
Symbol Parameter Input High Voltage DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE LVCMOS_CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE LVCMOS_CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE LVCMOS_CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE LVCMOS_CLK Test Conditions VDDI = 3.465V VDDI = 3.465V VDDI = 3.465V VDDI = 3.465V VIN = 3.465V VIN = 3.465V VIN = 0V VIN = 0V VDDI = 3.135V, VDDO = 2.375V IOH = -27mA VDDI = 3.135V, VDDO = 2.375V IOH = 27mA -150 -5 1.8 Minimum 2 2 -0.3 -0.3 Typical Maximum 3.8 3.8 0.8 1.3 5 150 Units V V V V A A A A V
VIH
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
VOH
Output High Voltage
VOL
Output Low Voltage
0.5
V
8701I
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REV. A MARCH 16, 2001
Integrated Circuit Systems, Inc.
ICS8701I LOW SKEW 1, 2
CLOCK GENERATOR
Maximum 250 0MHZ f 200MHz 0MHZ f 200MHz Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 30% to 70% 30% to 70% 0MHZ f 200MHz 200 200 tCYCLE/2 - 0.6 1.9 2.4 2.4 3.7 3.7 225 250 300 650 900 900 tCYCLE/2 + 0.6 3.1 Units MHz ns ns ps ps ps ps ps ps ns ns ns ns
TABLE 5B. AC CHARACTERISTICS, VDDI=3.3V5%, VDDO=2.5V5%, TA=-40C TO 85C
Symbol fMAX tpLH tpHL tsk(b) tsk(o) tsk(w) tsk(pp) tR tF tPW Parameter Maximum Input Frequency Propagation Delay, Low-to-High Propagation Delay, High-to-Low Bank Skew; NOTE 2 Output Skew; NOTE 3 Multiple Frequency Skew; NOTE 4 Par t to Par t Skew; NOTE 5 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Pulse Width Test Conditions Minimum Typical
tCYCLE/2
f = 200MHz 2.5 Output Enable Time; f = 10MHz 6 tEN NOTE 6 Output Disable Time; tDIS f = 10MHz 6 NOTE 6 NOTE 1: All parameters measured at 200MHz unless noted otherwise. All outputs terminated with 50W to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defined as the skew at different outputs on different devices operating at the same supply voltages and with equal load conditions. NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
8701I
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REV. A MARCH 16, 2001
Integrated Circuit Systems, Inc.
ICS8701I LOW SKEW 1, 2
CLOCK GENERATOR
FIGURE 1A, 1B - TIMING DIAGRAMS
CLK
Qx, /1
Qx, /2
FIGURE 1A - ACTIVE, /1, /2
nMR/OE
CLK
Qx, /1
Qx, /2 High Impedance Active
FIGURE 1B - RESET TO ACTIVE, /1, /2
8701I
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REV. A MARCH 16, 2001
Integrated Circuit Systems, Inc.
ICS8701I LOW SKEW 1, 2
CLOCK GENERATOR
FIGURE 2A, 2B - TIMING WAVEFORMS
CLK
tPHL Q
tPLH
VDDO/2
FIGURE 2A - PROPAGATION DELAYS
fin = 200MHz, Vamp = 3.3V, tr = tf = 600ps
nMR/OE, BANK_ENx
3.3V
BANK_ENx
0V tPHZ tPZH VOH - 300mV VDDO/2 tPLZ VDDO/2 VOL + 300mV tPZL
Q
VOH
Q
VOL
FIGURE 2B - DISABLE AND ENABLE TIMES
fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps
8701I
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REV. A MARCH 16, 2001
Integrated Circuit Systems, Inc.
ICS8701I LOW SKEW 1, 2
CLOCK GENERATOR
FIGURE 3A, 3B - SKEW DEFINITIONS & WAVEFORMS
Bank Skew - Skew between outputs within a bank. Outputs operating at the same temperature, supply voltages and with equal load conditions.
CLK
Qx0

VDDO/2
VDDO/2

tsk(b)
tsk(b)
Qx4
VDDO/2
VDDO/2
FIGURE 3A - BANK SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
Output Skew - Skew between outputs of any bank. Outputs operating at the same temperature, supply voltages and with equal load conditions.
CLK
QA0 - QA4
VDDO/2
VDDO/2
tsk(o) QB0 - QB4 QC0 - QC4 QD0 - QD4 VDDO/2
tsk(o)
VDDO/2
FIGURE 3B - OUTPUT SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
8701I
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REV. A MARCH 16, 2001
Integrated Circuit Systems, Inc.
ICS8701I LOW SKEW 1, 2
CLOCK GENERATOR
FIGURE 3C, 3D - SKEW DEFINITIONS & WAVEFORMS
Multiple Frequency Skew - Skew between banks of outputs operating at different frequencies. Outputs operating at the same temperature, supply voltages and with equal load conditions.
CLK
QA0 - QA4, QB0 - QB4, QC0 - QC4, or QD0 - QD4 in /1
VDDO/2
VDDO/2
tsk(w)
tsk(w)
VDDO/2 QA0 - QA4, QB0 - QB4, QC0 - QC4, or QD0 - QD4 in /2
VDDO/2
FIGURE 3C - MULTIPLE FREQUENCY SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
Part to Part Skew - Skew between outputs of any bank on different parts. Outputs operating at the same temperature, supply voltages and with equal load conditions.
CLK
VDDO/2
VDDO/2
PART 1 QA0 - QA4 QB0 - QB4 QC0 - QC4 QD0 - QD4
tsk(p)
tsk(p)
VDDO/2
VDDO/2
PART 2 QA0 - QA4 QB0 - QB4 QC0 - QC4 QD0 - QD4
FIGURE 3B - OUTPUT SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps www.icst.com/products/hiperclocks.html
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REV. A MARCH 16, 2001
8701I
Integrated Circuit Systems, Inc.
ICS8701I LOW SKEW 1, 2
CLOCK GENERATOR
PACKAGE OUTLINE - Y SUFFIX
D
D2
48
1 2 3
37 36
L
E
E1
E2
N
12 13
24
25
e
A
A2
D1 -CSEATING PLANE
ccc C
A1
b
c
TABLE 6. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BCC SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L 0.45 0 0.05 1.35 0.17 0.09 9.00 BASIC 7.00 BASIC 5.50 9.00 BASIC 7.00 BASIC 5.50 0.5 BASIC 0.60 0.75 7 0.08 1.40 0.22 MINIMUM NOMINAL 48 1.60 0.15 1.45 0.27 0.20 MAXIMUM
q
ccc
Reference Document: JEDEC Publication 95, MS-026
8701I
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REV. A MARCH 16, 2001
Integrated Circuit Systems, Inc.
ICS8701I LOW SKEW 1, 2
CLOCK GENERATOR
Temperature -40C to 85C -40C to 85C
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS8701CYI ICS8701CYIT Marking ICS8701CYI ICS8701CYI Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 2000
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8701I
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REV. A MARCH 16, 2001

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